Semiconductor structure

Abstract

The invention provides a semiconductor structure and a forming method thereof. According to the semiconductor integrated circuit, the electrical conduction structure is arranged on the trench isolation structure, and the space above the trench isolation structure is utilized, so that the space occupied by the electrical conduction structure in the whole semiconductor integrated circuit can be reduced, and the size of the formed semiconductor integrated circuit can be reduced.

Description

[0001] This application is a divisional application of application No. 201910591043.4, titled "Semiconductor structure and forming method thereof", filed on July 2, 2019. TECHNICAL FIELD

[0002] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure. BACKGROUND

[0003] Shallow Trench Isolation (STI) is a main method for realizing device isolation in large-scale integrated circuits. For example, adjacent active areas (AA) can be isolated from each other by using a trench isolation structure, so as to avoid mutual interference of components formed on different active areas. In addition, a large number of electrically conductive structures are usually provided in semiconductor integrated circuits, which can be used to realize electrical transmission or only as redundant components (i.e. not to realize electrical function). Generally, the electrically conductive structures in the integrated circuit are arranged away from the trench isolation structure, and therefore a certain accommodation space needs to be reserved for the electrically conductive structures.

[0004] With the continuous development of semiconductor technology, the size of integrated circuits tends to be reduced. Even though the size of the electrically conductive structure can be reduced to achieve the size reduction of the integrated circuit, the overall size of the semiconductor integrated circuit is difficult to be further reduced due to the need to reserve a larger space for the electrically conductive structure. SUMMARY

[0005] The purpose of the present application is to provide a semiconductor structure to facilitate the reduction of the overall size of the semiconductor integrated circuit.

[0006] To solve the above technical problems, the present application provides a semiconductor structure, comprising:

[0007] a trench isolation structure formed in an isolation trench of a substrate, wherein the trench isolation structure comprises a plurality of insulating layers, the plurality of insulating layers cover the inner wall of the isolation trench in sequence, and the top surface of the innermost insulating layer of the plurality of insulating layers is more sunken relative to the top surface of the substrate to form a first groove in the isolation trench; and

[0008] an electrically conductive structure formed on the substrate and at least partially located on the trench isolation structure, and the electrically conductive structure completely fills the first groove; wherein the electrically conductive structure comprises a first conductive layer and a second conductive layer, the first conductive layer fills the first groove and extends out of the isolation trench, and the second conductive layer is formed on the first conductive layer.

[0009] Based on the semiconductor structure as described above, the present application further provides a forming method of the semiconductor structure, comprising:

[0010] providing a substrate, and forming an isolation trench in the substrate;

[0011] sequentially forming a plurality of insulating layers in the isolation trench to form a trench isolation structure, and a top surface of an innermost insulating layer of the plurality of insulating layers is more sunken relative to a top surface of the substrate to form a first recess in the isolation trench; and

[0012] forming a first conductive layer and a second conductive layer on the substrate, and the first conductive layer completely fills the first recess and extends out of the isolation trench, and the second conductive layer is formed on the first conductive layer.

[0013] In the semiconductor structure provided by the present application, based on the trench isolation structure formed in the substrate, at least part of the electrically conductive structure is formed on the trench isolation structure, so that the space above the trench isolation structure can be effectively utilized, and accordingly the space reserved for the electrically conductive structure can be reduced, or even the electrically conductive structure can not need to reserve space. In this way, it is beneficial to realize the size reduction of the semiconductor integrated circuit formed thereby. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 a schematic view of the semiconductor structure in an embodiment of the present application;

[0015] Figure 2 a flowchart of the forming method of the semiconductor structure in an embodiment of the present application;

[0016] Figures 3a to 3d a schematic view of the semiconductor structure in an embodiment of the present application in the preparation process thereof.

[0017] In the drawings, the reference signs are as follows:

[0018] 100 - substrate;

[0019] 200a - isolation trench;

[0020] 200b - first recess;

[0021] 200c - second recess;

[0022] 200 - trench isolation structure;

[0023] 210 - first insulating layer;

[0024] 220 - second insulating layer;

[0025] 230 - third insulating layer;

[0026] 300 - electrically conductive structure;

[0027] 300a - dummy gate structure;

[0028] 300b - gate structure;

[0029] 310a / 310b - first electrically conductive layer;

[0030] 320a / 320b - second electrically conductive layer;

[0031] 330a / 330b - third electrically conductive layer;

[0032] 340a / 340b - masking layer;

[0033] 341 - slit;

[0034] 400 - sidewall structure;

[0035] 410 - first isolation layer;

[0036] 420 - second isolation layer. DETAILED DESCRIPTION

[0037] The semiconductor structure and the method for forming the same according to the present application will be further described below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present application will be more apparent from the following description. It should be noted that the accompanying drawings are in a very simplified form and are not drawn to scale, and are only used to facilitate, clarify and assist in the description of the embodiments of the present application.

[0038] Figure 1 A schematic diagram of the semiconductor structure in an embodiment of the present application is shown in FIG. 1, which includes: Figure 1

[0039] a trench isolation structure 200 formed in an isolation trench 200a of a substrate 100, and at least a portion of a top surface of the trench isolation structure 200 is more sunken than a top surface of the substrate 100; and

[0040] an electrically conductive structure 300 formed on the substrate 100, the electrically conductive structure 300 at least partially located above the trench isolation structure 200 and filling the isolation trench 200a.

[0041] ​The electrically conductive structure 300 includes a first conductive layer 310a and a second conductive layer 320a. The first conductive layer 310a fills the isolation trench 200a and extends out of the isolation trench 200a. The second conductive layer 320a is formed on the first conductive layer 310a. In this embodiment, the first conductive layer 310a extends out of the isolation trench 200a, so that the entire top surface of the first conductive layer 310a is higher than the top surface of the substrate 100.

[0042] It should be noted that by forming the electrically conductive structure 300 on the trench isolation structure 200, the space above the trench isolation structure 200 can be effectively utilized, so that the accommodation space reserved for the electrically conductive structure can be reduced, or the electrically conductive structure 300 can not need to be additionally reserved. In this way, it is beneficial to reduce the size of the entire integrated circuit.

[0043] In addition, it should be noted that the electrically conductive structure 300 formed on the trench isolation structure 200 is partially embedded in the isolation trench 200a, but this does not greatly affect the performance of the electrically conductive structure 300. For example, when the electrically conductive structure 300 is used to realize electrical transmission, although the electrically conductive structure 300 is partially filled in the isolation trench 200a, the electrical transmission performance of the first conductive layer 310a and the second conductive layer 320a still meets the requirements. Or, when the electrically conductive structure 300 is used to constitute a redundant component, for example, to constitute a dummy gate, at this time, since the redundant component does not need to realize electrical function, there is no problem of function being affected.

[0044] In this embodiment, the projection area of the second conductive layer 320a in the height direction is not less than the top surface area of the first conductive layer 310a. That is, the top surface of the first conductive layer 310a is not exposed under the direct or indirect coverage of the second conductive layer 320a, so that only the side wall of the first conductive layer 310a is laterally exposed relative to the second conductive layer 320a. The material of the first conductive layer 310a includes doped polysilicon (poly), and the second conductive layer 320a can be a metal layer, for example, the material of the second conductive layer 320a includes tungsten (W).

[0045] Further, the trench isolation structure 200 has a multilayer insulating layer, which sequentially covers the inner wall of the isolation trench 200a, and the top surface of the innermost insulating layer in the multilayer insulating layer is more sunken relative to the top surface of the substrate, to constitute a first groove in the isolation trench 200a.

[0046] In the embodiment, the sidewall boundary of the electrically conductive structure 300 is between the boundary of the first recess and the boundary of the isolation trench 200a, so that the electrically conductive structure 300 completely fills the first recess, that is, the first conductive layer 310a in the electrically conductive structure 300 is at least partially formed on the innermost insulating layer to completely fill the first recess and further extend out of the isolation trench 200a. It should be noted that the "sidewall boundary of the electrically conductive structure" herein refers to, for example, the sidewall of the electrically conductive structure extending in the length direction.

[0047] With continued reference to Figure 1 As shown, in the embodiment, the multilayer insulating layer in the trench isolation structure 200 includes a first insulating layer 210, a second insulating layer 220, and a third insulating layer 230. The first insulating layer 210 and the second insulating layer 220 conformally cover the inner wall of the isolation trench 200a in turn, and the third insulating layer 230 is located at the innermost layer of the multilayer insulating layer to fill the isolation trench 200a. That is, the second insulating layer 220 is located between the first insulating layer 210 and the third insulating layer 230, and the third insulating layer 230 constitutes the innermost layer of the trench isolation structure 200, and the top surface of the third insulating layer 230 is lower than the top of the isolation trench 200a, so that the third insulating layer 230 is more sunken relative to the top surface of the substrate 100.

[0048] Further, the top surface of the third insulating layer 230 is also lower than the top surface of the second insulating layer 220, so that the second insulating layer 220 surrounds the first recess above the third insulating layer 230.

[0049] With continued reference to Figure 1 As shown, the sidewall boundary of the electrically conductive structure 300 exceeds the sidewall boundary of the third insulating layer 230 and overlaps on the second insulating layer 220. It can be understood that the width dimension of the electrically conductive structure 300 in a predetermined direction is greater than the opening dimension of the first recess surrounded by the second insulating layer and is less than the width dimension of the trench isolation structure 200.

[0050] In the embodiment, the first conductive layer 310a in the electrically conductive structure 300 fills the first recess surrounded by the second insulating layer 220 to cover the sidewall of the third insulating layer 230 and the second insulating layer 220 close to the third insulating layer, and further extends out of the first recess, so that the sidewall boundary of the first conductive layer 310a overlaps on the top of the second insulating layer 220, and correspondingly, the first conductive layer 310a has a sidewall extending out of the first recess.

[0051] In an alternative, the top surface of the first insulating layer 210 can also be recessed relative to the second insulating layer 220 and the substrate 100, so that a micro second recess can be formed by the sidewall of the second insulating layer 220, the sidewall of the isolation trench 200a and the top surface of the first insulating layer 210, i.e. the second recess is located between the sidewall of the second insulating layer 220 and the isolation trench.

[0052] Based on this, for example, the first insulating layer 210 and the third insulating layer 230 can comprise the same material, and the second insulating layer 220 can have a material different from the third insulating layer 230, so that when the trench isolation structure 200 is formed by the etch-back process, the top surface of the first insulating layer 210 and the third insulating layer 230 can be recessed relative to the top surface of the substrate 100. In addition, since the second insulating layer 220 can have a material different from the third insulating layer 230, the first insulating layer 210 and the third insulating layer 230 can also be lower than the top surface of the second insulating layer 220 by the etch-back process.

[0053] Specifically, the material of the first insulating layer 210 and the third insulating layer 230, for example, comprises silicon oxide (SiO), and the material of the second insulating layer 220, for example, comprises silicon nitride (SiN), so that the trench isolation structure 200 presents an ONO structure to improve the isolation performance of the trench isolation structure 200.

[0054] Referring next to Figure 1 As shown, the semiconductor structure further comprises a side wall structure 400 covering at least the sidewall of the electrically conductive structure 300, so that the side wall structure 400 covers at least the sidewall of the first conductive layer 310a extending out of the isolation trench 200a and the sidewall of the second conductive layer 320a.

[0055] In the embodiment, the width dimension of the electrically conductive structure 300 in a predetermined direction is greater than the width dimension of the third insulating layer 230 and less than the width dimension of the trench isolation structure 200, so that the electrically conductive structure 300 does not cover the second recess between the second insulating layer and the sidewall of the isolation trench. Based on this, the side wall structure 400 can further extend to cover the second insulating layer 220 and the first insulating layer 210, so that the side wall structure 400 also embeds into the second recess. That is, the second recess is also filled by the side wall structure 400, so that the gap of the edge portion of the isolation trench 200a can be compensated.

[0056] The side wall structure 400 can be a single layer structure or a stacked layer structure. In this embodiment, the side wall structure 400 includes a first isolation layer 410 and a second isolation layer 420, which are sequentially arranged on the sidewall of the electrically conductive structure 300 and further fill the second recess in the second insulating layer 220. Specifically, the first isolation layer 410 and the second isolation layer 420 can have different materials, for example, the material of the first isolation layer 410 includes silicon oxide and the material of the second isolation layer 420 includes silicon nitride.

[0057] Of course, in other embodiments, the side wall structure can further include three isolation layers, which are sequentially arranged on the sidewall of the electrically conductive structure. In addition, the three isolation layers in the side wall structure can have materials such as silicon oxide, silicon nitride, and silicon oxide, respectively, to form an ONO structure isolation structure.

[0058] It can be understood that the trench isolation structure 200 further defines a first recess in the isolation trench 200a, and the first conductive layer 310a fills the first recess in the isolation trench 200a, and the sidewall boundary of the first conductive layer 310a also overlaps the top of the sidewall of the first recess. In addition, the trench isolation structure 200 further defines a second recess in the isolation trench 200a, which is located at the side of the first recess and can make the side wall structure 400 fill the second recess to compensate for the gap in the edge area of the isolation trench 200a.

[0059] Specifically referring to Figure 1 As shown, in combination with the above, the sidewall boundary of the first conductive layer 310a also overlaps the top of the sidewall of the first recess, so that a first recess is formed in the first conductive layer 310a corresponding to the top surface of the isolation trench 200a (more specifically, a first recess is formed in the first conductive layer 310a corresponding to the top surface of the first recess), and the bottom of the first recess is higher than the top of the isolation trench 200a. In addition, the second conductive layer 320a is located above the first conductive layer 310a, and correspondingly, the bottom surface of the second conductive layer 320a corresponding to the isolation trench 200a protrudes in the direction of the first conductive layer 310a, and the top surface of the second conductive layer 320a corresponding to the isolation trench 200a is recessed in the direction of the first conductive layer 310a to form a second recess.

[0060] That is, in the present embodiment, the first recess on the first conductive layer 310a and the second recess on the second conductive layer 320a are corresponding, more specifically, the bottom of the first recess on the first conductive layer 310a and the bottom of the second recess on the second conductive layer 320a are aligned on the same vertical line.

[0061] With continued reference to Figure 1 As shown, the electrically conductive structure 300 further includes a third conductive layer 330a formed between the first conductive layer 310a and the second conductive layer 320a. The material of the third conductive layer 330a includes, for example, titanium nitride.

[0062] In the present embodiment, the third conductive layer 330a is conformal to cover the top surface of the first conductive layer 310a, so that the third conductive layer 330a presents a bent structure corresponding to the first recess of the first conductive layer 310a. That is, the portion of the third conductive layer 330a corresponding to the bottom of the first recess protrudes into the first recess, and the top surface of the third conductive layer 330a corresponding to the first recess is recessed in a direction towards the first conductive layer 310a to form a third recess. In addition, the portion of the second conductive layer 320a close to the third conductive layer protrudes into the third recess.

[0063] With continued reference to Figure 1 As shown, the electrically conductive structure 300 further includes a shielding layer 340a formed on the second conductive layer 320a, and the top surface of the shielding layer 340a is more planar than the top surface of the second conductive layer 320a. Specifically, the shielding layer 340a can have a planar top surface by, for example, a planarization process.

[0064] In addition, in the present embodiment, the bottom surface of the shielding layer 340a corresponding to the second recess further surrounds a gap 341. Specifically, the top surface of the second conductive layer 320a has the second recess, so that the gap 341 can be formed above the second recess.

[0065] With continued reference to Figure 1 As shown, the semiconductor structure of the present embodiment includes at least two trench isolation structures 200, and an active area (AA) can be defined by adjacent trench isolation structures 200, and a semiconductor device can be disposed in the active area. In the present embodiment, an electrically conductive structure is also formed on the active area, and the electrically conductive structure in the active area can include a first conductive layer, a third conductive layer, a second conductive layer and a shielding layer stacked in sequence.

[0066] Specifically, the electrically conductive structure in the semiconductor device is used to form a gate structure 300b, for example. That is, the gate structure 300b may include a first conductive layer 310b and a second conductive layer 320b, and may further include a third conductive layer 330b and a shielding layer 340b.

[0067] Furthermore, the gate structure 300b located in the active region and the electrically conductive structure 300 located in the isolation region (corresponding to the region of the trench isolation structure) constitute a semiconductor integrated circuit, such as a peripheral circuit of a memory. The gate structure 300b located in the active region can further constitute a switching transistor in the peripheral circuit. Furthermore, the electrically conductive structure 300 located in the isolation region can be used to achieve electrical transmission or to constitute a dummy gate structure.

[0068] As described above, when the electrically conductive structure 300 in the isolation region is used to achieve electrical transmission, even if the bottom of the electrically conductive structure 300 extends into the isolation trench 200a, the electrical transmission performance of the first conductive layer 310a and the second conductive layer 320a in the electrically conductive structure 300 can still be guaranteed. In addition, in this embodiment, the width of the electrically conductive structure 300 in the isolation region is smaller than the width of the isolation trench 200a. This prevents the electrically conductive structure 300 in the isolation region from extending into the active region and thus preventing interference with semiconductor devices in the active region.

[0069] The following takes the electrically conductive structure 300 in the isolation region as an example for forming the dummy gate structure 300 a for further explanation.

[0070] like Figure 1 As shown, the gate structure 300b is formed on the top surface of the substrate 100, and the top surface of the first conductive layer 310b in the gate structure 300b is flatter than the top surface of the first conductive layer 310a in the dummy gate structure 300a. Accordingly, the top surfaces of the third conductive layer 330b and the second conductive layer 320b in the gate structure 300b are flatter than the top surfaces of the third conductive layer 330a and the second conductive layer 320a in the dummy gate structure 300a.

[0071] Furthermore, in the gate structure 300 b , the bottom surface of the shielding layer 340 b is in close contact with the top surface of the second conductive layer 320 b , and thus no gap is formed in the shielding layer 340 b of the gate structure 300 b .

[0072] In addition, the top surface of the first conductive layer 310b in the gate structure 300b is also higher than the top surface of the first conductive layer 310a in the dummy gate structure 300a. Correspondingly, the third conductive layer 330b in the gate structure 300b is also higher than the third conductive layer 330a in the dummy gate structure 300a; and the second conductive layer 320b in the gate structure 300b is also higher than the second conductive layer 320a in the dummy gate structure 300a. However, it should be noted that in the embodiment, the top surface of the shielding layer 340b in the gate structure 300b can be flush with the top surface of the shielding layer 340a in the dummy gate structure 300a, i.e., the top surfaces of the shielding layer on the trench isolation structure and the shielding layer on the active region are coplanar.

[0073] Based on the semiconductor structure as described above, the embodiment also provides a forming method of the semiconductor structure. Figure 1 For the flowchart of the forming method of the semiconductor structure in an embodiment of the present application, as shown in Figure 2 the forming method of the semiconductor structure in the embodiment includes:

[0074] In step S100, a substrate is provided, and an isolation trench is formed in the substrate;

[0075] In step S200, a trench isolation structure is formed in the isolation trench, and at least part of the top surface of the trench isolation structure is more sunken relative to the top surface of the substrate;

[0076] In step S300, a first conductive layer and a second conductive layer are formed on the substrate, the first conductive layer fills the isolation trench and extends out of the isolation trench, and the second conductive layer is formed on the first conductive layer.

[0077] Figure 2 For the structural diagram of the semiconductor structure in the preparation process in an embodiment of the present application, the following will describe in detail each step of forming the semiconductor structure in the embodiment in combination with the drawings.

[0078] In step S100, specifically referring to Figures 3a to 3d a substrate 100 is provided, and an isolation trench 200a is formed in the substrate 100.

[0079] The forming method of the isolation trench 200a includes, for example, first, forming a mask layer (not shown in the figure) on the substrate 100 to define the pattern of the isolation trench by using the mask layer; and then, etching the substrate 100 with the mask layer as a mask to form the isolation trench 200a.

[0080] Specifically referring to Figure 3aAs shown, in the embodiment, the opening size of the isolation trench 200a can be gradually reduced from the top of the trench to the bottom of the trench, so that the isolation trench 200a has an inclined sidewall. By forming the isolation trench 200a with the inclined sidewall, the filling performance of the insulation material can be effectively improved when filling the insulation material in the isolation trench 200a subsequently, and the problem of voids in the insulation material layer filled in the isolation trench 200a can be avoided.

[0081] In step S200, with reference to Figure 3a As shown, the trench isolation structure 200 is formed in the isolation trench 200a, and at least part of the top surface of the trench isolation structure 200 is more sunken relative to the top surface of the substrate 100.

[0082] It should be noted that in the conventional process, the planarization process is often used to prepare the trench isolation structure, so that the top surface of the formed trench isolation structure is flush with the top surface of the substrate, or even the trench isolation structure protrudes from the top surface of the substrate (i.e., the top surface of the trench isolation structure is higher than the top surface of the substrate).

[0083] In the embodiment, the multilayer insulation layer is formed in the isolation trench 200a based on the etching process to form the trench isolation structure 200, so as to at least reduce the height of the innermost insulation layer in the trench isolation structure 200, thereby realizing that the formed trench isolation structure 200 can be recessed relative to the top surface of the substrate 100.

[0084] Specifically, the forming method of the trench isolation structure 200 includes the following steps, for example.

[0085] Step one, sequentially forming a first insulation material layer and a second insulation material layer on the substrate 100, the first insulation material layer and the second insulation material layer conformally cover the inner wall (including the bottom wall and the sidewall) of the isolation trench 200a, and also cover the top surface of the substrate 100.

[0086] In the embodiment, the first insulation material layer includes a silicon oxide layer, and the second insulation material layer includes a silicon nitride layer. The silicon oxide layer can be formed by oxidation process, and the silicon nitride layer can be formed by chemical vapor deposition process.

[0087] Step two, depositing a third insulation material layer on the substrate 100, the third insulation material layer covers the second insulation material layer and fills the isolation trench 200a. The material of the third insulation material layer includes silicon oxide, for example.

[0088] Step three, performing an etching process to etch the third insulating material layer, the second insulating material layer and the first insulating material layer, so as to remove the portions of the third insulating material layer, the second insulating material layer and the first insulating material layer on the top surface of the substrate, and make the remaining third insulating material layer, second insulating material layer and first insulating material layer fill in the isolation trench, to form a third insulating layer 230, a second insulating layer 220 and a first insulating layer 210 respectively, wherein the top surface of the third insulating layer 230 is lower than the top surface of the substrate 100.

[0089] Specifically, the third insulating material layer covers the top layer, so in the etching process, the etchant preferentially etches the third insulating material layer to remove the portions of the third insulating material layer on the top surface of the substrate, thereby exposing the second insulating material layer; then, the second insulating material layer on the top surface of the substrate is continuously removed, so that the second insulating material layer remaining in the isolation trench 200a forms the second insulating layer 220; then, the exposed first insulating material layer can be etched to form the first insulating layer 210.

[0090] Further, when etching the first insulating material layer and / or the second insulating material layer, the etchant also etches the third insulating material layer in the isolation trench, so that the third insulating material layer remaining in the isolation trench 200a can be more sunken relative to the top surface of the substrate 100.

[0091] In the embodiment, when etching the first insulating material layer, the etchant also etches the third insulating material layer in the isolation trench, so that the third insulating material layer and the first insulating material layer remaining in the isolation trench 200a are both more sunken relative to the top surface of the substrate 100, and form the third insulating layer 230 and the first insulating layer 210 respectively.

[0092] That is, in the embodiment, the top surfaces of the first insulating layer 210 and the third insulating layer 230 are both lower than the top surface of the second insulating layer 220. In this way, the first recess 200b can be surrounded by the second insulating layer 220 in the isolation trench 200a; and the second recess 200c can also be surrounded by the second insulating layer 220 and the side wall of the isolation trench 200a.

[0093] In addition, it should be noted that at least two trench isolation structures 200 are formed on the substrate 100, and the active area (AA) of the semiconductor device can be further defined by the adjacent trench isolation structures 200. In subsequent processes, the corresponding semiconductor device can be prepared in the active area.

[0094] In step S300, with reference toFigure 3b As shown, a first conductive layer 310a and a second conductive layer 320a are formed on the substrate 100, wherein the sidewall boundary of the first conductive layer 310a is between the boundary of the first recess 200b and the boundary of the isolation trench 200a to fill the first recess 200b, and the top of the first conductive layer 310a further extends out of the isolation trench 200a, and the second conductive layer 320a is formed on the first conductive layer 310a. The first conductive layer 310a and the second conductive layer 320a can be used to form an electrically conductive structure 300.

[0095] Further, the projection area of the second conductive layer 320a in the height direction can be not less than the top surface area of the first conductive layer 310a. In this embodiment, the sidewall boundary of the second conductive layer 320a coincides with the sidewall boundary of the first conductive layer 310a.

[0096] In this embodiment, the electrically conductive structure has a part formed on the trench isolation structure 200, and can further form a dummy gate structure 300a.

[0097] In an optional solution, when the electrically conductive structure (dummy gate structure 300a) is prepared on the trench isolation structure 200, the electrically conductive structure can also be prepared on the active region at the same time to form a gate structure 300b in the active region. Specifically, the method for simultaneously forming the dummy gate structure 300a and the gate structure 300b includes the following steps.

[0098] The first step is to deposit a first conductive material layer on the substrate 100. In this embodiment, the first conductive material layer covers the substrate of the active region, and covers the trench isolation structure 200 and fills the first recess 200b.

[0099] Corresponding to the top surface of the first recess 200b, a first recess is formed in the first conductive material layer, and the bottom of the first recess is higher than the top of the isolation trench 200a. That is, the top surface of the first conductive material layer corresponding to the active region is flatter than the top surface of the first conductive material layer corresponding to the isolation region.

[0100] The second step is to deposit a second conductive material layer on the first conductive material layer.

[0101] Similarly, the second conductive material layer covers the active region and the isolation region (i.e., the trench isolation structure), and the bottom surface of the second conductive material layer corresponding to the first recess protrudes in the direction of the first conductive material layer, and the top surface of the second conductive material layer corresponding to the first recess is recessed in the direction of the first conductive material layer to form a second recess.

[0102] Further, before depositing the second conductive material layer, the method further comprises: depositing a third conductive material layer on the first conductive material layer; and the second conductive material layer is formed on the third conductive material layer.

[0103] Further, after depositing the second conductive material layer, the method further comprises: forming a shielding material layer on the second conductive material layer. Specifically, the shielding material layer can be formed by a planarization process, so that the top surface of the shielding material layer is more planar relative to the top surface of the second conductive material layer, i.e., the top surface of the shielding material layer in the isolation region and the top surface of the shielding material layer in the active region are flush.

[0104] In addition, in the embodiment, the second conductive material layer in the isolation region has a second recess, based on which, when the shielding material layer is deposited, a gap is formed in the part of the shielding material layer corresponding to the second recess.

[0105] Third step, patterning the second conductive material layer and the first conductive material layer to form the second conductive layer and the first conductive layer arranged in a stack. Specifically, the patterning method of the second conductive material layer and the first conductive material layer, for example, includes:

[0106] First, forming a patterned mask layer on the second conductive material layer; in the embodiment, the mask layer is formed on the shielding material layer, and the pattern of the mask layer includes a dummy gate pattern corresponding to the isolation region and a gate pattern corresponding to the active region;

[0107] Then, taking the mask layer as a mask, etching the second conductive material layer and the first conductive material layer in sequence to form the second conductive layer and the first conductive layer, respectively. In the embodiment, the shielding material layer and the third conductive material layer are also etched with the mask layer as a mask to form a shielding layer and a third conductive layer, respectively. As described above, the top surface of the shielding material layer in the isolation region and the top surface of the shielding material layer in the active region are flush, based on which, after the shielding layer is formed on the isolation region and the active region, respectively, the top surfaces of the shielding layer in the isolation region and the shielding layer in the active region are coplanar.

[0108] Key reference Figure 3cAs shown, the first conductive layer, the third conductive layer, the second conductive layer, and the shielding layer are formed in the isolation region (corresponding to the trench isolation structure) and the active region. The first conductive layer 310a, the third conductive layer 330a, the second conductive layer 320a, and the shielding layer 340a in the isolation region are used to form a dummy gate structure 300a; and the first conductive layer 310b, the third conductive layer 330b, the second conductive layer 320b, and the shielding layer 340b in the active region are used to form a gate structure 300b.

[0109] In this embodiment, the dummy gate structure 300a fills the first groove 200b of the isolation trench 200a, and the sidewall boundary of the dummy gate structure 300a overlaps the second insulating layer 220, that is, the dummy gate structure 300a does not fill the second groove 200c in the isolation trench 200a.

[0110] In a further solution, the method for forming a semiconductor structure further includes: step S400, forming a sidewall structure.

[0111] Specific reference Figure 3c As shown, the spacer structure 400 at least covers the sidewalls of the first conductive layer 310a extending out of the isolation trench and the sidewalls of the second conductive layer 320a, and further extends into the second groove to fill the second groove.

[0112] like Figure 3d Figure 3d As shown, in this embodiment, a sidewall structure 400 is formed on the sidewall of the dummy gate structure 300a, and a sidewall structure is also formed on the sidewall of the gate structure 300b to cover the sidewalls of the first conductive layer 310b, the third conductive layer 330b and the second conductive layer 320b in the gate structure 300b.

[0113] At this point, it is achieved that the gate structure 300b can be formed in the active area and the dummy gate structure 300a can be formed in the isolation area at the same time using the same process steps, and the sidewall structure 400 can be formed on the side walls of the gate structure 300b and the dummy gate structure 300a at the same time, which is conducive to simplifying the process.

[0114] In summary, in the semiconductor structure of this embodiment, by arranging at least a portion of the electrically conductive structure above the trench isolation structure, the space above the trench isolation structure can be fully utilized, which is equivalent to reducing the space occupied by the electrically conductive structure in the entire semiconductor integrated circuit, thereby facilitating the size reduction of the constructed semiconductor integrated circuit.

[0115] In an optional solution, the width of the electrically conductive structure used to form the dummy gate structure is smaller than the opening of the isolation trench, so as to prevent the dummy gate structure from interfering with the semiconductor devices in the active region (e.g., affecting the gate structure in the active region).

[0116] In a further solution, even if the trench isolation structure is formed by multiple layers of insulating material, the same etching process is used to etch the multiple layers of insulating material one by one. At this time, due to the difference in etching rate of different insulating materials, the height difference exists between the multiple layers of insulating material (e.g., the height difference exists between the first insulating layer and the second insulating layer in the embodiment). In addition, since the electrically conductive structure in the isolation region does not extend to the edge of the isolation trench in a predetermined direction (e.g., the width direction of the electrically conductive structure), the second groove surrounded by the second insulating layer and the side wall of the isolation trench in the isolation trench is not filled by the electrically conductive structure. Based on this, the side wall structure can further fill the second groove on the basis of covering the side wall of the electrically conductive structure, so as to compensate for the gap at the edge of the isolation trench and guarantee the isolation performance of the trench isolation structure.

[0117] It should be noted that, in the conventional trench isolation structure formed by the planarization process, when the trench isolation structure includes multiple layers of insulating material, the planarization process needs to be performed for the specific material of each layer of insulating material, which is relatively complicated in operation steps. It can be seen that, compared with the conventional process, the trench isolation structure in the embodiment can simplify the process while guaranteeing the isolation performance of the trench isolation structure.

[0118] It should be noted that the above description is only a description of the preferred embodiments of the present application, and does not limit the scope of the present application in any way. For any person skilled in the art, many possible changes and modifications to the technical solutions disclosed above, or equivalent embodiments with equivalent changes, can be made without departing from the scope of the technical solutions of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the technical solutions of the present application, shall still fall within the scope of protection of the technical solutions of the present application.

[0119] It should be further noted that, unless specifically described or indicated, the terms "first", "second", "third" and the like in the description are only used to distinguish the components, elements, steps and the like in the description, and do not represent the logical relationship or sequence relationship between the components, elements, steps and the like. In addition, the word "or" should be understood as having the definition of logical "or", not the definition of logical "exclusive or", unless the context clearly indicates the opposite intention.

Claims

1. A semiconductor structure, characterized in that include: A trench isolation structure is formed in an isolation trench of a substrate, the trench isolation structure defining an active area, wherein the trench isolation structure includes multiple insulating layers, the multiple insulating layers sequentially covering inner walls of the isolation trench, and a top surface of an innermost insulating layer of the multiple insulating layers is sunken relative to a top surface of the substrate to form a first recess in the isolation trench; a dummy gate structure formed on the substrate and at least partially located on the trench isolation structure, wherein the dummy gate structure completely fills the first groove; wherein the dummy gate structure includes a first conductive layer and a second conductive layer, the first conductive layer fills the first groove and extends out of the isolation trench, and the second conductive layer is formed on the first conductive layer; a gate structure formed on the active region; and A spacer structure is formed on the sidewalls of the gate structure and the dummy gate structure.

2. The semiconductor structure according to claim 1, wherein A sidewall boundary of the dummy gate structure is located between a boundary of the first recess and a boundary of the isolation trench.

3. The semiconductor structure according to claim 1, wherein: The multi-layer insulation layer includes a first insulation layer, a second insulation layer and a third insulation layer. The first insulation layer and the second insulation layer sequentially cover the inner wall of the isolation trench. The third insulation layer is located at the innermost layer of the multi-layer insulation layer.

4. The semiconductor structure according to claim 3, wherein: A top surface of the third insulating layer is lower than a top surface of the second insulating layer, so that the first groove is surrounded by the second insulating layer and is above the third insulating layer.

5. The semiconductor structure according to claim 3, wherein: The sidewall boundary of the dummy gate structure exceeds the sidewall boundary of the third insulating layer and overlaps the second insulating layer.

6. The semiconductor structure according to claim 1, wherein A first recess is formed on the top surface of the first conductive layer corresponding to the first groove, and a bottom of the first recess is higher than a top of the first groove.

7. The semiconductor structure according to claim 6, wherein: The electrically conductive structure further includes a third conductive layer formed between the first conductive layer and the second conductive layer; and a bottom portion of the third conductive layer corresponding to the first recess protrudes into the first recess, and a top surface of the third conductive layer corresponding to the first recess is recessed in a direction toward the first conductive layer.

8. The semiconductor structure according to claim 1, wherein: The bottom surface of the second conductive layer corresponding to the first groove is convex toward the first conductive layer, and the top surface of the second conductive layer corresponding to the first groove is concave toward the first conductive layer to form a second depression.

9. The semiconductor structure according to claim 8, wherein: The dummy gate structure further includes a shielding layer formed on the second conductive layer, and the shielding layer forms a gap around the second recess with a bottom surface corresponding to the second recess.

10. The semiconductor structure according to claim 1, wherein: The gate structure includes a first conductive layer, a third conductive layer and a second conductive layer stacked in sequence; Wherein, the dummy gate structure located on the trench isolation structure and the gate structure located on the active area both include a shielding layer, and the shielding layer is formed on the dummy gate structure and the second conductive layer of the gate structure.

11. The semiconductor structure according to claim 10, wherein: The top surface of the first conductive layer in the gate structure is flatter than the top surface of the first conductive layer in the dummy gate structure; The top surface of the third conductive layer in the gate structure is flatter than the top surface of the third conductive layer in the dummy gate structure; A top surface of the second conductive layer in the gate structure is flatter than a top surface of the second conductive layer in the dummy gate structure.

12. The semiconductor structure according to claim 10, wherein: The top surface of the first conductive layer in the gate structure is higher than the top surface of the first conductive layer in the dummy gate structure; the top surface of the third conductive layer in the gate structure is higher than the top surface of the third conductive layer in the dummy gate structure; A top surface of the second conductive layer in the gate structure is higher than a top surface of the second conductive layer in the dummy gate structure.

13. The semiconductor structure according to claim 11, wherein: In the gate structure, a bottom surface of the shielding layer and a top surface of the second conductive layer are in closed contact.

14. A semiconductor structure, characterized in that include: A trench isolation structure is formed in an isolation trench of a substrate, wherein at least a portion of a top surface of the trench isolation structure is sunken relative to a top surface of the substrate; an electrically conductive structure formed on the trench isolation structure of the substrate and filling the isolation trench, wherein the electrically conductive structure comprises a first conductive layer and a second conductive layer, the first conductive layer filling the isolation trench and extending out of the isolation trench, the second conductive layer formed on the first conductive layer, and recesses formed on top surfaces of the first conductive layer and the second conductive layer corresponding to the isolation trench; a shielding layer formed on the second conductive layer of the electrically conductive structure, wherein a recess in the shielding layer corresponding to the second conductive layer and the recess in the second conductive layer form a gap; as well as, The sidewall structure is formed on the sidewall of the electrically conductive structure.

15. A semiconductor structure, characterized in that include: A trench isolation structure is formed in an isolation trench of a substrate, wherein the trench isolation structure comprises a first insulating layer, a second insulating layer, and a third insulating layer, wherein the first insulating layer and the second insulating layer sequentially cover inner walls of the isolation trench, and the third insulating layer is located at the innermost layer of the multiple insulating layers; An electrically conductive structure is formed on the trench isolation structure of the substrate and fills the isolation trench. The sidewall boundary of the electrically conductive structure exceeds the sidewall boundary of the third insulating layer and overlaps the second insulating layer.

16. A semiconductor structure, characterized in that include: A trench isolation structure is formed in an isolation trench of a substrate, the trench isolation structure defining an active area, wherein the trench isolation structure includes multiple insulating layers, the multiple insulating layers sequentially covering inner walls of the isolation trench, and a top surface of an innermost insulating layer of the multiple insulating layers is sunken relative to a top surface of the substrate to form a first recess in the isolation trench; a dummy gate structure formed on the substrate and at least partially located on the trench isolation structure, wherein the dummy gate structure completely fills the first groove; wherein the dummy gate structure includes a conductive layer; and a gate structure formed on the active area, wherein the gate structure includes a conductive layer; Wherein, a top surface of the conductive layer in the gate structure is higher than a top surface of the conductive layer in the dummy gate structure.

17. The semiconductor structure according to claim 16, wherein: The pseudo gate structure includes a first conductive layer, a third conductive layer and a second conductive layer, the first conductive layer fills the first groove and extends out of the isolation trench, the third conductive layer is formed on the first conductive layer, and the second conductive layer is formed on the third conductive layer; the gate structure includes a first conductive layer, a third conductive layer and a second conductive layer stacked in sequence.

18. The semiconductor structure according to claim 17, wherein: The top surface of the first conductive layer in the gate structure is higher than the top surface of the first conductive layer in the dummy gate structure; the top surface of the third conductive layer in the gate structure is higher than the top surface of the third conductive layer in the dummy gate structure; A top surface of the second conductive layer in the gate structure is higher than a top surface of the second conductive layer in the dummy gate structure.

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