Integrated processing method for synchronously etching groove and through hole
By simultaneously forming high aspect ratio interconnect structures in a single process chamber, the problems of polymer accumulation and sidewall morphology control during trench and via etching are solved, achieving efficient and stable trench and via etching and improving the etching effect.
Patent Information
- Application Number
- CN202510782466.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-11
- Publication Date
- 2025-10-17
AI Technical Summary
Existing technologies suffer from problems such as excessive polymer buildup in the reaction chamber and etching stoppage due to high etching rates during simultaneous etching of trenches and vias. Furthermore, existing process parameters cannot simultaneously protect the copper layer and control the sidewall morphology, resulting in contour collapse.
A method for simultaneously forming high aspect ratio interconnect structures in a single process chamber is adopted, including bottom etching, plasma treatment, enhanced etching steps in the main etching stage, and low-damage residue removal. By adjusting the bias voltage and dynamic pressure regulation, fluorine-containing reactive gas and plasma treatment are used to achieve conformal etching of trenches and vias.
It achieves integrated and efficient etching of trenches and through holes, solving problems such as uncontrolled sidewall roughness, bottom residue and metal layer damage in traditional high aspect ratio processes, and ensuring the stability and accuracy of the etching process.
Smart Images
Figure CN120809673A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor technology, in particular to a trench and via simultaneous etching integrated processing method. BACKGROUND
[0002] The current AIO (All-In-One) process faces two technical bottlenecks when etching trenches and vias simultaneously:
[0003] 1. High etching rate causes excessive polymer accumulation in the reaction chamber, causing etching stop (ET stop)
[0004] 2. Existing process parameters cannot balance copper layer protection and sidewall morphology control. The traditional single-step trench process is particularly prone to profile collapse in multi-component film layer (including PR / BARC / TiN / USG / NDC / Cu) etching.
[0005] To solve the above problems, a new trench and via simultaneous etching integrated processing method is needed. SUMMARY
[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a trench and via simultaneous etching integrated processing method to solve the technical bottleneck problem of trench and via simultaneous etching in the prior art.
[0007] To achieve the above-mentioned purposes and other related purposes, the present application provides a trench and via simultaneous etching integrated processing method for simultaneously forming high aspect ratio interconnection structures in a single process chamber, comprising:
[0008] Step one, performing bottom etching on the composite dielectric layer to establish the basis for conformal etching of trenches and vias;
[0009] Step two, removing etching by-products by plasma treatment;
[0010] Step three, performing main etching stage to simultaneously form trench main structure and via opening;
[0011] Step four, starting the enhanced etching step during the metal layer exposure stage at the bottom of the via, and simultaneously applying enhanced negative bias voltage and dynamic pressure regulation;
[0012] Step five, completing low-damage residue removal.
[0013] Preferably, the composite dielectric layer in step one includes a barrier layer, an intermediate dielectric layer and a hard mask layer formed in sequence on the metal interconnection layer.
[0014] Preferably, the material of the barrier layer in step one is a nitrogen-doped silicon carbide layer.
[0015] Preferably, the material of the intermediate dielectric layer in step one is undoped silicate glass.
[0016] Preferably, the material of the hard mask layer in step one is titanium nitride.
[0017] Preferably, the metal interconnection layer in step one includes various conductive components to connect various IC devices to the integrated circuit, and further includes interlayer dielectric layers to separate and isolate the various conductive components.
[0018] Preferably, the absolute value of the bias voltage in step four is 500-800V.
[0019] Preferably, the dynamic pressure regulation range in step four is 0-100 mTorr.
[0020] Preferably, the etching in step four uses fluorine-containing reaction gas as the ion source.
[0021] Preferably, the fluorine-containing reaction gas in step four includes at least one of CF4, CHF3, and C4F6.
[0022] Preferably, the high aspect ratio interconnection structure satisfies: trench aspect ratio > 60:1, via aspect ratio > 5:1.
[0023] As described above, the integrated trench and via synchronous etching method of the present application has the following beneficial effects:
[0024] The present application can realize integrated efficient etching of trenches and vias, and solve the key problems of uncontrolled sidewall roughness, bottom residue, and metal layer damage in traditional high aspect ratio processes. BRIEF DESCRIPTION OF DRAWINGS
[0025] Figure 1 The figure shows the process flow diagram of the present application;
[0026] Figure 2 The figure shows the etching area defined by photolithography of the present application;
[0027] Figure 3 The figure shows the trench and via synchronous etching morphology of the present application. DETAILED DESCRIPTION
[0028] The embodiments of the present application are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the disclosure. The present application can also be implemented or applied through other different embodiments, and the details in the specification can be modified or changed based on different views and applications without departing from the spirit of the present application.
[0029] Please refer to Figure 1 The present application provides a trench and via simultaneous etching integrated processing method, which synchronously forms high aspect ratio interconnection structure in single process chamber, comprising:
[0030] Step one, bottom etching is performed on the composite dielectric layer to establish the conformal etching basis of trench and via.
[0031] In some embodiments, the composite dielectric layer is formed on the metal interconnection layer, and the composite dielectric layer comprises, from bottom to top, a barrier layer 103, an intermediate dielectric layer 104 and a hard mask layer 105. The barrier layer 103 can be made of nitrogen-doped silicon carbide (NDC) material, which is used to prevent copper diffusion of the metal interconnection layer and improve interface adhesion; the intermediate dielectric layer 104 is made of undoped silicate glass (USG), which gives the structure low dielectric constant characteristics; the hard mask layer 105 is preferably titanium nitride (TiN), which provides high selectivity etching mask. By anisotropic dry etching, a preliminary opening is formed to form a conformal profile of the trench and the via. It should be noted that the composite dielectric layer can also be other known materials in other embodiments, which are not limited here.
[0032] In some embodiments, the metal interconnection layer includes various conductive components 102 to connect various IC devices to an integrated circuit, and the metal interconnection layer also includes an interlayer dielectric layer 101 to separate and isolate various conductive components 102. For example, the conductive components 102 are metal lines, which can include copper, aluminum-copper alloy, other suitable conductive materials, or combinations thereof. The interlayer dielectric layer 101 includes a dielectric material such as silicon oxide, a low-k dielectric material, other suitable dielectric materials, or combinations thereof.
[0033] Step two, etching by-products are removed by plasma treatment.
[0034] In some embodiments, after the bottom etching is completed, an oxygen-containing or hydrogen-containing plasma is introduced to remove the residual polymers and fluorocarbons attached to the sidewall and the bottom. The plasma treatment not only removes the etching by-products, but also repairs the sidewall micro-damage, reducing the defect accumulation in the subsequent process.
[0035] Step three, the main etching stage is performed to simultaneously form the trench main structure and the via opening.
[0036] In some embodiments, a plasma of fluorine-containing reaction gas (such as CF4, C4F6) mixed with inert gas (such as Ar) is used to simultaneously deepen the trench and expand the via opening by adjusting the radio frequency power and the gas ratio. Through the synergistic regulation of chamber pressure and gas distribution, the synchronous growth of the trench and via depth is realized, avoiding local over-etching.
[0037] In some embodiments, during the etching process, the anti-reflective coating 106 and the photoresist layer 107 can be deposited in sequence, and then the photoresist layer 107 is opened by photolithography to define the etching area, forming a structure as shown in Figure 2 .
[0038] Step four, start the enhanced etching step when the metal layer at the bottom of the via is exposed, and apply the enhanced negative bias voltage and dynamic pressure adjustment simultaneously.
[0039] In some embodiments, when the copper metal layer at the bottom of the via is exposed, the negative bias voltage is increased to 500-800V, and the dynamic adjustment of the chamber pressure (0-100 mTorr) is combined. At this time, fluorine-containing gas (such as CF4, CHF3, or C4F6) is introduced, and the ion bombardment energy is enhanced by high bias voltage to promote the reaction of fluorine ions with copper surface oxides; at the same time, the low-pressure environment accelerates the escape of by-products, inhibiting the accumulation of CXFY polymers on the sidewall of the trench. This step significantly reduces the micro-trench effect at the edge of the metal layer and improves the steepness of the sidewall at the bottom of the via through the synergistic effect of high-energy ion bombardment and dynamic gas pumping.
[0040] Step five, complete the low-damage residue removal, forming a structure as shown in Figure 3 .
[0041] In some embodiments, a low-temperature hydrogen plasma or fluorocarbon compound light etching process is used to completely remove residual metal oxides and fluorocarbon polymers, ensuring the cleanliness of high-aspect-ratio structures. The low-damage removal process removes contaminants while avoiding secondary damage to fragile deep-hole structures.
[0042] Further, the aspect ratio of the high-aspect-ratio interconnection structure satisfies: trench aspect ratio > 60:1, via aspect ratio > 5:1.
[0043] It should be noted that the dynamic pressure adjustment is achieved through a feedback control system. When the copper layer exposure signal is detected, the pressure is instantaneously reduced from the standard etching value, and maintained at a stepwise decreasing level in subsequent etching. This dynamic adjustment not only ensures the stability of the plasma density, but also effectively inhibits the attachment of by-products.
[0044] Through the synergistic optimization of the above steps, this method can achieve integrated and efficient etching of trenches and vias, solving key problems such as uncontrolled sidewall roughness, bottom residue, and metal layer damage in traditional high-aspect-ratio processes.
[0045] It should be noted that the diagrams provided in the embodiments only illustrate the basic concepts of the present application in a schematic manner, and only show the components related to the present application in the diagrams, not the number, shape, and size of the components when actually implemented. The actual implementation of each component may be arbitrarily changed in terms of its type, number, and proportion, and the layout pattern of the components may be more complex.
[0046] In summary, the present application can realize integrated high-efficiency etching of the groove and the via, and solve the key problems such as the out-of-control side wall roughness, bottom residue and metal layer damage in the traditional high aspect ratio process. Therefore, the present application effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0047] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.
Claims
1. An integrated processing method for simultaneous etching of trenches and through-holes, which simultaneously forms a high aspect ratio interconnect structure in a single process chamber, characterized in that: At least: Step 1: Perform bottom etching on the composite dielectric layer to establish a conformal etching foundation for the trenches and through-holes; Step 2: removing etching byproducts through plasma treatment; Step 3: Perform the main etching phase to simultaneously form the trench main structure and the through-hole opening; Step 4: starting the enhanced etching step when the metal layer at the bottom of the through hole is exposed, and simultaneously applying an enhanced negative bias voltage and dynamic pressure adjustment; Step 5: Complete the removal of low-damage residue.
2. The integrated processing method for synchronous etching of trenches and through holes according to claim 1, characterized in that: The composite dielectric layer in step 1 includes a barrier layer, an intermediate dielectric layer and a hard mask layer formed sequentially on the metal interconnection layer.
3. The integrated processing method for synchronous etching of trenches and through holes according to claim 2, characterized in that: The material of the barrier layer in step 1 is a nitrogen-doped silicon carbide layer.
4. The integrated processing method for synchronous etching of trenches and through holes according to claim 2, characterized in that: The material of the intermediate dielectric layer in step 1 is undoped silicate glass.
5. The integrated processing method for synchronous etching of trenches and through holes according to claim 2, characterized in that: The material of the hard mask layer in step 1 is titanium nitride.
6. The integrated processing method for synchronous etching of trenches and through holes according to claim 2, characterized in that: The metal interconnection layer in step 1 includes various conductive components to connect various IC devices to the integrated circuit, and the metal interconnection layer also includes an interlayer dielectric layer to separate and isolate the various conductive components.
7. The integrated processing method for synchronous etching of trenches and through holes according to claim 1, characterized in that: The absolute value of the bias voltage in step 4 is 500-800V.
8. The integrated processing method for synchronous etching of trenches and through holes according to claim 1, characterized in that: The dynamic pressure adjustment range in step 4 is 0-100 mTorr.
9. The integrated processing method for synchronous etching of trenches and through holes according to claim 1, characterized in that: The etching in step 4 is performed by introducing a fluorine-containing reaction gas as an ion source.
10. The integrated processing method for synchronous etching of trenches and through holes according to claim 8, characterized in that: The fluorine-containing reaction gas in step 4 includes at least one of CF4, CHF3, and C4F6.
11. The integrated processing method for simultaneous etching of trenches and through holes according to claim 1, characterized in that: The material of the metal layer in step 4 is copper.
12. The integrated processing method for synchronous etching of trenches and through holes according to claim 1, characterized in that: The high aspect ratio interconnect structure satisfies the following requirements: trench aspect ratio>60:1, through hole aspect ratio>5:1.