Preparation method of metal interconnection structure
By performing re-sputtering and graded tantalum deposition processes after the deposition of the tantalum nitride layer, a selectively thinned diffusion barrier layer is formed, which solves the problem of vacancy aggregation in the copper interconnect structure during the electromigration process and improves the anti-electromigration performance and electrical performance.
Patent Information
- Application Number
- CN202510809126.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-17
- Publication Date
- 2025-10-17
AI Technical Summary
During the electromigration process, copper interconnect structures are prone to vacancy aggregation, leading to void formation, which causes circuit failure. The high current density at the through-hole position accelerates failure. Existing technologies make it difficult to effectively improve anti-electromigration performance.
By performing a re-sputtering process after the deposition of the tantalum nitride layer, and performing the tantalum deposition process twice, with re-sputtering after each time, the power difference of the sputtering source is controlled to form a selectively thinned diffusion barrier layer, the thickness of the tantalum layer at the bottom of the through hole is thinned, and the difference in sputtering efficiency of different morphologies is utilized to fill the metal atoms in the vacancies.
The anti-electromigration performance and electrical performance of the metal interconnect structure are improved, the through-hole contact resistance is reduced, and the overall electrical performance is improved.
Smart Images
Figure CN120809677A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a preparation method of a metal interconnection structure. BACKGROUND
[0002] With the improvement of technology nodes and the pursuit of low RC delay, copper interconnection has become a new generation of interconnection technology. However, like the last generation of aluminum interconnection process, copper interconnection process also faces severe reliability tests including electromigration (EM).
[0003] Electromigration can cause stress to change continuously on the interconnection line, thereby causing a large number of vacancies in the metal line, especially in the terminal metal line. On the one hand, these vacancies are usually gathered at the bottom of the via and near the interface, leading to the formation of a cavity, the disconnection of the connection line, and further leading to the failure of the circuit. On the other hand, due to the high current density at the via position, the failure process is further accelerated due to the effects of current accumulation and the poor adhesion of copper and the barrier layer. SUMMARY
[0004] The present application provides a preparation method of a metal interconnection structure, which can improve the electromigration resistance of the whole copper interconnection.
[0005] The present application provides a preparation method of a metal interconnection structure, which comprises: S1: providing a semiconductor structure, a metal interconnection layer is formed in the semiconductor structure, a barrier layer and a low-K dielectric layer are sequentially formed on the semiconductor structure from bottom to top, and the barrier layer covers the semiconductor structure and the metal interconnection layer; S2: etching the low-K dielectric layer and the barrier layer to form a trench and a via, the via is located at the bottom of the trench and communicates with the trench, and the metal interconnection layer at the bottom of the via is exposed; S3: depositing a tantalum nitride layer, the tantalum nitride layer covers the side wall and bottom wall of the trench, the side wall of the via, and the metal interconnection layer exposed from the bottom of the via; S4: performing at least one resputtering process on the tantalum nitride layer; S4: performing at least two tantalum deposition processes, and after each tantalum deposition process, performing a resputtering process, thereby forming a tantalum layer covering the tantalum nitride layer; The tantalum nitride layer and the tantalum layer jointly form a diffusion barrier layer; S5: forming a metal material layer, the metal material layer fills the via and the trench, and is connected with the metal interconnection layer, to obtain a metal interconnection structure.
[0006] In some embodiments, in the step of performing at least one re-sputtering process on the tantalum nitride layer, the input power of the sputtering source when performing the re-sputtering process is 200 W to 1000 W.
[0007] In some embodiments, in the step S4, the input power of the sputtering source when performing the re-sputtering process is 200 W to 1000 W.
[0008] In some embodiments, in the step S4, the input power of the sputtering source used in the re-sputtering process performed later is greater than the input power of the sputtering source used in the re-sputtering process performed earlier.
[0009] In some embodiments, the material of the barrier layer is SiCN.
[0010] In some embodiments, the material of the metal interconnection layer is copper.
[0011] In some embodiments, the material of the metal material layer is copper.
[0012] In some embodiments, in the step S5, the thickness of the tantalum deposited by each tantalum deposition process is the same, and the thickness is in the range of 20 angstroms to 50 angstroms, and the thickness of the tantalum layer finally formed is in the range of 80 angstroms to 130 angstroms.
[0013] The technical scheme of the present application has at least the following advantages: 1. On the one hand, by increasing the re-sputtering process after the deposition of the tantalum nitride, the influence of different morphologies on the re-sputtering efficiency can be utilized, that is, the re-sputtering efficiency is lower for the trenches with relatively vertical four sides, and the re-sputtering efficiency is higher for the through holes with more inclined sidewalls, thereby realizing the selective thinning of the tantalum nitride layer at the bottom of the through hole; on the other hand, by dividing the deposition process of the tantalum layer into at least two tantalum deposition processes, and performing a re-sputtering process after each tantalum deposition process, the selective thinning of the tantalum layer at the bottom of the through hole can be realized, thereby thinning the diffusion barrier layer composed of the tantalum nitride layer and the tantalum layer at the bottom of the through hole, facilitating the diffusion of metal atoms to the vacancies and filling in the vacancies, and improving the electromigration resistance of the metal interconnection structure.
[0014] 2. Due to the thinning of the diffusion barrier layer at the bottom of the through hole, the contact resistance of the through hole is reduced, and the electrical performance of the metal interconnection structure is further improved.
[0015] 3. By setting the input power of the sputtering source used in the re-sputtering process performed later to be greater than the input power of the sputtering source used in the re-sputtering process performed earlier after multiple tantalum deposition processes, a balance between the selective thinning of the bottom tantalum layer and the protection of the sidewall low-K dielectric layer can be achieved. BRIEF DESCRIPTION OF DRAWINGS
[0016] In order to more clearly illustrate the technical solutions in the specific embodiments or the prior art of the present application, the accompanying drawings needed to be used in the description of the specific embodiments or the prior art will be briefly introduced. Obviously, the accompanying drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.
[0017] Figure 1 is a flow chart of a method for preparing a metal interconnection structure provided by an exemplary embodiment of the present application; Figures 2-7 is a schematic diagram of a semiconductor structure in the process steps of the method for preparing a metal interconnection structure provided by an exemplary embodiment of the present application; Figure 8 is a comparison table for the thickness of the diffusion barrier layer obtained before and after using the method provided by an exemplary embodiment of the present application.
[0018] Legend: 1, semiconductor structure; 11, metal interconnection layer; 12, diffusion barrier layer; 2, barrier layer; 3, low-K dielectric layer; 4, trench; 5, via hole; 6, tantalum nitride layer; 7, tantalum layer; 8, metal material layer. DETAILED DESCRIPTION
[0019] The technical solutions in the present application will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort fall within the scope of the present application.
[0020] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.
[0021] In the description of the present application, it should be noted that unless specifically defined and limited otherwise, the terms "mounting", "connection", "connecting" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, or the internal connection of two elements, it can be wireless connection, or wired connection. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0022] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as there is no conflict between them.
[0023] The present application provides a preparation method of metal interconnection structure, referring to Figure 1 The method comprises the following steps: S1: providing a semiconductor structure, a metal interconnection layer is formed in the semiconductor structure, and a barrier layer and a low-K dielectric layer are sequentially formed from bottom to top on the semiconductor structure, the barrier layer covers the semiconductor structure and the metal interconnection layer.
[0024] For example, referring to Figure 2 , there is provided a semiconductor structure 1, a metal interconnection layer 11 is formed in the semiconductor structure 1. A barrier layer 2 and a low-K dielectric layer 3 are sequentially formed from bottom to top on the semiconductor structure 1.
[0025] Further, the material of the metal interconnection layer 11 is copper.
[0026] Further, the material of the barrier layer 2 can be SiCN.
[0027] Further, a diffusion inhibition layer 12 is also formed between the metal interconnection layer 11 and the semiconductor structure 1, which can be a stack of tantalum nitride and tantalum.
[0028] S2: etching the low-K dielectric layer and the barrier layer to form a trench and a via, the via is located at the bottom of the trench and communicates with the trench, and the metal interconnection layer at the bottom of the via is exposed.
[0029] For example, referring to Figure 3 The low-K dielectric layer 3 and the barrier layer 2 can be etched by an integrated etching process to form a connected trench 4 and a via 5. The via 5 is located at the bottom of the trench 4, and the metal interconnection layer 11 at the bottom of the via 5 is exposed. At the same time, the side wall profile of the trench 4 is more vertical, and the side wall profile of the via 5 has higher inclination.
[0030] S3: depositing a tantalum nitride layer, the tantalum nitride layer covers the side wall and bottom wall of the trench, the side wall of the via, and the metal interconnection layer exposed from the bottom of the via.
[0031] For example, referring to Figure 4 The tantalum nitride layer 6 can be deposited on the low-K dielectric layer 3 by a physical vapor deposition process, and covers the sidewalls and bottom wall of the trench 4, the sidewalls of the via 5 and the metal interconnection layer 11 exposed from the bottom of the via 5. The thickness of the tantalum nitride layer can be 20-70 angstroms.
[0032] S4: performing at least one resputtering process on the tantalum nitride layer.
[0033] For example, after the deposition of the tantalum nitride layer 6, at least one resputtering process is performed to thin the tantalum nitride layer 6 in the trench 4 and the via 5. During the resputtering process, the sidewall profile of the trench 4 is more vertical, and the sidewall profile of the via 5 has a higher inclination, so that the resputtering efficiency of the tantalum nitride layer 6 at the bottom of the trench 4 is lower, and the resputtering efficiency of the tantalum nitride layer 6 at the bottom of the via 5 is higher, thereby achieving selective thinning of the tantalum nitride layer 6 at the bottom of the via 5.
[0034] Further, in this step, the input power of the sputtering source during the resputtering process is 200-1000 W. When the resputtering process is set to multiple times, the input power of the sputtering source is appropriately reduced compared to when the resputtering process is performed only once, and is still within the range of 200-1000 W.
[0035] S5: performing at least two tantalum deposition processes, and after each tantalum deposition process, performing one resputtering process, thereby forming a tantalum layer covering the tantalum nitride layer.
[0036] For example, at least two tantalum deposition processes are performed, and after each tantalum deposition process, one resputtering process is performed, and finally a tantalum layer 7 covering the tantalum nitride layer 6 is formed, as shown in Figure 5 The tantalum layer 7 and the tantalum nitride layer 6 together form the diffusion barrier layer 2.
[0037] Further, in this step, the tantalum deposition process can be a physical vapor deposition process.
[0038] Further, the thickness of the tantalum deposited in each tantalum deposition process is the same, and is within the range of 20-50 angstroms, and the thickness of the finally formed tantalum layer 7 is 80-130 angstroms.
[0039] Further, the input power of the sputtering source used in the resputtering process after different tantalum deposition processes is also different, and the input power of the sputtering source used in the later resputtering process is greater than the input power of the sputtering source used in the earlier resputtering process, i.e. the input power of the sputtering source used in the resputtering process is gradually increased.
[0040] Furthermore, in this step, the input power of the sputtering source during the re-sputtering process is 200W to 1000W.
[0041] In this step, by dividing the deposition process of the tantalum layer 7 into at least two tantalum deposition processes, and performing a re-sputtering process after each tantalum deposition process, the tantalum layer 7 at the bottom of the through-hole 5 can be selectively thinned. This further reduces the thickness of the diffusion barrier layer 2 composed of the tantalum nitride layer 6 and the tantalum layer 7 at the bottom of the through-hole 5, facilitating the diffusion of metal atoms into and filling the vacancies, thereby improving the electromigration resistance of the metal interconnect structure. At the same time, by controlling the input power of the sputtering source, a balance can be achieved between the selective thinning of the bottom tantalum layer 7 and the protection of the sidewall low-K dielectric layer 3.
[0042] S6: forming a metal material layer, which fills the through holes and the trenches and is connected to the metal interconnection layer to obtain a metal interconnection structure.
[0043] For example, Figure 6 As shown, a layer of metal material is first deposited to cover the surface of the diffusion barrier layer 2 and fill the trench 4 and the through hole 5. Afterwards, the metal material and the diffusion barrier layer 2 above the surface of the low-K dielectric layer 3 are removed by chemical mechanical polishing. The remaining metal material is formed as shown in FIG. Figure 7 The metal material layer 8 is shown. The metal material layer 8 is connected to the metal interconnection layer 11 at the bottom to form a metal interconnection structure.
[0044] Furthermore, the metal material layer 8 is made of copper.
[0045] The preparation method of the metal interconnect structure provided in the embodiment of the present application, on the one hand, by adding a re-sputtering process after the deposition of tantalum nitride, can utilize the influence of different morphologies on the re-sputtering efficiency, that is, for grooves with relatively vertical sides, the re-sputtering efficiency is lower, and for through-holes with more inclined side walls, the re-sputtering efficiency is higher, thereby achieving selective thinning of the tantalum nitride layer at the bottom of the through-hole; on the other hand, by dividing the deposition process of the tantalum layer into at least two tantalum deposition processes, and performing a re-sputtering process after each tantalum deposition process, it is possible to achieve selective thinning of the tantalum layer at the bottom of the through-hole, thereby thinning the thickness of the diffusion barrier layer composed of the tantalum nitride layer and the tantalum layer at the bottom of the through-hole, making it easier for metal atoms to diffuse into and fill the vacancies, thereby improving the anti-electromigration performance of the metal interconnect structure. In the formation process of the tantalum layer, the input power of the sputtering source used in the subsequent re-sputtering process is set to be greater than the input power of the sputtering source used in the previous re-sputtering process, so as to achieve a balance between the selective thinning of the bottom tantalum layer and the protection of the low-K dielectric layer on the sidewalls. As Figure 8As shown, the thickness of the diffusion barrier layer at the bottom of the trench and the bottom of the via before and after using the method is compared. It can be found that the thickness reduction of the diffusion barrier layer at the bottom of the trench is significantly lower than that of the diffusion barrier layer at the bottom of the via. At the same time, due to the thickness reduction of the diffusion barrier layer at the bottom of the via, the contact resistance of the via is reduced, further improving the electrical performance of the metal interconnection structure.
[0046] Obviously, the above embodiments are only examples for clearly illustrating, but not limitation to the embodiments. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, all the embodiments are not required to be exhausted, and the obvious changes or variations derived therefrom are still within the protection scope of the present application.
Claims
1. A method for preparing a metal interconnect structure, characterized in that: include: S1: providing a semiconductor structure, wherein a metal interconnection layer is formed in the semiconductor structure, and a barrier layer and a low-K dielectric layer are sequentially formed on the semiconductor structure from bottom to top, wherein the barrier layer covers the semiconductor structure and the metal interconnection layer; S2: etching the low-K dielectric layer and the barrier layer to form a trench and a through hole, wherein the through hole is located at the bottom of the trench and communicates with the trench, and the metal interconnection layer at the bottom of the through hole is exposed; S3: depositing a tantalum nitride layer, wherein the tantalum nitride layer covers the sidewalls and bottom wall of the trench, the sidewalls of the through hole, and the metal interconnection layer exposed from the bottom of the through hole; S4: performing at least one re-sputtering process on the tantalum nitride layer; S5: performing at least two tantalum deposition processes, and performing a re-sputtering process after each tantalum deposition process, thereby forming a tantalum layer covering the tantalum nitride layer; The tantalum nitride layer and the tantalum layer together form a diffusion barrier layer; S6: forming a metal material layer, wherein the metal material layer fills the through hole and the trench and is connected to the metal interconnection layer to obtain a metal interconnection structure.
2. The method for preparing a metal interconnect structure according to claim 1, wherein: In the step of performing at least one re-sputtering process on the tantalum nitride layer, the input power of the sputtering source during the re-sputtering process is 200W to 1000W.
3. The method for preparing a metal interconnect structure according to claim 1, wherein: In step S4, the input power of the sputtering source during the re-sputtering process is 200W to 1000W.
4. The method for preparing a metal interconnect structure according to claim 3, wherein: In the step S4 , the input power of the sputtering source used in the subsequent re-sputtering process is greater than the input power of the sputtering source used in the previous re-sputtering process.
5. The method for preparing a metal interconnect structure according to claim 1, wherein: The barrier layer is made of SiCN.
6. The method for preparing a metal interconnect structure according to claim 1, wherein: The metal interconnection layer is made of copper.
7. The method for preparing a metal interconnect structure according to claim 1, wherein: The material of the metal material layer is copper.
8. The method for preparing a metal interconnect structure according to claim 1, wherein: In step S5 , the thickness of the tantalum deposited in each tantalum deposition process is the same and is within a range of 20 angstroms to 50 angstroms. The thickness of the tantalum layer finally formed is 80 angstroms to 130 angstroms.