Method for improving interlayer copper cavity
By adjusting the pattern load of AIO etching and performing multi-step etching processes during semiconductor manufacturing, the problem of copper void formation in the interlayer was solved, ensuring the integrity of the copper layer and the stability of the process.
Patent Information
- Application Number
- CN202511232184.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-29
- Publication Date
- 2025-10-17
AI Technical Summary
In the prior art, copper void defects in the interlayer are formed in the next layer process, mainly due to electrochemical reactions caused by charge accumulation after AIO etching, especially Cu diffusion and charge accumulation in the sealing ring region, which leads to the generation of copper voids.
By forming a first etch stop layer and an interlayer film on the underlying structure, and adjusting the pattern load during AIO etching, the first etch stop layer at the bottom of the widest trench is prevented from being etched through, thus avoiding charge accumulation. The first etch stop layer is then removed by a second etching process, including wet and dry etching, to prevent electrochemical reactions.
This effectively prevents the underlying copper layer from being consumed in subsequent processes, avoids the formation of copper voids, and ensures the integrity of the copper layer and the stability of the process.
Smart Images
Figure CN120809681A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a semiconductor integrated circuit manufacturing method, in particular to a method for improving barrier copper voids. BACKGROUND
[0002] Barrier voids are defects that are clean when the on-site CMP is scanned for defects, but appear only when the next layer CMP is scanned for defects. In order to trace the barrier voids to the process step where they first appeared, defects are scanned after each station to determine the source of the defects. It is found that barrier voids do not appear after film deposition (Dep), but appear after all-in-one (AIO) etching of the next layer. Subsequent scanning of defects at the AIO etching station finds Cu diffuse defects in the seal ring area. FIG. 1A As shown in FIG. 1, the copper diffuse defects are generated after the AIO etching is completed after the normal CMP of the underlying copper layer. FIG. 1A The defect 101 in FIG. 1 is a copper diffuse defect.
[0003] The design of the seal ring is metal 0.5 μm & via bar 0.1 μm, where metal 0.5 μm represents the width of the metal line as 0.5 μm, and via bar 0.1 μm represents the width of the via as 0.1 μm. It is also seen that the defects are mainly concentrated in the edge area of the wafer. FIB shows that the underlying metal Cu is almost hollowed out, and the composition of the defect 101 in FIG. 1 is mainly Cu & Co. FIG. 1A
[0004] The AIO etch by-product is rich in the large-line-width seal ring area. The large-line-width seal ring area causes the AIO etch to etch through the etch stop layer due to the pattern loading effect. The etch stop layer usually includes an aluminum nitride layer (AlN), an oxygen-doped silicon carbide layer (ODC), and an aluminum oxide layer (AlO) stacked in sequence. After the AIO etching is completed, ALO wet etching (Wet clean) is required to remove the aluminum oxide layer, also known as ALO RM. In the existing method, Cu diffuse occurs during the ALO RM process. Therefore, it is suspected that the exposed Cu in the seal ring area undergoes an electrochemical reaction during the ALO RM to cause the Cu diffuse.
[0005] At the same time, the AIO Etch station will open the entire barrier layer under the Seal Ring area, and the Seal Ring will be connected to the silicon substrate through the M0 & V0 & silicon ridge, M0 represents the zero layer metal layer, V0 represents the zero layer via, which will cause the charge generated by the AIO Etch station to accumulate to the silicon substrate, and then connected to the Metal wire through the device above, the charge accumulates in the metal wire, and then the Wet Clean will cause an electrochemical reaction, and then a Void will be generated, and the charge is more likely to accumulate on the wide line. FIG. 1B As shown in the prior art, the copper layer CMP is normal, and the copper cavity defect of the barrier layer is generated after the subsequent AIO etching is completed; FIG. 1B In the copper layer 102, there is a cavity defect shown by a mark 105, the cavity defect appears at the bottom of the via opening, and the top of the via opening is a trench, FIG. 1B In the copper layer 102, there is a cavity defect shown by a mark 105, the cavity defect appears at the bottom of the via opening, and the top of the via opening is a trench,
[0006] As shown in the prior art, the copper layer CMP is normal, and the copper cavity defect of the barrier layer is generated after the subsequent AIO etching is completed; FIG. 1C As shown in the prior art, the copper layer CMP is normal, and the copper cavity defect of the barrier layer is generated after the subsequent AIO etching is completed; a first etching stop layer 203 is formed on a semiconductor substrate with a bottom layer interlayer film 201 and a bottom layer copper layer 202, the first etching stop layer 203 includes an aluminum nitride layer 203a, an oxygen-doped silicon carbide layer 203b and an aluminum oxide layer 203c which are stacked in sequence.
[0007] A bottom silicon oxide layer 204, an interlayer film 205, a nitrogen-doped silicon carbide (NDC) 206 and a nitrogen-free anti-reflective coating (NFDARC) 207 are sequentially formed on the first etching stop layer 203.
[0008] The AIO etching will etch and form the trench and the via opening after defining the formation area of the trench and the formation area of the via opening, and the hard mask layer defining the via opening is removed at the same time. However, in the prior art, since the width of the trench is different in different areas, for example, the width of the trench in the seal ring area is relatively large, so after the AIO etching is completed, the first etching stop layer 203 is easily etched through in the seal ring area, FIG. 1CIn the embodiment, the cross-sectional structure of the area where the first etching stop layer 203 is etched through is shown. After the first etching stop layer 203 is etched through, electric charges 208 are easily accumulated in the bottom copper layer 202. However, since the first etching stop layer 203 in most areas is still retained, after the AIO etching, a step of removing the first etching stop layer 203 is needed. The removal of the first etching stop layer 203 includes sequentially removing the aluminum oxide layer 203c, the oxygen-doped silicon carbide layer 203b and the aluminum nitride layer 203a. The removal of the aluminum oxide layer 203c uses wet etching. Under the action of the electric charges 208 accumulated in the bottom copper layer 202, an electrochemical reaction shown by the mark 210 occurs, thereby generating copper cavities. SUMMARY
[0009] The technical problem to be solved by the present application is to provide a method for improving the barrier layer copper cavity, which can improve the defect that the copper layer is consumed in the next process to form a copper cavity.
[0010] To solve the above technical problem, the method for improving the barrier layer copper cavity provided by the present application comprises the following steps:
[0011] A bottom structure is provided, which has a bottom copper layer formed thereon and the CMP of the bottom copper layer is completed.
[0012] A first etching stop layer and an interlayer film are formed on the bottom structure.
[0013] An AIO etching is performed to simultaneously form a via opening and a trench in the interlayer film, the via opening is located at the bottom of the trench in some areas; the AIO etching stops on the top surface of the first etching stop layer, the first etching stop layer at the bottom of the via opening is exposed after the AIO etching is completed; the trench has multiple widths, the pattern load of the AIO etching is adjusted to ensure that the first etching stop layer at the bottom of the via opening at the bottom of the trench with the largest width is not etched through, and thereby the electric charges generated in the AIO etching are prevented from being accumulated to the surface of the bottom copper layer.
[0014] A second etching process is performed to remove the first etching stop layer exposed at the bottom of each via opening.
[0015] Further improvement is that the first etching stop layer comprises an aluminum nitride layer, an oxygen-doped silicon carbide layer and an aluminum oxide layer which are sequentially stacked.
[0016] Further improvement is that the second etching process sequentially etches the aluminum oxide layer, the oxygen-doped silicon carbide layer and the aluminum nitride layer.
[0017] Further improvement is that the second etching process comprises a first wet etching, and the first wet etching is used to remove the aluminum oxide layer.
[0018] Further improvement is that the second etching process further includes a second dry etching for removing the oxygen-doped silicon carbide layer.
[0019] Further improvement is that the second etching process further includes a third wet etching for removing the aluminum nitride layer.
[0020] Further improvement is that the interlayer film includes a low dielectric constant layer.
[0021] Further improvement is that a bottom silicon oxide layer is further formed between the aluminum oxide layer and the low dielectric constant layer.
[0022] Further improvement is that the bottom silicon oxide layer is formed by a PECVD process and the silicon source is TEOS.
[0023] Further improvement is that a nitrogen-doped silicon carbide and a nitrogen-free anti-reflective coating are further formed on the top of the low dielectric constant layer.
[0024] Further improvement is that before the AIO etching, the following is further included:
[0025] A metal hard mask layer is formed on the surface of the nitrogen-free anti-reflective coating.
[0026] The metal hard mask layer is patterned and etched to open a trench formation area.
[0027] A via hard mask layer is formed.
[0028] The via hard mask layer is patterned and etched to open a via opening formation area.
[0029] Further improvement is that the via hard mask layer is removed in the AIO etching.
[0030] Further improvement is that the material of the metal hard mask layer includes TiN.
[0031] Further improvement is that the trenches are formed in both a chip area and a seal ring area, the seal ring area is located on the periphery of the chip area, and the width of the trenches in the seal ring area is greater than the width of the trenches in the chip area.
[0032] Further improvement is that the bottom structure includes a semiconductor substrate on which a semiconductor device is formed, and the bottom copper layer is separated from the semiconductor substrate by a bottom interlayer film.
[0033] The present application is to improve the copper diffusion defect of the bottom copper layer after the CMP process of the bottom copper layer is completed, and the subsequent process is carried out under the condition that the bottom copper layer after the CMP process has no copper cavity defect, and the copper layer of the previous layer is realized by using the dual damascene process in the subsequent process, wherein the through hole opening and the trench are formed at the same time by using the AIO etching in the dual damascene process, wherein the trench is used to fill the copper layer and form the copper line, and the through hole opening is used to fill the copper layer to form the through hole. Since the widths of the copper lines in different regions are different, the trench has a plurality of different widths, the present application adjusts the pattern load of the AIO etching, so that the first etching stop layer at the bottom of the through hole with the maximum width is not etched through, so that the surface of the bottom copper layer at the bottom of the through hole in each region is not exposed, and therefore the electric charge generated in the AIO etching is not accumulated on the surface of the bottom copper layer. In the second etching process for removing the first etching stop layer, the bottom copper layer is not damaged, for example, the electrochemical reaction of etching copper is not generated in the wet etching process for removing the aluminum oxide layer, so that the copper cavity is not generated at last. Therefore, the present application can improve the defect that the copper layer is consumed in the next layer process to form the copper cavity. BRIEF DESCRIPTION OF DRAWINGS
[0034] The present application will be further described in detail below in combination with the drawings and specific embodiments:
[0035] FIG. 1A is the copper diffusion defect generated after the subsequent AIO etching is completed after the normal CMP of the existing bottom copper layer;
[0036] FIG. 1B is the barrier copper cavity defect generated after the subsequent AIO etching is completed after the normal CMP of the existing bottom copper layer;
[0037] FIG. 1C is the device structure diagram when the barrier copper cavity is generated after the subsequent AIO etching is completed after the normal CMP of the existing bottom copper layer;
[0038] FIG. 2 is the flowchart of the method for improving the barrier copper cavity according to the embodiment of the present application;
[0039] FIGS. 3A-3B is the device structure diagram in each step of the method for improving the barrier copper cavity according to the embodiment of the present application. DETAILED DESCRIPTION
[0040] As shown in FIG. 2 , it is the flowchart of the method for improving the barrier copper cavity according to the embodiment of the present application; as shown in FIGS. 3A-3B , it is the device structure diagram in each step of the method for improving the barrier copper cavity according to the embodiment of the present application; the method for improving the barrier copper cavity according to the embodiment of the present application comprises the following steps:
[0041] Step S101, as shown in FIG. 3AAs shown, a bottom structure is provided, and a bottom copper layer 202 is formed on the bottom structure and CMP is performed on the bottom copper layer 202.
[0042] In the embodiment of the present application, the bottom structure includes a semiconductor substrate (not shown) on which a semiconductor device is formed; and the bottom copper layer 202 is formed on the semiconductor substrate and is separated from the bottom copper layer 202 by a bottom interlayer film 201.
[0043] In step S102, as shown in FIG. 2, a first etching stop layer 203 and an interlayer film 205 are formed on the bottom structure. FIG. 3A
[0044] In the embodiment of the present application, the first etching stop layer 203 includes an aluminum nitride layer 203a, an oxygen-doped silicon carbide layer 203b and an aluminum oxide layer 203c which are sequentially stacked.
[0045] In the embodiment of the present application, the interlayer film 205 includes a low dielectric constant layer. In the field of semiconductor manufacturing, the low dielectric constant layer generally refers to a dielectric layer whose dielectric constant is lower than that of silicon oxide. In some preferred embodiments, the interlayer film 205 uses an ultra low dielectric constant (ULK) material, and in some embodiments, the ULK can use black diamond (BD) whose constituent elements include silicon, oxygen, carbon and hydrogen, i.e. SiOCH material.
[0046] A bottom silicon oxide layer 204 is further formed between the aluminum oxide layer 203c and the low dielectric constant layer.
[0047] The bottom silicon oxide layer 204 is formed by PECVD process and uses TEOS as silicon source, i.e. the bottom silicon oxide layer 204 is a TEOS oxide layer.
[0048] A nitrogen-doped silicon carbide layer 206 and a nitrogen-free anti-reflective coating layer 207 are further formed on the top of the low dielectric constant layer.
[0049] In step S103, as shown in FIG. 3, AIO etching is performed to simultaneously form a via opening 302 and a trench 301 in the interlayer film 205, and the via opening 302 is located at the bottom of the trench 301 in a partial region. FIG. 3A FIG. 3A In the embodiment of the present application, only the cross-sectional view of the formation region of the via opening 302 is shown, and therefore the via opening 302 and the trench 301 are connected together in up and down directions.
[0050] The AIO etching stops on the top surface of the first etching stop layer 203, and the first etching stop layer 203 at the bottom of the via opening 302 is exposed after the AIO etching is completed; the trench 301 has multiple widths, and the pattern load of the AIO etching is adjusted to ensure that the first etching stop layer 203 at the bottom of the via opening 302 at the bottom of the trench 301 with the largest width is not etched through, and thereby preventing the charges generated in the AIO etching from accumulating to the surface of the bottom copper layer 202.
[0051] In the embodiments of the present application, the following steps are further included before the AIO etching is performed:
[0052] A metal hard mask layer (not shown) is formed on the surface of the nitrogen-free anti-reflective coating 207.
[0053] The metal hard mask layer is patterned and etched to open the trench 301 formation area.
[0054] A via hard mask layer is formed.
[0055] The via hard mask layer is patterned and etched to open the via opening 302 formation area.
[0056] After the trench 301 formation area and the via opening 302 formation area are both opened, the AIO etching is performed to simultaneously form the trench 301 and the via opening 302. The via hard mask layer is removed in the AIO etching.
[0057] In some embodiments, the material of the metal hard mask layer includes TiN. The via hard mask layer includes an oxidation layer, an oxygen-doped silicon carbide layer, and an oxidation layer which are sequentially stacked.
[0058] In the embodiments of the present application, the trench 301 is formed in the chip area and the sealing ring area, the sealing ring area is located on the periphery of the chip area, and the width of the trench 301 in the sealing ring area is greater than the width of the trench 301 in the chip area. The sealing ring area forms multiple metal layers and vias connecting between the metal layers, so as to form a sealing ring on the periphery of the chip area to prevent the adverse effects of water vapor on the chip area. Generally, the pattern of the metal layer in the sealing ring, such as the width of the copper line, is large, so the width of the trench 301 in the sealing ring area is also large, and when the first etching stop layer 203 in the sealing ring area is not etched through, the first etching stop layer 203 in each area is generally not etched through.
[0059] Step S104, as shown in FIG. 3B The second etching process is performed to remove the first etching stop layer 203 exposed at the bottom of each via opening 302.
[0060] In the embodiment of the present application, the second etching process is sequentially performed on the aluminum oxide layer 203c, the oxygen-doped silicon carbide layer 203b and the aluminum nitride layer 203a.
[0061] The second etching process adopts a wet etching, a dry etching and a wet etching, including a first wet etching, a second dry etching and a third wet etching. The first wet etching is used to remove the aluminum oxide layer 203c. The second dry etching is used to remove the oxygen-doped silicon carbide layer 203b. The third wet etching is used to remove the aluminum nitride layer 203a.
[0062] and FIG. 1C It can be seen that, in the embodiment of the present application, FIG. 3B In the first wet etching, the bottom copper layer 202 does not accumulate electric charges, so the electrochemical reaction that causes the bottom copper layer 202 to be consumed does not occur, and thus no void defects are generated in the bottom copper layer 202, i.e., no barrier voids are generated.
[0063] After the trench 301 and the via opening 302 are formed, copper electroplating is subsequently performed to simultaneously form a via in the via opening 302 and a copper line in the trench 301.
[0064] In the embodiment of the present application, after the CMP of the bottom copper layer 202 is completed, subsequent processes are performed under the condition that the bottom copper layer 202 after the CMP has no copper void defects. In the subsequent processes, the copper layer of the previous layer is realized by a double damascene process. In the double damascene process, the AIO etching is used to simultaneously form the via opening 302 and the trench 301. The trench 301 is used to fill the copper layer and form a copper line, and the via opening 302 is used to fill the copper layer and form a via. Since the widths of the copper lines in different regions are different, the trench 301 has a plurality of different widths. The pattern load of the AIO etching is adjusted in the embodiment of the present application, so that the first etching stop layer 203 at the bottom of the via at the bottom of the widest trench 301 is not etched through. In this way, the surface of the bottom copper layer 202 at the bottom of the via in each region is not exposed, and thus the electric charges generated in the AIO etching do not accumulate on the surface of the bottom copper layer 202. In the second etching process for removing the first etching stop layer 203, the bottom copper layer 202 is not consumed, for example, the electrochemical reaction that causes the copper to be corroded does not occur in the wet etching for removing the aluminum oxide layer 203c, and thus no copper voids are generated. Therefore, the embodiment of the present application can improve the defect that the copper layer is consumed in the next layer process and forms a copper void.
[0065] The application is described in detail above with specific examples, but these do not constitute a limitation on the application. Those skilled in the art can make many modifications and improvements without departing from the principles of the application, and these should be considered as within the scope of the application.
Claims
1. A method for improving interlayer copper voids, characterized in that: The steps include: Providing an underlying structure, on which an underlying copper layer is formed and a CMP of the underlying copper layer is performed; forming a first etch stop layer and an interlayer film on the underlying structure; AIO etching is performed to simultaneously form a through-hole opening and a trench in the interlayer film, wherein the through-hole opening is located at the bottom of the trench in a partial area; the AIO etching stops on the top surface of the first etch-stop layer, and after the AIO etching is completed, the first etch-stop layer at the bottom of the through-hole opening is exposed; the trenches have various widths, and the pattern load of the AIO etching is adjusted to ensure that the first etch-stop layer at the bottom of the through-hole opening at the bottom of the trench with the largest width is not etched through, thereby preventing charges generated during the AIO etching from accumulating on the surface of the underlying copper layer; A second etching process is performed to remove the first etch stop layer exposed at the bottom of each through hole opening.
2. The method for improving interlayer copper voids according to claim 1, wherein: The first etch stop layer includes an aluminum nitride layer, an oxygen-doped silicon carbide layer and an aluminum oxide layer stacked in sequence.
3. The method for improving interlayer copper voids according to claim 2, wherein: The second etching process etches the aluminum oxide layer, the oxygen-doped silicon carbide layer, and the aluminum nitride layer in sequence.
4. The method for improving interlayer copper voids according to claim 3, wherein: The second etching process includes a first wet etching process, and the first wet etching process is used to remove the aluminum oxide layer.
5. The method for improving interlayer copper voids according to claim 4, wherein: The second etching process further includes a second dry etching, and the second dry etching is used to remove the oxygen-doped silicon carbide layer.
6. The method for improving interlayer copper voids according to claim 5, wherein: The second etching process further includes a third wet etching, and the third wet etching is used to remove the aluminum nitride layer.
7. The method for improving interlayer copper voids according to claim 3, wherein: The interlayer film includes a low dielectric constant layer.
8. The method for improving interlayer copper voids according to claim 7, wherein: A bottom silicon oxide layer is formed between the aluminum oxide layer and the low dielectric constant layer.
9. The method for improving interlayer copper voids according to claim 8, wherein: The bottom silicon oxide layer is formed by using a PECVD process and a silicon source is TEOS.
10. The method for improving interlayer copper voids according to claim 7, wherein: Nitrogen-doped silicon carbide and a nitrogen-free anti-reflection coating are also formed on top of the low dielectric constant layer.
11. The method for improving interlayer copper voids according to claim 10, wherein: Before performing the AIO etching, the following steps are also included: forming a metal hard mask layer on the surface of the nitrogen-free anti-reflective coating; performing patterned etching on the metal hard mask layer to open a trench forming area; forming a through-hole hard mask layer; The through-hole hard mask layer is pattern-etched to open a through-hole opening forming area.
12. The method for improving interlayer copper voids according to claim 11, wherein: The through hole hard mask layer is removed during the AIO etching.
13. The method for improving interlayer copper voids according to claim 11, wherein: The material of the metal hard mask layer includes TiN.
14. The method for improving interlayer copper voids according to claim 11, wherein: The trench is formed in both the chip area and the seal ring area. The seal ring area is located at the peripheral side of the chip area. The width of the trench in the seal ring area is greater than the width of the trench in the chip area.
15. The method for improving interlayer copper voids according to claim 1, wherein: The bottom structure includes a semiconductor substrate, on which a semiconductor device is formed; the bottom copper layer is formed on the semiconductor substrate, and a bottom interlayer film is formed between the bottom copper layers.