Semiconductor structure, forming method, device and electronic device
By forming a protective layer in the non-pad area of the pad metal layer and forming a bump structure and a stress dispersion layer in the pad area, the problem of easy cracking of low dielectric constant materials is solved, the reliability and yield of integrated circuits are improved, and the manufacturing cost is reduced.
Patent Information
- Application Number
- CN202410424766.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-09
- Publication Date
- 2025-10-17
AI Technical Summary
In integrated circuits, low-k dielectric materials have poor mechanical properties and are prone to cracking when stress distribution is uneven, resulting in a decrease in yield.
A protective layer is formed in the non-pad area of the pad metal layer, and a bump structure and a stress dispersion layer are formed in the pad area, so that the bump structure is exposed on the surface of the stress dispersion layer to disperse stress and avoid stress concentration leading to dielectric layer rupture.
By dispersing stress, the reliability and yield of the semiconductor structure are improved, and the manufacturing cost of the integrated circuit is reduced.
Smart Images
Figure CN120809701A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, and in particular, to a semiconductor structure, a forming method, a device and an electronic device. BACKGROUND
[0002] With the improvement of the integration of integrated circuits (IC), the interconnection becomes more and more complex, and the multi-layer interconnection gradually replaces the single-layer interconnection. For the multi-layer interconnection, parasitic capacitance is generated between different interconnection layers. At present, in order to reduce the parasitic capacitance between the interconnection layers, a low dielectric constant (Low-k) or ultra low dielectric constant (Ultra Low-k) material is usually used as the dielectric layer material between the interconnections.
[0003] However, the low dielectric constant material such as germanium silicon carbon usually has poor mechanical properties. When the stress distribution in the integrated circuit is uneven, it is easy to crack, thereby causing the failure of the integrated circuit and leading to the decrease of the yield. SUMMARY
[0004] In order to solve the above technical problems, the present application provides a semiconductor structure, a forming method, a device and an electronic device.
[0005] In a first aspect, the embodiments of the present application disclose a semiconductor structure, comprising: a substrate structure, a pad metal layer, a bump structure, a protective layer and a stress dispersion layer;
[0006] The dielectric layer is formed in the substrate structure.
[0007] The pad metal layer is formed on the substrate structure.
[0008] The pad metal layer comprises a pad region and a non-pad region, the bump structure is formed on the pad region of the pad metal layer, and the protective layer is formed on the non-pad region of the pad metal layer.
[0009] The stress dispersion layer is formed on the protective layer.
[0010] The bump structure exposes the surface of the stress dispersion layer.
[0011] In a second aspect, the embodiments of the present application disclose a forming method of a semiconductor structure, comprising:
[0012] An initial semiconductor structure is provided, the initial semiconductor structure comprising a substrate structure, a pad metal layer and a protective layer; the dielectric layer is formed in the substrate structure; the pad metal layer is formed on the substrate structure; the pad metal layer comprises a pad region and a non-pad region, the protective layer is formed on the non-pad region of the pad metal layer, and the pad region of the pad metal layer exposes the surface of the protective layer;
[0013] Form a bump structure on the pad area, and form a stress dispersion layer on the protection layer to obtain the semiconductor structure; wherein the bump structure exposes the surface of the stress dispersion layer.
[0014] In a third aspect, the embodiments of the present application disclose a memory device, the memory device comprising the semiconductor structure as described above.
[0015] In a fourth aspect, the embodiments of the present application disclose an electronic device, the electronic device comprising the memory device as described above.
[0016] The above technical solutions have the following technical effects:
[0017] The semiconductor structure, the forming method, the device and the electronic device provided by the embodiments of the present application can reduce the parasitic capacitance in the base structure, thereby improving the performance of the semiconductor structure; the protection layer formed on the non-pad area of the pad metal layer can protect the semiconductor structure, thereby improving the reliability of the semiconductor structure; the bump structure formed on the pad area of the pad metal layer and the stress dispersion layer formed on the protection layer, and the bump structure exposing the surface of the stress dispersion layer can make the stress dispersion layer disperse the stress generated by the bump structure, avoid stress concentration from causing the dielectric layer to break, thereby improving the yield of the integrated circuit and reducing the manufacturing cost of the integrated circuit. BRIEF DESCRIPTION OF DRAWINGS
[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, and the advantages thereof, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative effort.
[0019] Figure 1 is a structural schematic diagram of a semiconductor structure provided by the embodiments of the present application;
[0020] Figure 2 is a flowchart of a forming method of a semiconductor structure provided by the embodiments of the present application;
[0021] Figures 3-11 is a structural schematic diagram of a semiconductor structure forming process provided by the embodiments of the present application.
[0022] The following is a supplementary description of the drawings:
[0023] 10 - base structure; 110 - base; 120 - wiring structure; 121 - first wiring layer; 122 - dielectric layer; 123 - second wiring layer; 20 - first isolation layer; 30 - pad metal layer; 40 - second isolation layer; 50 - protection layer; 60 - buffer layer; 70 - stress dispersion layer; 80 - bump structure; 810 - first metal layer; 820 - second metal layer; 830 - solder layer; 90 - mask. DETAILED DESCRIPTION
[0024] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.
[0025] It should be noted that the "one embodiment" or "an embodiment" in the specification of the embodiments of the present application means that a specific feature, structure or characteristic can be included in at least one implementation of the present application. It should be understood that in the specification and claims of the embodiments of the present application and the above drawings, the terms "upper", "lower", "top", "bottom", etc. indicate the orientation or positional relationship shown in the drawings, and are only used for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. The terms "first", "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features limited by "first", "second" can explicitly or implicitly include one or more of the features. Moreover, the terms "first", "second", etc. are used to distinguish similar objects, and do not necessarily describe a particular order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, in the description of the embodiments, the meaning of "a plurality of" is two or more, unless otherwise specified. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system or product including a series of steps or units does not necessarily limit to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to the process, method, product or device.
[0026] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application are further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the embodiments of the present application and not to limit the embodiments of the present application.
[0027] With the increasing of flip chip size and package size, and the increasing of advanced process requirement for integrated circuit device performance, copper bump is an inevitable choice for large chip of advanced process. Copper bump is used to realize the connection between chip and substrate in the process of integrated circuit packaging. Copper bump has superior electrical performance, thermal performance and reliability. However, copper bump has large stress, especially the copper bump at the corner position of the chip has large tensile stress in the packaging process, which is particularly prone to cause the rupture of low dielectric constant material layer in the chip.
[0028] Therefore, the embodiments of the present application provide a semiconductor structure, a forming method, a device and an electronic device. By forming a dielectric layer 122 in the base structure 10, the parasitic capacitance in the base structure 10 can be reduced, thereby improving the performance of the semiconductor structure. By forming a protection layer 50 in the non-pad area of the pad metal layer 30, the semiconductor structure can be protected, thereby improving the reliability of the semiconductor structure. By forming a bump structure 80 in the pad area of the pad metal layer 30 and a stress dispersion layer 70 on the protection layer 50, and exposing the surface of the stress dispersion layer 70 to the bump structure 80, the stress dispersion layer 70 can disperse the stress generated by the bump structure 80, thereby avoiding stress concentration and causing the dielectric layer 122 to rupture, thereby improving the yield of integrated circuits and reducing the manufacturing cost of integrated circuits.
[0029] Please refer to Figure 1 , Figure 1 is a structure diagram of a semiconductor structure provided by the embodiments of the present application. As Figure 1 shown, the semiconductor structure includes a base structure 10, a pad metal layer 30, a bump structure 80, a protection layer 50 and a stress dispersion layer 70.
[0030] In the embodiments of the present application, the base structure 10 includes a base 110 and a wire structure 120. The base 110 has a semiconductor device formed therein. Optionally, the semiconductor device formed in the base 110 can be an active device or a passive device. The base 110 can be obtained by processing a semiconductor wafer. Optionally, the semiconductor wafer includes but is not limited to a silicon wafer, a silicon-on-insulator wafer, etc. Optionally, the process for processing the semiconductor wafer includes but is not limited to oxidation, photolithography, etching, thin film deposition, etc.
[0031] The connection structure 120 is formed on the surface of the substrate 110. In an integrated circuit, the connection structure 120 is used to connect various semiconductor devices in the substrate 110, so as to realize the functions of the integrated circuit. Specifically, the functions realized by the connection structure 120 include but are not limited to signal transmission, power and ground connection, device interconnection, signal isolation, layout and wiring, etc. In order to realize the above functions, the connection structure can generally include two or more connection layers. Optionally, the material of the connection layer is at least one of aluminum, nickel, copper, tungsten, titanium, silver, gold, etc. Optionally, the materials of different connection layers can be the same or different.
[0032] Since the capacitance is generated between different connection layers, which increases the power consumption and signal delay of the circuit, in order to eliminate the adverse effects, the two adjacent connection layers can be separated by a dielectric layer 122. The dielectric layer 122 is usually formed of a low dielectric constant or ultra-low dielectric constant material, such as silicon oxide, silicon nitride, germanium silicon carbon, etc.
[0033] As an example, the connection structure 120 can include a first connection layer 121, a second connection layer 123 and a dielectric layer 122. The first connection layer 121 is formed on the substrate 110, the dielectric layer 122 is formed on the first connection layer 121, and the second connection layer 123 is formed on the dielectric layer 122. The materials of the first connection layer 121 and the second connection layer 123 are both copper.
[0034] In the embodiment of the present application, a pad metal layer 30 is further formed on the connection structure 120. The pad metal layer 30 is used to form a pad, so as to realize the connection with an external circuit such as a printed circuit board, etc. Optionally, the material of the pad metal layer 30 is at least one of aluminum, nickel, copper, tungsten, titanium, silver, gold, etc., such as aluminum which is a metal with lower use cost. The pad metal layer 30 needs to be separated from the connection layers in the connection structure. Specifically, an isolation layer is formed on the connection layers in the connection structure, and the pad metal layer 30 is formed on the isolation layer. As an example, in the case that the uppermost connection layer in the connection structure is the second connection layer 123, a first isolation layer 20 is further formed on the second connection layer 123. Optionally, the material of the first isolation layer 20 is at least one of silicon oxide, silicon nitride, aluminum oxide, etc.
[0035] The pad metal layer 30 includes a pad region and a non-pad region. The pad region is used to form the bump structure 80. The bump structure 80 includes a first metal layer 810, a second metal layer 820 and a solder layer 830. The first metal layer 810 is formed on the pad metal layer 30. In the process of forming the bump structure 80, it is usually required to form the first metal layer 810 as a metal seed layer on the pad region first, so as to improve the adhesion between the second metal layer 820 and the pad metal layer 30 and ensure good connection therebetween. Optionally, the material of the first metal layer 810 is at least one of aluminum, nickel, copper, tungsten, titanium, silver and gold, for example, the material of the first metal layer 810 is titanium which has good adhesion. In some embodiments, the first metal layer 810 can also be composed of two or more sub-metal layers. The material of the upper sub-metal layer, i.e., the sub-metal layer far away from the pad metal layer 30, can be selected according to the material of the second metal layer 820, for example, when the material of the second metal layer 820 is copper or copper alloy, the material of the upper sub-metal layer can be copper.
[0036] The second metal layer 820 is formed on the first metal layer 810. Optionally, the material of the second metal layer 820 is at least one of aluminum, nickel, copper, tungsten, titanium, silver and gold, for example, the material of the second metal layer 820 is copper or copper-nickel alloy which has good conductivity. The thickness of the second metal layer 820 is 20 μm to 60 μm, for example, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, etc.
[0037] The solder layer 830 is formed on the second metal layer 820. The material of the solder layer 830 can be a metal with low melting point, for example, tin, lead or alloy thereof. The thickness of the solder layer 830 is 10 μm to 50 μm, for example, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, etc.
[0038] In the embodiments of the present application, a protection layer 50 can be formed on the non-pad metal region in the pad metal layer 30, so as to protect the semiconductor structure. Optionally, the material of the protection layer 50 can be silicon oxide, silicon nitride, etc.
[0039] In some embodiments, a second isolation layer 40 is further arranged between the non-pad metal region in the pad metal layer 30 and the protection layer 50. The second isolation layer 40 is formed on the non-pad metal region in the pad metal layer 30, and the protection layer 50 is formed on the second isolation layer 40. The second isolation layer 40 is used to separate the non-pad metal region in the pad metal layer 30 from other layers, so as to prevent current leakage in the non-pad region and ensure normal operation and reliability of the integrated circuit. Optionally, the material of the second isolation layer 40 is at least one of silicon oxide, silicon nitride, aluminum oxide, etc.
[0040] In the embodiment of the present application, the semiconductor structure further comprises a buffer layer 60 formed on the protective layer 50. The buffer layer 60 can be made of a material having a buffering property, such as polyimide, so as to protect the semiconductor structure. Optionally, the thickness of the buffer layer 60 is 5 μm-20 μm, such as 5 μm, 10 μm, 15 μm, 20 μm, etc.
[0041] In the embodiment of the present application, the stress dispersion layer 70 is used to disperse the stress suffered by the semiconductor structure in the subsequent processing process, so as to avoid the stress from being concentrated around the bump structure 80, which leads to the rupture of the dielectric layer 122. In addition, since the stress dispersion layer 70 is formed around the bump structure 80, the stress dispersion layer 70 can also function to fix the bump structure 80. Specifically, the stress dispersion layer 70 is formed on the buffer layer 60 and covers around the bump structure 80. The bump structure 80 needs to expose the surface of the stress dispersion layer 70, so as to realize the connection with the external circuit. In some optional embodiments, the upper surface of the second metal layer 820 in the bump structure 80, i.e., the surface away from the pad metal layer 30, is slightly higher than the surface of the stress dispersion layer 70. The material of the stress dispersion layer 70 can be an organic non-metal or an inorganic non-metal. For example, plastic, resin, ceramic, etc. In actual application, in order to reduce the packaging cost, the commonly used packaging material can be selected to make the stress dispersion layer 70, such as using epoxy plastic packaging material to make the stress dispersion layer 70. Optionally, the thickness of the stress dispersion layer 70 can be 5 μm-20 μm, such as 5 μm, 10 μm, 15 μm, 20 μm, etc.
[0042] In the above semiconductor structure, in the embodiment of the present application, since the stress dispersion layer 70 covering the buffer layer 60 is formed on the side surface of the bump structure 80, the stress dispersion layer 70 is closely attached to the bump structure 80, so that the stress in the bump structure 80 can be dispersed to each part of the base structure 10, thereby avoiding the rupture of the dielectric layer 122 in the subsequent packaging process. According to actual test statistics, in the original packaging process, the rupture of the dielectric layer 122 in the base structure 10 is about 50%. However, in the above semiconductor structure, the rupture of the dielectric layer 122 in the packaging process is almost 0, which greatly improves the yield and reliability of the packaging.
[0043] The embodiment of the present application further provides a forming method of a semiconductor structure, Figure 2 is a flowchart of the forming method of the semiconductor structure provided by the embodiment of the present application, as Figure 2 shown, the forming method comprises the following steps.
[0044] S1: providing an initial semiconductor structure; the initial semiconductor structure comprises a base structure, a pad metal layer and a protection layer; a dielectric layer is formed in the base structure; the pad metal layer is formed on the base structure; the pad metal layer comprises a pad region and a non-pad region; the protection layer is formed on the non-pad region of the pad metal layer, and the pad region of the pad metal layer is exposed on the surface of the protection layer.
[0045] In the embodiment of the present application, the initial semiconductor structure refers to an intermediate product structure in the process of processing a semiconductor structure, and the initial semiconductor structure can be obtained by processing the base 110 through a plurality of processing processes.
[0046] As an optional implementation, Figure 3 is a structural schematic diagram of an initial semiconductor structure provided by the embodiment of the present application, as Figure 3 shown, in the initial semiconductor structure, the base structure 10 can comprise a base 110 and a connection structure 120. The base 110 comprises a semiconductor device, and the connection structure 120 is formed on the surface of the base 110. The connection structure can comprise two or more connection layers. As an example, the connection structure 120 can comprise a first connection layer 121, a second connection layer 123 and a dielectric layer 122. The first connection layer 121 is formed on the base 110, the dielectric layer 122 is formed on the first connection layer 121, and the second connection layer 123 is formed on the dielectric layer 122. The material of the first connection layer 121 can be at least one of aluminum, nickel, copper, tungsten, titanium, silver and gold. The material of the second connection layer 123 can be at least one of aluminum, nickel, copper, tungsten, titanium, silver and gold. The material of the first connection layer 121 can be the same as or different from the material of the second connection layer 123.
[0047] As shown in Figure 3 , in the initial semiconductor structure, a first isolation layer 20 is formed on the connection layer in the connection structure, and the first isolation layer 20 is used to separate the connection layer in the connection structure from other structure layers to prevent current leakage in the connection layer. Optionally, the material of the first isolation layer 20 is at least one of silicon oxide, silicon nitride and aluminum oxide.
[0048] As shown in Figure 3As shown, a pad metal layer 30 is formed on the first isolation layer 20. Optionally, the pad metal layer 30 is made of at least one of aluminum, nickel, copper, tungsten, titanium, silver, and gold. The pad metal layer 30 includes a pad region and a non-pad region. A second isolation layer 40, a protection layer 50, and a buffer layer 60 are sequentially formed on the non-pad region. The second isolation layer 40 is used to isolate the non-pad region of the pad metal layer 30 from other layers, so as to prevent current leakage in the non-pad region. Optionally, the second isolation layer 40 is made of at least one of silicon oxide, silicon nitride, aluminum oxide, etc. The protection layer 50 is used to protect the semiconductor structure. Optionally, the protection layer 50 is made of silicon oxide, silicon nitride, etc. The buffer layer 60 is made of a material having a buffering property, such as polyimide, so as to protect the semiconductor structure.
[0049] As shown in FIG. 1, the semiconductor structure includes a substrate 10, a first isolation layer 20, a pad metal layer 30, a second isolation layer 40, a protection layer 50, a buffer layer 60, a dielectric layer 122, a second metal layer 820, and a bump structure 80. Figure 3 As shown, in the initial semiconductor structure, the pad region of the pad metal layer 30 is exposed, so that the bump structure 80 can be formed thereon.
[0050] S3: forming a bump structure on the pad region and forming a stress dispersion layer on the protection layer, to obtain a semiconductor structure; wherein the bump structure exposes the surface of the stress dispersion layer.
[0051] In the embodiments of the present application, the bump structure 80 has a small volume, and concentrated stress is easily generated in the subsequent process. The concentrated stress can cause the dielectric layer 122 with high brittleness to break. In order to avoid this problem, when the bump structure 80 is formed in the pad region of the pad metal layer 30, the stress dispersion layer 70 can be simultaneously formed to disperse the stress of the bump structure 80, so as to avoid the dielectric layer 122 from breaking due to the stress concentration of the bump structure 80.
[0052] Specifically, when the bump structure 80 is formed on the pad region, a first metal layer 810 can be first formed on the surface of the initial semiconductor structure. The first metal layer 810 is a metal seed layer, which is used to improve the adhesion between the second metal layer 820 and the pad metal layer 30, and ensure good connection therebetween. In some embodiments, the first metal layer 810 can also be composed of two or more sub-metal layers. The bottom sub-metal layer, i.e., the sub-metal layer close to the pad metal layer 30, can be made of titanium metal. The upper sub-metal layer, i.e., the sub-metal layer away from the pad metal layer 30, can be made of a material selected according to the material of the second metal layer 820, for example, when the material of the second metal layer 820 is copper or copper alloy, the material of the upper sub-metal layer can be copper. Optionally, the method for forming the first metal layer 810 includes, but is not limited to, sputtering, evaporation, atomic layer deposition, chemical deposition, etc.
[0053] As an example,Figure 4 is a structure schematic diagram of an initial semiconductor structure after a first metal layer 810 is formed on the initial semiconductor structure, as shown in Figure 4 The first metal layer 810 is formed on the buffer layer 60 and the pad metal layer. In some embodiments, the first metal layer 810 can be composed of two sub-metal layers, in which the material of the bottom sub-metal layer is titanium, and the material of the top sub-metal layer is copper.
[0054] Since the bump structure 80 is formed on the pad area of the pad metal layer 30, after the first metal layer 810 is formed on the initial semiconductor structure, a mask 90 can be formed on the first metal layer 810 to expose the first metal layer 810 above the pad area, so as to form a second metal layer 820 on the pad area. Specifically, Figure 5 is a structure schematic diagram of an initial semiconductor structure after a mask 90 is formed on the first metal layer 810, as shown in Figure 5 After the first metal layer 810 is formed on the initial semiconductor structure, the mask 90 can be formed on the first metal layer 810. Optionally, the material of the mask 90 includes but is not limited to photoresist, electron beam photoresist, silicon oxide, etc. Optionally, the method of forming the mask 90 includes but is not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD), etc.
[0055] After the mask 90 is formed on the first metal layer 810, the mask 90 can be etched. Specifically, Figure 6 is a structure schematic diagram of an initial semiconductor structure after the mask 90 is etched, as shown in Figure 6 By etching the mask 90, the first metal layer 810 above the pad area can be exposed.
[0056] Then, a second metal layer 820 with a first preset thickness can be formed on the exposed first metal layer 810. Specifically, Figure 7 is a structure schematic diagram of an initial semiconductor structure after a second metal layer 820 with a first preset thickness is formed on the first metal layer 810, as shown in Figure 7 The second metal layer 820 with the first preset thickness is formed in the window exposed by the mask 90. Optionally, the first preset thickness can be slightly smaller than the thickness of the mask 90, or can be the same as the thickness of the mask 90. Optionally, the material of the second metal layer 820 can be at least one of aluminum, nickel, copper, tungsten, titanium, silver, gold, such as copper-nickel alloy. Optionally, the method of forming the second metal layer 820 with the first preset thickness includes but is not limited to sputtering, evaporation, atomic layer deposition, chemical deposition, etc.
[0057] like Figure 7 As shown, after forming the second metal layer 820 of the first predetermined thickness, the mask 90 is removed, and then the stress dispersion layer 70 can be formed on the surface of the semiconductor structure after removing the mask 90. Specifically, when forming the stress dispersion layer 70 on the non-pad region of the pad metal layer 30, it is necessary to first etch the first metal layer 810 on the non-pad region of the pad metal layer 30 to expose the surface of the buffer layer 60 above the non-pad region of the pad metal layer 30, and then form the stress dispersion layer 70 on the surface of the semiconductor structure after removing the mask 90. Figure 8 FIG. 1 is a schematic diagram of a structure in which a stress dispersion layer 70 is formed on the surface of a semiconductor structure after removing the mask 90, as provided in an embodiment of the present application. Figure 8 As shown, the formed stress dispersion layer 70 covers the surface of the buffer layer 60 and the surface of the second metal layer 820. Optionally, the material of the stress dispersion layer 70 can be plastic, resin, ceramic, etc., such as epoxy molding compound.
[0058] Next, the stress dispersion layer 70 is polished. Figure 9 : is a schematic diagram of a structure after the stress dispersion layer 70 is ground, as provided in an embodiment of the present application. Figure 9 As shown, by grinding the stress dispersion layer 70, the second metal layer 820 can be exposed on the surface of the stress dispersion layer 70, so as to facilitate the subsequent preparation of the bump structure 80. When grinding the stress dispersion layer 70, if the process conditions permit, the surface of the stress dispersion layer 70 can be exposed on the second metal layer 820. Generally, in order to reduce the process requirements, when grinding the stress dispersion layer 70, a certain thickness of the second metal layer 820 can also be ground and removed at the same time to ensure that the second metal layer 820 can expose the surface of the stress dispersion layer 70. After the stress dispersion layer 70 is ground, the thickness of the stress dispersion layer 70 can be 5μm to 20μm. The thickness of the stress dispersion layer 70 should not be too thick, so as not to excessively increase the size of the final semiconductor structure. The thickness of the stress dispersion layer 70 should not be too thin, so as not to fail to achieve a good stress dispersion effect.
[0059] After the second metal layer 820 exposes the surface of the stress dispersion layer 70, a second metal layer 820 of a second preset thickness may be formed on the second metal layer 820. Specifically, a mask 90 may be formed before forming the second metal layer 820 of the second preset thickness. Figure 10 Schematic diagram of a structure after forming a mask 90 provided in an embodiment of the present application, such as Figure 10As shown in FIG. 8, the mask 90 is formed on the stress dispersion layer 70 and the second metal layer 820. Optionally, the material of the mask 90 includes, but is not limited to, photoresist, electron beam photoresist, silicon oxide, etc. Optionally, the method of forming the mask 90 includes, but is not limited to, physical vapor deposition, chemical vapor deposition, etc.
[0060] Then, the second metal layer 820 is exposed by removing the mask 90 above the second metal layer 820, so that the second metal layer 820 with the second preset thickness and the solder layer 830 can be formed on the exposed second metal layer 820. Figure 11 FIG. 9 is a structural schematic diagram of the electronic device after forming the second metal layer 820 with the second preset thickness and the solder layer 830 according to an embodiment of the present application. Figure 11 As shown in FIG. 9, the second metal layer 820 with the first preset thickness and the second metal layer 820 with the second preset thickness form the second metal layer 820 with the target thickness. Optionally, the target thickness is 20 μm to 60 μm. Optionally, the method of forming the second metal layer 820 with the second preset thickness includes, but is not limited to, sputtering, evaporation, atomic layer deposition, chemical deposition, etc.
[0061] As shown in FIG. 9, the solder layer 830 is formed on the second metal layer 820. The material of the solder layer 830 can be a metal with a low melting point, such as tin, lead, etc. or an alloy thereof. Optionally, the method of forming the solder layer 830 includes, but is not limited to, sputtering, evaporation, atomic layer deposition, chemical deposition, etc. Figure 11 After forming the second metal layer 820 with the second preset thickness and the solder layer 830, the mask 90 can be removed, and the solder layer 830 can be surface treated, so as to obtain the semiconductor structure as shown in FIG. 10.
[0062] Figure 1 The electronic device according to the embodiment of the present application can be an integrated circuit realized by using advanced packaging technology. Since the electronic device contains the semiconductor structure as described above, and since the stress dispersion layer covering the buffer layer is formed on the side surface of the bump structure, and the stress dispersion layer is closely attached to the bump structure, the stress in the bump structure can be dispersed to each part of the base structure, so as to improve the reliability of the packaging. In addition, the packaging cost of the electronic device is reduced due to the reduction of the dielectric layer cracking.
[0063] The electronic device according to the embodiment of the present application can be an integrated circuit realized by using advanced packaging technology. Since the electronic device contains the semiconductor structure as described above, and since the stress dispersion layer covering the buffer layer is formed on the side surface of the bump structure, and the stress dispersion layer is closely attached to the bump structure, the stress in the bump structure can be dispersed to each part of the base structure, so as to improve the reliability of the packaging. In addition, the packaging cost of the electronic device is reduced due to the reduction of the dielectric layer cracking.
[0064] The electronic device according to the embodiment of the present application can be an integrated circuit realized by using advanced packaging technology. Since the electronic device contains the semiconductor structure as described above, and since the stress dispersion layer covering the buffer layer is formed on the side surface of the bump structure, and the stress dispersion layer is closely attached to the bump structure, the stress in the bump structure can be dispersed to each part of the base structure, so as to improve the reliability of the packaging. In addition, the packaging cost of the electronic device is reduced due to the reduction of the dielectric layer cracking.
[0065] The electronic device according to the embodiment of the present application can be an integrated circuit realized by using advanced packaging technology. Since the electronic device contains the semiconductor structure as described above, and since the stress dispersion layer covering the buffer layer is formed on the side surface of the bump structure, and the stress dispersion layer is closely attached to the bump structure, the stress in the bump structure can be dispersed to each part of the base structure, so as to improve the reliability of the packaging. In addition, the packaging cost of the electronic device is reduced due to the reduction of the dielectric layer cracking.
[0066] The electronic device described in the embodiments of the present application can be any electronic product or device such as a smart phone, a desktop computer, a tablet computer, a notebook computer, a digital assistant, an augmented reality (AR) / virtual reality (VR) device, a smart voice interaction device, a smart household appliance, a smart wearable device, a vehicle-mounted terminal device, or the like, and can also be any intermediate product including the above-mentioned memory device.
[0067] The electronic device described in the embodiments of the present application includes the above-mentioned electronic device, and the electronic device includes the above-mentioned semiconductor structure. In the semiconductor structure, a stress dispersion layer of a covering buffer layer is formed on the side surface of the bump structure, and the stress dispersion layer is closely attached to the bump structure. Therefore, the stress in the bump structure can be dispersed to each part of the base structure, thereby improving the reliability of the package. In addition, the package cost of the electronic device is relatively reduced due to the reduction of the dielectric layer cracking. Therefore, the electronic device also has similar advantages.
[0068] It should be noted that the above-mentioned sequence of the embodiments of the present application is only for description, and does not represent the advantages and disadvantages of the embodiments. The above describes specific embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in an order different from the order in the embodiments and still achieve the desired result. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multi-task processing and parallel processing are possible or can be advantageous.
[0069] Each of the embodiments in the present specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiments.
[0070] Those of ordinary skill in the art can understand that all or part of the steps of the above-mentioned embodiments can be completed by hardware, or by a program instructing relevant hardware to complete, and the program can be stored in a computer readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.
[0071] The above-mentioned is only the preferred embodiment of the present application, and is not used to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A semiconductor structure, characterized in that include: Base structure, pad metal layer, bump structure, protection layer and stress dispersion layer; A dielectric layer is formed in the base structure; The pad metal layer is formed on the base structure; The pad metal layer includes a pad area and a non-pad area, the bump structure is formed on the pad area of the pad metal layer, and the protection layer is formed on the non-pad area of the pad metal layer; The stress dispersion layer is formed on the protective layer; The bump structure exposes the surface of the stress dispersion layer.
2. The semiconductor structure according to claim 1, wherein: The base structure includes a base and a connection structure; The wiring structure includes a first wiring layer, a second wiring layer and the dielectric layer; The first wiring layer is formed on the substrate, the dielectric layer is formed on the first wiring layer, and the second wiring layer is formed on the dielectric layer.
3. The semiconductor structure according to claim 2, wherein: The semiconductor structure further includes a first isolation layer formed on the second wiring layer.
4. The semiconductor structure according to claim 1, wherein: The bump structure includes a first metal layer, a second metal layer and a solder layer; The first metal layer is formed on the pad metal layer, the second metal layer is formed on the first metal layer, and the solder layer is formed on the second metal layer.
5. The semiconductor structure according to claim 4, wherein: The thickness of the second metal layer is 20 μm-60 μm; The thickness of the solder layer is 10 μm-50 μm. The semiconductor structure according to claim 1 , wherein: The material of the stress dispersion layer is at least one of plastic, resin and ceramic.
7. The semiconductor structure according to any one of claims 1 to 6, characterized in that: The thickness of the stress dispersion layer is 5 μm-20 μm.
8. The semiconductor structure according to any one of claims 1 to 6, characterized in that: The semiconductor structure further includes a second isolation layer, which is formed on a non-pad region of the pad metal layer, and the protection layer is formed on the second isolation layer.
9. The semiconductor structure according to any one of claims 1 to 6, characterized in that: The semiconductor structure further includes a buffer layer formed on the protection layer, and the stress dispersion layer is formed on the buffer layer.
10. The semiconductor structure according to claim 9, wherein: The thickness of the buffer layer is 5 μm-20 μm.
11. A method for forming a semiconductor structure, characterized in that: include: providing an initial semiconductor structure; The initial semiconductor structure includes a base structure, a pad metal layer and a protective layer; A dielectric layer is formed in the base structure; the pad metal layer is formed on the base structure; the pad metal layer includes a pad area and a non-pad area, the protective layer is formed on the non-pad area of the pad metal layer, and the pad area of the pad metal layer is exposed on the surface of the protective layer; A bump structure is formed on the pad area, and a stress dispersion layer is formed on the protective layer to obtain a semiconductor structure; wherein the bump structure exposes the surface of the stress dispersion layer.
12. The method according to claim 11, characterized in that The bump structure includes a first metal layer, a second metal layer of target thickness, and a solder layer; the bump structure is formed on the pad area, and a stress dispersion layer is formed on the protective layer to obtain a semiconductor structure, including: forming the first metal layer on the pad area; forming a second metal layer of the target thickness on the first metal layer, and forming a stress dispersion layer on the protective layer; wherein the second metal layer of the target thickness exposes a surface of the stress dispersion layer; The solder layer is formed on the second metal layer of the target thickness to obtain the semiconductor structure.
13. The method according to claim 12, characterized in that The step of forming a second metal layer having the target thickness on the first metal layer and forming a stress dispersion layer on the protective layer comprises: forming a second metal layer of a first predetermined thickness on the first metal; forming a stress dispersion layer on the protective layer and the second metal layer of the first preset thickness; grinding the stress dispersion layer so that a surface of the second metal layer with the first preset thickness is exposed from a surface of the stress dispersion layer; A second metal layer of a second preset thickness is formed on the surface of the second metal layer of the first preset thickness; the second metal layer of the first preset thickness and the second metal layer of the second preset thickness form a second metal layer of the target thickness.
14. An electronic device, characterized in that: A semiconductor structure comprising any one of claims 1 to 10.
15. An electronic device, characterized in that: The electronic apparatus comprises the electronic device according to claim 14.