Packaging structure with directly interconnected bare chips and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor packaging, and discloses a packaging structure with directly interconnected bare chips and a preparation method thereof, and the packaging structure with directly interconnected bare chips comprises a first bare chip which is provided with a first metal projection and a second metal projection; the second bare chip is provided with a third metal bulge which is arranged opposite to the first metal bulge; the first bare chip is connected with the third metal bulge on the second bare chip through the first metal bulge; the rewiring structure is positioned on the side surface of the first bare chip, and one end is connected with the second metal bulge; and the grid ball array is connected with the other end of the rewiring structure. According to the invention, the metal bulges of the first bare chip and the second bare chip are directly connected, so that longitudinal linear interconnection between the bare chips is realized, and the connection path between the first bare chip and the second bare chip is shorter; the first bare chip and the gate ball array are connected through a rewiring structure, a circuit board can be directly and externally connected, the use of a packaging substrate is reduced, the process is simpler, and the cost is lower.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, and particularly relates to a die-to-die interconnection packaging structure and a preparation method thereof. BACKGROUND

[0002] Die-to-die interconnection refers to direct interconnection between dies in the same package. High-bandwidth and low-delay communication between dies is achieved through interconnection structures in the package, such as through-silicon vias (TSVs) or redistribution layers (RDLs).

[0003] The existing Die-to-Die vertical interconnection structure has two major categories: package on package (POP) and package in package (PIP) and 3D interconnection. The conventional POP and PIP packaging processes are simple, low in cost, and large in pin pitch, but the interconnection path is long, the signal integrity is poor, the number of pins is small, and multiple substrates need to be used. To this end, the existing scheme proposes a 3D interconnection packaging, which has a short interconnection path, high signal integrity, and a large number of pins. However, the 3D interconnection packaging needs to use a TSV process and has a small pin pitch, and a substrate needs to be used, so that the process of the 3D interconnection packaging is relatively complex and the cost is relatively high.

[0004] Therefore, the prior art still needs to be improved and developed. SUMMARY

[0005] In view of the deficiencies of the prior art, the purpose of the present application is to provide a die-to-die interconnection packaging structure and a preparation method thereof, so as to solve the problem of complex process and high cost of the existing Die-to-Die interconnection packaging structure.

[0006] The technical scheme of the present application is as follows: In a first aspect, the present application provides a die-to-die interconnection packaging structure, which comprises: a first die, wherein a first metal bump and a second metal bump are arranged on the first die; a second die, wherein a third metal bump is arranged on the second die opposite to the first metal bump; the first die is connected to the third metal bump on the second die through the first metal bump; a re-distribution structure, wherein one end of the re-distribution structure is connected to the second metal bump, and the re-distribution structure is located on a side surface of the first die; A grid ball array is connected to the other end of the re-wiring structure.

[0007] Further, the first metal bump is arranged in an array on the upper surface of the first die; and the second metal bump is arranged around the first metal bump on the edge of the first die. Further, the first metal bump is arranged in an array on the upper surface of the first die; and the second metal bump is arranged around the first metal bump on the edge of the first die.

[0008] Further, the re-wiring structure comprises a first re-wiring layer, a second re-wiring layer and a copper column. The first re-wiring layer is located above the first die and connected to the second metal bump. The second re-wiring layer is located below the first die and connected to the grid ball array. The copper column is located on the side of the first die and connected between the first re-wiring layer and the second re-wiring layer.

[0009] Further, the upper surface of the copper column is provided with a seed plating layer, and the seed plating layer is connected to the second metal via.

[0010] Further, the die direct interconnection package structure further comprises a first packaging layer; the copper column and the first die are covered in the first packaging layer; and the copper column, the first metal bump and the second metal bump are exposed from the first packaging layer.

[0011] Further, the first re-wiring layer comprises a second packaging layer, a first metal interconnection layer, a first metal via and a second metal via. The first metal interconnection layer is located above the first die. The first metal via is connected between the second metal bump and the first metal interconnection layer. The second metal via is connected between the first metal interconnection layer and the copper column. The copper column is connected between the first metal interconnection layer and the second re-wiring layer. The first metal interconnection layer and the first metal via are covered in the second packaging layer; and the first metal via and the second metal via are exposed from the second packaging layer.

[0012] Further, the second re-wiring layer comprises a third packaging layer, a second metal interconnection layer, a third metal interconnection layer, a third metal via and a fourth metal via. The second metal interconnection layer is located below the first die; The third metal interconnection layer is located below the second metal interconnection layer and connected with the grid ball array; The third metal via is connected between the copper column and the second metal interconnection layer; The fourth metal via is connected between the second metal interconnection layer and the third metal interconnection layer; The third packaging layer is located below the first packaging layer; the second metal interconnection layer, the third metal interconnection layer, the third metal via and the fourth metal via are covered in the third packaging layer; wherein the third metal interconnection layer is exposed from the third packaging layer.

[0013] Further provided by the application, the die direct interconnection packaging structure further comprises a glue material connecting layer; the glue material connecting layer is connected between the first metal bump and the third metal bump; Further comprising a capacitor, a resistor or an inductor; the capacitor, the inductor and the inductor are arranged on the first metal interconnection layer.

[0014] In a second aspect, the application further provides a preparation method of the die direct interconnection packaging structure as described above, which comprises the following steps: A first substrate is provided, and a copper column is generated on the first substrate; A first die with a first metal bump and a second bump is attached to the first substrate, and a plastic material is used to cover the copper column and the first die and form a first packaging layer; wherein the surface of the copper column is exposed; A second re-wiring layer is prepared on the first surface of the first packaging layer, and the copper column is connected with the second re-wiring layer; A second substrate is added above the second re-wiring layer, and the first substrate is removed; A first re-wiring layer is prepared on the second surface of the first packaging layer, and the first re-wiring layer is connected with the copper column and the second metal bump respectively; The first metal bump of the first die is exposed from the first packaging layer, and a second die with a third metal bump is connected with the first die, and then glue material is poured at the connection between the first metal bump and the third metal bump; A third substrate is prepared on the second die, and the second substrate is removed; A grid ball array is prepared on the second re-wiring layer, and the third substrate is removed.

[0015] Further provided by the application, the step of preparing the second re-wiring layer on the first surface of the first packaging layer and connecting the copper column with the second re-wiring layer comprises: A polyimide layer is pasted on the first surface of the first encapsulation layer and is windowed to expose the copper pillar, and then conductive metal is plated to form a third metal via and a second metal interconnection layer; A polyimide layer is pasted on the surface of the second metal interconnection layer and is windowed to expose the second metal interconnection layer, and then conductive metal is plated to obtain a fourth metal via and a third metal interconnection layer; A plastic material is used to encapsulate the second metal interconnection layer, the third metal interconnection layer, the third metal via and the fourth metal via, and a third encapsulation layer is obtained; The step of preparing a first re-distribution layer on the second surface of the first encapsulation layer and connecting the first re-distribution layer with the copper pillar and the second metal bump, respectively, comprises: A polyimide layer is pasted on the second surface of the first encapsulation layer and is windowed, and then a conductive metal layer is plated to obtain a first metal via, a second metal via and a first metal interconnection layer.

[0016] The packaging structure of the die direct interconnection and the preparation method thereof provided by the application, the packaging structure of the die direct interconnection comprises: a first die, a first metal bump and a second metal bump are arranged on the first die; a second die, a third metal bump is arranged on the second die and is arranged opposite to the first metal bump; the first die is connected with the third metal bump on the second die through the first metal bump; a re-distribution structure, one end of the re-distribution structure is connected with the second metal bump; a ball grid array, the other end of the re-distribution structure is connected with the ball grid array. The metal bumps of the first die and the second die are directly connected, the vertical linear interconnection between the dies is realized, the connection path between the first die and the second die is shorter, the signal integrity is better, and the delay is shorter. The re-distribution structure is used to connect between the first die and the ball grid array, the signal fan-out is realized, the spacing between the signal pins is larger, the circuit board can be directly connected, the use of the packaging substrate is reduced, the process of the existing vertical direct connection packaging structure is simpler, and the cost is lower. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only some embodiments of the application, and for those skilled in the art, without creative labor, other drawings can also be obtained from the structure shown in the drawings.

[0018] Figure 1 It is a structure diagram of the packaging structure of the die direct interconnection in the application.

[0019] Figure 2 FIG. 4 is a schematic diagram of the layout of the first metal protrusion and the second metal protrusion in one embodiment of the present invention.

[0020] Figure 3 FIG. 4 is a schematic diagram of the layout of the first metal protrusion and the second metal protrusion in another embodiment of the present invention.

[0021] Figure 4 FIG. 1 is a schematic diagram of a structure in which a packaging structure in which bare chips are directly interconnected is integrated with capacitors in one embodiment of the present invention.

[0022] Figure 5 It is a flow chart of a method for preparing a packaging structure with direct interconnection of bare chips in the present invention.

[0023] Figure 6 It is a schematic structural diagram of preparing a copper layer in one embodiment of the present invention.

[0024] Figure 7 It is a schematic structural diagram of preparing a copper column in one embodiment of the present invention.

[0025] Figure 8 It is a schematic structural diagram of preparing a first bare chip in one embodiment of the present invention.

[0026] Figure 9 It is a schematic diagram of the structure of packaging the first bare chip and the copper pillar in one embodiment of the present invention.

[0027] Figure 10 It is a schematic structural diagram of preparing a second metal interconnection structure in one embodiment of the present invention.

[0028] Figure 11 It is a structural schematic diagram of preparing the second substrate and removing the first substrate in one embodiment of the present invention.

[0029] Figure 12 In one embodiment of the present invention, Figure 11 Schematic diagram of the structure after flipping.

[0030] Figure 13 It is a schematic structural diagram of preparing a first metal interconnection structure in one embodiment of the present invention.

[0031] Figure 14 It is a structural diagram of connecting the second bare chip to the first bare chip in one embodiment of the present invention.

[0032] Figure 15 It is a structural schematic diagram of preparing a third substrate and removing the second substrate in one embodiment of the present invention.

[0033] Figure 16 It is a schematic structural diagram of preparing a ball grid array in one embodiment of the present invention.

[0034] Figure 17 is a schematic diagram of a structure for removing a third substrate in one embodiment of the present application.

[0035] In the drawings: 1, first die; 11, first metal bump; 12, second metal bump; 2, second die; 21, third metal bump; 3, re-wiring structure; 31, first re-wiring layer; 311, second packaging layer; 312, first metal interconnection layer; 313, first metal via; 314, second metal via; 32, second re-wiring layer; 321, third packaging layer; 322, second metal interconnection layer; 323, third metal interconnection layer; 324, third metal via; 325, fourth metal via; 33, copper pillar; 331, seed plating layer; 4, grid ball array; 5, first packaging layer; 6, adhesive connection layer; 7, capacitor; 8, copper layer; 101, first substrate; 102, second substrate; 103, third substrate. DETAILED DESCRIPTION

[0036] The present application provides a die direct interconnection packaging structure and a preparation method thereof. In order to make the purpose, technical scheme and effects of the present application more clear and explicit, the present application is further described in detail below with reference to the drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0037] In the embodiments and the patent application scope, unless the article is specifically limited in the text, "one", "a", "said" and "the" can also include plural forms. If the description of "first", "second" and the like is involved in the embodiments of the present application, the description of "first", "second" and the like is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include at least one of the features.

[0038] It should be further understood that the phrase "comprising" used in the specification of the present application means that the features, integers, steps, operations, elements and / or components exist, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when an element is said to be "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intermediate elements. In addition, "connection" or "coupling" used herein can include wireless connection or wireless coupling. The phrase "and / or" used herein includes all or any single unit and all combinations of the associated listed items.

[0039] Those skilled in the art can understand that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art in the field of the present application. It should also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0040] In addition, the technical solutions among various embodiments can be combined with each other, but it must be based on the fact that a person skilled in the art can realize the combination, and when the combination of technical solutions contradicts each other or cannot be realized, it should be considered that the combination of technical solutions does not exist and is not within the protection scope required by the present application.

[0041] Please refer to Figures 1 to 4 The present application provides a preferred embodiment of a die direct interconnection packaging structure.

[0042] In some embodiments, as Figure 1 shown, the present application provides a die direct interconnection packaging structure, which comprises a first die 1, a second die 2, a rewiring structure 3 and a grid ball array 4. Wherein, the first die 1 is provided with a first metal bump 11 and a second metal bump 12; the second die 2 is provided with a third metal bump 21 which is arranged opposite to the first metal bump 11; the first die 1 is connected to the second die 2 through the first metal bump 11 and the third metal bump 21 on the second die 2; the rewiring structure 3 is located on the side of the first die 1, one end of the rewiring structure 3 is connected to the second metal bump 12; and the other end of the rewiring structure 3 is connected to the grid ball array 4.

[0043] In the embodiment, the first die 1 has the first metal bump 11 and the second metal bump 12 arranged in an array, and the second die 2 has the third metal bump 21 arranged corresponding to the first metal bump 11. The grid ball array 4 is composed of a plurality of tin balls. The first metal bump 11 is directly connected to the third metal bump 21, so that the first die 1 and the second die 2 are linearly interconnected in the longitudinal direction. The rewiring structure 3 is connected to the second metal bump 12 of the first die 1 and the grid ball array 4, and can transmit the signals dispersed around the first die 1 to the rewiring structure 3 through fan-out, and then further transmit the signals to the grid ball array 4 through the rewiring structure 3. The signal pin pitch is further increased after the fan-out of the rewiring structure 3, so that the packaging structure can be directly ball-mounted without using a substrate.

[0044] In the technical scheme, the first die 1 and the second die 2 are directly interconnected in the longitudinal direction, so that the connection path between the first die 1 and the second die 2 is shorter, the signal integrity is better, and the delay is shorter. In addition, the first die 1 and the grid array 4 are connected through the re-wiring structure 3, so that the through-silicon via technology is not needed, the process difficulty is reduced, the cost is lower, and the signal pin spacing is increased through the re-wiring structure 3, so that the packaging substrate is not needed, the cost is reduced, the thickness of the packaging structure is effectively reduced, and the packaging design has obvious advantages in the high requirement of lightness, thinness and smallness, such as smart phones and tablet computers.

[0045] In some embodiments, as shown in Figure 2 The first metal bumps 11 are arranged in an array on the upper surface of the first die 1, and the second metal bumps 12 are arranged in an array on the two sides of the first die 1.

[0046] In this embodiment, the upper surface of the first die 1 refers to the side opposite to the second die 2. The first metal bumps 11 are arranged in an array in the center of the upper surface of the first die 1, and the second metal bumps 12 are arranged in an array on the first die 1 and distributed on the two sides of the first metal bumps 11. The third metal bumps 21 on the second die 2 are arranged correspondingly to the first metal bumps 11 on the first die 1.

[0047] In other embodiments, as shown in Figure 3 The first metal bumps 11 are arranged in an array on the upper surface of the first die 1, and the second metal bumps 12 are arranged around the first metal bumps 11 on the edge of the first die 1.

[0048] In this embodiment, the first metal bumps 11 are arranged in an array in the center of the first die 1. The second metal bumps 12 are arranged in an array around the first die 1. The third metal bumps 21 on the second die 2 are arranged correspondingly to the first metal bumps 11 on the first die 1.

[0049] In some embodiments, the first metal bumps 11, the second metal bumps 12 and the third metal bumps 21 can be, but are not limited to, copper metal bumps.

[0050] In some embodiments, as shown in Figure 1As shown, the re-wiring structure 3 includes a first re-wiring layer 31, a second re-wiring layer 32 and a copper pillar 33. The first re-wiring layer 31 is above the first die 1 and connected with the second metal bump 12; the second re-wiring layer 32 is below the first die 1 and connected with the LGA 4; the copper pillar 33 is on the side of the first die 1 and connected between the first re-wiring layer 31 and the second re-wiring layer 32.

[0051] In this embodiment, the re-wiring structure 3 is composed of the first re-wiring layer 31, the second re-wiring layer 32 and the copper pillar 33. The first re-wiring layer 31 is above the first die 1 and connected with the second metal bump 12 on the first die 1. The second re-wiring layer 32 is below the first die 1 and connected with the LGA 4. The copper pillar 33 is connected between the first re-wiring layer 31 and the second re-wiring layer 32. In this way, the signal fan-out and the increase of the pin pitch are realized through the re-wiring of the first re-wiring layer 31, the second re-wiring layer 32 and the copper pillar 33, so that the packaging structure can be directly connected with the circuit board, reducing the use of packaging substrate.

[0052] In some embodiments, as Figure 1 As shown, the die direct interconnection packaging structure further includes a first packaging layer 5; the copper pillar 33 and the first die 1 are encapsulated in the first packaging layer 5; wherein the copper pillar 33, the first metal bump 11 and the second metal bump 12 are exposed on the surface of the first packaging layer 5.

[0053] In this embodiment, the first packaging layer 5 is a plastic packaging material, which is used to encapsulate the first die 1 and the copper pillar 33 to protect and support the first die 1 and the copper pillar 33. The first metal bump 11 and the second metal bump 12 protrude from the surface of the first packaging layer 5, and the copper pillar 33 is exposed on the surface of the first packaging layer 5 through windowing processing.

[0054] In some embodiments, as Figure 1As shown, the first rewiring layer 31 includes: a second packaging layer 311, a first metal interconnect layer 312, a first metal via 313, and a second metal via 314. The first metal interconnect layer 312 is located above the first die 1; the first metal via 313 is connected between the second metal protrusion 12 and the first metal interconnect layer; the second metal via 314 is connected between the first metal interconnect layer 312 and the copper pillar 33; the copper pillar 33 is connected between the first metal interconnect layer and the second rewiring layer 32; the first metal interconnect layer 312 and the first metal via 313 are encapsulated in the second packaging layer 311; the first metal via 313 and the second metal via 314 are exposed from the second packaging layer 311.

[0055] In this embodiment, the first metal vias 313 and the second metal vias 314 are conductive vias made of a polyimide material plated with copper. The first metal vias 313 are connected to the second metal protrusions 12, while the second metal vias 314 are connected to the copper pillars 33. The first metal interconnect layer is connected between the first and second metal vias 313, 314, thereby connecting the first die 1 to the copper pillars 33. The second encapsulation layer 311 is made of a plastic encapsulation material and provides support and protection for the first metal interconnect layer, the first metal vias 313, and the second metal vias 314.

[0056] In some embodiments, as Figure 1 As shown, the second rewiring layer 32 includes: a third packaging layer 321, a second metal interconnect layer 322, a third metal interconnect layer 323, a third metal via 324, and a fourth metal via 325. The second metal interconnect layer is located below the first die 1; the third metal interconnect layer 323 is located below the second metal interconnect layer 322 and connected to the ball grid array 4; the third metal via 324 is connected between the copper pillar 33 and the second metal interconnect layer; the fourth metal via 325 is connected between the second metal interconnect layer 322 and the third metal interconnect layer 323; the third packaging layer 321 is located below the first packaging layer 5; the second metal interconnect layer 322, the third metal interconnect layer 323, the third metal via 324, and the fourth metal via 325 are encapsulated within the third packaging layer 321; and the third metal interconnect layer is exposed from the third packaging layer 321.

[0057] In the embodiment, the third metal through hole 324 and the fourth metal through hole 325 are prepared by polyimide material and further plated with copper. The third metal through hole 324 is connected between the copper pillar 33 and the second metal interconnection layer 322, and the fourth metal through hole 325 is connected between the second metal interconnection layer 322 and the third metal interconnection layer 323. The third packaging layer 321 is made of plastic packaging material, and the first packaging layer 5 is used for packaging the third metal through hole 324, the fourth metal through hole 325, the second metal interconnection layer 322 and the third metal interconnection layer 323, which has a supporting and protecting effect on the first packaging layer 5 used for packaging the third metal through hole 324, the fourth metal through hole 325, the second metal interconnection layer 322 and the third metal interconnection layer 323. The third metal interconnection layer is exposed to the third packaging layer 321 to be connected with the grid ball array 4. In this way, the copper pillar 33 is connected with the grid ball array 4 through the third metal through hole 324, the second metal interconnection layer 322, the fourth metal through hole 325 and the third metal interconnection layer 323, so as to realize the transmission of the fan-out signal of the first die 1 to the grid ball array 4.

[0058] In some embodiments, as shown in Figure 1 The upper surface of the copper pillar 33 is provided with a seed plating layer 331 connected with the second metal through hole 314.

[0059] In the embodiment, by coating a seed plating layer 331 on the upper surface of the copper pillar 33, the conductivity of the copper pillar 33 can be improved, and the adhesion can be enhanced.

[0060] In some embodiments, as shown in Figure 1 The die direct interconnection packaging structure further comprises a glue material connecting layer 6 connected between the first metal bump 11 and the third metal bump 21.

[0061] In the embodiment, the glue material connecting layer 6 is connected between the first metal bump 11 and the third metal bump 21, which has a supporting and protecting effect on the first metal bump 11 and the third metal bump 21.

[0062] In some embodiments, as shown in Figure 4 The die direct interconnection packaging structure further comprises a capacitor 7, a resistor or an inductor, and the capacitor 7, the inductor and the inductor are arranged on the first metal interconnection layer.

[0063] In the embodiment, the die direct interconnection packaging structure can further integrate a capacitor 7, a resistor, an inductor and the like to expand the function of the die direct interconnection packaging structure and reduce the structure of the peripheral circuit. As shown inFigure 4 As shown, the first metal interconnection layer is provided with a capacitor 7.

[0064] In some embodiments, as shown, the first metal bump 11 is provided on the first die 1. Figure 5 As shown, and in combination with Figures 6 to 17 The application also provides a method for manufacturing the die direct interconnection package structure as described above, which comprises the following steps: S100, providing a first substrate 101, and generating a copper column 33 on the first substrate 101, as shown in Figure 6 and Figure 7 As shown; Specifically, the first substrate 101 is a glass substrate, and the copper column 33 is produced by sputtering a copper layer 8 on the surface of the first substrate 101, and then by an electroplating process.

[0065] S200, pasting the first die 1 with the first metal bump 11 and the second bump on one side of the first substrate 101, and covering the copper column 33 and the first die 1 with plastic material to form a first packaging layer 5; wherein the surface of the copper column 33 is exposed, as shown in Figure 8 As shown; Specifically, the first die 1 with the first metal bump 11 and the second metal bump 12 is pasted on the first substrate 101 with the side down, and then sealed with plastic material, and the surface of the copper column 33 is exposed.

[0066] S300, preparing a second re-wiring layer 32 on the first surface of the first packaging layer 5, and connecting the copper column 33 with the second re-wiring layer 32, as shown in Figure 9 and Figure 10 As shown; S400, adding a second substrate 102 above the second re-wiring layer 32, and removing the first substrate 101, as shown in Figure 11 As shown; S500, preparing a first re-wiring layer 31 on the second surface of the first packaging layer 5, and connecting the first re-wiring layer 31 with the copper column 33 and the second metal bump 12 respectively, and exposing the first metal bump 11 from the first packaging layer 5, as shown in Figure 12 and Figure 13 As shown; S600, exposing the first metal bump 11 of the first die 1 from the first packaging layer 5, and connecting the second die 2 with the third metal bump 21 on one side of the first die 1, and then filling the glue material at the connection between the first metal bump 11 and the third metal bump 21, as shown in Figure 14 As shown; Specifically, after the second die 2 is connected with the first die 1, glue material is poured at the connection between the first metal bump 11 and the third metal bump 21 to support and protect the connection.

[0067] S700, a third substrate 103 is prepared on the second die 2 and the second substrate 102 is removed, as shown in Figure 15 S800, a grid ball array 4 is prepared on the second re-wiring layer 32 and the third substrate 103 is removed, as shown in Figure 16 Figure 17

[0068] In some embodiments, as shown in Figure 9 Figure 10 The step of preparing the second re-wiring layer 32 on the first surface of the first packaging layer 5 and connecting the copper column 33 with the second re-wiring layer 32 includes: S310, a polyimide layer is pasted on the first surface of the first packaging layer 5 and windowing is performed to expose the copper column 33, and then conductive metal is plated to form a third metal via hole 324 and a second metal interconnection layer 322; S320, a polyimide layer is pasted on the surface of the second metal interconnection layer 322 and windowing is performed to expose the second metal interconnection layer, and then conductive metal is plated to obtain a fourth metal via hole 325 and a third metal interconnection layer 323; S330, a plastic material is used to encapsulate the second metal interconnection layer, the third metal interconnection layer, the third metal via hole 324 and the fourth metal via hole 325 and obtain a third packaging layer 321.

[0069] Specifically, a polyimide layer is pasted on the first surface of the first packaging layer 5 and windowing is performed to expose the copper column 33, and then copper plating is performed to obtain a third metal via hole 324 and a second metal interconnection layer 322. In the same way, a fourth metal via hole 325 and a third metal interconnection layer 323 are obtained on the surface of the second metal interconnection layer 322 to form an overall second re-wiring layer below the first die 1, so that the copper column 33 is in communication with the third metal interconnection layer 323. The third packaging layer 321 has the function of supporting and protecting the second metal interconnection layer 322.

[0070] In some embodiments, the step of preparing the first re-wiring layer 31 on the second surface of the first packaging layer 5 and connecting the first re-wiring layer 31 with the copper column 33 and the second metal bump 12 respectively and exposing the first metal bump 11 from the first packaging layer 5 includes: ​​​​S510, a polyimide layer is pasted on the second surface of the first packaging layer 5 and windowing treatment is performed, after which a conductive metal layer is plated to obtain the first metal through hole 313, the second metal through hole 314 and the first metal interconnection layer, and the first metal bump 11 is connected with the first metal through hole 313 and the second metal bump 12 is connected with the second metal through hole 314, and the copper column 33 is connected with the second metal through hole 314.

[0071] Specifically, first, a polyimide is added on the surface of the first packaging layer 5, and then a copper plating treatment is performed to obtain the first metal through hole 313, the second metal through hole 314 and the first metal interconnection layer.

[0072] In summary, the packaging structure of the die direct interconnection and the preparation method thereof have the following beneficial effects: The first die and the second die are vertically directly interconnected, so that the connection path between the first die and the second die is shorter, the signal integrity is better, and the delay is shorter; The first die and the grid ball array are connected through the re-wiring structure, so that the through-silicon via technology is not needed, the process difficulty is reduced, the cost is lower, and the spacing of the signal pins is increased through the re-wiring structure, so that the packaging substrate is not needed, the cost is reduced, the thickness of the packaging structure is effectively reduced, and the packaging design has obvious advantages in the requirement of lightness, thinness and smallness.

[0073] It should be understood that the application of the present application is not limited to the above examples, and those skilled in the art can improve or change it according to the above description, and all these improvements and changes should belong to the protection scope of the appended claims of the present application.

Claims

1. A package structure for direct interconnection of bare chips, characterized in that: include: a first bare die, wherein a first metal protrusion and a second metal protrusion are provided on the first bare die; a second bare chip, wherein a third metal protrusion disposed opposite to the first metal protrusion is provided on the second bare chip; The first die is connected to the third metal protrusion on the second die through the first metal protrusion; a rewiring structure, the rewiring structure being located on a side of the first die, and one end of the rewiring structure being connected to the second metal protrusion; A ball grid array is connected to the other end of the rewiring structure.

2. The die direct interconnect packaging structure according to claim 1, wherein: The first metal protrusions are arranged in an array on the upper surface of the first die; the second metal protrusions are distributed in an array on both sides of the first die; Alternatively, the first metal protrusions are arranged in an array on the upper surface of the first die; and the second metal protrusions are arranged around the first metal protrusions at the edge of the first die.

3. The die direct interconnect packaging structure according to claim 1, wherein: The rewiring structure comprises: a first rewiring layer, a second rewiring layer and a copper pillar; The first redistribution layer is located above the first die and connected to the second metal protrusion; The second redistribution layer is located below the first die and connected to the ball grid array; The copper pillar is located on a side of the first die and connected between the first redistribution layer and the second redistribution layer.

4. The die direct interconnect packaging structure according to claim 3, wherein: It also includes a first packaging layer; the copper column and the first bare chip are encapsulated in the first packaging layer; wherein the copper column, the first metal protrusion and the second metal protrusion are exposed in the first packaging layer.

5. The package structure for direct die interconnection according to claim 4, wherein: The first rewiring layer includes: a second packaging layer, a first metal interconnection layer, a first metal through hole and a second metal through hole; The first metal interconnect layer is located above the first die; The first metal via is connected between the second metal protrusion and the first metal interconnection layer; The second metal via is connected between the first metal interconnect layer and the copper pillar; The copper pillar is connected between the first metal interconnect layer and the second redistribution layer; The first metal interconnection layer and the first metal through-hole are encapsulated in the second packaging layer; wherein the first metal through-hole and the second metal through-hole are exposed in the second packaging layer.

6. The die direct interconnect packaging structure according to claim 5, wherein: The second rewiring layer includes: a third packaging layer, a second metal interconnection layer, a third metal interconnection layer, a third metal through hole and a fourth metal through hole; The second metal interconnect layer is located below the first die; A third metal interconnection layer is located below the second metal interconnection layer and is connected to the gate ball array; The third metal via is connected between the copper pillar and the second metal interconnect layer; The fourth metal via is connected between the second metal interconnection layer and the third metal interconnection layer; The third packaging layer is located below the first packaging layer; the second metal interconnection layer, the third metal interconnection layer, the third metal through-hole and the fourth metal through-hole are encapsulated in the third packaging layer; wherein the third metal interconnection layer is exposed in the third packaging layer.

7. The package structure for direct die interconnection according to claim 5, wherein: A seed plating layer is provided on the upper surface of the copper column, and the seed plating layer is connected to the second metal through hole.

8. The package structure for direct die interconnection according to claim 5, wherein: Also includes: Adhesive connecting layer; The adhesive connecting layer is connected between the first metal protrusion and the third metal protrusion; Also includes: capacitance, resistance or inductance; The capacitor, the inductor and the resistor are arranged on the first metal interconnection layer.

9. A method for preparing a package structure for direct die interconnection according to any one of claims 3 to 8, characterized in that: Including steps: Providing a first substrate, and growing copper pillars on the first substrate; The first die is attached to the first substrate on one side thereof having the first metal protrusion and the second protrusion, and the copper pillar and the first die are covered with a plastic material to form a first packaging layer; wherein the surface of the copper pillar is exposed; Preparing a second redistribution layer on the first surface of the first packaging layer, and connecting the copper pillars to the second redistribution layer; adding a second substrate above the second redistribution layer and removing the first substrate; Preparing a first redistribution layer on the second surface of the first packaging layer, and connecting the first redistribution layer to the copper pillar and the second metal protrusion respectively, and making the first metal protrusion exposed from the first packaging layer; Exposing the first metal protrusion of the first die from the first packaging layer, connecting the side of the second die having the third metal protrusion to the first die, and then pouring glue at the connection between the first metal protrusion and the third metal protrusion; preparing a third substrate on the second die and removing the second substrate; A ball grid array is fabricated on the second redistribution layer and the third substrate is removed.

10. The method for preparing a package structure with direct die interconnection according to claim 9, wherein: The step of preparing a second redistribution layer on the first surface of the first packaging layer and connecting the copper pillars to the second redistribution layer comprises: A polyimide layer is attached to the first surface of the first packaging layer and a window is opened to expose the copper pillar, and then a conductive metal is plated to form a third metal through hole and a second metal interconnection layer; A polyimide layer is attached to the surface of the second metal interconnection layer and a window is opened to expose the second metal interconnection layer, and then a conductive metal is plated to obtain a fourth metal through hole and a third metal interconnection layer; Using plastic material to encapsulate the second metal interconnection layer, the third metal interconnection layer, the third metal through hole and the fourth metal through hole to obtain a third encapsulation layer; The steps of preparing a first redistribution layer on the second surface of the first packaging layer and connecting the first redistribution layer to the copper pillar and the second metal protrusion respectively include: A polyimide layer is attached to the second surface of the first packaging layer and a window opening process is performed, and then a conductive metal layer is plated to obtain a first metal through hole, a second metal through hole and a first metal interconnection layer.

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