A phase-to-phase current equalization control method and system for a multiphase power management chip

Abstract

The application provides a phase-to-phase current equalization control method and system of a multiphase power management chip, relates to the technical field of power electronics, and acquires the phase number information of the multiphase power management chip, determines the phase difference of the pulse width modulation signals of two adjacent phase circuits, generates the pulse width modulation signals of the phase circuits in combination with a reference clock signal, divides and processes the power ground plane through differential wiring, sets the printed circuit board layout of the multiphase power management chip, acquires the current spectrum information of the phase circuits under the action of the pulse width modulation signals, filters the current spectrum information when high-frequency interference exists in the phase circuits, obtains the filtered current spectrum information, dynamically adjusts the switching timing of the phase circuits through a logic control algorithm based on the filtered current spectrum information, so that the current between the phase circuits is kept balanced, and high-precision, fast dynamic equalization adjustment of the phase-to-phase current of the multiphase power is realized in a complex noise environment.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power electronics, and particularly relates to a phase-to-phase current equalization control method and system of a multi-phase power management chip. BACKGROUND

[0002] In application scenarios such as high-performance computing, data center servers, and high-end graphics processing units, multi-phase power management chips are widely used to provide stable, efficient, and low-noise power supply for processor cores. With the continuous rise of chip power consumption and the significant increase of power supply current, multi-phase parallel power supply architecture has become a key technology to meet the demand for large current and low voltage. Under this background, ensuring high equalization of each phase output current has become a core challenge to improve system efficiency, reduce thermal stress concentration, and prolong the life of components. If the phase-to-phase current distribution is uneven, it will not only cause some phase overloads and rapid temperature rise, but also may cause power loop stability to decline, seriously affecting the reliability and dynamic response performance of the power supply system.

[0003] At present, the existing scheme has proposed to realize phase-to-phase equalization by introducing a matching active filter circuit in each phase current sampling path, and combining a fixed period average current comparison algorithm in the digital domain. In the analog front end, a differential current detection structure is constructed by using a precision resistor and an operational amplifier to extract the real-time current signal of each phase, and a low-pass filter with a preset cutoff frequency is used to suppress the influence of switching noise on sampling accuracy. Subsequently, the digital control unit periodically collects the average current values of each phase, judges the current deviation according to the preset error threshold, and adjusts the duty cycle of the corresponding phase for closed-loop correction. However, the existing scheme still has obvious limitations when facing high-frequency interference coupling and transient load changes. Since its filtering strategy relies on fixed frequency response characteristics, it is easy to misjudge the current level of each phase in a noisy environment, thereby causing deviation in duty cycle adjustment; the comparison mechanism based on average values has a slow response speed and cannot track the rapidly changing current distribution trend in time, making it difficult to achieve accurate dynamic compensation, etc. SUMMARY

[0004] The present application aims to provide a phase-to-phase current equalization control method and system of a multi-phase power management chip to solve the problems of deviation in duty cycle adjustment caused by misjudgment of the current level of each phase in a noisy environment, and difficulty in achieving accurate dynamic compensation caused by slow response speed of the mechanism, etc.

[0005] To solve the above technical problems, in a first aspect, the present application provides a phase-to-phase current equalization control method of a multi-phase power management chip, comprising:

[0006] Obtaining the phase number information of the multiphase power management chip, determining the phase difference of the pulse width modulation signals of two adjacent phase circuits according to the phase number information, and generating the pulse width modulation signals of each phase circuit of the multiphase power management chip in combination with a reference clock signal;

[0007] By power ground plane segmentation and differential trace processing, the printed circuit board layout of the multiphase power management chip is set to reduce the crosstalk generated by each phase circuit when transmitting the pulse width modulation signals;

[0008] Obtaining the current spectrum information of each phase circuit under the action of the pulse width modulation signals;

[0009] When high-frequency interference is monitored in each phase circuit, the current spectrum information is filtered to obtain filtered current spectrum information;

[0010] Based on the filtered current spectrum information, the switching timing of each phase circuit is dynamically adjusted by a logic control algorithm to balance the current between each phase circuit.

[0011] Optionally, by power ground plane segmentation and differential trace processing, the printed circuit board layout of the multiphase power management chip is set, including:

[0012] According to the transmission path of the pulse width modulation signals of each phase circuit, the power layer and the ground layer of the printed circuit board are divided into a plurality of independent regions corresponding to each phase circuit, so that the power supply and the ground loop of each phase circuit are limited in the corresponding independent region;

[0013] Based on the independent region, the direction and spacing of the wires in the differential pair of the pulse width modulation signals of each phase circuit are adjusted to obtain an adjusted differential pair;

[0014] Based on all independent regions and the adjusted differential pair, the printed circuit board layout is formed.

[0015] Optionally, based on the independent region, the direction and spacing of the wires in the differential pair of the pulse width modulation signals of each phase circuit are adjusted to obtain an adjusted differential pair, including:

[0016] Determining the signal start point and the signal end point of the differential pair of the pulse width modulation signals of each phase circuit in the corresponding independent region, and defining the transmission path range of the differential pair with the signal start point and the signal end point as endpoints;

[0017] Within the transmission path range, the direction of the two wires in the differential pair is adjusted according to the position of the circuit element in the independent region, to obtain direction-adjusted wires, wherein when the wire needs to turn, an arc corner is used instead of a right-angle corner to make the turning angle and position of the two wires symmetrical;

[0018] If the lengths of the two adjusted wires are different, a non-critical path segment of the target wire is adjusted so that the length difference between the two adjusted wires is less than a preset length threshold, to obtain an adjusted wire, the non-critical path segment being a path segment that does not affect the transmission of the signal from the signal start point to the signal end point.

[0019] The spacing between the two adjusted wires is set in the signal start point to the preset start point boundary range and the signal end point to the preset end point boundary range to determine the adjusted differential wire pair, and the spacing between the preset start point boundary range and the preset end point boundary range is adjusted according to the path bending degree.

[0020] Optionally, the current spectrum information of each phase circuit under the action of the pulse width modulation signal is obtained, including:

[0021] The current signal of each phase circuit is collected, and the current signal is converted into a digital form signal;

[0022] According to the period of the pulse width modulation signal, the digital form signal is segmented and processed to obtain a segmented digital signal corresponding to each period;

[0023] Each segmented digital signal is frequency-decomposed to obtain signal components of each segmented digital signal in a plurality of preset frequency bands;

[0024] The amplitude parameter and the phase parameter of each preset frequency band signal component are extracted, and all amplitude parameters and phase parameters are arranged to form the current spectrum information of each phase circuit.

[0025] Optionally, when high-frequency interference is monitored in each phase circuit, the current spectrum information is filtered to obtain filtered current spectrum information, including:

[0026] When high-frequency interference is monitored in each phase circuit, a high-frequency interference monitoring band is selected from a plurality of preset frequency bands of the current spectrum information, the high-frequency interference monitoring band is set as a high-frequency band range, a target amplitude parameter of each phase circuit in the high-frequency band range under a normal working state is counted, and the target amplitude parameter is set as an amplitude threshold value;

[0027] The amplitude parameters of the signal components of each preset frequency band in the current spectrum information are compared with the amplitude threshold value to screen out a first target signal component whose amplitude parameter exceeds the amplitude threshold value in the high-frequency band range, and a preset frequency band corresponding to the first target signal component is recorded as an interference frequency band;

[0028] According to the interference frequency segment, a target frequency range for filtering processing is determined, and an attenuation parameter corresponding to the target frequency range is determined in combination with a difference between an amplitude parameter of a signal component of the interference frequency segment and the amplitude threshold value;

[0029] A second target signal component belonging to the target frequency range in the current spectrum information is located, and an amplitude parameter of the second target signal component is adjusted according to the attenuation parameter to obtain filtered current spectrum information.

[0030] Optionally, according to the interference frequency segment, a target frequency range for filtering processing is determined, and an attenuation parameter corresponding to the target frequency range is determined in combination with a difference between an amplitude parameter of a signal component of the interference frequency segment and the amplitude threshold value, including:

[0031] The minimum frequency interval between two adjacent interference frequency segments is calculated, and two adjacent interference frequency segments with a minimum frequency interval less than a preset frequency interval threshold value are merged to obtain a merged interference frequency segment;

[0032] Based on a starting frequency value and an ending frequency value of each merged interference frequency segment, a target frequency range is determined in combination with a preset low-frequency extension value and a preset high-frequency extension value;

[0033] The amplitude parameter of all signal components in each merged interference frequency segment is subtracted from the amplitude threshold value to obtain a plurality of amplitude difference values, and the largest amplitude difference value is taken as a target amplitude difference value corresponding to the merged interference frequency segment;

[0034] According to a preset difference interval, a basic attenuation value corresponding to the target amplitude difference value is determined;

[0035] According to the ending frequency value and the starting frequency value of the merged interference frequency segment, a frequency bandwidth is calculated to determine a width coefficient, and an attenuation parameter corresponding to the target frequency range is generated in combination with the basic attenuation value.

[0036] Optionally, based on the filtered current spectrum information, a logical control algorithm is used to dynamically adjust the switching sequence of each phase circuit to keep the currents between the phase circuits balanced, including:

[0037] From the filtered current spectrum information, a current amplitude parameter of each phase circuit in a preset reference frequency segment is extracted, and the current amplitude parameter is taken as a circuit current level;

[0038] According to the circuit current level of each phase circuit, a plurality of inter-phase current difference values are calculated, and the absolute value of the largest inter-phase current difference value is selected as a target adjustment difference value, and a reference phase circuit and a to-be-adjusted phase circuit corresponding to the target adjustment difference value are determined, wherein the difference between the circuit current level of the reference phase circuit and a preset balanced current value is smaller than that of the to-be-adjusted phase circuit.

[0039] determining an adjustment direction and an adjustment amplitude of the switch timing of the phase circuit to be adjusted according to the target adjustment difference, wherein when the circuit current level of the phase circuit to be adjusted is higher than that of the reference phase circuit, the adjustment direction is to reduce the current output, and when the circuit current level of the phase circuit to be adjusted is lower than that of the reference phase circuit, the adjustment direction is to increase the current output;

[0040] modifying a pulse starting time or a pulse duration in the switch timing of the phase circuit to be adjusted according to the adjustment direction and the adjustment amplitude, until the absolute values of all the phase-to-phase current differences are less than a preset balancing threshold, so as to keep the currents between the phase circuits balanced.

[0041] In a second aspect, the present application provides a phase-to-phase current balancing control system of a multi-phase power management chip, comprising:

[0042] a generation module configured to acquire phase number information of the multi-phase power management chip, determine a phase difference of pulse width modulation signals of two adjacent phase circuits according to the phase number information, and generate pulse width modulation signals of each phase circuit of the multi-phase power management chip in combination with a reference clock signal;

[0043] a processing module configured to set a printed circuit board layout of the multi-phase power management chip through power ground plane segmentation and differential trace processing, so as to reduce crosstalk generated by each phase circuit when transmitting the pulse width modulation signals;

[0044] an acquisition module configured to acquire current spectrum information of each phase circuit under the action of the pulse width modulation signals;

[0045] a filtering module configured to perform filtering processing on the current spectrum information to obtain filtered current spectrum information when high-frequency interference exists in each phase circuit is monitored;

[0046] an adjustment module configured to dynamically adjust the switch timing of each phase circuit through a logic control algorithm based on the filtered current spectrum information, so as to keep the currents between the phase circuits balanced.

[0047] In a third aspect, the present application provides an electronic device, comprising:

[0048] a memory configured to store a computer program;

[0049] a processor configured to implement the steps of the phase-to-phase current balancing control method of the multi-phase power management chip according to the first aspect when executing the computer program.

[0050] In a fourth aspect, the present application provides a computer readable storage medium, wherein a computer program is stored in the computer readable storage medium, and the computer program, when executed by a processor, enables the steps of the phase-to-phase current equalization control method of the multi-phase power management chip according to the first aspect to be implemented.

[0051] The application provides a phase-to-phase current equalization control method of a multiphase power management chip. The phase-to-phase current equalization control method comprises the following steps: obtaining phase number information of the multiphase power management chip, determining a phase difference of pulse width modulation signals of adjacent two-phase circuits, generating the pulse width modulation signals of the phase circuits in combination with a reference clock signal, setting a printed circuit board layout of the multiphase power management chip through power ground plane segmentation and differential wiring processing, obtaining current spectrum information of the phase circuits under the action of the pulse width modulation signals, filtering the current spectrum information when high-frequency interference is monitored in the phase circuits, and dynamically adjusting switching timing of the phase circuits through a logic control algorithm to keep the current between the phase circuits balanced. The phase-to-phase current equalization control method realizes accurate synchronization of switching timing of a multiphase system, reduces the risk of current imbalance caused by phase deviation from the signal source, suppresses electromagnetic crosstalk and ground bounce noise of each phase driving signal in the transmission process through the printed circuit board layout design, improves the integrity of the control signal, and provides a physical basis for realizing accurate current regulation. The current spectrum information acquisition can comprehensively capture dynamic components and interference characteristics in the current signal, and provide data support for subsequent interference identification and processing. When high-frequency interference is detected, the current spectrum information is filtered, the noise component and the real current information can be separated, and the interference is avoided to mislead the equalization judgment. Based on the filtered spectrum information, the logic control algorithm is used to dynamically adjust the switching timing of each phase, realize rapid response and closed-loop compensation of the current deviation, and thus maintain the continuous balance of the phase current under complex working conditions. Further, by analyzing the signal characteristics of multiple preset frequency bands in the current spectrum, a specific high-frequency band is selected as the interference monitoring range, and a dynamic amplitude threshold is set based on the amplitude level under the normal working state of the system. By comparing the real-time spectrum with the threshold, the high-frequency signal component exceeding the threshold is identified to determine the interference frequency band, and the target frequency range of the filtering is determined accordingly. According to the difference between the interference intensity and the threshold, the corresponding attenuation parameter is set to adjust the amplitude of the interference signal component in the target frequency range, and finally the purified current spectrum information is generated. The application breaks through the limitation of the traditional fixed filtering strategy in the complex electromagnetic environment, can adaptively identify and locate the high-frequency interference frequency band according to the actual running state of the system, and avoids excessive filtering caused by misjudging the real current dynamic as noise. By constructing a dynamic threshold and a demand-based attenuation mechanism, accurate suppression of the interference signal is realized, the effective information of the current change is retained, the accuracy of the spectrum analysis is improved, the reliability of the current detection under the high-frequency crosstalk and the transient load superposition scene is enhanced, a high-quality feedback basis is provided for the accurate adjustment of the switching timing, the phase-to-phase current mismatch problem caused by interference misjudgment and response lag is alleviated, and the stability and current sharing accuracy of the multiphase power system in high-performance computing and other high-dynamic load application scenarios are improved. BRIEF DESCRIPTION OF DRAWINGS

[0052] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the accompanying drawings required by the embodiments or prior art description will be briefly introduced. Obviously, the described embodiments are only some of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the scope of protection of the present application.

[0053] Figure 1 A flowchart of a phase-to-phase current balance control method of a multiphase power management chip provided by an embodiment of the present application is shown in the figure.

[0054] Figure 2 A specific implementation diagram of a phase-to-phase current balance control method of a multiphase power management chip provided by an embodiment of the present application is shown in the figure.

[0055] Figure 3 A structure diagram of a phase-to-phase current balance control system of a multiphase power management chip provided by an embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0056] In high-performance computing chip power supply, the transmission delay difference of each phase pulse width modulation signal is often caused by the asymmetry of the printed circuit board layout, and the high-frequency switching noise is coupled into the current detection path through the ground bounce and crosstalk, which distorts the sampling signal. The existing method relies on fixed parameter filtering and periodic average comparison, and it is difficult to quickly identify transient current changes and real interference. When the load suddenly changes, the response lags, causing a persistent mismatch between the phases, affecting system efficiency and heat distribution. The present application starts from the optimization of the signal generation source and the system anti-interference ability, constructs a clock synchronization mechanism by analyzing the relationship between the number of phases and the pulse width modulation phase difference, reduces the electromagnetic coupling between the signal paths by combining the power ground plane segmentation and differential wiring, and then introduces spectrum analysis and dynamic filtering in current monitoring to identify and suppress interference components. Finally, the logic control algorithm is used to adjust the switching timing of each phase in real time, so that the current distribution can still maintain balance under transient load and noise interference.

[0057] In order to enable those skilled in the art to better understand the present application, the present application will be further described in detail below in combination with the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without doing creative work are within the scope of protection of the present application.

[0058] The core of the present application is to provide a phase-to-phase current balance control method of a multiphase power management chip, and a flowchart of a specific embodiment of the method is shown in the figure. Figure 1 The method comprises:

[0059] Step 101: Obtain the phase number information of the multiphase power management chip, determine the phase difference of the pulse width modulation signals of the adjacent two-phase circuits according to the phase number information, and generate the pulse width modulation signals of each phase circuit of the multiphase power management chip in combination with the reference clock signal.

[0060] In this step, the phase number information refers to the total number information of the phase circuits contained in the multiphase power management chip, which is used to determine the phase distribution of each phase pulse width modulation signal. The phase difference of the pulse width modulation signal refers to the offset angle of the pulse width modulation signals of the adjacent two-phase circuits on the time axis, which is used to ensure that the switching actions of each phase circuit are uniformly distributed in time sequence. The reference clock signal refers to the basic clock signal used to synchronize the working time sequence of each phase circuit in the multiphase power management chip, which is used as the time reference for generating each phase pulse width modulation signal. The pulse width modulation signal refers to a periodic electrical signal used to control the on-off state of the switching device in the phase circuit.

[0061] In the embodiment of the present application, the total number of phase circuits contained in the chip, i.e. the phase number information, is obtained by reading the phase circuit number parameter recorded in the internal configuration register of the multiphase power management chip or detecting the pin level combination of the multiphase power management chip external for identifying the phase number. The offset angle of the adjacent two-phase pulse width modulation signals in time, i.e. the phase difference, is obtained by dividing 360 degrees by the total number of phase circuits in the phase number information. For example, if the phase number is 4, 360 degrees divided by 4 is 90 degrees, i.e. the phase difference of the adjacent two phases is 90 degrees. The reference clock signal is used as the initial time sequence reference, and the reference clock signal is sequentially shifted in time sequence according to the determined phase difference to generate a plurality of groups of pulse width modulation signals corresponding to the phase number. The pulse width modulation signal of the first phase circuit is directly generated based on the reference clock signal, the pulse width modulation signal of the second phase circuit is shifted by one phase difference based on the first phase signal, and the subsequent phases are sequentially shifted.

[0062] Step 102: The printed circuit board layout of the multiphase power management chip is set through power ground plane segmentation and differential wiring processing to reduce the crosstalk generated by each phase circuit when transmitting the pulse width modulation signal.

[0063] In this step, the printed circuit board layout refers to the physical wiring and layer structure design of the multiphase power management chip on the printed circuit board, which is used to reduce the signal crosstalk between each phase circuit.

[0064] Step 103: Obtain the current spectrum information of each phase circuit under the action of the pulse width modulation signal.

[0065] In this step, the current spectrum information refers to the information set quantized from the current spectrum, including the amplitude parameter and phase parameter of the signal component of each preset frequency band, which is obtained based on the collection, conversion and frequency decomposition of the current signal.

[0066] Step 104: When high-frequency interference is monitored in each phase circuit, the current spectrum information is filtered to obtain filtered current spectrum information.

[0067] In this step, high-frequency interference refers to interference signals with a frequency higher than the lower limit of the preset high-frequency range and an amplitude exceeding the amplitude threshold in the current spectrum, including high-frequency components introduced by electromagnetic coupling, signal crosstalk, etc., which can affect the accuracy of current detection. The filtered current spectrum information refers to the spectrum information obtained after filtering the current spectrum information containing high-frequency interference, including the signal component parameters of each frequency range after removing or attenuating high-frequency interference components, which is used to more accurately reflect the real current state of each phase circuit.

[0068] Step 105: Based on the filtered current spectrum information, the switching sequence of each phase circuit is dynamically adjusted through a logic control algorithm to maintain the balance of current between each phase circuit.

[0069] In this step, the switching sequence of each phase circuit refers to the time sequence and duration of the switching devices in each phase circuit turning on and off, including the switching action time corresponding to the pulse width modulation signal. By dynamically adjusting, the output current of the phase circuit can be changed to achieve inter-phase current balance.

[0070] The embodiment of the present application solves the timing offset problem caused by inaccurate phase distribution of the multi-phase pulse width modulation signal in the prior art, and provides a control signal with higher synchronization for each phase circuit. Uniform phase distribution reduces the superimposed interference of each phase switching action, reduces the current fluctuation caused by timing chaos, and lays a reliable signal foundation for subsequent layout optimization of printed circuit boards to reduce crosstalk, accurate monitoring of current spectrum, and dynamic adjustment of switching sequence. It helps to improve the current balance accuracy of the multi-phase power management chip under complex electromagnetic environment and dynamic load conditions, thereby improving system efficiency, reducing thermal stress concentration, enhancing the reliability and dynamic response performance of the power supply system.

[0071] The present application provides a specific embodiment, step 102, by power plane segmentation and differential wiring processing, the layout of the printed circuit board of the multi-phase power management chip is set to reduce the crosstalk generated by each phase circuit when transmitting the pulse width modulation signal, which specifically includes the following steps:

[0072] Step 201: According to the transmission path of the pulse width modulation signal of each phase circuit, the power layer and the ground layer of the printed circuit board are divided into multiple independent areas corresponding to each phase circuit, so that the power supply and ground loop of each phase circuit are limited in the corresponding independent area;

[0073] Step 202: adjusting the orientation and spacing of the conductive lines in the differential pair of the pulse width modulation signal of each phase circuit based on the independent region, to obtain an adjusted differential pair;

[0074] Step 203: forming a printed circuit board layout based on all the independent regions and the adjusted differential pair.

[0075] Optionally, step 202, adjusting the orientation and spacing of the conductive lines in the differential pair of the pulse width modulation signal of each phase circuit, to obtain an adjusted differential pair, specifically includes the following steps:

[0076] Step 211: determining the signal start point and the signal end point of the differential pair of the pulse width modulation signal of each phase circuit in the corresponding independent region, and delineating the transmission path range of the differential pair with the signal start point and the signal end point as endpoints;

[0077] Step 212: adjusting the orientation of the two conductive lines in the differential pair according to the position of the circuit element in the independent region within the transmission path range, to obtain the orientation-adjusted conductive lines, wherein when the conductive lines need to turn, an arc corner is used to replace a right-angle corner, so that the turning angle and position of the two conductive lines are kept symmetrical;

[0078] Step 213: if there is a difference in the length of the two orientation-adjusted conductive lines, adjusting the non-critical path segment of the target conductive line, so that the length difference of the two orientation-adjusted conductive lines is less than a preset length threshold, to obtain the length-adjusted conductive lines, the non-critical path segment is a path part that does not affect the transmission from the signal start point to the signal end point;

[0079] Step 214: setting the spacing between the two length-adjusted conductive lines within the signal start point to the preset start point boundary range and the signal end point to the preset end point boundary range, to determine the adjusted differential pair, wherein the spacing between the preset start point boundary range and the preset end point boundary range is adjusted according to the path curvature.

[0080] In the above steps, the independent area refers to a partition on the power supply layer and the ground layer of the printed circuit board corresponding to each phase circuit, which is used to limit the power supply and ground circuit of each phase circuit within the area to avoid interference between different phase circuits through the common power supply or ground plane. The differential line pair refers to two mutually coordinated conductive lines used to transmit pulse width modulation signals, including a pair of conductive lines carrying the same information but with opposite polarities, which is used to transmit information through the signal difference of the two conductive lines, and reduce the influence of external interference on the signal. The wire direction refers to the path direction of the two conductive lines in the differential line pair from the starting point to the ending point, which is used to ensure that the signal can avoid other circuit elements and be smoothly transmitted within the independent area. The wire spacing refers to the distance between the two conductive lines in the differential line pair, which is used to maintain the transmission characteristics of the differential signal and reduce the mutual interference between the signals. The adjusted differential line pair refers to the differential line pair after the adjustment of the wire direction, length and spacing, including the wire pair that meets the symmetry of the wire direction, the difference in length within the threshold value, and the spacing that meets the set requirements, which is used to more stably transmit the pulse width modulation signal. The signal starting point refers to the starting position of the transmission of the pulse width modulation signal by the differential line pair, including the output interface of the pulse width modulation signal generation end, which is the starting point of signal transmission. The signal ending point refers to the termination position of the transmission of the pulse width modulation signal by the differential line pair, including the input interface of the pulse width modulation signal in the phase circuit, which is the end point of signal transmission. The transmission path range of the differential line pair refers to the signal transmission path boundary drawn within the corresponding independent area with the signal starting point and the signal ending point as the end points, which ensures that the wire does not exceed the independent area. The circuit element position refers to the installation position of other electronic elements (such as resistors, capacitors, chip pins, etc.) in the independent area, including the coordinate information of each element on the printed circuit board, which is used to avoid these elements when adjusting the wire direction. The wire after direction adjustment refers to the wire in the differential line pair after the adjustment of the wire direction, including the wire with arc-shaped corners and symmetric turning angles and positions, which is used to avoid signal reflection and interference caused by right-angle corners. The non-critical path segment refers to the path part of the differential line pair that does not affect the transmission of the signal from the starting point to the ending point, including the wire segment that can be appropriately lengthened or shortened without changing the integrity of the signal transmission, which is used to avoid affecting the signal quality when adjusting the wire length. The preset length threshold refers to the maximum value of the allowed length difference between the two wires, which is used to ensure that the lengths of the two wires are basically consistent and reduce the signal delay difference. The wire after length adjustment refers to the wire after length calibration after the wire direction adjustment, including the wire with a length difference less than the preset length threshold, which is used to reduce the inconsistent signal transmission delay caused by the length difference. The preset starting point boundary range refers to the path range extending from the signal starting point to the signal ending point in a preset length, which is used to uniformly set the wire spacing within the range. The preset ending point boundary range refers to the path range extending from the signal ending point to the signal starting point in a preset length, which is used to uniformly set the wire spacing within the range.

[0081] In the embodiment of the present application, first, the independent area is divided through step 201, specifically: the transmission path of the pulse width modulation signal of each phase circuit from the generation end to the receiving end is determined, and then an independent area is drawn for each phase circuit on the power supply layer and the ground layer of the printed circuit board according to the path, so that the power supply line (such as a power supply line) and the ground line (such as a ground line) of each phase circuit are distributed only in the corresponding independent area and do not cross the power supply or ground line of other phases. Secondly, the differential line pair is adjusted through step 202, specifically: the signal starting point (such as the output pin of the pulse width modulation signal generation chip) and the signal ending point (such as the control pin of the switching device in the phase circuit) of the differential line pair in the corresponding independent area of each phase circuit are found, and the transmission path range (which is completely within the independent area) in which the wires can be laid is determined with the two points as the two ends; within the determined transmission path range, the positions of other circuit elements (such as capacitors and resistors) in the independent area are viewed, the directions of the two wires in the differential line pair are adjusted, if the wires need to turn, such as avoiding a certain resistor, a curved corner is used instead of a right-angled corner, and the turning angles (such as 90-degree arcs) and turning positions (such as turning at a distance of 5 mm from the resistor) of the two wires are consistent, to obtain the adjusted wires; the lengths of the two adjusted wires are measured, if one is longer than the other, such as 2 mm longer, the non-critical path segment of the longer wire is adjusted, such as adding a small arc to a straight line part to shorten the length, until the length difference between the two wires is less than a preset length threshold (such as less than 0.5 mm), to obtain the length-adjusted wires; in the signal starting point to the preset starting point boundary range (such as within 10 mm from the starting point) and the signal ending point to the preset ending point boundary range (such as within 10 mm from the ending point), the spacing between the two length-adjusted wires is set to a fixed value (such as 2 mm), and in the middle segment between the two ranges, the spacing is adjusted according to the path curvature, such as a little larger spacing for a more curved path, but not more than a preset maximum deviation, such as not more than 0.3 mm, to finally obtain the adjusted differential line pair. Finally, the printed circuit board layout is formed through step 203, specifically: the independent areas corresponding to all phase circuits and the adjusted differential line pairs are integrated together, the specific positions of the areas and wires on the printed circuit board are determined, and a complete printed circuit board layout is formed.

[0082] Assume that a 4-phase power management chip (hereinafter referred to as A chip) needs to set a printed circuit board layout, first determine the pulse width modulation signal transmission path of the 4-phase circuit of the A chip, specifically from the pulse width modulation output pin of the A chip to the metal oxide semiconductor field effect transistor control pin of each phase circuit, and then divide an independent area for each phase circuit on the power layer and the ground layer of the printed circuit board, wherein area 1 corresponds to phase 1 circuit, area 2 corresponds to phase 2 circuit, etc., so that the power supply line and the ground line of the phase 1 circuit are only distributed in the area 1 and do not enter other areas. Subsequently, for the phase 1 circuit, the signal starting point of the differential line pair is the pulse width modulation 1 output pin of the A chip, the signal ending point is the control pin of the phase 1 metal oxide semiconductor field effect transistor, and the transmission path range is limited in the area 1; the two conductive lines of the differential line pair are adjusted in the direction, because there is a capacitor C1 in the area 1, the conductive lines need to turn left at the left side of C1, so an arc corner is used, and the two conductive lines are turned at a distance of 3 mm from the edge of C1 with the same turning angle, thereby obtaining the conductive lines after the adjustment in the direction. Then the lengths of the two conductive lines after the adjustment in the direction are measured, it is found that one is 15 mm long and the other is 14 mm long, because there is a difference in length, the non-critical path segment of the longer conductive line is adjusted (a small arc is added at a straight line), so that the length difference becomes 0.3 mm (less than the preset length threshold 0.5 mm), and the conductive lines after the length adjustment are obtained. Then the spacing of the two conductive lines after the length adjustment is set, within the signal starting point to the preset starting point boundary range (the first 10 mm) and the signal ending point to the preset ending point boundary range (the last 10 mm), the spacing is set to 2 mm; the spacing is adjusted to 2.2 mm (without exceeding the preset deviation 0.3 mm) in the middle segment because of an arc bending, and the adjusted differential line pair of the phase 1 circuit is obtained. The independent area division and the differential line pair adjustment of the other 3 phases are completed under the same conditions and in the same way, and then the 4 independent areas and the 4 groups of adjusted differential line pairs are integrated to form the printed circuit board layout of the A chip.

[0083] The embodiment of the present application limits the power supply and ground loop of each phase circuit by dividing an independent area, reduces the interference generated by different phases through a common power supply or ground plane, adjusts the direction, length and spacing of the differential line pair, reduces the crosstalk and signal distortion in the pulse width modulation signal transmission process, solves the signal interference problem caused by unreasonable layout, makes the pulse width modulation signal more stably transmitted to each phase circuit, provides a reliable signal basis for subsequent accurate current monitoring and switch timing adjustment, and helps to improve the working stability of the multi-phase power management chip.

[0084] The present application provides a specific embodiment, step 103, obtaining the current spectrum information of each phase circuit under the action of the pulse width modulation signal, specifically including the following steps:

[0085] Step 301: Collecting the current signal of each phase circuit, converting the current signal into a digital form signal.

[0086] In this step, the digital form signal refers to a discrete numerical signal obtained by analog-to-digital conversion of the analog current signal of each phase circuit, which is used for subsequent digital domain processing and is converted based on the analog current signal.

[0087] In the embodiment of the present application, the current fluctuation of each phase circuit under the action of the pulse width modulation signal is obtained in real time through the current sensor, and a continuously changing analog current signal is obtained. The analog current signal is discretized by the analog-to-digital conversion device, and the current amplitude at each time is converted into a corresponding digital quantity to form a digital form signal composed of a series of numbers.

[0088] Step 302: segmenting the digital form signal according to the period of the pulse width modulation signal to obtain a segmented digital signal corresponding to each period.

[0089] In this step, the segmented digital signal refers to a signal obtained by segmenting the digital form signal according to the period of the pulse width modulation signal, including a digital signal segment corresponding to each pulse width modulation period, which is used for analyzing the current characteristics of each period and is obtained based on the digital form signal and the period of the pulse width modulation signal.

[0090] In the embodiment of the present application, the known period length of the pulse width modulation signal is first determined (for example, each period is 10 microseconds), and then the digital form signal is segmented according to the period length, so that each signal segment corresponds to a period of the pulse width modulation signal, thereby obtaining a plurality of segmented digital signals, each of which corresponds to one period.

[0091] Step 303: frequency decomposing each segmented digital signal to obtain signal components of the segmented digital signal in a plurality of preset frequency bands.

[0092] In this step, the preset frequency band refers to a plurality of continuous frequency ranges set in advance, which are used for decomposing the current signal into different frequency ranges for analysis and are set based on the possible frequency characteristics of the current signal. The signal component refers to the signal part of the segmented digital signal in a certain preset frequency band, including the amplitude and phase characteristics of the current signal in the frequency band, reflecting the distribution of the current signal in the frequency band, and is obtained based on the frequency decomposition of the segmented digital signal.

[0093] In the embodiment of the present application, each segmented digital signal is decomposed into a plurality of frequency ranges (i.e., preset frequency bands) set in advance, and the signal part in each preset frequency band is the signal component of the segmented digital signal in the frequency band, thereby obtaining the signal components corresponding to each segmented digital signal in different preset frequency bands.

[0094] Step 304: extracting the amplitude parameter and the phase parameter of the signal component of each preset frequency band, arranging all the amplitude parameters and the phase parameters to form the current spectrum information of the phase circuit.

[0095] In this step, the amplitude parameter refers to the intensity value of the signal component in the corresponding preset frequency band, including a parameter reflecting the energy size of the current signal in the frequency band, used to characterize the strength of the current at different frequencies. The phase parameter refers to the phase position value of the signal component in the corresponding preset frequency band, including a parameter reflecting the offset of the current signal in the frequency band relative to the reference time, used to characterize the phase characteristics of the current signal.

[0096] In the embodiment of the present application, the amplitude parameter reflecting the signal intensity and the phase parameter reflecting the signal phase position are extracted from the signal component of each preset frequency band, and then the amplitude parameter and the phase parameter corresponding to each frequency band are arranged in turn according to the high-low order of the preset frequency band to form the current spectrum information capable of reflecting the characteristics of the current of the phase circuit at different frequencies.

[0097] The embodiment of the present application realizes the fine time domain division of the phase current signal by converting the current signal into a digital form and segmenting it according to the pulse width modulation period; accurately captures the frequency characteristics of the current signal by obtaining the signal components of different preset frequency bands and the corresponding amplitude and phase parameters, solves the current detection distortion problem caused by the inability to effectively distinguish high-frequency noise from real current components, provides an accurate frequency spectrum basis for subsequent filtering processing, helps to improve the recognition accuracy of high-frequency interference, and further provides a reliable current state basis for inter-phase current equalization control, thereby enhancing the current detection reliability of the power supply system in a complex electromagnetic environment.

[0098] The present application provides a specific embodiment as shown in Figure 2 Step 104, when high-frequency interference is detected in the phase circuit, the current spectrum information is filtered to obtain filtered current spectrum information, specifically including the following steps:

[0099] Step 401: when high-frequency interference is detected in the phase circuit, a high-frequency interference monitoring segment is selected from the plurality of preset frequency bands of the current spectrum information, the high-frequency interference monitoring segment is taken as a high-frequency segment range, a target amplitude parameter of the phase circuit in the high-frequency segment range under normal working state is counted, and the target amplitude parameter is set as an amplitude threshold value;

[0100] Step 402: comparing the amplitude parameter of the signal component of each preset frequency band in the current spectrum information with the amplitude threshold value to screen out a first target signal component whose amplitude parameter exceeds the amplitude threshold value in the high-frequency segment range, and recording the preset frequency band corresponding to the first target signal component as an interference frequency band;

[0101] Step 403: determining a target frequency range for filtering according to the interference frequency segment, and determining an attenuation parameter corresponding to the target frequency range in combination with a difference between an amplitude parameter of a signal component of the interference frequency segment and the amplitude threshold value;

[0102] Step 404: positioning a second target signal component belonging to the target frequency range in the current spectrum information, and adjusting an amplitude parameter of the second target signal component according to the attenuation parameter to obtain filtered current spectrum information.

[0103] Optionally, in step 403, the target frequency range for filtering is determined according to the interference frequency segment, and the attenuation parameter corresponding to the target frequency range is determined in combination with a difference between an amplitude parameter of a signal component of the interference frequency segment and the amplitude threshold value, which can specifically include the following steps:

[0104] Step 411: calculating a minimum frequency interval between two adjacent interference frequency segments, and merging two adjacent interference frequency segments with a minimum frequency interval less than a preset frequency interval threshold to obtain a merged interference frequency segment;

[0105] Step 412: determining a target frequency range based on a starting frequency value and an ending frequency value of each merged interference frequency segment in combination with a preset low-frequency extension value and a preset high-frequency extension value;

[0106] Step 413: performing subtraction operation on an amplitude parameter of all signal components in each merged interference frequency segment and the amplitude threshold value to obtain a plurality of amplitude difference values, and taking a maximum amplitude difference value as a target amplitude difference value corresponding to the merged interference frequency segment;

[0107] Step 414: determining a basic attenuation value corresponding to the target amplitude difference value according to a preset difference interval;

[0108] Step 415: calculating a frequency bandwidth according to the ending frequency value and the starting frequency value of the merged interference frequency segment to determine a width coefficient, and generating an attenuation parameter corresponding to the target frequency range in combination with the basic attenuation value.

[0109] In the above steps, the high-frequency interference monitoring segment refers to a specific frequency segment selected from multiple preset frequency segments of current spectrum information for monitoring high-frequency interference, including a frequency range in which high-frequency interference may exist, used to define a monitoring interval of high-frequency interference, and is selected based on preset frequency segments of current spectrum information. The high-frequency segment range refers to a high-frequency signal coverage range taking the selected high-frequency interference monitoring segment as the high-frequency signal coverage range, used to subsequently statistically determine amplitude parameters in a normal working state, and is determined based on the high-frequency interference monitoring segment. The target amplitude parameter refers to an amplitude parameter of a signal component of each phase circuit in the high-frequency segment range in the normal working state, used to set a threshold for judging high-frequency interference, and is statistically determined based on current spectrum information in the normal working state. The amplitude threshold refers to a critical value set based on the target amplitude parameter for judging whether high-frequency interference exists, used to screen signal components exceeding the value, and is set based on the target amplitude parameter. The first target signal component refers to a signal component in the high-frequency segment range whose amplitude parameter exceeds the amplitude threshold, reflecting possible high-frequency interference, and is screened based on a comparison between current spectrum information and the amplitude threshold. The interference frequency segment refers to a preset frequency segment corresponding to the first target signal component, used to determine a frequency range requiring filtering processing, and is recorded based on the first target signal component. The target frequency range refers to a frequency range requiring filtering processing determined according to the interference frequency segment, used to locate a signal component to be adjusted, and is determined based on the interference frequency segment. The attenuation parameter refers to a parameter for adjusting the amplitude of a signal component in the target frequency range, used to weaken the intensity of high-frequency interference, and is determined based on the difference between the signal component of the interference frequency segment and the amplitude threshold. The second target signal component refers to a signal component belonging to the target frequency range in the current spectrum information, used for subsequent filtering processing, and is located based on the target frequency range. The minimum frequency interval refers to the minimum frequency distance between two adjacent interference frequency segments, used to judge whether the interference frequency segments need to be merged, and is calculated based on the frequencies of adjacent interference frequency segments. The preset frequency interval threshold refers to a preset interval critical value for judging whether adjacent interference frequency segments need to be merged, used to determine whether adjacent interference frequency segments are merged, and is preset based on the characteristics of the interference frequency segment. The merged interference frequency segment refers to a frequency segment formed by merging adjacent interference frequency segments whose minimum frequency intervals are less than the preset frequency interval threshold, used to simplify the frequency range of filtering processing, and is obtained based on the merging of adjacent interference frequency segments. The start frequency value refers to the starting frequency value of the merged interference frequency segment, used to determine the starting boundary of the target frequency range, and is determined based on the characteristics of the merged interference frequency segment. The end frequency value refers to the ending frequency value of the merged interference frequency segment, used to determine the ending boundary of the target frequency range, and is determined based on the characteristics of the merged interference frequency segment. The preset low-frequency expansion value refers to a preset value for expanding the target frequency range in the low-frequency direction, used to expand the filtering range to cover possible interference, and is preset based on filtering requirements. The preset high-frequency expansion value refers to a preset value for expanding the target frequency range in the high-frequency direction, used to expand the filtering range to cover possible interference, and is preset based on filtering requirements.The amplitude difference refers to a difference between an amplitude parameter of a signal component in the combined interference frequency segment and an amplitude threshold value, is used as a basis for determining the attenuation parameter, and is obtained based on a subtraction operation between the amplitude parameter and the amplitude threshold value. The target amplitude difference refers to a difference with the largest value among a plurality of amplitude differences in the combined interference frequency segment, is used for determining a corresponding basic attenuation value, and is obtained based on selection of the plurality of amplitude differences. The preset difference interval refers to a range of amplitude differences that is preset for corresponding different basic attenuation values, is used for matching the corresponding basic attenuation values, and is preset based on a setting requirement of the attenuation parameter. The basic attenuation value refers to a basic numerical value corresponding to the preset difference interval and used for calculating the attenuation parameter, is used for generating a final attenuation parameter in combination with the width coefficient, and is determined based on the preset difference interval. The frequency bandwidth refers to a difference between a terminal frequency value and a starting frequency value of the combined interference frequency segment, is used for determining the width coefficient, and is calculated based on the terminal frequency value and the starting frequency value. The width coefficient refers to a coefficient determined according to the frequency bandwidth and used for adjusting the basic attenuation value, is used for generating the attenuation parameter in combination with the basic attenuation value, and is determined based on the frequency bandwidth.

[0110] In the embodiment of the present application, firstly, high-frequency interference monitoring segment selection and amplitude threshold setting are performed, specifically: when high-frequency interference is monitored in each phase circuit, a high-frequency interference monitoring segment is selected from a plurality of preset frequency segments of current spectrum information and is taken as a high-frequency segment range, then target amplitude parameters of each phase circuit in the high-frequency segment range under normal working state are counted, and the target amplitude parameters are set as amplitude threshold values. Secondly, the first target signal component is screened and the interference frequency segment is recorded, specifically: the amplitude parameters of the signal components of each preset frequency segment in the current spectrum information are compared with the amplitude threshold values, the first target signal component with the amplitude parameter exceeding the amplitude threshold value in the high-frequency segment range is screened, and the preset frequency segment corresponding to the first target signal component is recorded as the interference frequency segment. The target frequency range and the attenuation parameter are determined, specifically: the minimum frequency interval between two adjacent interference frequency segments is calculated, two adjacent interference frequency segments with a minimum frequency interval less than a preset frequency interval threshold value are combined to obtain a combined interference frequency segment; the target frequency range is determined based on the starting frequency value and the ending frequency value of each combined interference frequency segment, in combination with a preset low-frequency expansion value and a preset high-frequency expansion value; then the amplitude parameters of all signal components in each combined interference frequency segment are subtracted from the amplitude threshold value to obtain a plurality of amplitude difference values, and the maximum amplitude difference value is taken as the target amplitude difference value of the corresponding combined interference frequency segment; the target amplitude difference value corresponds to a basic attenuation value according to a preset difference interval; the frequency bandwidth of the combined interference frequency segment is calculated based on the ending frequency value and the starting frequency value to determine the width coefficient, and then the basic attenuation value is combined to generate the attenuation parameter corresponding to the target frequency range. Finally, the signal component adjustment is performed to obtain the filtered current spectrum information: the second target signal component belonging to the target frequency range in the current spectrum information is located, the amplitude parameter of the second target signal component is adjusted according to the attenuation parameter, and the filtered current spectrum information is obtained.

[0111] For example, after the printed circuit board layout of the A chip is set and the current spectrum information of each phase circuit is obtained, the current spectrum information is filtered. When high-frequency interference is monitored in each phase circuit of the A chip, 100 kHz-1 MHz is selected as a high-frequency interference monitoring segment from multiple preset frequency segments of the current spectrum information and is taken as a high-frequency segment range, the target amplitude parameter of each phase circuit in the range under a normal working state is 5 V, 5 V is set as an amplitude threshold value, the amplitude parameters of signal components of each preset frequency segment are compared with 5 V, a first target signal component with an amplitude exceeding 5 V in the high-frequency segment range is screened out, and the corresponding preset frequency segments 120 kHz-150 kHz and 160 kHz-180 kHz are recorded as interference frequency segments; the minimum frequency interval of the two interference frequency segments is 10 kHz, which is less than a preset frequency interval threshold value 15 kHz, and the two interference frequency segments are combined into a combined interference frequency segment 120 kHz-180 kHz; based on the starting frequency value 120 kHz and the ending frequency value 180 kHz of the combined interference frequency segment, in combination with a preset low-frequency expansion value 10 kHz and a preset high-frequency expansion value 10 kHz, a target frequency range is determined as 110 kHz-190 kHz; the amplitude parameters of signal components in the combined interference frequency segment are subtracted from 5 V to obtain multiple amplitude difference values, of which the maximum is 3 V, as a target amplitude difference value; according to a preset difference interval, the basic attenuation value corresponding to 3 V is 0.6; the frequency bandwidth of the combined interference frequency segment is calculated as 60 kHz, a width coefficient is determined as 1.2, 0.6 is multiplied by 1.2 to obtain an attenuation parameter 0.72; a second target signal component belonging to 110 kHz-190 kHz in the current spectrum information is located, and the amplitude parameter of the second target signal component is adjusted according to the attenuation parameter 0.72 to obtain filtered current spectrum information.

[0112] The embodiment of the present application can accurately screen out signal components and interference frequency segments corresponding to high-frequency interference by selecting a high-frequency interference monitoring segment and setting an amplitude threshold value, can distinguish high-frequency noise from real current components, can realize targeted filtering processing of high-frequency interference, can avoid misjudgment and adjustment deviation caused by a fixed filtering strategy, can provide accurate current spectrum information for subsequent dynamic adjustment of switching timing of each phase circuit to realize current balancing, and can improve working stability and reliability of a multi-phase power management chip in a complex electromagnetic environment.

[0113] The present application provides a specific embodiment, step 105, based on the filtered current spectrum information, the switching timing of each phase circuit is dynamically adjusted by a logic control algorithm, so that the current between each phase circuit remains balanced, specifically including the following steps:

[0114] Step 501: Extract the current amplitude parameter of each phase circuit in the preset reference frequency segment from the filtered current spectrum information, and take the current amplitude parameter as the circuit current level.

[0115] In this step, the preset reference frequency band refers to a specific frequency band that is preset for measuring the current level of each phase circuit, reflecting the working state of each phase circuit at this frequency, and is set based on the working characteristics of the multi-phase power management chip. The current amplitude parameter refers to the current signal strength value of each phase circuit in the preset reference frequency band, reflecting the size of the current at this frequency band, and is used as a basis for measuring the current level of the circuit, and is extracted based on the filtered current spectrum information. The circuit current level refers to the current size state of each phase circuit determined based on the current amplitude parameter, reflecting the load condition of each phase circuit, and is used to calculate the inter-phase current difference, and is determined based on the current amplitude parameter.

[0116] In the embodiment of the present application, first, the preset reference frequency band for reflecting the actual working state of each phase circuit is determined, and then the current amplitude parameters of each phase circuit in this frequency band are extracted from the filtered current spectrum information, which are directly used as the circuit current level for measuring the current size of each phase circuit.

[0117] Step 502: According to the circuit current level of each phase circuit, a plurality of inter-phase current differences are calculated, and the absolute value of the largest inter-phase current difference is selected as the target adjustment difference, and the reference phase circuit and the phase circuit to be adjusted corresponding to the target adjustment difference are determined, wherein the difference between the circuit current level of the reference phase circuit and the preset balanced current value is smaller than that of the phase circuit to be adjusted.

[0118] In this step, the inter-phase current difference refers to the difference between the circuit current levels of any two phase circuits, reflecting the current difference between different phase circuits, and is used to judge whether the phase currents are balanced, and is calculated based on the circuit current level of each phase circuit. The target adjustment difference refers to the absolute value of the largest difference selected from a plurality of inter-phase current differences, reflecting the most unbalanced current difference among the phase circuits, and is used to determine the object to be adjusted, and is selected based on the inter-phase current difference. The reference phase circuit refers to one phase circuit in the two phase circuits corresponding to the target adjustment difference, whose circuit current level has a smaller difference with the preset balanced current value, reflecting the circuit that is relatively closer to the balanced state, and is used as a reference for adjusting the phase circuit to be adjusted, and is determined based on the target adjustment difference and the preset balanced current value. The phase circuit to be adjusted refers to one phase circuit in the two phase circuits corresponding to the target adjustment difference, whose circuit current level has a larger difference with the preset balanced current value, reflecting the circuit that needs to be adjusted to achieve the balanced state, and is used to accept the modification of the switching sequence, and is determined based on the target adjustment difference and the preset balanced current value. The preset balanced current value refers to a preset ideal current value that each phase circuit should reach, reflecting the current state of the balanced working of each phase circuit, and is used to judge the difference between the circuit current level of each phase circuit and the balanced state, and is set based on the design parameters of the multi-phase power management chip.

[0119] In this embodiment of the invention, by subtracting the circuit current levels of any two phase circuits, multiple sets of phase current differences are obtained. Then, the one with the largest absolute value is selected as the target adjustment difference. The difference between the circuit current levels of the two phase circuits corresponding to this difference and the preset equalization current value is compared. The phase with the smaller difference is determined as the reference phase circuit, and the other phase is determined as the phase circuit to be adjusted.

[0120] Step 503: Based on the target adjustment difference, determine the adjustment direction and adjustment range of the switching timing of the phase circuit to be adjusted. When the circuit current level of the phase circuit to be adjusted is higher than that of the reference phase circuit, the adjustment direction is to reduce the current output. When the circuit current level of the phase circuit to be adjusted is lower than that of the reference phase circuit, the adjustment direction is to increase the current output.

[0121] In this step, the adjustment direction refers to the direction in which the current output of the phase circuit to be adjusted is changed, including increasing or decreasing the current output. This guides the modification of the switching timing and is determined based on a comparison of the circuit current levels of the phase circuit to be adjusted and the reference phase circuit. The adjustment magnitude refers to the degree to which the current output of the phase circuit to be adjusted is changed, reflecting the magnitude of the amount that needs to be adjusted. This determines the extent of the switching timing modification and is determined based on the magnitude of the target adjustment difference.

[0122] In this embodiment of the invention, the current levels of the phase circuit to be adjusted and the reference phase circuit are determined based on the sign of the target adjustment difference, thereby determining the adjustment direction. At the same time, the required adjustment range is determined based on the magnitude of the target adjustment difference; the larger the difference, the larger the adjustment range.

[0123] Step 504: Based on the adjustment direction and adjustment range, modify the pulse start time or pulse duration in the switching sequence of the phase circuit to be adjusted until the absolute value of the current difference between all phases is less than the preset equalization threshold, so as to keep the current between each phase circuit balanced.

[0124] In this step, the pulse start time refers to the point in time when the pulse signal begins in the switching sequence, reflecting the moment when the switching device starts working. It is used to control the start time of current output, thus affecting the current magnitude, and is an important parameter of the switching sequence. The pulse duration refers to the length of time the pulse signal lasts in the switching sequence, reflecting the duration of operation of the switching device, directly affecting the current output magnitude, and is a key parameter of the switching sequence. The preset equalization threshold refers to the pre-set maximum current difference allowed between each phase circuit, reflecting the allowable range of current balance between each phase, used to determine whether each phase circuit has reached a balanced state, and is set based on the operating requirements of the multi-phase power management chip.

[0125] In the embodiment of the present application, the starting time or the pulse duration of the pulse in the switch timing affecting the current output of the to-be-adjusted phase circuit is modified according to the determined adjustment direction and adjustment amplitude, for example, the pulse duration is shortened when the current output needs to be reduced, and then the current difference between phases is recalculated, and the modification process is repeated until the absolute values of all the current differences between phases are less than the preset balancing threshold.

[0126] The embodiment of the present application accurately determines the current level of each phase circuit by extracting effective current parameters from the filtered current spectrum information, and then calculates the current difference between phases and selects the target adjustment difference, thereby determining the object that needs to be adjusted first. By modifying the switch timing of the to-be-adjusted phase circuit, the dynamic adjustment of the current of each phase is realized, the precise dynamic compensation is realized, the inter-phase current balancing accuracy of the multi-phase power management chip under dynamic load conditions is improved, the problems of overloading and temperature rise of some phases caused by uneven current distribution are reduced, and the reliability and dynamic response performance of the power supply system are enhanced.

[0127] Figure 3 A specific implementation structure diagram of a multi-phase power management chip inter-phase current balancing control system provided by the embodiment of the present application is shown in Figure 3 The system can include:

[0128] The generation module 21 is configured to obtain the phase number information of the multi-phase power management chip, determine the phase difference of the pulse width modulation signals of the adjacent two phase circuits according to the phase number information, and generate the pulse width modulation signals of each phase circuit of the multi-phase power management chip in combination with the reference clock signal.

[0129] The processing module 22 is configured to process the layout of the printed circuit board of the multi-phase power management chip through power ground plane segmentation and differential wiring processing, so as to reduce the crosstalk generated by each phase circuit when transmitting the pulse width modulation signal.

[0130] The acquisition module 23 is configured to acquire the current spectrum information of each phase circuit under the action of the pulse width modulation signal.

[0131] The filtering module 24 is configured to perform filtering processing on the current spectrum information when high-frequency interference exists in each phase circuit, to obtain filtered current spectrum information.

[0132] The adjustment module 25 is configured to dynamically adjust the switch timing of each phase circuit based on the filtered current spectrum information through a logic control algorithm, so that the current between each phase circuit remains balanced.

[0133] The phase-to-phase current equalization control system of the multi-phase power management chip according to an embodiment of the present application is used to implement the phase-to-phase current equalization control method of the multi-phase power management chip, and the specific embodiments of the phase-to-phase current equalization control system of the multi-phase power management chip can be found in the foregoing embodiment part of the phase-to-phase current equalization control method of the multi-phase power management chip. The specific embodiments can be referred to the description of the corresponding embodiment part, and will not be described here again.

[0134] The present application further provides an electronic device, comprising: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of the phase-to-phase current equalization control method of the multi-phase power management chip.

[0135] The present application further provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of the phase-to-phase current equalization control method of the multi-phase power management chip.

[0136] In an exemplary embodiment, the computer readable storage medium can include, but is not limited to, a U disk, a read-only memory, a random access memory, a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0137] The present application further provides a computer program product, wherein the computer program product comprises a computer program, and the computer program is executed by a processor to implement the steps in the phase-to-phase current equalization control method of the multi-phase power management chip.

[0138] The skilled person can further realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in the foregoing description in general terms. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0139] The above describes in detail the phase-to-phase current equalization control method and system of the multi-phase power management chip provided by the present application. The principles and implementation manners of the present application are described by using specific examples, and the above description of the embodiments is only used to help understand the method of the present application and its core idea. It should be pointed out that, for those skilled in the art, some improvements and modifications can be made to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the protection scope of the present application.

Claims

1. A method for phase-to-phase current balancing control of a multiphase power management chip, characterized in that, The method comprises the following steps: acquiring phase number information of a multiphase power management chip, determining a phase difference of pulse width modulation signals of two adjacent phase circuits according to the phase number information, and generating the pulse width modulation signals of each phase circuit of the multiphase power management chip in combination with a reference clock signal; processing a printed circuit board layout of the multiphase power management chip through power ground plane segmentation and differential wiring to reduce crosstalk generated by each phase circuit when transmitting the pulse width modulation signals; acquiring current spectrum information of each phase circuit under the action of the pulse width modulation signals; when high-frequency interference is monitored in each phase circuit, performing filtering processing on the current spectrum information to obtain filtered current spectrum information; based on the filtered current spectrum information, dynamically adjusting switching timing of each phase circuit through a logic control algorithm to keep the current of each phase circuit balanced; when high-frequency interference is monitored in each phase circuit, performing filtering processing on the current spectrum information to obtain filtered current spectrum information, comprising: when high-frequency interference is monitored in each phase circuit, selecting a high-frequency interference monitoring segment from a plurality of preset frequency segments of the current spectrum information, taking the high-frequency interference monitoring segment as a high-frequency segment range, and statistically determining a target amplitude parameter of each phase circuit in the high-frequency segment range under a normal working state, and taking the target amplitude parameter as an amplitude threshold value; comparing amplitude parameters of signal components of each preset frequency segment in the current spectrum information with the amplitude threshold value to screen out a first target signal component with an amplitude parameter exceeding the amplitude threshold value in the high-frequency segment range, and recording a preset frequency segment corresponding to the first target signal component as an interference frequency segment; determining a target frequency range for filtering processing according to the interference frequency segment, and determining an attenuation parameter of the corresponding target frequency range in combination with a difference between the amplitude parameter of the signal component of the interference frequency segment and the amplitude threshold value; locating a second target signal component belonging to the target frequency range in the current spectrum information, and adjusting the amplitude parameter of the second target signal component according to the attenuation parameter to obtain filtered current spectrum information; determining a target frequency range for filtering processing according to the interference frequency segment, and determining an attenuation parameter of the corresponding target frequency range in combination with a difference between the amplitude parameter of the signal component of the interference frequency segment and the amplitude threshold value, comprising: calculating a minimum frequency interval between two adjacent interference frequency segments, merging two adjacent interference frequency segments with a minimum frequency interval less than a preset frequency interval threshold to obtain a merged interference frequency segment; determining a target frequency range based on a starting frequency value and an ending frequency value of each merged interference frequency segment, in combination with a preset low-frequency expansion value and a preset high-frequency expansion value; performing subtraction operation on the amplitude parameters of all signal components in each merged interference frequency segment and the amplitude threshold value to obtain a plurality of amplitude difference values, and taking the amplitude difference value with the largest value as a target amplitude difference value of the corresponding merged interference frequency segment; determining a basic attenuation value corresponding to the target amplitude difference value according to a preset difference interval; According to the end frequency value and the start frequency value of the combined interference frequency band, a frequency bandwidth is calculated to determine a width coefficient, and in combination with the basic attenuation value, an attenuation parameter corresponding to a target frequency range is generated.

2. The method of claim 1, wherein, The printed circuit board layout of the multiphase power management chip is set by power ground plane segmentation and differential trace processing, comprising: According to the transmission path of the pulse width modulation signal of each phase circuit, the power layer and the ground layer of the printed circuit board are divided into a plurality of independent regions corresponding to each phase circuit, so that the power supply and the ground loop of each phase circuit are limited in the corresponding independent region; Based on the independent region, the direction and spacing of the conductors in the differential pair of the pulse width modulation signal of each phase circuit are adjusted to obtain an adjusted differential pair; Based on all the independent regions and the adjusted differential pair, the printed circuit board layout is formed.

3. The method of claim 2, wherein, Based on the independent region, the direction and spacing of the conductors in the differential pair of the pulse width modulation signal of each phase circuit are adjusted to obtain an adjusted differential pair, comprising: Determine the signal start point and signal end point of the differential pair of the pulse width modulation signal of each phase circuit in the corresponding independent region, and draw the transmission path range of the differential pair with the signal start point and signal end point as the endpoints; Within the transmission path range, the direction of the two conductors in the differential pair is adjusted according to the position of the circuit elements in the independent region to obtain direction-adjusted conductors, wherein when the conductor needs to turn, an arc corner is used instead of a right-angled corner to make the turning angle and position of the two conductors symmetrical; If the lengths of the two direction-adjusted conductors differ, adjust the non-critical path segment of the target conductor so that the length difference between the two direction-adjusted conductors is less than a predetermined length threshold to obtain length-adjusted conductors, and the non-critical path segment is a path segment that does not affect the transmission from the signal start point to the signal end point; Within the signal start point to the preset start point boundary range and the signal end point to the preset end point boundary range, the spacing between the two length-adjusted conductors is set to determine the adjusted differential pair, wherein the spacing between the preset start point boundary range and the preset end point boundary range is adjusted according to the path curvature.

4. The method of claim 1, wherein, Obtaining current spectrum information of each phase circuit under the action of the pulse width modulation signal, comprising: Collecting the current signal of each phase circuit and converting the current signal into a digital form signal; According to the period of the pulse width modulation signal, the digital form signal is segmented to obtain a segmented digital signal corresponding to each period; Frequency decomposition is performed on each segmented digital signal to obtain signal components of each segmented digital signal in a plurality of preset frequency bands; The amplitude parameter and the phase parameter of the signal component of each preset frequency band are extracted, and all the amplitude parameters and the phase parameters are arranged to form the current spectrum information of each phase circuit.

5. The method of claim 1, wherein, Based on the filtered current spectrum information, the switching sequence of each phase circuit is dynamically adjusted by a logic control algorithm to balance the current between each phase circuit, comprising: Extracting the current amplitude parameter of each phase circuit in a preset reference frequency band from the filtered current spectrum information, and taking the current amplitude parameter as the circuit current level; According to the circuit current level of each phase circuit, a plurality of sets of phase-to-phase current difference values are calculated, and the absolute value of the largest phase-to-phase current difference value is selected as a target adjustment difference value, and the reference phase circuit and the phase circuit to be adjusted corresponding to the target adjustment difference value are determined, wherein the difference between the circuit current level of the reference phase circuit and the preset balanced current value is smaller than that of the phase circuit to be adjusted; According to the target adjustment difference value, the adjustment direction and the adjustment amplitude of the switching time sequence of the phase circuit to be adjusted are determined, wherein when the circuit current level of the phase circuit to be adjusted is higher than that of the reference phase circuit, the adjustment direction is to reduce the current output, and when the circuit current level of the phase circuit to be adjusted is lower than that of the reference phase circuit, the adjustment direction is to increase the current output; According to the adjustment direction and the adjustment amplitude, the pulse starting time or the pulse duration in the switching time sequence of the phase circuit to be adjusted is modified until the absolute values of all phase-to-phase current difference values are less than a preset balanced threshold, so that the currents between the phase circuits are balanced.

6. A phase-to-phase current equalization control system for a multiphase power management chip, the system comprising: Comprise: The generation module is used for acquiring the phase number information of the multi-phase power management chip, determining the phase difference of the pulse width modulation signals of the adjacent two phase circuits according to the phase number information, and generating the pulse width modulation signals of each phase circuit of the multi-phase power management chip in combination with a reference clock signal; The processing module is used for processing the printed circuit board layout of the multi-phase power management chip through power ground plane segmentation and differential wiring to reduce the crosstalk generated by each phase circuit when transmitting the pulse width modulation signals; The acquisition module is used for acquiring the current spectrum information of each phase circuit under the action of the pulse width modulation signals; The filtering module is used for filtering the current spectrum information when high-frequency interference exists in each phase circuit to obtain filtered current spectrum information; The adjustment module is used for dynamically adjusting the switching time sequence of each phase circuit based on the filtered current spectrum information through a logic control algorithm, so that the currents between the phase circuits are balanced; When high-frequency interference exists in each phase circuit, the current spectrum information is filtered to obtain filtered current spectrum information, which comprises: When high-frequency interference exists in each phase circuit, a high-frequency interference monitoring segment is selected from a plurality of preset frequency segments of the current spectrum information, the high-frequency interference monitoring segment is taken as a high-frequency segment range, a target amplitude parameter of each phase circuit in the high-frequency segment range under a normal working state is counted, and the target amplitude parameter is set as an amplitude threshold value; The amplitude parameters of the signal components of each preset frequency segment in the current spectrum information are compared with the amplitude threshold value to screen out a first target signal component whose amplitude parameter in the high-frequency segment range exceeds the amplitude threshold value, and a preset frequency segment corresponding to the first target signal component is recorded as an interference frequency segment; According to the interference frequency segment, a target frequency range for filtering is determined, and an attenuation parameter corresponding to the target frequency range is determined in combination with the difference between the amplitude parameter of the signal component of the interference frequency segment and the amplitude threshold value. Positioning a second target signal component belonging to the target frequency range in the current spectrum information, adjusting an amplitude parameter of the second target signal component according to the attenuation parameter, and obtaining filtered current spectrum information; According to the interference frequency segment, determine the target frequency range of the filtering processing, combine the difference between the amplitude parameter of the signal component of the interference frequency segment and the amplitude threshold value, and determine the attenuation parameter corresponding to the target frequency range, including: Calculate the minimum frequency interval between two adjacent interference frequency segments, and combine two adjacent interference frequency segments with a minimum frequency interval less than a preset frequency interval threshold to obtain a combined interference frequency segment; Based on the starting frequency value and the ending frequency value of each combined interference frequency segment, combine the preset low frequency expansion value and the preset high frequency expansion value to determine the target frequency range; Subtract the amplitude parameter of all signal components in each combined interference frequency segment from the amplitude threshold value to obtain a plurality of amplitude difference values, and take the largest amplitude difference value as the target amplitude difference value corresponding to the combined interference frequency segment; According to the preset difference interval, determine the basic attenuation value corresponding to the target amplitude difference value; According to the ending frequency value and the starting frequency value of the combined interference frequency segment, calculate the frequency bandwidth to determine the width coefficient, combine the basic attenuation value, and generate the attenuation parameter corresponding to the target frequency range.

7. An electronic device, comprising: Including: Memory for storing computer programs; The processor is used to execute the computer program to realize the steps of the phase-to-phase current equalization control method of the multi-phase power management chip according to any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by the processor to realize the phase-to-phase current equalization control method of the multi-phase power management chip according to any one of claims 1 to 5.

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