Ring oscillator
By using analog and digital signal control of the power supply and tuning unit, combined with a cross-coupled inverter, the performance bottleneck of traditional ring oscillators in terms of low power consumption and wide bandwidth is solved, and the accuracy of frequency tuning and power consumption are optimized.
Patent Information
- Application Number
- CN202510921702.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-04
- Publication Date
- 2025-10-17
AI Technical Summary
Traditional ring oscillators have bottlenecks in low-power performance and cannot meet the requirements of wide bandwidth and low power consumption. In addition, load tuning is significantly affected by the nonlinearity of transistor parasitic parameters.
A power supply and tuning unit is used, including a basic power supply sub-unit, a fine tuning sub-unit and a coarse tuning sub-unit. The bias current is controlled by analog and digital tuning signals, and frequency tuning is achieved by combining a cross-coupled inverter structure.
It achieves synergistic optimization of wide tuning range and low power consumption, improves frequency tuning accuracy, reduces phase noise, and eliminates the influence of transistor parasitic parameters on the tuning curve.
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Figure CN120811327A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of integrated circuit design, and particularly relates to a ring oscillator. BACKGROUND
[0002] As a core module of high-frequency clock generation in modern system on chip (SoC), the tuning range and power consumption characteristics of voltage-controlled oscillator (VCO) directly determine the adaptability of the system to multi-band communication and low-power scenarios.
[0003] As a specific implementation of voltage-controlled oscillator, the traditional ring oscillator mainly relies on load tuning mechanism (such as variable capacitance / resistance load or power voltage regulation) to realize frequency control. However, load tuning needs to maintain a fixed bias current to ensure the stability of transconductance, which will have considerable power consumption even at low frequency oscillation. With the continuous improvement of the low-power performance requirements of electronic devices, this high-power characteristic has undoubtedly become an important factor restricting the further application of traditional ring oscillators. In addition, the adjustment of load capacitance / resistance is significantly affected by the nonlinearity of transistor parasitic parameters, and its performance bottleneck has failed to meet the demand of wide frequency band and low power consumption under advanced process. SUMMARY
[0004] In view of the above problems of the prior art, the technical problem to be solved by the present application is to provide a ring oscillator with wide tuning and low power consumption.
[0005] To solve the above technical problems, one technical scheme adopted by the present application is to provide a ring oscillator, comprising a power supply and tuning unit and a ring oscillation unit, an input end of the power supply and tuning unit is connected to a power supply signal, a modulation power output end of the power supply and tuning unit is electrically connected with a power input end of the ring oscillation unit, a signal output end of the ring oscillation unit outputs a differential clock signal, and the power supply and tuning unit is used to output corresponding bias current according to a tuning control signal, so as to realize frequency tuning of the ring oscillation unit.
[0006] Further, the power supply and adjustment unit comprises a basic power supply subunit, a fine adjustment subunit and a coarse adjustment subunit; the power input ends of the basic power supply subunit, the fine adjustment subunit and the coarse adjustment subunit are connected and input power signals as the input end of the power supply and adjustment unit, the output ends of the basic power supply subunit, the fine adjustment subunit and the coarse adjustment subunit are connected and output modulated power as the modulated power output end of the power supply and adjustment unit and the power input end of the ring oscillation unit, the control signal input end of the basic power supply subunit is grounded; the tuning control signal comprises an analog tuning voltage signal and a digital tuning control signal, the control signal input end of the fine adjustment subunit is inputted with the analog tuning voltage signal, and the input end of the coarse adjustment subunit is inputted with the digital tuning control signal.
[0007] Further, the basic power supply subunit comprises a PMOS tube M1, the gate of the PMOS tube M1 is grounded as the control signal input end of the basic power supply subunit, the source of the PMOS tube M1 is inputted with a power signal as the power input end of the basic power supply subunit, and the drain of the PMOS tube M1 is connected with the power input end of the ring oscillation unit as the output end of the basic power supply subunit.
[0008] Further, the fine adjustment subunit comprises a PMOS tube M2, the gate of the PMOS tube M2 is inputted with an analog tuning voltage signal as the control signal input end of the fine adjustment subunit, the source of the PMOS tube M2 is inputted with a power signal as the power input end of the fine adjustment subunit, and the drain of the PMOS tube M2 is connected with the power input end of the ring oscillation unit as the output end of the fine adjustment subunit.
[0009] Further, the coarse adjustment subunit comprises a plurality of parallel PMOS tubes, the gate of each PMOS tube is inputted with an independent digital tuning control signal as the control signal input end of the coarse adjustment subunit, the source of each PMOS tube is inputted with a power signal as the power input end of the coarse adjustment subunit, and the drain of each PMOS tube is connected with the power input end of the ring oscillation unit as the output end of the coarse adjustment subunit.
[0010] Further, the ring oscillator unit comprises K delay sub-units, K≥2; the positive output end of the 1st to (K-1)th delay sub-units is electrically connected with the positive input end of the next delay sub-unit, and the negative output end of the 1st to (K-1)th delay sub-units is electrically connected with the negative input end of the next delay sub-unit; the positive output end of the Kth delay sub-unit is electrically connected with the negative input end of the 1st delay sub-unit, and the negative output end of the Kth delay sub-unit is electrically connected with the positive input end of the 1st delay sub-unit; the power supply ends of the delay sub-units are electrically connected with each other and connected with the modulated power output end of the power supply and tuning unit as the power input end of the ring oscillator unit.
[0011] Further, the delay sub-unit comprises a first inverter and a second inverter; the input end of the first inverter is connected with the positive input signal INP as the positive input end of the delay sub-unit, and the output end of the first inverter outputs the positive output signal VOP as the positive output end of the delay sub-unit; the input end of the second inverter is connected with the negative input signal INN as the negative input end of the delay sub-unit, and the output end of the second inverter outputs the negative output signal VON as the negative output end of the delay sub-unit; the power supply end of the first inverter and the power supply end of the second inverter are electrically connected with each other and connected with the modulated power output end of the power supply and tuning unit as the power supply end of the delay sub-unit.
[0012] Further, the first inverter comprises a PMOS tube P1 and an NMOS tube N1; the gate of the PMOS tube P1 and the gate of the NMOS tube N1 are electrically connected and connected with the positive input signal INP as the input end of the first inverter, the drain of the PMOS tube P1 and the drain of the NMOS tube N1 are electrically connected and output the positive output signal VOP as the output end of the first inverter, the source of the PMOS tube P1 is connected with the modulated power output end of the power supply and tuning unit as the power supply end of the first inverter, and the source of the NMOS tube N1 is grounded.
[0013] The second inverter comprises a PMOS tube P2 and an NMOS tube N2; the gate of the PMOS tube P2 and the gate of the NMOS tube N2 are electrically connected and connected with the negative input signal INN as the input end of the second inverter, the drain of the PMOS tube P2 and the drain of the NMOS tube N2 are electrically connected and output the negative output signal VON as the output end of the second inverter, the source of the PMOS tube P2 is connected with the modulated power output end of the power supply and tuning unit as the power supply end of the second inverter, and the source of the NMOS tube N2 is grounded.
[0014] Further, the delay subunit further comprises a third inverter and a fourth inverter, an input end of the third inverter is electrically connected with an output end of the fourth inverter, an output end of the third inverter is electrically connected with an output end of the first inverter, an input end of the fourth inverter is electrically connected with an output end of the third inverter, and an output end of the fourth inverter is electrically connected with an output end of the second inverter.
[0015] Further, the third inverter comprises a PMOS tube P3 and an NMOS tube N3, a gate of the PMOS tube P3 is electrically connected with a gate of the NMOS tube N3 and serves as an input end of the third inverter and an output end of the fourth inverter, a drain of the PMOS tube P3 is electrically connected with a drain of the NMOS tube N3 and serves as an output end of the third inverter and an output end of the first inverter, a source of the PMOS tube P3 is electrically connected with a modulation power output end of the power supply and tuning unit, and a source of the NMOS tube N3 is grounded.
[0016] The fourth inverter comprises a PMOS tube P4 and an NMOS tube N4, a gate of the PMOS tube P4 is electrically connected with a gate of the NMOS tube N4 and serves as an input end of the fourth inverter and an output end of the third inverter, a drain of the PMOS tube P4 is electrically connected with a drain of the NMOS tube N4 and serves as an output end of the fourth inverter and an output end of the second inverter, a source of the PMOS tube P4 is electrically connected with a modulation power output end of the power supply and tuning unit, and a source of the NMOS tube N4 is grounded.
[0017] The ring oscillator of the present invention has at least the following beneficial effects: the present invention realizes wide frequency band coverage through the discrete digital tuning control signal of the coarse tuning subunit, and fine tuning is achieved by combining the analog tuning voltage signal of the fine tuning subunit, thereby breaking through the linear limitation of traditional load tuning and expanding the tuning range; the basic power supply subunit provides a constant bias current, and the coarse tuning / fine tuning subunits are connected in parallel to supplement the current as needed, thereby avoiding the static power consumption waste caused by the fixed bias current in the traditional structure, realizing dynamic power consumption management, and thus achieving the coordinated optimization of wide tuning range and low power consumption; the linear superposition of current is realized by the parallel structure of PMOS tubes, and the bias current is controlled by the basic The sum of the basic current output by the power supply subunit and the variable current output by the coarse tuning subunit and the fine tuning subunit is dynamically adjusted to directly control the flipping rate of the delay subunit, avoiding the transconductance stability problem in traditional load tuning and significantly improving the frequency tuning accuracy; the third and fourth inverters are introduced into the delay subunit to form a cross-coupling structure, and positive feedback is used to accelerate signal flipping, making the signal output signal duty cycle more uniform, reducing phase noise, and maintaining low power consumption characteristics; abandoning the traditional tuning method that relies on capacitor / resistor loads, the oscillation frequency is directly adjusted through current control, eliminating the influence of the nonlinearity of transistor parasitic parameters on the tuning curve. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0019] Figure 1 FIG. 4 is a structural diagram of a ring oscillator according to an embodiment of the present invention.
[0020] Figure 2 This is a circuit diagram of an embodiment of a delay subunit of a ring oscillator according to the present invention.
[0021] Figure 3 for Figure 1 Figure 2 shows the simulation results of the ring oscillator output clock tuning frequency range. DETAILED DESCRIPTION
[0022] The present invention will be further described below with reference to the accompanying drawings.
[0023] See also Figure 1The ring oscillator of the present application comprises a power supply and tuning unit 100 and a ring oscillation unit 200. The input end of the power supply and tuning unit 100 is connected to a power supply signal VDD, the modulated power supply output end of the power supply and tuning unit 100 is electrically connected to the power supply input end VCO_VDD of the ring oscillation unit 200, and the signal output end of the ring oscillation unit 200 outputs a differential clock signal (i.e. the positive output signal VOP and the negative output signal VON mentioned below). The power supply and tuning unit 100 is used to output a corresponding bias current according to a tuning control signal, thereby realizing frequency tuning of the ring oscillation unit 200, wherein the tuning control signal comprises an analog tuning voltage signal VCONT and (n-2) digital tuning control signals (S0...Sn-2). n-3 ), n≥3. The number of digital tuning control signals is determined by the required tuning range and the frequency step accuracy.
[0024] The power supply and tuning unit 100 provides a working current for the ring oscillation unit 200, and the current size directly determines the flip rate of the delay sub-unit in the ring oscillation unit 200, i.e. the oscillation frequency. The power supply and tuning unit 100 comprises a basic power supply sub-unit 110, a fine tuning sub-unit 120 and a coarse tuning sub-unit 130. The power supply input ends of the basic power supply sub-unit 110, the fine tuning sub-unit 120 and the coarse tuning sub-unit 130 are connected and serve as the input end of the power supply and tuning unit 100 to connect the power supply signal VDD. The output ends of the basic power supply sub-unit 110, the fine tuning sub-unit 120 and the coarse tuning sub-unit 130 are connected and serve as the modulated power supply output end of the power supply and tuning unit 100 and are electrically connected to the power supply input end VCO_VDD of the ring oscillation unit 200. The control signal input end of the basic power supply sub-unit 110 is connected to the ground GND; the control signal input end of the fine tuning sub-unit 120 is connected to the analog tuning voltage signal VCONT; and the input end of the coarse tuning sub-unit 130 is connected to the digital tuning control signal (S0...Sn-2). n-3 ).
[0025] The basic power supply sub-unit 110 comprises a PMOS transistor M1. The gate of the PMOS transistor M1 serves as the control signal input end of the basic power supply sub-unit 110 and is connected to the ground GND. The PMOS transistor M1 is always on and provides a constant bias current for the ring oscillation unit 200, thereby completing the power supply function. The source of the PMOS transistor M1 serves as the power supply input end of the basic power supply sub-unit 110 and is connected to the power supply signal VDD. The drain of the PMOS transistor M1 serves as the output end of the basic power supply sub-unit 110 and is electrically connected to the power supply input end VCO_VDD of the ring oscillation unit 200.
[0026] The fine tuning subunit 120 comprises a PMOS transistor M2. The gate of the PMOS transistor M2 is connected to an analog tuning voltage signal VCONT as a control signal input of the fine tuning subunit 120 to realize continuous frequency fine tuning. The source of the PMOS transistor M2 is connected to a power supply signal VDD as a power supply input of the fine tuning subunit 120. The drain of the PMOS transistor M2 is electrically connected to a power supply input VCO_VDD of the ring oscillator subunit 200 as an output of the fine tuning subunit 120. Since the PMOS transistor M2 is connected in parallel with the PMOS transistor M1, the bias current of the ring oscillator subunit 200 is the sum of the current I D1 of the PMOS transistor M1 and the current I D2 of the PMOS transistor M2. When the gate of the PMOS transistor M2 is connected to the analog tuning voltage signal VCONT, the current I D2 of the PMOS transistor M2 is:
[0027]
[0028] wherein μ P represents the hole mobility, C ox represents the gate oxide capacitance per unit area, W / L represents the width-length ratio of the PMOS transistor M2, VDD represents the power supply voltage, and V THP represents the threshold voltage of the PMOS transistor. According to the above formula, the size of the analog tuning voltage signal VCONT can control the size of the current I D2 of the PMOS transistor M2, and further control the delay time of the delay subunit in the ring oscillator subunit 200. The oscillation frequency f0 of the differential ring oscillator subunit 200 is:
[0029]
[0030] wherein K represents the number of the delay subunits in the ring oscillator subunit 200, and ΔT represents the delay time of a single delay subunit. Therefore, the size of the analog tuning voltage signal VCONT can ultimately affect the oscillation frequency of the ring oscillator subunit 200, and realize the function of voltage-controlled oscillation frequency.
[0031] The coarse tuning subunit 130 comprises a plurality of PMOS transistors connected in parallel. The gate of each PMOS transistor is connected to an independent digital tuning control signal as a control signal input of the coarse tuning subunit 130 to realize discrete frequency coarse tuning. In the present embodiment, the coarse tuning subunit 130 comprises a PMOS transistor M3 to a PMOS transistor Mn. The gate of the PMOS transistor M3 is connected to a digital tuning control signal S0, and the gate of the PMOS transistor Mn is connected to a digital tuning control signal S n-3The source of each PMOS is connected to the power supply signal VDD as the power input of the coarse tuning subunit 130, and the drain of each PMOS is electrically connected to the power input VCO_VDD of the ring oscillator unit 200 as the output of the coarse tuning subunit 130. According to the tuning principle of the fine tuning subunit 120, it can be known that the digital tuning control signals S0...Sn control the opening and closing of the PMOS M3...PMOS Mn, and further control the bias current and the delay time of the delay subunit, and finally the different control codes can control the different frequency bands of the oscillation frequency of the ring oscillator unit 200. The digital tuning control signals S0...Sn control the opening and closing of the PMOS M3...PMOS Mn, and further control the bias current and the delay time of the delay subunit, and finally the different control codes can control the different frequency bands of the oscillation frequency of the ring oscillator unit 200. n-3 The control of the opening and closing of the PMOS M3...PMOS Mn, and further control the bias current and the delay time of the delay subunit, and finally the different control codes can control the different frequency bands of the oscillation frequency of the ring oscillator unit 200. The digital tuning control signals S0...Sn control the opening and closing of the PMOS M3...PMOS Mn, and further control the bias current and the delay time of the delay subunit, and finally the different control codes can control the different frequency bands of the oscillation frequency of the ring oscillator unit 200. n-3 As a coarse tuning signal to expand the oscillation frequency range of the ring oscillator, the analog tuning voltage signal VCONT is used as a fine tuning signal to finely tune the oscillation frequency to reduce the output jitter of the ring oscillator.
[0032] The ring oscillator unit 200 includes K delay subunits, K≥2, the positive output of the 1st to (K-1)th delay subunits is electrically connected to the positive input of the next delay subunit, and the negative output of the 1st to (K-1)th delay subunits is electrically connected to the negative input of the next delay subunit. The positive output of the Kth delay subunit is electrically connected to the negative input of the 1st delay subunit, and the negative output of the Kth delay subunit is electrically connected to the positive input of the 1st delay subunit. The power supply terminals of each delay subunit are electrically connected to each other and are electrically connected to the power input VCO_VDD of the ring oscillator unit 200 and the modulated power output of the power supply and tuning unit 100. This scheme can further expand the tuning range by increasing the number of delay subunits without modifying the core tuning circuit, reducing the design iteration cost. In this embodiment, K is 2, and the ring oscillator unit 200 includes a first delay subunit 210 and a second delay subunit 220. The positive output of the first delay subunit 210 is electrically connected to the positive input of the second delay subunit 220, and the negative output of the first delay subunit 210 is electrically connected to the negative input of the second delay subunit 220. The positive output of the second delay subunit 220 is electrically connected to the negative input of the first delay subunit 210, and the negative output of the second delay subunit 220 is electrically connected to the positive input of the first delay subunit 210. The power supply terminals of the first delay subunit 210 and the second delay subunit 220 are electrically connected and are electrically connected to the power input VCO_VDD of the ring oscillator unit 200 and the modulated power output of the power supply and tuning unit 100.
[0033] Please refer to Figure 2The delay subunit comprises a first inverter 211 and a second inverter 212. An input end of the first inverter 211 is connected to a positive input signal INP as a positive input end of the delay subunit, and an output end of the first inverter 211 outputs a positive output signal VOP as a positive output end of the delay subunit. An input end of the second inverter 212 is connected to a negative input signal INN as a negative input end of the delay subunit, and an output end of the second inverter 212 outputs a negative output signal VON as a negative output end of the delay subunit. A power supply end of the first inverter 211 and a power supply end of the second inverter 212 are electrically connected to a modulation power output end of the power supply and tuning unit 100 as a power supply end of the delay subunit. The first inverter 211 comprises a PMOS transistor P1 and an NMOS transistor N1. A gate of the PMOS transistor P1 and a gate of the NMOS transistor N1 are electrically connected and connected to the positive input signal INP as an input end of the first inverter 211; a drain of the PMOS transistor P1 and a drain of the NMOS transistor N1 are electrically connected and output the positive output signal VOP as an output end of the first inverter 211; a source of the PMOS transistor P1 is electrically connected to the modulation power output end of the power supply and tuning unit 100 as a power supply end of the first inverter 211, and a source of the NMOS transistor N1 is grounded. The second inverter 212 comprises a PMOS transistor P2 and an NMOS transistor N2. A gate of the PMOS transistor P2 and a gate of the NMOS transistor N2 are electrically connected and connected to the negative input signal INN as an input end of the second inverter 212; a drain of the PMOS transistor P2 and a drain of the NMOS transistor N2 are electrically connected and output the negative output signal VON as an output end of the second inverter 212; a source of the PMOS transistor P2 is electrically connected to the modulation power output end of the power supply and tuning unit 100 as a power supply end of the second inverter 212, and a source of the NMOS transistor N2 is grounded.
[0034] In order to reduce power consumption while accelerating signal flip, as a preferred embodiment, the delay subunit is further provided with a third inverter 213 and a fourth inverter 214. The input end of the third inverter 213 is electrically connected with the output end of the fourth inverter 214, the output end of the third inverter 213 is electrically connected with the output end of the first inverter 211, the input end of the fourth inverter 214 is electrically connected with the output end of the third inverter 213, and the output end of the fourth inverter 214 is electrically connected with the output end of the second inverter 212. The third inverter 213 comprises a PMOS tube P3 and an NMOS tube N3. The gate of the PMOS tube P3 is electrically connected with the gate of the NMOS tube N3 and serves as the input end of the third inverter 213 and the output end of the fourth inverter 214; the drain of the PMOS tube P3 is electrically connected with the drain of the NMOS tube N3 and serves as the output end of the third inverter 213 and the output end of the first inverter 211; the source of the PMOS tube P3 is electrically connected with the modulation power output end of the power supply and tuning unit 100, and the source of the NMOS tube N3 is grounded GND. The fourth inverter 214 comprises a PMOS tube P4 and an NMOS tube N4. The gate of the PMOS tube P4 is electrically connected with the gate of the NMOS tube N4 and serves as the input end of the fourth inverter 214 and the output end of the third inverter 213; the drain of the PMOS tube P4 is electrically connected with the drain of the NMOS tube N4 and serves as the output end of the fourth inverter 214 and the output end of the second inverter 212; the source of the PMOS tube P4 is electrically connected with the modulation power output end of the power supply and tuning unit 100, and the source of the NMOS tube N4 is grounded GND.
[0035] The first inverter 211 phase shifts and delays the positive input signal INP into the positive output signal VOP, and the second inverter 212 phase shifts and delays the negative input signal INN into the negative output signal VON. The third inverter 213 and the fourth inverter 214 constitute a set of cross-coupled inverters, which make the positive output signal VOP and the negative output signal VON flip more quickly and make the output signal duty cycle more uniform when the positive output signal VOP is at the signal rising edge and the negative output signal VON is at the signal falling edge, and when the positive output signal VOP is at the signal falling edge and the negative output signal VON is at the signal rising edge.
[0036] The output clock tuning frequency range simulation result graph of the ring oscillator of the present application is as follows when the 4-bit digital tuning control signal S<3:0> is sequentially changed from 0000 to 1111 under the condition of 65nm CMOS process and 1.2V power supply voltage. Figure 3As shown, the tuning frequency range is 3.86-10.37GHz, the tuning range reaches 91.5%, and the overall power consumption of the circuit is only 2.664mW when outputting a 10GHz clock. The expected effect of the index of the ring oscillator of the application is successfully verified through simulation.
[0037] The application realizes wide frequency band coverage through the discrete digital tuning control signal of the coarse tuning subunit 130, combines the fine tuning of the analog tuning voltage signal of the fine tuning subunit 120, breaks through the linear limitation of traditional load tuning, and expands the tuning range; the constant bias current is provided by the basic current supply subunit 110, the coarse tuning / fine tuning subunit 120 supplements the current in parallel as needed, avoids the waste of static power consumption caused by the fixed bias current in the traditional structure, realizes dynamic power consumption management, and thus realizes the synergistic optimization of wide tuning range and low power consumption; the linear superposition of the current is realized through the parallel structure of the PMOS tube, the bias current is dynamically adjusted by the sum of the basic current output by the basic current supply subunit 110 and the variable current output by the coarse tuning subunit 130 and the fine tuning subunit 120, the flip rate of the delay subunit is directly controlled, the transconductance stability problem in the traditional load tuning is avoided, and the frequency tuning accuracy is significantly improved; the third and fourth inverters 214 are introduced into the delay subunit to form a cross-coupled structure, the signal flip is accelerated by using positive feedback, the signal output signal duty cycle is more uniform, the phase noise is reduced, and the low power consumption characteristic is maintained at the same time; the traditional tuning mode depending on the capacitance / resistance load is abandoned, the oscillation frequency is directly adjusted through current control, and the influence of the nonlinear parasitic parameters of the transistor on the tuning curve is eliminated.
[0038] The above only expresses the preferred embodiments of the application, which are described in detail and in detail, but cannot be understood as limiting the scope of the patent. It should be noted that for ordinary skilled persons in the art, without departing from the concept of the application, a number of modifications and improvements can be made, which are within the scope of the application. Therefore, the protection scope of the patent of the application should be subject to the appended claims.
Claims
1. A ring oscillator, characterized in that: The device comprises a power supply and tuning unit and a ring oscillation unit. The input end of the power supply and tuning unit is connected to a power signal. The modulated power output end of the power supply and tuning unit is electrically connected to the power input end of the ring oscillation unit. The signal output end of the ring oscillation unit outputs a differential clock signal. The power supply and tuning unit is used to output a corresponding bias current according to a tuning control signal, thereby achieving frequency tuning of the ring oscillation unit.
2. The ring oscillator according to claim 1, wherein: The power supply and adjustment unit includes a basic power supply subunit, a fine tuning subunit and a coarse tuning subunit; the power input terminals of the basic power supply subunit, the fine tuning subunit and the coarse tuning subunit are connected and receive a power signal as the input terminal of the power supply and tuning unit, the output terminals of the basic power supply subunit, the fine tuning subunit and the coarse tuning subunit are connected and electrically connected to the power input terminal of the ring oscillation unit as the modulation power output terminal of the power supply and tuning unit, and the control signal input terminal of the basic power supply subunit is grounded; the tuning control signal includes an analog tuning voltage signal and a digital tuning control signal, the control signal input terminal of the fine tuning subunit receives an analog tuning voltage signal, and the input terminal of the coarse tuning subunit receives a digital tuning control signal.
3. The ring oscillator according to claim 2, wherein: The basic power supply subunit includes a PMOS tube M1, the gate of the PMOS tube M1 is grounded as the control signal input terminal of the basic power supply subunit, the source of the PMOS tube M1 is connected to the power signal as the power input terminal of the basic power supply subunit, and the drain of the PMOS tube M1 is electrically connected to the power input terminal of the ring oscillator unit as the output terminal of the basic power supply subunit.
4. The ring oscillator according to claim 2, wherein: The fine tuning subunit includes a PMOS tube M2, the gate of the PMOS tube M2 serves as the control signal input terminal of the fine tuning subunit to receive the analog tuning voltage signal, the source of the PMOS tube M2 serves as the power input terminal of the fine tuning subunit to receive the power signal, and the drain of the PMOS tube M2 serves as the output terminal of the fine tuning subunit to be electrically connected to the power input terminal of the ring oscillation unit.
5. The ring oscillator according to claim 2, wherein: The coarse tuning subunit includes several PMOS tubes connected in parallel, the gate of each PMOS tube serves as the control signal input terminal of the coarse tuning subunit to receive an independent digital tuning control signal, the source of each PMOS tube serves as the power input terminal of the coarse tuning subunit to receive a power signal, and the drain of each PMOS tube serves as the output terminal of the coarse tuning subunit to be electrically connected to the power input terminal of the ring oscillation unit.
6. The ring oscillator according to claim 1, wherein: The ring oscillation unit includes K levels of delay subunits, K≥2; the positive output ends of the delay subunits of the 1st to (K-1)th levels are respectively electrically connected to the positive input ends of the delay subunits of the next level, and the negative output ends of the delay subunits of the 1st to (K-1)th levels are respectively electrically connected to the negative input ends of the delay subunits of the next level; the positive output end of the Kth level delay subunit is electrically connected to the negative input end of the 1st level delay subunit, and the negative output end of the Kth level delay subunit is electrically connected to the positive input end of the 1st level delay subunit, and the power supply ends of each of the delay subunits are electrically connected to each other and serve as the power input end of the ring oscillation unit and are electrically connected to the modulation power output end of the power supply and tuning unit.
7. The ring oscillator according to claim 6, wherein: The delay subunit includes a first inverter and a second inverter. The input end of the first inverter serves as the positive input end of the delay subunit to receive the positive input signal INP, and the output end of the first inverter serves as the positive output end of the delay subunit to output the positive output signal VOP; the input end of the second inverter serves as the negative input end of the delay subunit to receive the negative input signal INN, and the output end of the second inverter serves as the negative output end of the delay subunit to output the negative output signal VON. The power supply end of the first inverter and the power supply end of the second inverter serve together as the power supply end of the delay subunit and are electrically connected to the modulation power supply output end of the power supply and tuning unit.
8. The ring oscillator according to claim 7, wherein: The first inverter includes a PMOS transistor P1 and an NMOS transistor N1; the gate of the PMOS transistor P1 is electrically connected to the gate of the NMOS transistor N1 and serves as an input terminal of the first inverter to receive a positive input signal INP; the drain of the PMOS transistor P1 is electrically connected to the drain of the NMOS transistor N1 and serves as an output terminal of the first inverter to output a positive output signal VOP; the source of the PMOS transistor P1 serves as a power supply terminal of the first inverter and is electrically connected to the modulated power output terminal of the power supply and tuning unit; the source of the NMOS transistor N1 is grounded; The second inverter includes a PMOS transistor P2 and an NMOS transistor N2; the gate of the PMOS transistor P2 is electrically connected to the gate of the NMOS transistor N2 and serves as the input terminal of the second inverter to receive the negative input signal INN; the drain of the PMOS transistor P2 is electrically connected to the drain of the NMOS transistor N2 and serves as the output terminal of the second inverter to output the negative output signal VON; the source of the PMOS transistor P2 serves as the power supply terminal of the second inverter and is electrically connected to the modulated power supply output terminal of the power supply and tuning unit; the source of the NMOS transistor N2 is grounded.
9. The ring oscillator according to claim 7, wherein: The delay subunit further includes a third inverter and a fourth inverter, wherein the input end of the third inverter is electrically connected to the output end of the fourth inverter, the output end of the third inverter is electrically connected to the output end of the first inverter, the input end of the fourth inverter is electrically connected to the output end of the third inverter, and the output end of the fourth inverter is electrically connected to the output end of the second inverter.
10. The ring oscillator according to claim 9, wherein: The third inverter includes a PMOS transistor P3 and an NMOS transistor N3; the gate of the PMOS transistor P3 is electrically connected to the gate of the NMOS transistor N3 and serves as the input of the third inverter and is electrically connected to the output of the fourth inverter; the drain of the PMOS transistor P3 is electrically connected to the drain of the NMOS transistor N3 and serves as the output of the third inverter and is electrically connected to the output of the first inverter; the source of the PMOS transistor P3 is electrically connected to the modulated power output of the power supply and tuning unit; and the source of the NMOS transistor N3 is grounded; The fourth inverter includes a PMOS transistor P4 and an NMOS transistor N4; the gate of the PMOS transistor P4 is electrically connected to the gate of the NMOS transistor N4 and is electrically connected to the output of the third inverter as the input of the fourth inverter; the drain of the PMOS transistor P4 is electrically connected to the drain of the NMOS transistor N4 and is electrically connected to the output of the second inverter as the output of the fourth inverter; the source of the PMOS transistor P4 is electrically connected to the modulated power output of the power supply and tuning unit; and the source of the NMOS transistor N4 is grounded.