Decoding method for reducing noise influence of power signal line and decoding circuit thereof

Abstract

The invention provides a decoding method for reducing the noise influence of a power signal line and a decoding circuit thereof. The method comprises the following steps of: comparing a voltage level of an analog signal to be decoded with a plurality of reference voltages to generate a current level number; performing an edge detection program by using the current order number at each time to obtain a first edge detection signal; setting a current level number smaller than a low level number in the current level numbers at each time as the low level number, and then performing the edge detection program to obtain a second edge detection signal; after setting the current order number greater than a high order number in the current order numbers at each time as the high order number, performing the edge detection program to obtain a third edge detection signal; and decoding the first edge detection signal, the second edge detection signal and the third edge detection signal to obtain an optimal edge detection signal with the minimum difference.

Description

TECHNICAL FIELD

[0001] The present application relates to a noise suppression technique, and in particular, to a decoding method and decoding circuit for reducing the effect of power signal line noise. BACKGROUND

[0002] Automatic charging is a popular device at present, and the Universal Serial Bus Power Delivery (USB PD) protocol is the most commonly used transmission specification. In addition to charging and discharging through the power flat cable pressure point (VBUS pin), another related interface signal is on the channel configuration pressure point (CC pin). During data transmission (bit rate about 300K / s), the voltage level of the channel configuration pressure point (CC pin) is about 1.1V. Therefore, if any noise is disturbed during transmission, it will affect the effect of correctly receiving data during information transmission in the Universal Serial Bus Power Delivery.

[0003] The Universal Serial Bus Power Delivery protocol not only includes power, but also handles the coordination of data flow, data format and master-slave relationship between two devices. Through the transmission of the channel configuration pressure point, when converted into a digital signal, its data packet also includes cyclic redundancy check calculation and comparison to avoid using incorrect packet data caused by noise.

[0004] Therefore, in the known noise authentication process, the following three different noise authentication conditions are included:

[0005] Test noise conditions

[0006] From the above three different noise authentication conditions, it can be seen that the DC voltage level will drift up or down due to different test conditions. SUMMARY

[0007] The present application provides a decoding method for reducing the effect of power signal line noise, and a decoding circuit used thereby and a power supply / receiving device used thereby, to adjust the edge detection strategy before demodulation in the case of known signals, thereby overcoming the above noise conditions before the subsequent carrier is demodulated into a digital signal, so as to solve the correct digital signal.

[0008] Embodiments of the present application provide a decoding method for reducing the effect of power supply signal line noise. The decoding method includes comparing the voltage level of an analog signal to be decoded with a plurality of reference voltages to generate a current bit level; performing an edge detection procedure on the current bit level at each time to obtain a first edge detection signal; performing the edge detection procedure on the current bit level at each time after setting the current bit level less than a low bit level to the low bit level to obtain a second edge detection signal; performing the edge detection procedure on the current bit level at each time after setting the current bit level greater than a high bit level to the high bit level to obtain a third edge detection signal; decoding the first, second and third edge detection signals to obtain first, second and third bit restoration signals, and comparing the first, second and third bit restoration signals with bit time length specifications in a decoding specification to obtain a best bit restoration signal with the least difference; and selecting a best edge detection signal from the first, second and third edge detection signals by using the best bit restoration signal as an edge detection signal for subsequent decoding, wherein the analog signal to be decoded is obtained according to a known signal transmission.

[0009] Embodiments of the present application provide a decoding circuit. The decoding circuit includes a plurality of comparators, a noise filtering and signal edge detection circuit, and a digital signal information processing circuit. The plurality of comparators include a first end, a second end, and an output end. The first end of the plurality of comparators receives an analog signal to be decoded. The second end of the plurality of comparators is coupled to one of a plurality of reference voltage levels, wherein the plurality of reference voltage levels are all different. The noise filtering and signal edge detection circuit is coupled to the output end of the plurality of comparators to output a best edge detection signal. The digital signal information processing circuit is coupled to the output end of the noise filtering and signal edge detection circuit to generate a decoded signal according to the best edge detection signal.

[0010] The noise filter and signal edge detection circuit judges the current level of the analog signal to be decoded according to the signal outputted from the output terminal of the comparator to obtain a current level digital number. The noise filter and signal edge detection circuit performs an edge detection procedure according to the current level digital number at each time to obtain a first edge detection signal. The noise filter and signal edge detection circuit performs the edge detection procedure after setting the current level digital number less than a low level digital number to the low level digital number to obtain a second edge detection signal. The noise filter and signal edge detection circuit performs the edge detection procedure after setting the current level digital number greater than a high level digital number to the high level digital number to obtain a third edge detection signal. The digital signal information processing circuit coupled to the output terminal of the noise filter and signal edge detection circuit decodes the first edge detection signal, the second edge detection signal and the third edge detection signal to obtain a first bit restoration signal, a second bit restoration signal and a third bit restoration signal, and compares the first bit restoration signal, the second bit restoration signal and the third bit restoration signal with the bit time length specification in the decoding specification to obtain a best bit restoration signal with the least difference, wherein the digital signal information processing circuit selects a best edge detection signal corresponding to the first edge detection signal, the second edge detection signal and the third edge detection signal according to the best bit restoration signal as an edge detection signal for subsequent decoding, and wherein the analog signal to be decoded is obtained according to a known signal transmission.

[0011] The method for reducing the influence of power signal line noise on decoding and the decoding circuit using the same according to the preferred embodiment of the present application, the analog signal to be decoded is obtained from a channel configuration voltage point (CC pin) of a universal serial bus port. In a preferred embodiment of the present application, the analog signal to be decoded is modulated according to a bi-phase mark code.

[0012] For a further understanding of the technical solutions, means and effects of the present application, reference can be made to the following detailed description and accompanying drawings, so that the purpose, features and concepts of the present application can be thoroughly and specifically understood. However, the following detailed description and accompanying drawings are only used for reference and illustration of the implementation of the present application, and are not used to limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0013] The accompanying drawings provided to further enable those skilled in the art to understand the present application, and are incorporated in and constitute a part of the specification, illustrate embodiments of the present application and serve to explain the principles of the present application. The drawings are as follows:

[0014] Figure 1A system block diagram of a power supply providing / receiving device according to a preferred embodiment of the present application is shown.

[0015] Figure 2 A circuit diagram of the analog circuit block 104 according to a preferred embodiment of the present application is shown.

[0016] Figure 3 An operation flow chart of the noise filtering and signal edge detection circuit 105 according to a preferred embodiment of the present application in performing the current bit level in_level is shown.

[0017] Figure 4 An operation flow chart of the noise filtering and signal edge detection circuit 105 according to a preferred embodiment of the present application in performing the highest bit level variable Hi_count and the lowest bit level variable Low_count is shown.

[0018] Figure 5 An operation waveform diagram of the noise filtering and signal edge detection circuit 105 according to a preferred embodiment of the present application is shown.

[0019] Figure 6 An operation waveform diagram of the noise filtering and signal edge detection circuit 105 according to a preferred embodiment of the present application is shown.

[0020] Figure 7 An operation waveform diagram of the first comparator 201, the second comparator 202 and the third comparator 203 when encountering noise according to a preferred embodiment of the present application is shown.

[0021] Figure 8 An operation waveform diagram of the noise filtering and signal edge detection circuit 105 according to a preferred embodiment of the present application is shown.

[0022] Figure 9 A circuit block diagram of the noise filtering and signal edge detection circuit 105 according to a preferred embodiment of the present application is shown.

[0023] Figure 10 A flow chart of a method for reducing the effect of power signal line noise on decoding according to a preferred embodiment of the present application is shown.

[0024] Figure 11 A flow chart of an edge detection procedure of a method for reducing the effect of power signal line noise on decoding according to a preferred embodiment of the present application is shown.

[0025] Legend of symbols

[0026] 101: Universal Serial Bus

[0027] 102: Decoding circuit

[0028] 103: Power supply providing / receiving circuit

[0029] CCpin: channel configuration pressure point

[0030] 104: Analog circuit block

[0031] 105: Noise filtering and signal edge detection circuit

[0032] 106: Digital signal information processing circuit

[0033] Bit_OUT: edge detection signal

[0034] 201-203: Comparator

[0035] Analog_RCed: analog signal to be decoded

[0036] HTH, MTH, LTH: Reference voltage level

[0037] Comparator_Slice OUT[2]: comparison signal outputted by the output terminal of the first comparator 201

[0038] Comparator_Slice OUT[1]: comparison signal outputted by the output terminal of the second comparator 202

[0039] Comparator_Slice OUT[0]: comparison signal outputted by the output terminal of the third comparator 203

[0040] Hi_count: highest level variable

[0041] Low_cout: lowest level variable

[0042] in_level: current level number

[0043] S301~S308: Steps

[0044] S401~S407:Steps

[0045] Edge_detected: The edge detection pulse output by the noise filtering and signal edge detection circuit 105

[0046] 701, 702, 703, 704: Noise pulses

[0047] 901: First processing path

[0048] 902: Second processing path

[0049] 903: Third processing path

[0050] 904: Digital Signal Information Processing Circuit

[0051] Vedge1: first edge detection signal

[0052] Vedge2: second edge detection signal

[0053] Vedge3: third edge detection signal

[0054] S1001-S1007: flow steps of the method for reducing the influence of power signal line noise on decoding in a preferred embodiment of the present application

[0055] S1101-S1105: flow steps of the edge detection procedure of the method for reducing the influence of power signal line noise on decoding in a preferred embodiment of the present application DETAILED DESCRIPTION

[0056] Reference will now be made in detail to the exemplary embodiments of the present application, which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. In addition, the exemplary embodiments are merely one of the design concepts of the present application, and the following exemplary embodiments are not intended to limit the present application.

[0057] Figure 1 A system block diagram of a power supply / receiving device in a preferred embodiment of the present application is shown. Please refer to Figure 1 In this embodiment, a power supply / receiving device in accordance with the Universal Serial Bus Power Delivery (USB-PD) protocol is exemplified. The power supply / receiving device includes a Universal Serial Bus (USB) 101, a decoding circuit 102, and a power supply / receiving circuit 103. The USB 101 includes a Channel Configuration (CC) pin. The decoding circuit 102 includes an analog circuit block 104, a noise filtering and signal edge detection circuit 105, and a digital signal information processing circuit 106. The power supply / receiving circuit 103 is coupled to the USB 101 and the decoding circuit 102, receives an edge detection signal Bit_OUT (packet data bit output) provided by the decoding circuit 102, and thereby communicates the power supply capability and demand with a device coupled to the other end of the USB 101. Because of the reception of data, in the USB-PD system, in addition to the voltage signal inputted through the CC pin, digital sampling processing is also performed to convert the noise-eliminated real digital information data, so as to facilitate the decoding of the content on the data packet.

[0058] Figure 2 A circuit diagram of the analog circuit block 104 in a preferred embodiment of the present application is shown. Please refer to Figure 2In this embodiment, the analog circuit block 104 comprises a first comparator 201, a second comparator 202 and a third comparator 203. Each of the comparators 201, 202 and 203 comprises a first end, a second end and an output end. The first end of each of the comparators 201, 202 and 203 receives the analog signal Analog_RCed to be decoded obtained from the channel configuration voltage pin CCpin. The second end of each of the comparators 201, 202 and 203 is coupled to a corresponding reference voltage level HTH (High Threshold), MTH (Middle Threshold) and LTH (Low Threshold) respectively. The output signals of the comparators 201, 202 and 203 are denoted as Comparator_Slice OUT[2], Comparator_Slice OUT[1] and Comparator_Slice OUT[0] respectively.

[0059] The noise filtering and signal edge detection circuit 105 is coupled to the output ends of the comparators 201, 202 and 203. In the noise filtering and signal edge detection circuit 105, three variables are set, which are the highest bit variable Hi_count, the lowest bit variable Low_count and the current level number in_level.

[0060] Figure 3 The operation flow chart of the noise filtering and signal edge detection circuit 105, which is a preferred embodiment of the present application, in performing the current level number in_level is shown. Please refer to Figure 3 In this embodiment, the operation of the noise filtering and signal edge detection circuit 105 in performing the current level number in_level comprises the following steps:

[0061] Step S301: initial reset.

[0062] Step S302: determine whether the signal Comparator_Slice OUT[2] at the output end of the comparator 201 is a logic high voltage. If the determination is yes, proceed to step S305. If the determination is no, proceed to step S303.

[0063] Step S303: determine whether the signal Comparator_Slice OUT[1] at the output end of the comparator 202 is a logic high voltage. If the determination is yes, proceed to step S306. If the determination is no, proceed to step S304.

[0064] Step S304: Determine whether the signal Comparator_Slice OUT[0] at the output terminal of the comparator 203 is a logic high voltage. If the determination is yes, proceed to step S307. If the determination is no, proceed to step S308.

[0065] Step S305: Set the current level number in_level to the three-digit number 011.

[0066] Step S306: Set the current level number in_level to the three-digit number 010.

[0067] Step S307: Set the current level number in_level to the three-digit number 001.

[0068] Step S308: Set the current level number in_level to the three-digit number 000.

[0069] The running time (sampling time) of the above flow steps can be designed according to different requirements, and will not be described here.

[0070] Figure 4 The noise filtering and signal edge detection circuit 105 of a preferred embodiment of the present application is shown in the operation flowchart of the highest level variable Hi_count and the lowest level variable Low_cout. Please refer to Figure 4 The operation of the noise filtering and signal edge detection circuit 105 of the highest level variable Hi_count and the lowest level variable Low_cout includes the following steps:

[0071] Step S401: Initial reset. Set the highest level variable Hi_count and the lowest level variable Low_cout to 0.

[0072] Step S402: Input the current level number in_level.

[0073] Step S403: Determine whether the current level number in_level is greater than the highest level variable Hi_count. If the determination is yes, proceed to step S405.

[0074] Step S404: Determine whether the current level number in_level is less than the lowest level variable Low_cout. If the determination is yes, proceed to step S406.

[0075] Step S405: Set the highest level variable Hi_count to the current level number in_level. Then, proceed to step S407.

[0076] Step S406: Set the lowest bit variable Low_cout to the current bit number in_level. Then, proceed to step S407.

[0077] Step S407: Determine whether the difference between the highest bit variable Hi_count and the lowest bit variable Low_cout is greater than a noise tolerance difference. In this embodiment, the noise tolerance difference is set to 1. When the difference between the highest bit variable Hi_count and the lowest bit variable Low_cout is greater than the noise tolerance difference, the noise filter and signal edge detection circuit 105 is triggered to output an edge detection pulse, and the highest bit variable Hi_count and the lowest bit variable Low_cout are set to the current bit number in_level.

[0078] Figure 5 The operation waveform diagram of the noise filter and signal edge detection circuit 105, which is a preferred embodiment of the present application, is shown in FIG. 4. Please refer to Figure 5 , in order to allow those skilled in the art to understand the above-mentioned embodiments of Figure 3 , Figure 4 , the variable visualization graph is used to mark the change of the variable on the graph. As can be seen, at the beginning, when the signal Comparator_Slice OUT[0] at the output end of the comparator 203 changes from a logic low voltage to a logic high voltage, the highest bit variable Hi_count becomes 1, the lowest bit variable Low_cout remains 0, and the current bit number in_level changes from 0 to 1 via the flow of Figure 4 . Next, when the signal Comparator_Slice OUT[1] at the output end of the comparator 202 changes from a logic low voltage to a logic high voltage, the highest bit variable Hi_count becomes 2, the lowest bit variable Low_cout remains 0, and the current bit number in_level changes from 1 to 2 via the flow of Figure 4 . Since step S407 is triggered at this time, the noise filter and signal edge detection circuit 105 outputs an edge detection pulse, and the highest bit variable Hi_count becomes 2, the lowest bit variable Low_cout also changes to 2, and the current bit number in_level becomes 2.

[0079] Next, when the signal Comparator_Slice OUT[2] at the output end of the comparator 203 changes from a logic low voltage to a logic high voltage, the highest bit variable Hi_count becomes 3, the lowest bit variable Low_cout remains 2, and the current bit number in_level changes from 2 to 3 via the flow of Figure 4In the process, the highest level variable Hi_count will become 3, the lowest level variable Low_cout will maintain 2, and the current level number in_level will change from 2 to 3. Then, when the signal Comparator_Slice OUT[2] at the output end of the comparator 203 changes from a logic high voltage to a logic low voltage, Figure 4 In the process, the highest level variable Hi_count will maintain 3, the lowest level variable Low_cout will maintain 2, and the current level number in_level will change from 3 to 2. When the signal Comparator_Slice OUT[1] at the output end of the comparator 202 changes from a logic high voltage to a logic low voltage, Figure 4 In the process, the highest-level variable Hi_count remains at 3, the lowest-level variable Low_cout becomes 1, and the current-level number in_level changes from 2 to 1. Similarly, at this time, since step S407 is triggered, the noise filtering and signal edge detection circuit 105 outputs an edge detection pulse, and the highest-level variable Hi_count becomes 1, the lowest-level variable Low_cout also changes to 1, and the current-level number in_level becomes 1.

[0080] Next, when the signal Comparator_Slice OUT[0] at the output terminal of the comparator 201 changes from a logic high voltage to a logic low voltage, Figure 4 In the process, the highest level variable Hi_count will maintain 1, the lowest level variable Low_cout will become 0, and the current level number in_level will change from 1 to 0. Then, when the signal Comparator_Slice OUT[0] at the output end of the comparator 201 changes from a logic low voltage to a logic high voltage, Figure 4 In the process, the highest level variable Hi_count will maintain 1, the lowest level variable Low_cout will maintain 0, and the current level number in_level will change from 0 to 1. The following embodiments can be deduced from the above rules. Therefore, they will not be described in detail here.

[0081] Figure 6 FIG2 is a waveform diagram of the operation of the noise filtering and signal edge detection circuit 105 according to a preferred embodiment of the present application. Figure 6 , where Edge_detected is the edge detection pulse output by the noise filtering and signal edge detection circuit 105. Bit_OUT is the noise-eliminated edge detection signal Bit_OUT decoded by the digital signal processing circuit 106 based on the edge detection pulse output by the noise filtering and signal edge detection circuit 105.

[0082] Figure 7 The operation waveform diagram of the first comparator 201, the second comparator 202, and the third comparator 203 when encountering noise is shown as a preferred embodiment of the present application. Please refer to Figure 7 In this embodiment, it can be seen that when the analog signal Analog_RCed to be decoded encounters noise passing through the reference voltage levels HTH, MTH, and LTH, the comparators 201, 202, 203 are triggered to change, resulting in the comparators 201, 202, 203 outputting inappropriate noise pulses 701, 702, 703, 704.

[0083] Figure 8 The operation waveform diagram of the noise filtering and signal edge detection circuit 105 is shown as a preferred embodiment of the present application. Please refer to Figure 8 In this embodiment, it can be seen that before the time of label 701, the highest bit variable Hi_count and the lowest bit variable Low_cout are both set to 1 due to the triggering of step S407. Therefore, at the time of label 701, the highest bit variable Hi_count changes to 2, and the lowest bit variable Low_cout remains at 1, so the noise filtering and signal edge detection circuit 105 is not triggered to output an edge detection pulse. By the same token, at the time of label 703, the highest bit variable Hi_count is 1, and the lowest bit variable Low_cout remains at 0, so the noise filtering and signal edge detection circuit 105 is not triggered to output an edge detection pulse. At the time of label 704, the highest bit variable Hi_count is 2, and the lowest bit variable Low_cout remains at 2, so the noise filtering and signal edge detection circuit 105 is also not triggered to output an edge detection pulse.

[0084] The above embodiments are for those skilled in the art to understand the present application, so three comparators 201, 202, 203 and three values are used as examples, and the noise tolerance difference is simply set to 1. However, those skilled in the art should understand that the more comparators are designed, the more digital designs are made, and the noise tolerance difference is also designed to be larger, so that more accurate noise filtering results can be obtained. In addition, although the above embodiments are exemplified by the Universal Serial Bus Power Delivery (USB PD) protocol, and the Bi-Phase Marker Coded (BMC) decoding is used as an example. However, those skilled in the art should know that other encoding methods in other application fields, such as Manchester encoding, can also use the decoding and noise filtering techniques of the present application, so the present application is not limited thereto.

[0085] The above embodiment is an edge detection technique for noise elimination of a burst pulse. However, there are also three types of DC noise as described in the prior art, i.e. the DC voltage amplitude of an external signal, which often causes the voltage of the input signal to deviate from the allowed logic voltage level, further causing errors in decoding. In the following embodiment, the above edge detection method is also used. The difference is that the noise filter and signal edge detection circuit 105 is optimized according to the above-processed DC noise.

[0086] Figure 9 A circuit block diagram of the noise filter and signal edge detection circuit 105 according to a preferred embodiment of the present application is shown. Referring to Figure 9 The noise filter and signal edge detection circuit 105 includes a first processing path 901, a second processing path 902, and a third processing path 903. In order to allow those skilled in the art to understand the technology, a digital signal information processing circuit 904 is also shown in the diagram to decode the edge detection signals Vedge1, Vedge2, Vedge3 output by the above-mentioned first processing path 901, second processing path 902, and third processing path 903. In order to make the decoded signals of the first processing path 901, second processing path 902, and third processing path 903 predictable, in this embodiment, the analog signal Analog_RCed to be decoded is a transmitted known signal, and in this case, the preferred choice is a preamble. Since the preamble is a 64-bit 010101 interleaved signal, the ideal decoded signals of the edge detection signals Vedge1, Vedge2, Vedge3 are all predictable.

[0087] In this embodiment, the first processing path 901, second processing path 902, and third processing path 903 all use the above-mentioned Figures 1 to 8The noise filtering and signal edge detection techniques are illustrated. Since this embodiment is not directed to noise filtering, other edge detection techniques can still be used by those skilled in the art. In this embodiment, the first processing path 901 receives the signals Comparator_Slice OUT[0], Comparator_Slice OUT[1], Comparator_Slice OUT[2] from the outputs of the comparators 201, 202, 203 to generate the first edge detection signal Vedge 1 ; the second processing path 902 receives the comparison signals Comparator_Slice OUT[1], Comparator_Slice OUT[2] from the outputs of the comparators 202, 203 and the low-order bit stage voltage VH which is constantly set to logic 1 to generate the second edge detection signal Vedge 2; and the third processing path 903 receives the comparison signals Comparator_Slice OUT[0], Comparator_Slice OUT[1] from the outputs of the comparators 201, 202 and the high-order bit stage voltage V0 which is constantly set to logic 0 to generate the third edge detection signal Vedge 3.

[0088] As can be seen from the above embodiment, the second processing path 902 is equivalent to setting a lower limit for the current bit stage number in_level, which is referred to as the low-order bit stage number. For example, in the case of the noise authentication condition TX_GROUP_3, the logic low voltage is forced to rise to 250 mV, so in this case, the second bit restoration signal decoded by the second edge detection signal Vedge 2 generated by the second processing path 902 is closer to the ideal bit restoration signal. Similarly, the third processing path 903 is equivalent to setting an upper limit for the current bit stage number in_level, which is referred to as the high-order bit stage number. For example, in the case of the noise authentication condition TX_GROUP_2, the logic high voltage is forced to drop to 790 mV, so in this case, the third bit restoration signal decoded by the third edge detection signal Vedge 3 generated by the third processing path 903 is closer to the ideal bit restoration signal. Similarly, the first processing path 901 is equivalent to performing edge detection in the normal manner. For example, in the case of the noise authentication condition TX_GROUP_1, the logic high voltage is forced to rise to 1200 mV and the logic low voltage remains unchanged, so in this case, the first bit restoration signal decoded by the first edge detection signal Vedge 1 generated by the first processing path 901 is closer to the ideal bit restoration signal.

[0089] The digital signal information processing circuit 904 receives the first edge detection signal Vedgei, the second edge detection signal Vedge2, and the third edge detection signal Vedge3, decodes the first edge detection signal Vedgei, the second edge detection signal Vedge2, and the third edge detection signal Vedge3 to obtain the first bit restoration signal, the second bit restoration signal, and the third bit restoration signal, and compares the bit time length of the first bit restoration signal, the second bit restoration signal, and the third bit restoration signal with the standard bit time length in the decoding specification to obtain the bit restoration signal with the minimum difference. For example, if the bit rate is 270K and the frequency is 12MHz, one bit is about 44.4 frequency lengths. Therefore, the edge detection signal Vedgei, Vedge2, or Vedge3 corresponding to the decoded bit restoration signal with the minimum difference can be found by finding the decoded bit restoration signal with the minimum difference from the 44.4 frequency lengths. In this way, the subsequent data can use the optimal edge detection signal Vedgei, Vedge2, or Vedge3 selected by the above method as the edge detection signal for subsequent decoding.

[0090] Figure 10 A flow chart of a method for reducing the influence of power signal line noise on decoding, which is a preferred embodiment of the present application, is shown. Please refer to Figure 10 The method for reducing the influence of power signal line noise on decoding includes the following steps:

[0091] Step S1001: Start.

[0092] Step S1002: Compare the voltage level of an analog signal to be decoded with a plurality of reference voltages to generate a current bit level. In this embodiment, the analog signal to be decoded is a preamble signal. Since the preamble signal is a known signal, the decoded bits can also be predicted. Therefore, the preamble signal is used as an example in the preferred embodiment, and other known signals can also be used as examples in the technical field. Details are not described herein.

[0093] Step S1003: Perform an edge detection process using the current bit level at each time to obtain a first edge detection signal. The first processing path 901 is described above.

[0094] Step S1004: Perform the edge detection process after setting the current bit level less than a low bit level to the low bit level in the current bit level at each time to obtain a second edge detection signal. The second processing path 902 is described above.

[0095] Step S1005: setting the current level number greater than a high level number among the current level numbers of each time to the high level number, and performing the edge detection procedure to obtain a third edge detection signal. As the third processing path 903 described above.

[0096] Step S1006: decoding the first edge detection signal, the second edge detection signal and the third edge detection signal to obtain a first bit restoration signal, a second bit restoration signal and a third bit restoration signal, and comparing the first bit restoration signal, the second bit restoration signal and the third bit restoration signal with bit time length specifications in a decoding specification to obtain a best bit restoration signal with the least difference.

[0097] Step S1007: selecting a best edge detection signal from the first edge detection signal, the second edge detection signal and the third edge detection signal as an edge detection signal for subsequent decoding by means of the best bit restoration signal.

[0098] Figure 11 A flow chart of the edge detection procedure of the method for reducing the influence of power signal line noise on decoding according to a preferred embodiment of the present application is shown in FIG. 11. Referring to FIG. 11, the edge detection procedure includes the following steps: Figure 11

[0099] Step S1101: dividing the voltage level of an analog signal to be decoded into a plurality of levels. As described above in the preferred embodiment, a plurality of comparators are used to detect the voltage levels of the analog signal to be decoded. Figure 2

[0100] Step S1102: sequentially assigning a difference number to the plurality of levels. As described above in the preferred embodiment, 1, 2 and 3 are used as examples, and those skilled in the art can also use 2, 4, 6, etc. without limitation, and the numbers can be changed according to the difference between the levels.

[0101] Step S1103: judging the voltage level of the analog signal to be decoded and obtaining a current level number of the analog signal to be decoded. As described above, the method can be used. Figure 3

[0102] Step S1104: updating a highest level variable when the current level number is greater than the highest level variable, and updating a lowest level variable when the current level number is less than the lowest level variable. As described above in steps S403-S406 of the preferred embodiment.

[0103] ​​​Step S1105: When the difference between the lowest bit stage variable and the highest bit stage variable is greater than a noise tolerance difference value, output an edge detection pulse, and set the highest bit stage variable and the lowest bit stage variable to be the current bit stage number, and continue to judge the level of the analog signal to be decoded to obtain the current bit stage number.

[0104] In summary, the embodiments of the present application use a known signal, and through a plurality of comparators and a plurality of reference voltages, respectively sample the received signal to be decoded to convert into a current bit stage number to generate a first edge detection signal. And at the same time, set the current bit stage number to a low bit stage number as a lower limit to generate a second edge detection signal, and set the current bit stage number to a high bit stage number as an upper limit to generate a third edge detection signal, through the above three groups of edge detection signals, respectively decode and compare with the known signal to obtain the best edge detection signal, thereby subsequent decoding can be performed using the best edge detection signal. Therefore, the present application can solve the bit misjudgment caused by DC noise.

[0105] In addition, in the preferred embodiment, the edge detection procedure uses setting a plurality of levels, and defines the values corresponding to the plurality of levels, the current bit stage number, the highest bit stage variable and the lowest bit stage variable, and detects the time when the analog signal to be decoded reaches the plurality of levels, changes the current bit stage number, the highest bit stage variable and the lowest bit stage variable according to the bit stage reached by the analog signal to be decoded, when the difference between the highest bit stage variable and the lowest bit stage variable is greater than a noise tolerance difference value, triggers an edge detection pulse and sets the highest bit stage variable and the lowest bit stage variable to be equal to the current bit stage number, thereby even if the difference between the highest bit stage variable and the lowest bit stage variable is affected by noise, as long as it is less than the noise tolerance difference value, it will not cause any impact on the operation of the circuit.

[0106] It should be understood that the examples and embodiments described herein are for illustrative purposes only, and various modifications or changes will be suggested to one skilled in the art in light of this, and will be included within the spirit and scope of the present application and the scope of the appended claims.

Claims

1. A decoding method for reducing the influence of power signal line noise, characterized in that: include: Comparing the voltage level of an analog signal to be decoded with a plurality of reference voltages to generate a current level digital; Performing an edge detection process using the current level number at each time to obtain a first edge detection signal; After setting the current level number at each time point, which is smaller than a lower level number, as the lower level number, the edge detection process is performed to obtain a second edge detection signal; After setting the current level number greater than a higher-level level number among the current level numbers at each time as the higher-level level number, the edge detection process is performed to obtain a third edge detection signal; Decoding the first edge detection signal, the second edge detection signal, and the third edge detection signal to obtain a first bit restoration signal, a second bit restoration signal, and a third bit restoration signal; and comparing the first bit restoration signal, the second bit restoration signal, and the third bit restoration signal with a bit time length to obtain an optimal bit restoration signal with a minimum difference; By using the best bit restoration signal, an optimal edge detection signal is selected from the first edge detection signal, the second edge detection signal and the third edge detection signal as a specific edge detection signal for subsequent decoding. The analog signal to be decoded is obtained by transmitting a known signal.

2. The decoding method for reducing the influence of power signal line noise according to claim 1, characterized in that: The edge detection procedure includes: When the current level number is greater than a highest level variable, updating the highest level variable; When the current level number is less than a lowest level variable, updating the lowest level variable; and When the difference between the lowest-level variable and the highest-level variable is greater than a noise tolerance difference, an edge detection pulse is output, the highest-level variable and the lowest-level variable are set as the current-level number, and the level of the analog signal to be decoded is continuously determined to obtain the current-level number; and The specific edge detection signal is generated according to the edge detection pulse.

3. The decoding method for reducing the influence of power signal line noise according to claim 1, characterized in that: The analog signal to be decoded is obtained from a channel configuration voltage point of a universal serial bus connection port.

4. The decoding method for reducing the influence of power signal line noise according to claim 1, wherein: The analog signal to be decoded is modulated according to a bi-phase mark code.

5. The decoding method for reducing the influence of power signal line noise according to claim 1, characterized in that: The known signal is a preamble signal.

6. A decoding circuit, characterized in that: include: a plurality of comparators, wherein each of the plurality of comparators includes a first terminal, a second terminal, and an output terminal, the first terminals of the plurality of comparators receiving an analog signal to be decoded, and the second terminals of the plurality of comparators respectively coupled to a plurality of reference voltage levels, wherein the plurality of reference voltage levels are different; and a noise filtering and signal edge detection circuit, coupled to the output terminals of the plurality of comparators; The noise filtering and signal edge detection circuit determines the current level of the analog signal to be decoded according to the signal outputted by the output terminal of the comparator to obtain a current level number; wherein the noise filtering and signal edge detection circuit performs an edge detection process according to the current level number at each time to obtain a first edge detection signal; wherein the noise filtering and signal edge detection circuit sets the current level number of each time point, which is smaller than a lower level number, as the lower level number, and then performs the edge detection process to obtain a second edge detection signal; wherein the noise filtering and signal edge detection circuit sets the current level number greater than a higher-level level number among the current level numbers at each time as the higher-level level number, and then performs the edge detection process to obtain a third edge detection signal; Wherein, the decoding circuit further includes: a digital signal information processing circuit coupled to the output terminal of the noise filtering and signal edge detection circuit, decoding the first edge detection signal, the second edge detection signal, and the third edge detection signal to obtain a first bit restoration signal, a second bit restoration signal, and a third bit restoration signal; and comparing the first bit restoration signal, the second bit restoration signal, and the third bit restoration signal with a bit time length to obtain an optimal bit restoration signal with the minimum difference therefrom; The digital signal information processing circuit selects a corresponding best edge detection signal from the first edge detection signal, the second edge detection signal, and the third edge detection signal according to the best bit restoration signal as a specific edge detection signal for subsequent decoding. The analog signal to be decoded is obtained by transmitting a known signal.

7. The decoding circuit according to claim 6, wherein: The analog signal to be decoded is obtained from a channel configuration voltage point of a universal serial bus connection port.

8. The decoding circuit according to claim 6, wherein: The analog signal to be decoded is modulated according to a bi-phase mark code, and the digital signal information processing circuit is a bi-phase mark code decoding circuit.

9. The decoding circuit according to claim 6, wherein: The noise filtering and signal edge detection circuit determines the current level of the analog signal to be decoded according to the signal outputted by the output terminal of the comparator to obtain the current level number; The noise filtering and signal edge detection circuit has a highest-order variable and a lowest-order variable inside; When the current level number is greater than a highest level variable, the highest level variable is updated to be the current level number; When the current level number is less than a lowest level variable, the lowest level variable is updated to the current level number. Among them, when the difference between the lowest-level variable and the highest-level variable is greater than a noise tolerance difference, the noise filtering and signal edge detection circuit outputs an edge detection pulse, and sets the highest-level variable and the lowest-level variable as the current-level number, and continuously judges the level of the analog signal to be decoded to obtain the current-level number.

10. The decoding circuit according to claim 6, wherein: The known signal is a preamble signal.

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