Simultaneous multi-beam phased array transmitting chip

Abstract

The invention relates to the technical field of integrated circuits, and particularly discloses a simultaneous multi-beam phased array transmitting chip. The simultaneous multi-beam phased array transmitting chip comprises K driving amplifiers, a passive differential signal connection network, M transmitting channels and a control unit, the driving amplifier is used for amplifying the plurality of beam signals; the passive differential signal connection network is used for simultaneously connecting the plurality of beam signals to the M transmitting channels; the transmitting channel is used for performing amplitude and phase adjustment on a plurality of input beam signals, and performing synthesis and amplification output on the plurality of adjusted signals; the control circuit is used for controlling the amplitude, the phase and the beam signal gain of the plurality of beam signals; according to the invention, amplitude-phase adjustment, synthesis and conversion output are carried out on a plurality of transmitting beam signals in a current domain, simultaneous multi-beam signal transmission in one or more polarization directions is realized, the overall architecture is simplified, the number of on-chip passive devices is reduced, and the chip area and cost can be effectively reduced.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuits, and particularly discloses a simultaneous multi-beam phased array transmitting chip. BACKGROUND

[0002] In application scenarios such as satellite communication and 5G communication, performance requirements such as multi-connection, high reliability, low latency and high bandwidth require multi-beam phased arrays, which promote the phased array system to develop from single-beam to simultaneous multi-beam.

[0003] For a multi-beam transmitting phased array that needs to simultaneously transmit multiple beam signals, a complex multi-beam network is needed to realize the distribution and synthesis of multiple beam signals. In a traditional multi-beam transmitting phased array, a passive power division network is mainly used to realize the distribution and synthesis of signals, and the area and power consumption will increase sharply with the increase of the number of beams. Furthermore, this implementation method also brings out prominent problems such as complex system design, inter-channel / inter-beam electromagnetic crosstalk, and the corresponding multi-beam transmitting phased array system has many shortcomings such as thick profile, low efficiency, high cost and heavy weight, which to some extent limits the wide application of multi-beam transmitting phased arrays. SUMMARY

[0004] In order to solve the above problems in the prior art, the application provides a simultaneous multi-beam phased array transmitting chip. The high integration and miniaturization of the multi-beam transmitting phased array system are realized.

[0005] The technical scheme adopted by the application is: A simultaneous multi-beam phased array transmitting chip, comprising: K driving amplifiers, a passive differential signal connection network, a control unit and M transmitting channels, wherein M = 2 α , K = 2 β , and both α and β are integers greater than or equal to 0. The K driving amplifiers are used to convert K input beam signals into K pairs of differential beam signals and amplify them. The passive differential signal connection network is used to simultaneously connect the K pairs of differential beam signals to the M transmitting channels. The M transmitting channels are used to adjust the amplitude and phase of the K pairs of differential beam signals, synthesize, amplify and convert the adjusted multiple differential beam signals into single-ended signals and output them. The control unit is connected with the K driving amplifiers and the M transmitting channels, and is used to provide control instructions to the K driving amplifiers and the M transmitting channels.

[0006] Further, M is the maximum number of antennas that the chip can support, and K is the maximum number of beam signals that the chip can support.

[0007] Further, the passive differential signal connection network has K pairs of differential input ports and MxK pairs of differential output interfaces; in the passive differential signal connection network, any one pair of differential input ports is connected to M different differential output ports at the same time.

[0008] Further, the transmitting channel comprises K multi-stage adjustable transconductance units, a multi-beam current synthesis network, a conversion and synthesis unit and an output power amplifier; the K multi-stage adjustable transconductance units are connected to the multi-beam current synthesis network, and the multi-beam current synthesis network, the conversion and synthesis unit and the output power amplifier are sequentially connected.

[0009] Further, the multi-stage transconductance unit comprises a first differential adjustable transconductance unit, a first coupled inductor, a second differential adjustable transconductance unit and a third differential adjustable transconductance unit; the differential input port of the first differential adjustable transconductance unit is connected to the differential output interface of the passive differential signal connection network; the differential output port of the first differential adjustable transconductance unit is connected to both ends of the primary winding of the first coupled inductor, and the center tap of the primary winding of the first coupled inductor is connected to a power supply voltage; both ends of the secondary winding of the first coupled inductor are connected to the differential input ports of the second differential adjustable transconductance unit and the third differential adjustable transconductance unit, and the center tap of the secondary winding of the first coupled inductor is connected to ground; the output ports of the second differential adjustable transconductance unit and the third differential adjustable transconductance unit are respectively connected to corresponding ports of the multi-beam current synthesis network.

[0010] Further, the multi-beam current synthesis network has 2K differential input ports and two differential output ports; the output port of the second differential adjustable transconductance unit of each multi-stage adjustable transconductance unit is combined at one differential output port of the multi-beam current synthesis network, and the output port of the third differential adjustable transconductance unit of each multi-stage adjustable transconductance unit is combined at the other differential output port of the multi-beam current synthesis network.

[0011] Further, the conversion and synthesis unit comprises a second coupled inductor, a third coupled inductor and a quadrature signal synthesis unit; both ends of the primary winding of the second coupled inductor are connected to the differential output ports of the multi-beam current synthesis network, the center tap of the primary winding of the second coupled inductor is connected to a power supply voltage, and both ends of the secondary winding of the second coupled inductor are connected to one differential input port of the quadrature signal synthesis unit; the center tap of the secondary winding of the second coupled inductor is connected to ground; Two ends of the primary coil of the third coupling inductor are connected to another differential output port of the multi-beam current synthesis network, a center tap of the primary coil of the third coupling inductor is connected to a power supply voltage, two ends of the secondary coil of the third coupling inductor are connected to another differential input port of the quadrature signal synthesis unit, and a center tap of the secondary coil of the third coupling inductor is connected to the ground; The quadrature signal synthesis unit performs quadrature synthesis on two-way input differential signals and then outputs.

[0012] Further, the control circuit transmits control information through a serial bus; the control information includes gain information of the driving amplifier, gain and phase information of the transmission channel.

[0013] The present application has the following advantages: (1) the synthesis of multiple transmission beam signals is realized in the current domain, and the passive circuit occupying a large chip area required by the synthesis of voltage signals is abandoned; (2) multiple beam signals in each transmission channel can be independently controlled in phase and gain, so that multiple transmission beam signals are independent of each other and have reconfigurable and configurable capabilities; (3) the traditional high-complexity multi-beam transmission chip architecture is simplified, and high integration and low cost of the simultaneous multi-beam phased array transmission chip are realized. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 The overall architecture of the simultaneous multi-beam phased array transmission chip in the embodiment of the present application is shown in the figure; Figure 2 The circuit schematic diagram of the driving amplifier in the embodiment of the present application is shown in the figure; Figure 3 The connection scheme of the passive differential signal connection network in the embodiment of the present application when M=4 and K=4 is shown in the figure; Figure 4 The cross-sectional schematic diagram of the differential coplanar waveguide and the differential stripline used by the passive differential signal connection network in the embodiment of the present application is shown in the figure; Figure 5 The structure block diagram of the first differential adjustable transconductance unit in the embodiment of the present application is shown in the figure; Figure 6 The circuit schematic diagram of the transconductance stage used to compose the first differential adjustable transconductance unit in the embodiment of the present application is shown in the figure; Figure 7 The circuit schematic diagram of the second differential adjustable transconductance unit and the third differential adjustable transconductance unit in the embodiment of the present application is shown in the figure; Figure 8 The connection scheme of the multi-beam current synthesis network in the embodiment of the present application when K=4 is shown in the figure; Figure 9 The circuit schematic diagram of the quadrature signal synthesis unit in the embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0015] To further illustrate the advantages of the present application and the technical means adopted, the specific embodiments of the present application are described in detail below in conjunction with the accompanying drawings. It is understood that these embodiments are only used to illustrate the present application and not to limit the scope of the present application, and after reading the present application, various equivalent modifications of the present application by those skilled in the art should fall within the scope of the claims of the present application.

[0016] A simultaneous multi-beam phased array transmitting chip, characterized in that, comprising: K driving amplifiers, a passive differential signal connection network, M transmitting channels and a control unit, wherein M=2 α , K=2 β , and α, β are integers greater than or equal to 0. The K driving amplifiers are used to convert K input beam signals into K pairs of differential beam signals and amplify them. The passive differential signal connection network is used to simultaneously connect the K pairs of differential beam signals to the M transmitting channels. The M transmitting channels are used to adjust the amplitude and phase of the K pairs of differential beam signals, and to synthesize and amplify the adjusted multiple differential beam signals and convert them into single-ended signal outputs. The control unit is connected to the K driving amplifiers and the M transmitting channels, and is used to provide control instructions to the K driving amplifiers and the M transmitting channels.

[0017] The M is the maximum number of antennas that the chip can support, and the K is the maximum number of beam signals that the chip can support, and M and K can be equal or not equal.

[0018] The circuit structures of the K driving amplifiers are the same.

[0019] The passive differential signal connection network has K pairs of differential input ports {(B jP , B jN ), j=1…K}, and M×K pairs of differential output interfaces {(VP ij , VN ij ), i=1,…M, j=1,…K}. Wherein, the Lth pair of differential input ports (B LP , B LN ) is simultaneously connected to M differential output ports (VP 1L , VN 1L ), (VP 2L , VN 2L ), ···, (VP ML , VN ML ), and so on.

[0020] The M transmitting channels have the same structure, and one of the M transmitting channels includes K multi-stage adjustable transconductance units, a multi-beam current synthesis network, a conversion and synthesis unit, and an output power amplifier.

[0021] The multi-stage transconductance unit includes a first differential adjustable transconductance unit 101-1, a first coupled inductor 101-2, a second differential adjustable transconductance unit 101-3 and a third differential adjustable transconductance unit 101-4; The differential input port of the first differential adjustable transconductance unit 101-1 is connected to the differential output interface (VP) of the passive differential signal connection network. ij , VN ij ); The second differential adjustable transconductance unit and the third differential adjustable transconductance unit have the same circuit structure; The differential output port of the first differential adjustable transconductance unit 101 - 1 is connected to both ends of the primary coil of the first coupled inductor 101 - 2 , and the center tap of the primary coil of the first coupled inductor 101 - 2 is connected to a power supply voltage; Two ends of the secondary coil of the first coupled inductor 101-2 are connected to the differential input ends of the second differentially adjustable transconductance unit 101-3 and the third differentially adjustable transconductance unit 101-4, and a center tap of the secondary coil of the first coupled inductor 101-2 is connected to the ground; Output ports of the second differentially adjustable transconductance unit 101 - 3 and the third differentially adjustable transconductance unit 101 - 4 are respectively connected to corresponding ports of the multi-beam current synthesis network.

[0022] The multi-beam current synthesis network has 2K differential input ports (IP1, IN1), (QP1, QN1), (IP2, IN2), (QP2, QN2), . . . , (IP K , IN K )、(QP K , QN K ), with two differential output ports (IP, IN), (QP, QN), where (IP1, IN1), (IP2, IN2), ····, (IP K , IN K ) is connected to (IP, IN), (QP1, QN1), (QP2, QN2), ..., (QP K , QN K ) is connected with (QP, QN).

[0023] The conversion and synthesis unit comprises a second coupling inductor 110-1, a third coupling inductor 110-2 and a quadrature signal synthesis unit; Two ends of a primary coil of the second coupling inductor 110-1 are connected to differential output ports (IP, IN) of a multi-beam current synthesis network, a center tap of the primary coil of the second coupling inductor 110-1 is connected to a power supply voltage, and two ends of a secondary coil of the second coupling inductor 110-1 are connected to one differential input port of the quadrature signal synthesis unit; a center tap of the secondary coil of the second coupling inductor 110-1 is connected to ground. Two ends of a primary coil of the third coupling inductor 110-2 are connected to another differential output port (QP, QN) of the multi-beam current synthesis network, a center tap of the primary coil of the third coupling inductor 110-2 is connected to the power supply voltage, and two ends of a secondary coil of the third coupling inductor 110-2 are connected to another differential input port of the quadrature signal synthesis unit; a center tap of the secondary coil of the third coupling inductor 110-2 is connected to ground. The quadrature signal synthesis unit performs quadrature synthesis on two-way input differential signals and outputs the quadrature synthesized signals.

[0024] The control circuit transmits control information through a serial bus; the control information at least partially comprises: gain information of the driving amplifiers; gain and phase information of the transmission channels.

[0025] The application will be further described in detail below with reference to the accompanying drawings.

[0026] As shown in Figure 1 A simultaneous multi-beam phased array transmitting chip, characterized in that it comprises: K driving amplifiers, a passive differential signal connection network, M transmission channels and a control unit, wherein M = 2 α , K = 2 β , and α and β are integers greater than or equal to 0. The K driving amplifiers are used to convert K input beam signals into K pairs of differential beam signals and amplify the K pairs of differential beam signals. The passive differential signal connection network is used to simultaneously connect the K pairs of differential beam signals to the M transmission channels. The M transmission channels are used to adjust the amplitudes and phases of the K pairs of differential beam signals, amplify the adjusted differential beam signals and convert the amplified differential beam signals into single-ended signals and output the single-ended signals. The control unit is connected to the K driving amplifiers and the M transmission channels and is used to provide control instructions to the K driving amplifiers and the M transmission channels.

[0027] The working principle and signal flow of this simultaneous multi-beam phased array transmitting chip are as follows: K-way beam signals B1, B2, ····, B K The input is amplified and converted into a differential signal (B 1P , B 1N )、(B 2P , B 2N ) 、····、(B KP , B KN ) is input to the passive differential signal connection network, and the passive differential signal connection network converts the differential signal (B 1P , B 1N ) is divided into M differential signals (VP 11 , VN 11 )、(VP 21 ,VN 21 )、····、(VP M1 , VN M1 ), differential signal (B 2P , B 2N ) is divided into M differential signals (VP 12 , VN 12 )、(VP 22 ,VN 22 )、····、(VP M2 , VN M2 ), and so on, the differential signal (B KP , B KN ) is divided into M differential signals (VP 1K ,VN 1 K )、(VP 2 K , VN 2K )、····、(VP MK , VN M K ); thereby generating M×K differential signals which are input to the M bidirectional transmit and receive phase shift channels, and then the transmit channels are subjected to phase shifting, combining and amplification to generate M radio frequency signals RF1, RF2, ····, RF M .

[0028] M is the maximum number of antennas that the chip can support, and K is the maximum number of multiple beam signals that the chip can support. M and K may be equal or unequal.

[0029] The K driver amplifiers have the same circuit structure.

[0030] Figure 2 The circuit diagram of one of the driving amplifiers in this preferred embodiment is shown, including NMOS transistors M1, M2, M3, M4, coupled inductors T1, T2, and capacitor C IThe specific circuit connection is: the positive end of the primary inductor of T1 is connected to the port V RF , the negative terminal of the primary inductor of T1 is connected to the capacitor C I The positive end, C I The negative end of T1 is grounded, the positive and negative ends of the secondary inductor of T1 are connected to the gates of M1 and M2 respectively, and the center tap of the secondary inductor of T1 is connected to the bias voltage V B , the sources of M1 and M2 are grounded, the drains of M1 and M2 are connected to the sources of M3 and M4 respectively, and the gates of M3 and M4 are connected to the power supply voltage V DD , the drains of M3 and M4 are connected to the power supply, the positive and negative terminals of the primary inductor of T2, respectively, and the center tap of the primary inductor of T2 is connected to the power supply voltage V DD , the positive and negative terminals of the secondary inductor of T2 are connected to ports V P and V N .

[0031] Passive differential signal connection network with K pairs of differential input ports {(B jP , B jN ), j=1…K}, with M×K pairs of differential output interfaces {(VP ij , VN ij ), i=1,…M, j=1,…K}. Among them, the Lth pair of differential input ports (B LP , B LN ) are connected to M differential output ports (VP 1L , VN 1L )、(VP 2L , VN 2L )、····、(VP ML , VN ML ), and so on.

[0032] Figure 3 The figure shows the connection scheme of the passive differential signal connection network (30) in the preferred embodiment when M=4 and K=4; differential coplanar waveguide and differential stripline are used to transmit radio frequency signals in the vertical and horizontal directions respectively; when M and K take other values, the connection scheme of the passive differential signal connection network is similar; Figure 4 The figure shows a cross-sectional diagram of a differential coplanar waveguide and a differential stripline. The wiring metal of the differential coplanar waveguide uses the top metal layer with the lowest resistivity in the process, while the wiring metal of the differential stripline uses the inner layer metal. The left and right sides are connected to each metal layer through through-holes and grounded.

[0033] Specifically, the M transmitting channels have the same structure, and one of the M transmitting channels includes K multi-stage adjustable transconductance units, a multi-beam current synthesis network, a conversion and synthesis unit, and an output power amplifier.

[0034] In particular, the multi-stage transconductance unit comprises a first differential adjustable transconductance unit 101-1, a first coupled inductance 101-2, a second differential adjustable transconductance unit 101-3 and a third differential adjustable transconductance unit 101-4; The differential input port of the first differential adjustable transconductance unit 101-1 is connected to the differential output interface (V 11 , VN 11 ) of the passive differential signal connection network; Figure 5 The structure block diagram of the first differential adjustable transconductance unit 101-1 in the preferred embodiment is shown, which is composed of N transconductance stages with the same structure in parallel, g m1 , g m2 ,······、 g mN The input port of all the transconductance stages is connected to (V IP , V IN ), and the input port of all the transconductance stages is connected to (V I P , I N ). The control signal (C , NC ) are each independently provided. Figure 6 The circuit schematic of each transconductance stage in the preferred embodiment is shown, including NMOS transistors Ml, M2, M3, M4, M5, M6, M7. The specific circuit connections are: the gate and source of Ml are connected to control voltage V BIAS and ground, the drain of Ml is connected to the sources of M2 and M3; the drain of M2 is connected to the sources of M4 and M7, the gate of M2 is connected to control voltage NC , the gate of M3 is connected to a control voltage C M3, the drain of M5 and the source of M6; the gate of M4 and M5 connects port V IP M6 and M7, the drain of M5 and the source of M7; the gate of M4 and M6 connects port V IN M4 and M6, the drain of M5 and the source of M7; the gate of M4 and M6 connects port I N M5 and M7, the drain of M5 and the source of M7; the gate of M4 and M6 connects port I P Control voltage C and NC The control voltage P and NP are complementary signals, only 0 or 1, used to control the on-off of the signal, and the bias voltage V is used to control the bias current.

[0035] The circuit structure of the second differential adjustable transconductance unit 101-3 and the third adjustable transconductance unit 101-4 is the same; Figure 7 The circuit schematic diagram of the second differential adjustable transconductance unit 101-3 in the preferred embodiment is shown, including NMOS transistors M1, M2, M3, M4, M5, M6, and M7. The specific circuit connection is as follows: the gate and source of M1 are connected to the control voltage V BIAS and ground, respectively; the drain of M1 is connected to the sources of M2 and M3; the drain of M2 is connected to the sources of M4 and M7, the gate of M2 is connected to the control voltage P, the gate of M3 is connected to the control voltage NP, the drain of M3 is connected to the sources of M5 and M6; the gates of M4 and M5 are connected to the port V in+ , the gates of M6 and M7 are connected to the port V in- ; the drains of M4 and M6 are connected to the port I out- , and the drains of M5 and M7 are connected to the port I out+ .

[0036] Specifically, the control voltage P and NP are complementary signals, only 0 or 1, used to control the on-off of the signal, and the bias voltage V BIAS is used to control the bias current to change the transconductance size.

[0037] The differential output port of the first differential adjustable transconductance unit 101-1 is connected to both ends of the primary coil of the first coupled inductor 101-2, and the center tap of the primary coil of the first coupled inductor 101-2 is connected to the power supply voltage; The two ends of the secondary coil of the first coupled inductor 101-2 are connected to the differential input ends of the second differential adjustable transconductance unit 101-3 and the third differential adjustable transconductance unit 101-4, and the center tap of the secondary coil of the first coupled inductor 101-2 is connected to ground; The output ports of the second differential adjustable transconductance unit 101-3 and the third differential adjustable transconductance unit 101-4 are respectively connected to the corresponding ports of the multi-beam current synthesis network.

[0038] The multi-beam current synthesis network has 2K differential input ports (IP1, IN1), (QP1, QN1), (IP2, IN2), (QP2, QN2), ···, (IP K , IN K ), (QP K , QN K ), having two differential output ports (IP, IN), (QP, QN), wherein (IP1, IN1), (IP2, IN2), ···, (IP K , IN K ) are connected to (IP, IN), and (QP1, QN1), (QP2, QN2), ···, (QP K , QN K ) are connected to (QP, QN).

[0039] Figure 8 Fig. 4 shows a connection scheme of the multi-beam current synthesis network when K = 4 in the preferred embodiment; differential co-planar waveguides and differential stripline transmission RF signals shown in Figs. 3a and 3b are used in the vertical and horizontal directions respectively; the connection scheme of the multi-beam current synthesis network when K takes other values is similar. Figure 4

[0040] Specifically, the conversion and synthesis unit comprises a second coupled inductor 110-1, a third coupled inductor 110-2, and an orthogonal signal synthesis unit.

[0041] Two ends of a primary coil of the second coupled inductor 110-1 are connected to a differential output port (IP, IN) of the multi-beam current synthesis network, a center tap of the primary coil of the second coupled inductor 110-1 is connected to a power supply voltage, and two ends of a secondary coil of the second coupled inductor 110-1 are connected to one differential input port of the orthogonal signal synthesis unit; a center tap of the secondary coil of the second coupled inductor 110-1 is connected to ground.

[0042] Two ends of a primary coil of the third coupled inductor 110-2 are connected to a differential output port (QP, QN) of the multi-beam current synthesis network, a center tap of the primary coil of the third coupled inductor 110-2 is connected to the power supply voltage, and two ends of a secondary coil of the third coupled inductor 110-2 are connected to the other differential input port of the orthogonal signal synthesis unit, and a center tap of the secondary coil of the third coupled inductor 110-2 is connected to ground. The orthogonal signal synthesis unit uses its reciprocity to orthogonally synthesize two-way input differential signals and then output.

[0043] Figure 9 Fig. 6 shows a circuit implementation of the orthogonal signal synthesis unit in the preferred embodiment, a circuit schematic diagram, comprising resistors R1, R2, R3, R4, R5, R6, R7, R8, and capacitors C1, C2, C3, C4; C5, C6, C7, C8; the specific circuit connection is: the positive terminal of the resistor R1 and the positive terminal of the capacitor C4 are connected to the port V IP ​The positive terminal of the resistor R2 and the positive terminal of the capacitor C1 are connected to the port V IN The positive terminal of the resistor R3 and the positive terminal of the capacitor C2 are connected to the port V QP The positive terminal of the resistor R4 and the positive terminal of the capacitor C3 are connected to the port V QN The negative terminal of the resistor R1 and the negative terminal of the capacitor C1 are connected to the positive terminal of the resistor R5 and the positive terminal of the capacitor C8, the negative terminal of the resistor R2 and the negative terminal of the capacitor C2 are connected to the positive terminal of the resistor R6 and the positive terminal of the capacitor C5, the negative terminal of the resistor R3 and the negative terminal of the capacitor C3 are connected to the positive terminal of the resistor R7 and the positive terminal of the capacitor C6, the negative terminal of the resistor R4 and the negative terminal of the capacitor C4 are connected to the positive terminal of the resistor R8 and the positive terminal of the capacitor C8, the negative terminal of the resistor R5, the negative terminal of the capacitor C5, the negative terminal of the resistor R6 and the negative terminal of the capacitor C6 are connected to the port V OP The negative terminal of the resistor R7, the negative terminal of the capacitor C7, the negative terminal of the resistor R8 and the negative terminal of the capacitor C8 are connected to the port V ON .

[0044] Specifically, the control circuit transmits control information through a serial bus; the control information at least partially includes: gain information of the driving amplifier; gain and phase information of the transmitting channel.

[0045] It should be noted that the above only represents the preferred application examples of the present application, and is not intended to limit the protection scope of the present application. Any technical solution with equivalent substitution or equivalent transformation is within the protection scope of the present application.

Claims

1. A simultaneous multi-beam phased array transmitting chip, characterized in that: include: K driver amplifiers, passive differential signal connection network, control unit and M transmission channels, where M = 2 α , K=2 β , α and β are both integers ≥ 0; K driver amplifiers, used for converting the K input beam signals into K pairs of differential beam signals and amplifying them; The passive differential signal connection network is used to simultaneously connect K pairs of differential beam signals to M transmission channels; M transmitting channels, used to perform amplitude and phase adjustment on K pairs of differential beam signals, and synthesize, amplify and convert the adjusted multiple differential beam signals into single-ended signal output; A control unit is connected to the K driving amplifiers and the M transmitting channels, and is used to provide control instructions to the K driving amplifiers and the M transmitting channels.

2. The simultaneous multi-beam phased array transmitting chip according to claim 1, characterized in that: in, M is the maximum number of antennas that the chip can support, where K is the maximum number of multiple beam signals that the chip can support.

3. The simultaneous multi-beam phased array transmitting chip according to claim 1, characterized in that: The passive differential signal connection network has K pairs of differential input ports and M×K pairs of differential output interfaces. In the passive differential signal connection network, any pair of differential input ports is simultaneously connected to M different differential output ports.

4. The simultaneous multi-beam phased array transmitting chip according to claim 1, characterized in that: The transmitting channel includes K multi-stage adjustable transconductance units, a multi-beam current synthesis network, a conversion and synthesis unit, and an output power amplifier (111); the K multi-stage adjustable transconductance units are all connected to the multi-beam current synthesis network, and the multi-beam current synthesis network, the conversion and synthesis unit, and the output power amplifier (111) are connected in sequence.

5. The simultaneous multi-beam phased array transmitting chip according to claim 4, characterized in that: The multi-stage transconductance unit comprises a first differential adjustable transconductance unit (101-1), a first coupled inductor (101-2), a second differential adjustable transconductance unit (101-3) and a third differential adjustable transconductance unit (101-4); The differential input port of the first differential adjustable transconductance unit (101-1) is connected to the differential output interface of the passive differential signal connection network; The differential output port of the first differential adjustable transconductance unit (101-1) is connected to both ends of the primary coil of the first coupled inductor (101-2), and the center tap of the primary coil of the first coupled inductor (101-2) is connected to a power supply voltage; Two ends of the secondary coil of the first coupled inductor (101-2) are connected to the differential input ends of the second differentially adjustable transconductance unit (101-3) and the third differentially adjustable transconductance unit (101-4), and a center tap of the secondary coil of the first coupled inductor (101-2) is connected to the ground; The output ports of the second differentially adjustable transconductance unit (101-3) and the third differentially adjustable transconductance unit (101-4) are respectively connected to corresponding ports of the multi-beam current synthesis network.

6. The simultaneous multi-beam phased array transmitting chip according to claim 4, characterized in that: The multi-beam current synthesis network has 2K differential input ports and two differential output ports; the output port of the second differential adjustable transconductance unit (101-3) of each multi-stage adjustable transconductance unit is combined at one of the differential output ports of the multi-beam current synthesis network, and the output port of the third differential adjustable transconductance unit (101-4) of each multi-stage adjustable transconductance unit is combined at the other differential output port of the multi-beam current synthesis network.

7. The simultaneous multi-beam phased array transmitting chip according to claim 4, characterized in that: The conversion and synthesis unit comprises a second coupled inductor (110-1), a third coupled inductor (110-2) and an orthogonal signal synthesis unit; The two ends of the primary coil of the second coupled inductor (110-1) are connected to the differential output port of the multi-beam current synthesis network, the center tap of the primary coil of the second coupled inductor (110-1) is connected to the power supply voltage, the two ends of the secondary coil of the second coupled inductor (110-1) are connected to a differential input port of the orthogonal signal synthesis unit; the center tap of the secondary coil of the second coupled inductor (110-1) is connected to the ground; The two ends of the primary coil of the third coupled inductor (110-2) are connected to another differential output port of the multi-beam current synthesis network, the center tap of the primary coil of the third coupled inductor (110-2) is connected to the power supply voltage, the two ends of the secondary coil of the third coupled inductor (110-2) are connected to another differential input port of the orthogonal signal synthesis unit, and the center tap of the secondary coil of the third coupled inductor (110-2) is connected to the ground; The orthogonal signal synthesis unit utilizes its reciprocity to perform orthogonal synthesis on the two input differential signals and then outputs the result.

8. The simultaneous multi-beam phased array transmitting chip according to claim 1, characterized in that: The control unit transmits control information via a serial bus; the control information includes: gain information of the driving amplifier, gain and phase information of the transmitting channel.

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