Managing storage node contact structures in semiconductor devices

Abstract

The invention relates to a storage node contact structure in a semiconductor device and a manufacturing method thereof. An exemplary semiconductor device includes an array of memory cells. The memory cell array includes a first row of memory cells arranged in a first direction. At least one memory cell in the first row of memory cells includes a first vertical transistor, a first storage node contact structure, and a first storage structure stacked in a second direction perpendicular to the first direction. The first storage node contact structure includes a first top portion in contact with the first storage structure and a first bottom portion in contact with the first vertical transistor. The first top section of the first top portion is asymmetric.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to storage node contact structures in semiconductor devices and methods of manufacturing the same. BACKGROUND

[0002] The semiconductor industry is driven by the demand for producing smaller and faster chips. Manufacturers of memory devices and systems are also working to improve scaling technology. Dynamic random access memory (DRAM) is a common memory device that is widely used in computer systems. Thus, advanced techniques are needed to alleviate problems of DRAM devices and improve scaling of DRAM devices. SUMMARY

[0003] The present disclosure describes methods, devices, systems, and techniques for managing storage node contact structures in semiconductor devices, such as 3D memory devices, such as DRAM.

[0004] One aspect of the present disclosure features a semiconductor device including an array of memory cells. The array of memory cells includes a first row of memory cells arranged along a first direction. At least one memory cell of the first row of memory cells includes a first vertical transistor, a first storage node contact structure, and a first storage structure stacked along a second direction perpendicular to the first direction. The first storage node contact structure includes a first top portion in contact with the first storage structure and a first bottom portion in contact with the first vertical transistor. A first top cross-section of the first top portion is asymmetric.

[0005] In some implementations, the first top cross-section of the first top portion is asymmetric with respect to a first center cross-section of the first storage node contact structure. The first center cross-section is perpendicular to the first direction and extends from a center of a first bottom cross-section of the first bottom portion to the first top cross-section. The first top cross-section includes a first portion extending from the first center cross-section along the first direction and a second portion extending from the first center cross-section along a fourth direction opposite the first direction. Along the first direction, a dimension of the first portion of the first top cross-section is greater than a dimension of the second portion of the first top cross-section.

[0006] In some embodiments, the array of memory cells further includes a second row of memory cells adjacent to the first row of memory cells. At least one memory cell of the second row of memory cells includes a second vertical transistor, a second storage node contact structure, and a second storage structure stacked along a second direction. The second storage node contact structure includes a second top portion in contact with the second storage structure and a second bottom portion in contact with the second vertical transistor. A second top cross-section of the second top portion is asymmetric with respect to a second center cross-section of the second storage node contact structure. The second center cross-section is perpendicular to the first direction and extends from a center of a second bottom cross-section of the second bottom portion to the second top cross-section. The second top cross-section includes a first portion extending from the second center cross-section along the first direction and a second portion extending from the second center cross-section along a fourth direction. Along the first direction, a size of the second portion of the second top cross-section is greater than a size of the first portion of the second top cross-section.

[0007] In some embodiments, the first vertical transistor is coupled to the first storage structure through the first storage node contact structure.

[0008] In some embodiments, the first storage node contact structure includes at least one of a metal, a silicide, or doped silicon.

[0009] In some embodiments, the first vertical transistor includes one of a single gate structure, a dual gate structure, a tri-gate structure, or a gate-all-around (GAA) structure.

[0010] In some embodiments, the array of memory cells is coupled to the peripheral circuitry through conductive bonding contacts included in a bonding layer, and the bonding layer further includes a dielectric material electrically isolating the conductive bonding contacts.

[0011] Another aspect of the disclosure features a semiconductor device. The semiconductor device includes an array of memory cells including a first row of memory cells arranged along a first direction. At least one memory cell of the first row of memory cells includes a first vertical transistor, a first storage node contact structure, and a first storage structure stacked along a second direction perpendicular to the first direction. The first storage node contact structure includes a top portion in contact with the first storage structure and a bottom portion in contact with the first vertical transistor. A slope of a tangent plane to a side surface of the top portion of the first storage node contact structure on a first side is less than a slope of a tangent plane to a side surface of the bottom portion on the first side with respect to the first direction.

[0012] In some embodiments, the slope of the tangent plane to the side surface of the top portion of the first storage node contact structure on the first side is less than the slope of the tangent plane to the side surface of the top portion on a second side with respect to the first direction. The first side and the second side are opposite to each other with respect to a third direction perpendicular to the first direction and the second direction.

[0013] In some embodiments, a dimension of a cross-section of the top portion of the first storage node contact structure is greater than a dimension of a cross-section of the bottom portion of the first storage node contact structure.

[0014] In some embodiments, an angle between a side surface of the top portion of the first storage node contact structure on the first side and the first direction varies from 20 degrees to 70 degrees.

[0015] In some embodiments, the array of memory cells further includes a second row of memory cells adjacent to the first row of memory cells. At least one memory cell of the second row of memory cells includes a second vertical transistor, a second storage node contact structure, and a second storage structure stacked along a second direction. The second storage node contact structure includes a top portion in contact with the second storage structure and a bottom portion in contact with the second vertical transistor. A slope of a tangent plane of a side surface of the top portion of the second storage node contact structure on the second side is less than a slope of a tangent plane of a side surface of the bottom portion of the second storage node contact structure on the second side with respect to the first direction.

[0016] In some embodiments, the first vertical transistor is coupled to the first storage structure through the first storage node contact structure.

[0017] In some embodiments, the first storage node contact structure includes at least one of a metal, a silicide, or doped silicon.

[0018] Another aspect of the present disclosure features a method including forming an array of vertical transistors and a dielectric layer over the array of vertical transistors. The method further includes forming an array of storage node contact holes in the dielectric layer. The array of storage node contact holes includes a first row of storage node contact holes arranged along a first direction. Each storage node contact hole of the array of storage node contact holes extends along a second direction perpendicular to the first direction and has a top portion and a bottom portion along the second direction. The bottom portion is disposed on top of a respective vertical transistor of the array of vertical transistors. The method further includes, for each storage node contact hole of the first row of storage node contact holes, forming a first inner side surface on a first side of the top portion of the storage node contact hole. A slope of a tangent plane of the first inner side surface is less than a slope of a tangent plane of a second inner side surface on the first side of the bottom portion of the storage node contact hole with respect to the first direction.

[0019] In some embodiments, forming the array of storage node contact holes includes forming the array of storage node contact holes using a same reactive ion etching (RIE) process using a zero angle of incidence with respect to the second direction.

[0020] In some implementations, forming the first inner side surface of each of the first row of storage node contact holes includes forming the first inner side surface of each of the first row of storage node contact holes using a first incident angle that is perpendicular to the first inner side surface by a first directional ion beam etching (IBE) process.

[0021] In some implementations, the array of storage node contact holes further includes a second row of storage node contact holes adjacent to the first row of storage node contact holes. The method further includes, for each of the second row of storage node contact holes, forming a third inner side surface on a first side of a top portion of the storage node contact hole. A slope of a tangent plane of the third inner side surface relative to the first direction is less than a slope of a tangent plane of a fourth inner side surface on the first side of a bottom portion of the storage node contact hole relative to the first direction. The tangent plane of the third inner side surface and the tangent plane of the first inner side surface have a same slope relative to the first direction. The third inner side surface of each of the second row of storage node contact holes is formed during the first directional IBE process.

[0022] In some implementations, the array of storage node contact holes further includes a second row of storage node contact holes adjacent to the first row of storage node contact holes. The method further includes, for each of the second row of storage node contact holes, forming a third inner side surface on a second side of a top portion of the storage node contact hole. A slope of a tangent plane of the third inner side surface relative to the first direction is less than a slope of a tangent plane of a fourth inner side surface on the second side of a bottom portion of the storage node contact hole relative to the first direction. The second side is opposite the first side.

[0023] In some implementations, the third inner side surface of each of the second row of storage node contact holes is formed during a second directional IBE process using a second incident angle that is perpendicular to the third inner side surface. An opening of the second row of storage node contact holes is covered during the first directional IBE process. An opening of the first row of storage node contact holes is covered during the second directional IBE process.

[0024] Embodiments of the present disclosure can provide one or more of the following technical advantages and / or benefits. For example, the techniques provided in the present disclosure enable forming a source node contact (SNC) structure with a top portion having an asymmetric structure during fabrication of a memory device. The top portion can serve as a landing pad for a storage structure to be formed on top of the SNC structure. The landing pad can accommodate a lateral offset between a location of the storage structure and a location of the SNC structure, thus can provide a reliable connection between the storage structure and the SNC structure and allow the storage structure to have a larger critical dimension (CD). In addition, the techniques can avoid using complex techniques to build a separate storage node landing pad (SNLP), thus improving the reliability and performance of the memory device and reducing the manufacturing workload and cost. For example, these techniques can address issues caused by the increased density of memory cells in a chip and the hammering effect to reduce or eliminate disturb errors of the memory device.

[0025] The techniques implemented herein can be applied to different types of DRAM architectures, such as 8F 2 cell design, 6F 2 cell design, or 4F 2 cell design. These techniques can also enable scaling of DRAM devices from 18 nanometer (nm) process, 15 nm process, to 10 nm process, and even smaller size processes. The techniques can be applied to various types of semiconductor devices, volatile memory devices (e.g., DRAM memory devices), or non-volatile memory (NVM) devices (e.g., NAND flash, NOR flash, resistive random access memory (RRAM), phase change memory (PCM) such as phase change random access memory (PCRAM), spin transfer torque (STT)-magnetic random access memory (MRAM), etc.). The techniques can also be applied to charge-trapping based memory devices (e.g., silicon-oxide-nitride-oxide-silicon (SONOS) memory devices) and floating gate based memory devices. The techniques can be applied to three-dimensional (3D) memory devices. The techniques can be applied to various memory types, such as SLC (single level cell) devices, MLC (multi-level cell) devices). Additionally or alternatively, the techniques can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC) or solid state drives (SSD), embedded systems, and the like.

[0026] The details of one or more embodiments of the subject matter of the present disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims. BRIEF DESCRIPTION OF DRAWINGS

[0027] The accompanying drawings are incorporated herein and constitute part of the disclosure, illustrate aspects of the disclosure, and together with the description, further serve to explain the principles of the disclosure and to enable a person skilled in the relevant art to make and use the disclosure.

[0028] Figures 1A-1B A top view of an example memory cell array is shown.

[0029] Figure 2 A side view of a cross-section of an example three-dimensional (3D) semiconductor device is shown.

[0030] Figures 3A-3B An example 3D semiconductor device is shown.

[0031] Figure 4 A side view of an example storage node contact (SNC) structure is shown.

[0032] Figures 5A-5F An example manufacturing process for forming an array of SNC structures is shown.

[0033] Figure 6 A flowchart of an example process is shown.

[0034] Figure 7 A block diagram of an example system is shown.

[0035] Like reference numbers and designations in the various drawings indicate like elements. It will also be appreciated that the various example embodiments illustrated in the drawings are merely exemplary representations and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0036] Memory devices, such as dynamic random access memory (DRAM), can use a storage node landing pad (SNLP) to connect a storage node contact (SNC) structure and a storage node (SN) (also referred to as a storage structure). The SNLP can provide a more reliable connection between the SNC structure and the storage structure (e.g., a capacitor) and enable the storage structure in the memory device to have a larger critical dimension (CD).

[0037] Figures 1A-1B Top views of example memory cell arrays 100a and 100b in a semiconductor device, such as a memory device, are shown. Each of the memory cell arrays 100a and 100b can include, for example, DRAM cells. Note that the X, Y, and Z axes (also referred to as the X, Y, and Z directions) are included in the drawings to provide a frame of reference for the various example embodiments described herein. Figures 1A-1BThe spatial relationship of the components in the semiconductor device is further illustrated in the following. The substrate of the semiconductor device includes two lateral surfaces extending laterally in the XY plane: a top surface on the front side of the wafer on which the components of the semiconductor device can be formed, and a bottom surface on the back side of the wafer opposite to the front side. The Z direction is perpendicular to the X and Y directions. As used herein, when the substrate of the semiconductor device is located in the lowest plane of the semiconductor device in the Z direction (a vertical direction perpendicular to the XY plane, such as the thickness direction of the substrate), whether a component (e.g., a layer or device) of the semiconductor device is located "on", "above" or "below" another component (e.g., a layer or device) of the semiconductor device is determined relative to the substrate. The same concepts used to describe spatial relationships apply throughout this disclosure.

[0038] like Figure 1A As shown, each memory cell in the memory cell array 100a includes an SNC structure 101a and a storage structure 103a. The SNC structure 101a and the storage structure 103a are arranged in a square pattern, which allows each storage structure 103a to be aligned with and coupled to the corresponding SNC structure 101a along the vertical direction (e.g., the Z direction). Figure 1B The memory cell array 100b is shown to include SNC structures 101b and storage structures 103b. The SNC structures 101b are still arranged in a square pattern. The storage structures 103b are arranged in a triangular pattern. The triangular pattern allows the storage structures 103b to have a larger CD (compared to the Figure 1A 103b) to provide more space for the storage structure 103b while maintaining the same density. However, due to the difference between the arrangement patterns of the SNC structure 101b and the storage structure 103b, the vertical alignment between each SNC structure 101b and the corresponding storage structure 103b may not be perfect. In other words, the position of the SNC structure 101b and the position of the storage structure 103b may have an offset in the XY plane. Figure 1B As shown, the contact areas of the SNC structure 101b and the corresponding memory structure 103b may have a reduced size due to the offset, thereby making the connection between the SNC structure 101b and the memory structure 103b unstable.

[0039] Conventional techniques can add SNLPs after the SNC structure 101b is formed. For example, each SNLP can extend from the SNC structure 101b to the corresponding storage structure 103b to be connected to the SNLP. In this way, better connection between the SNC structure 101b and the storage structure 103b can be provided. However, forming separate SNC structures and SNLPs can involve complex techniques (e.g., self-aligned double patterning (SADP) and self-aligned reverse patterning (SARP)) and additional manufacturing processes, which can increase manufacturing cost and reduce yield.

[0040] Embodiments of the present disclosure provide techniques for forming SNC structures having top portions that serve as landing pads for storage structures. The top portions of the SNC structures can have asymmetric structures to have greater dimensions to serve as landing pads. Details of one or more embodiments of the subject matter of the present disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.

[0041] Figure 2 A side view of a cross-section of an exemplary 3D semiconductor device 200 is shown. In some embodiments, the 3D semiconductor device 200 can be a 3D DRAM using a 4F 2 cell design. In a 4F 2 cell design, F represents half a WL (word line) pitch as a minimum feature size, and 4F 2 cell means that the cell (e.g., a DRAM cell) has an area dimension of 4F 2 It is to be understood that Figure 2 are for illustration purposes only and do not necessarily reflect actual device structures (e.g., interconnects) in practice. In some embodiments, the 3D semiconductor device 200 is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104 stacked on the first semiconductor structure 102. The first semiconductor structure 102 and the second semiconductor structure 104 can be joined at a bonding interface 106 therebetween.

[0042] As Figure 2As shown, the first semiconductor structure 102 may include a substrate 110, which may include silicon (e.g., single crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material. The first semiconductor structure 102 may include peripheral circuitry 112 on and / or in the substrate 110. In some embodiments, the peripheral circuitry 112 includes a plurality of transistors 114 (e.g., planar transistors and / or 3D transistors). Trench isolation (e.g., shallow trench isolation (STI)) and doped regions (e.g., wells, sources, and drains of the transistors 114) may also be formed on or in the substrate 110. In some examples, the peripheral circuitry 112 is formed using complementary metal oxide semiconductor (CMOS) technology, and the first semiconductor structure 102 may also be formed on a semiconductor die, which may be referred to as a control die or a CMOS die 102.

[0043] In some embodiments, the first semiconductor structure 102 further includes an interconnect layer 116 above the peripheral circuit 112 to transmit electrical signals to and from the peripheral circuit 112. The interconnect layer 116 may include a plurality of interconnects (also referred to herein as "contacts"), including lateral interconnect lines and via contacts. The interconnect layer 116 may also include one or more interlayer dielectric (ILD) layers in which the interconnect lines and via contacts may be formed. That is, the interconnect layer 116 may include interconnect lines and via contacts in multiple ILD layers. In some embodiments, the peripheral circuits 112 are coupled to each other through the interconnects in the interconnect layer 116. The interconnects in the interconnect layer 116 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layer may be formed with a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0044] like Figure 2 As shown, the first semiconductor structure 102 has a front side and a back side, and the first semiconductor structure 102 may further include a bonding layer 118 located on the back side and above the interconnect layer 116 and the peripheral circuit 112 at the bonding interface 106. The bonding layer 118 may include a plurality of bonding contacts 119 and a dielectric electrically isolating the bonding contacts 119. The bonding contacts 119 may include a conductive material, such as Cu. The remaining area of ​​the bonding layer 118 may be formed of a dielectric material such as silicon oxide. The bonding contacts 119 and the surrounding dielectric in the bonding layer 118 may be used for hybrid bonding. Similarly, as Figure 2As shown, the second semiconductor structure 104 can also include a bonding layer 120 located at the bonding interface 106 and over the bonding layer 118 of the first semiconductor structure 102. The bonding layer 120 can include a plurality of bonding contacts 121 and a dielectric that electrically isolates the bonding contacts 121. The bonding contacts 121 can include a conductive material, such as Cu. The remaining areas of the bonding layer 120 can be formed of a dielectric material, such as silicon oxide. The bonding contacts 121 and the surrounding dielectric in the bonding layer 120 can be used for hybrid bonding. The bonding contacts 121 can be in contact with the bonding contacts 119 at the bonding interface 106. In some embodiments, the bonding layer 120 includes a dielectric layer opposite the memory cells (e.g., DRAM cells) 124, with the bit lines 123 located between the dielectric layer and the memory cells 124, as shown. Figure 2 The dielectric layer can include the bonding interface 106 with the bonding contacts 121.

[0045] The second semiconductor structure 104 can be bonded in a face-to-face manner on top of the first semiconductor structure 102 at the bonding interface 106. In some embodiments, the bonding interface 106 is disposed between the bonding layers 120 and 118 as a result of hybrid bonding (also referred to as “metal / dielectric hybrid bonding”), which is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer such as solder or adhesive) and can achieve both metal-metal bonding and dielectric-dielectric bonding simultaneously. In some embodiments, the bonding interface 106 is where the bonding layers 120 and 118 meet and bond. In some examples, the bonding interface 106 can be a layer with a thickness that includes a top surface of the bonding layer 118 of the first semiconductor structure 102 and a bottom surface of the bonding layer 120 of the second semiconductor structure 104.

[0046] In some embodiments, the second semiconductor structure 104 also includes an interconnect layer 122 to transport electrical signals, which includes the bit lines 123 located over the bonding layer 120. The interconnect layer 122 can include a plurality of interconnects, such as middle-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. In some embodiments, the interconnects in the interconnect layer 122 also include local interconnects, such as the bit lines 123 and word line contacts (not shown). The interconnect layer 122 can also include one or more ILD layers in which interconnect lines and via contacts can be formed. The interconnects in the interconnect layer 122 can include a conductive material, including but not limited to W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layers can be formed with a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof.

[0047] In some embodiments, the peripheral circuitry 112 includes word line drivers / row decoders coupled to word line contacts in the interconnect layer 122 through the bond layers 120 and 118 and the bond contacts 121 and 119 in the interconnect layer 116. In some embodiments, the peripheral circuitry 112 includes bit line drivers / column decoders coupled to the bit lines 123 and the bit line contacts in the interconnect layer 122 through the bond layers 120 and 118 and the bond contacts 121 and 119 in the interconnect layer 116. In some embodiments, the bit lines 123 are metal bit lines, rather than semiconductor bit lines (e.g., doped silicon bit lines). For example, the bit lines 123 can include W, Co, Cu, Al, or any other suitable metal having a higher electrical conductivity than doped silicon. In some embodiments, the bit line contacts are ohmic contacts, rather than Schottky contacts.

[0048] In some embodiments, the bit lines 123 are made of a composite conductive material that can be based on a metal material (e.g., W, Co, Cu, Al) and a semiconductor material (e.g., Si), for example, as discussed in further detail below. For example, the composite conductive material can include a metal silicide, such as WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having a higher electrical conductivity than doped silicon.

[0049] In some embodiments, the second semiconductor structure 104 includes a DRAM device in which memory cells are disposed in the form of an array of DRAM cells 124 above the interconnect layer 122 and the bond layer 120. That is, the interconnect layer 122 including the bit lines 123 can be disposed between the bond layer 120 and the array of DRAM cells 124. The bit lines 123 in the interconnect layer 122 can be coupled to strings of DRAM cells 124. In some embodiments, the second semiconductor structure 104 is formed on a semiconductor die and can be referred to as an array die 104.

[0050] In some implementations, a semiconductor device can include a plurality of array dies (e.g., array dies 104) and a CMOS die (e.g., CMOS die 102). The plurality of array dies and the CMOS die can be stacked and bonded together. The CMOS die can be coupled to and can individually drive each of the plurality of array dies to operate in a similar manner as the semiconductor device. The semiconductor device can be any suitable device. In some examples, the semiconductor device includes at least a first wafer and a second wafer that are face-to-face bonded. The array dies can be disposed on the first wafer along with other array dies, and the CMOS die can be disposed on the second wafer along with other CMOS dies. The first wafer and the second wafer can be bonded together, so the array dies on the first wafer can be bonded with corresponding CMOS dies on the second wafer. In some examples, the semiconductor device is a chip having at least array dies and CMOS dies that are bonded together. In an example, the chip is cut from the wafers that are bonded together. In another example, the semiconductor device is a semiconductor package that includes one or more semiconductor chips assembled on a package substrate.

[0051] Each DRAM cell 124 can include a vertical transistor 126 and a capacitor 128 coupled to the vertical transistor 126. The DRAM cell 124 can be a 1T1C cell composed of one transistor and one capacitor. It should be appreciated that the DRAM cell 124 can have any suitable configuration, such as a 2T1C cell, a 3T1C cell, etc. The vertical transistor 126 can be a MOSFET for switching the corresponding DRAM cell 124. In some implementations, the vertical transistor 126 includes a semiconductor body 130 (in which an active region of a channel can be formed) that extends vertically (in the z-direction) and a gate structure 136 in contact with one side of the semiconductor body 130. In a single-gate vertical transistor, the semiconductor body 130 can have a cuboid shape or a cylindrical shape, and the gate structure 136 can abut a single side of the semiconductor body 130 in a plan view, e.g., as shown in Figure 2 In some implementations, the vertical transistor 126 has a structure that includes two or more gates, such as a dual-gate structure, a tri-gate structure, or a gate-all-around (GAA) structure. In some implementations, the gate structure 136 includes a gate electrode 134 and a gate dielectric 132 laterally between the gate electrode 134 and the semiconductor body 130 in a bit line direction (e.g., in the x-direction). In some implementations, the gate dielectric 132 abuts one side of the semiconductor body 130, and the gate electrode 134 abuts the gate dielectric 132.

[0052] As shown in Figure 2 In some implementations, the semiconductor body 130 has two ends in the vertical direction (z-direction), as shown inFigure 2 and at least one end (e.g., the lower end) extends beyond the gate dielectric 132 into the ILD layer in the vertical direction (z-direction). In some embodiments, one end (e.g., the upper end) of the semiconductor body 130 is flush with a corresponding end (e.g., the upper end) of the gate dielectric 132. In some embodiments, both ends (the upper end and the lower end) of the semiconductor body 130 extend beyond the gate electrode 134 into the ILD layer in the vertical direction (z-direction). That is, the semiconductor body 130 can have a greater vertical dimension (e.g., depth) than a vertical dimension (e.g., in the z-direction) of the gate electrode 134, and neither end (the upper end and the lower end) of the semiconductor body 130 is flush with a corresponding end of the gate electrode 134. As a result, shorting between the bit line 123 and the word line / gate electrode 134 or between the word line / gate electrode 134 and the capacitor 128 can be avoided. The vertical transistor 126 can also include a source 138 and a drain 139 (which can also be referred to as a drain 138 and a source 139, as their positions can be interchangeable) disposed at both ends (the upper end and the lower end) of the semiconductor body 130 in the vertical direction (z-direction), respectively. In some embodiments, one of the source 138 and the drain 139 (e.g., the upper end in Figure 2 is coupled to the capacitor 128, and the other of the source 138 and the drain 139 (e.g., the lower end in Figure 2 is coupled to the bit line 123. That is, the vertical transistor 126 can have a first terminal in the positive z-direction and a second terminal opposite the first terminal in the negative z-direction, as shown in Figure 2 .

[0053] In some embodiments, the semiconductor body 130 includes a semiconductor material, such as single crystalline silicon, poly crystalline silicon, amorphous silicon, Ge, any other semiconductor material, or any combination thereof. In one example, the semiconductor body 130 can include single crystalline silicon. The source 138 and the drain 139 can be doped with N+ type dopants (e.g., phosphorus (P) or arsenic (As)) or P type dopants (e.g., boron (B) or gallium (Ga)) at a desired doping level. In some embodiments, a silicide layer, such as a metal silicide layer, is formed between the drain 139 of the vertical transistor 126 and the bit line 123 as a bit line contact, or between the source 138 of the vertical transistor 126 and the first electrode of the capacitor 128 as an SNC structure (also referred to as a capacitor contact) 142 to reduce contact resistance. In some embodiments, the gate dielectric 132 includes a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to AI2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In some embodiments, the gate electrode 134 includes a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, poly silicon, silicide, or any combination thereof. In some embodiments, the gate electrode 134 includes multiple conductive layers, such as a W layer on top of a TiN layer. In one example, the gate structure 136 can be a “gate oxide / gate poly” gate, where the gate dielectric 132 includes silicon oxide and the gate electrode 134 includes doped poly silicon. In another example, the gate structure 136 can be an HKMG, where the gate dielectric 132 includes a high-k dielectric and the gate electrode 134 includes a metal.

[0054] As described above, since the gate electrode 134 can be part of a word line or extend in a word line direction (e.g., the y direction) as a word line, the second semiconductor structure 104 of the 3D semiconductor device 200 can also include a plurality of word lines, each extending in the word line direction (y direction). Each word line 134 can be coupled to a row of DRAM cells 124. That is, the bit lines 123 and the word lines 134 can extend in two perpendicular lateral directions, and the semiconductor body 130 of the vertical transistor 126 can extend in a vertical direction perpendicular to the two lateral directions in which the bit lines 123 and the word lines 134 extend. The word lines 134 are in contact with word line contacts (not shown). In some embodiments, the word lines 134 include a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, poly silicon, silicide, or any combination thereof. In some embodiments, the word lines 134 include multiple conductive layers, such as a W layer on top of a TiN layer, as shown. Figure 2

[0055] In some embodiments, as Figure 2 ​As shown, vertical transistor 126 extends vertically through and contacts wordline 134, and a drain 139 of vertical transistor 126 contacts bitline 123 (or a bitline contact, if any) at its lower end. Therefore, due to the vertical arrangement of vertical transistor 126, wordline 134 and bitline 123 can be arranged in different planes in the vertical direction, which simplifies the routing of wordline 134 and bitline 123. In some embodiments, bitline 123 is vertically arranged between bonding layer 120 and wordline 134, and wordline 134 is vertically arranged between bitline 123 and capacitor 128. Wordline 134 can be coupled to peripheral circuitry 112 in first semiconductor structure 102 via a wordline contact (not shown) in interconnect layer 122, bonding contacts 121 and 119 in bonding layers 120 and 118, and interconnects in interconnect layer 116. Similarly, the bit lines 123 in the interconnect layer 122 may be coupled to the peripheral circuitry 112 in the first semiconductor structure 102 through the bonding contacts 121 and 119 in the bonding layers 120 and 118 and the interconnects in the interconnect layer 116 .

[0056] In some embodiments, vertical transistors 126 may be arranged in a mirror-symmetrical manner to increase the density of DRAM cells 124 in the bit line direction (x direction). Figure 2 As shown, two adjacent vertical transistors 126 in the bitline direction are mirror-imaged relative to the trench isolation 160. That is, the second semiconductor structure 104 may include a plurality of trench isolations 160, each trench isolation 160 extending in the wordline direction (y-direction) parallel to the wordline 134 and disposed between the semiconductor bodies 130 of two adjacent rows of vertical transistors 126. In some embodiments, the vertical transistors 126 in each row separated by the trench isolation 160 are mirror-imaged relative to each other relative to the trench isolation 160. The trench isolation 160 may be formed of a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. It should be understood that the trench isolation 160 may include air gaps, each air gap disposed laterally between adjacent semiconductor bodies 130. The air gaps may be formed due to the relatively small spacing between the vertical transistors 126 in the bitline direction (e.g., the x-direction). On the other hand, the relatively large dielectric constant of air in the air gap (e.g., approximately 4 times the dielectric constant of silicon oxide) compared to some dielectrics (e.g., silicon oxide) can improve the insulation effect between the vertical transistors 126 (and the rows of DRAM cells 124). Similarly, in some embodiments, depending on the spacing of the word lines / gate electrodes 134 in the bit line direction, air gaps are also formed laterally between the word lines / gate electrodes 134 in the bit line direction.

[0057] like Figure 2As shown, in some embodiments, the capacitor 128 includes a first electrode 144 over the source 138 of the vertical transistor 126 and coupled to the source 138 (e.g., the upper end of the semiconductor body 130) of the vertical transistor 126 via an SNC structure 142. In some embodiments, the SNC structure 142 is an ohmic contact, such as a metal silicide contact, rather than a Schottky contact. For example, the SNC structure 142 can include a metal silicide, such as WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having a higher electrical conductivity than doped silicon. The capacitor 128 can also include a capacitor dielectric over and in contact with the first electrode 144, and a second electrode over and in contact with the capacitor dielectric. That is, the capacitor 128 can be a vertical capacitor in which the electrodes and the capacitor dielectric are stacked vertically (in the z-direction), and the capacitor dielectric can be sandwiched between the electrodes. In some embodiments, each first electrode is coupled to the source 138 of a respective vertical transistor 126 in the same DRAM cell, while all second electrodes are coupled to a common plate 146, which is coupled to ground (e.g., a common ground). The capacitor 128 can have a first end in the negative z-direction and a second end opposite the first end in the positive z-direction, as shown. Figure 2 As shown, in some embodiments, the first end of the capacitor 128 is coupled to the first terminal of the vertical transistor 126 via an ohmic contact (e.g., the SNC structure 142 made of a metal silicide material). As shown, Figure 2 As shown, the second semiconductor structure 104 can also include a capacitor contact 147 (e.g., a conductor) in contact with the common plate 146 for directly coupling the capacitor 128 to the peripheral circuit 112 or ground. In some embodiments, the capacitor contact 147 (e.g., a conductor) extends from the dielectric layer of the bonding layer 120 in the z-direction to couple to the second end of the capacitor 128 via the common plate 146, as shown. Figure 2 As shown, in some embodiments, the ILD layer in which the capacitor 128 is formed has the same dielectric material as the two ILD layers in which the semiconductor bodies 130 extend, such as silicon oxide.

[0058] It should be appreciated that the structure and configuration of the capacitor 128 is not limited to Figure 3A2, or any combination thereof. It should be understood that in some examples, capacitor 128 can be a ferroelectric capacitor used in a FRAM cell, and the capacitor dielectric can be replaced by a ferroelectric layer having a ferroelectric material (e.g., PZT or SBT). In some embodiments, the electrode comprises a conductive material including, but not limited to, W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof.

[0059] like Figure 3A As shown, vertical transistor 126 extends vertically through and contacts word line 134, a drain 139 of vertical transistor 126 contacts bit line 123 at its lower end, and a source 138 of vertical transistor 126 is coupled to capacitor 128 at its upper end. That is, due to the vertical arrangement of the vertical transistors, bit line 123 and capacitor 128 can be arranged in different planes in the vertical direction and vertically coupled to opposite ends of vertical transistor 126 of DRAM cell 124. In some embodiments, bit line 123 and capacitor 128 are arranged on opposite sides of vertical transistor 126 in the vertical direction, which simplifies the routing of bit line 123 and reduces the coupling capacitance between bit line 123 and capacitor 128 compared to DRAM cells in which the bit line and capacitor are arranged on the same side of a planar transistor.

[0060] like Figure 3A As shown, in some embodiments, the vertical transistor 126 is vertically disposed between the capacitor 128 and the bonding interface 106. That is, the vertical transistor 126 can be disposed closer to the peripheral circuit 112 of the first semiconductor structure 102 and the bonding interface 106 than the capacitor 128. Since the bit line 123 and the capacitor 128 are coupled to opposite ends of the vertical transistor 126, the bit line 123 (as part of the interconnect layer 122) is vertically disposed between the vertical transistor 126 and the bonding interface 106. As a result, the interconnect layer 122 including the bit line 123 can be disposed close to the bonding interface 106 to reduce interconnect routing distance and complexity.

[0061] In some embodiments, the second semiconductor structure 104 further includes a substrate 148 disposed above the DRAM cell 124. As described below with respect to the manufacturing process, the substrate 148 can be part of a carrier wafer. It should be understood that in some examples, the substrate 148 may not be included in the second semiconductor structure 104.

[0062] like Figure 3B As shown, the second semiconductor structure 104 may further include a pad extraction interconnect layer 150 above the substrate 148 and the DRAM cell 124. The pad extraction interconnect layer 150 may include interconnects in one or more ILD layers, such as contact pads 154. The pad extraction interconnect layer 150 and the interconnect layer 122 may be formed on opposite sides of the DRAM cell 124. The capacitor 128 may be vertically disposed between the vertical transistor 126 and the pad extraction interconnect layer 150. In some embodiments, the interconnects in the pad extraction interconnect layer 150 may transmit electrical signals between the 3D semiconductor device 200 and external circuitry, for example, for pad extraction purposes.

[0063] In some embodiments, second semiconductor structure 104 further includes one or more contacts 152 extending through substrate 148 and portions of pad extraction interconnect layer 150 to couple pad extraction interconnect layer 150 to DRAM cell 124 and interconnect layer 122. As a result, peripheral circuit 112 can be coupled to DRAM cell 124 via interconnect layers 116 and 122 and bonding layers 120 and 118, and peripheral circuit 112 and DRAM cell 124 can be coupled to external circuitry via contacts 152 and pad extraction interconnect layer 150. Contact pads 154 and contacts 152 can include conductive materials including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. In one example, contact pads 154 can include Al, and contacts 152 can include W. In some embodiments, contacts 152 include vias surrounded by dielectric spacers (e.g., comprising silicon oxide) to electrically isolate the vias from substrate 148. Depending on the thickness of substrate 148 , contacts 152 may be ILVs with a sub-micron depth (eg, between 10 nm and 1 μm) or TSVs with a micron or tens of micron depth (eg, between 1 μm and 100 μm).

[0064] Although not shown, it should be understood that the pad extraction of the 3D memory device is not limited to the pad extraction from the device having the following characteristics: Figure 3B 1. The second semiconductor structure 104 of the DRAM cell 124 is shown and can be connected from the first semiconductor structure 102 with the peripheral circuit 112. Although not shown, it is also understood that the air gaps between the word lines 134 and / or between the semiconductor bodies 130 can be partially or completely filled with a dielectric. Although not shown, it is also understood that more than one array of DRAM cells 124 can be stacked on top of each other to vertically scale up the number of DRAM cells 124.

[0065] Figure 3A FIG. 3 shows a top view of an exemplary 3D semiconductor device 300. In some embodiments, the 3D semiconductor device 300 may be fabricated using 6F2 3D DRAM cell design. 2 In cell design, F represents half the WL (word line) spacing as the minimum feature size, and 6F 2 The cell indicates that the cell (e.g., a DRAM cell) has an area size of 6F. 2 To understand, Figure 4 For illustrative purposes only and does not necessarily reflect the actual device structure (e.g., interconnection) in practice. The 3D semiconductor device 300 includes word lines 302 (also called buried word lines) extending along the Y direction and bit lines 304 extending along the X direction. The 3D semiconductor device 300 includes an active area 306. The word lines 302 extend through the active area 306 to form an array of transistors 308. Specifically, each active area 306 is extended through by two parallel word lines 302, thereby forming two transistors sharing one terminal (source or drain) in the same active area. Figure 2 As shown, the source 310 and drain 312 of each transistor are disposed on either side of the word line 302. In some embodiments, 310 may be referred to as a drain and 312 may be referred to as a source because their positions may be interchanged.

[0066] The bit line 304 may be located on top of the active region 306. The 3D semiconductor device 300 further includes a capacitor array 314 (eg, Figures 3A-3B ). Capacitor array 314 includes an array of capacitors 316. Within one active region 306, two transistors 308 share a drain 312 connected to the same bit line 304. Transistor 308 has its source 310 coupled to two corresponding capacitors 316.

[0067] Figure 2 Shown along Figure 3B 3D semiconductor device 300 is a cross-sectional view of 3D semiconductor device 300 along cutting line AA′. 3D semiconductor device 300 further includes an SNC structure 318 located between active region 306 and capacitor array 314 along the Z direction. Each source 310 is coupled to a corresponding capacitor 316 of capacitor array 314 via a corresponding SNC structure 318.

[0068] Figure 2 A semiconductor device (eg, Figure 2 The semiconductor device 200 or Figure 2 FIG. 4 is a side view of an exemplary SNC structure 400 of a semiconductor device 300 of FIG. In some embodiments, the SNC structure 400 may be Figure 4 SNC structure 142 or Figure 4 An example of an SNC structure 318. The SNC structure 400 may be used in a DRAM cell (e.g., Figure 4124), and the transistors of the DRAM cell can be connected (e.g., Figure 4 vertical transistor 126) and the storage structure of the DRAM cell (e.g., Figure 4 The transistor, SNC structure 400, and memory structure may be stacked in a vertical direction (e.g., Z direction). In some embodiments, the SNC structure 400 may include a conductive material including, but not limited to, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The SNC structure 400 may include a conductive material connected to the memory structure ( Figure 4 The top portion 402 of the transistor (not shown) is in contact with the transistor ( Figures 5A-5F 4 and 5. The top portion 402 may have a top cross-section 403 extending in the XY plane (e.g., perpendicular to the Z direction). The bottom portion 404 may have a bottom cross-section 405 extending in the XY plane (e.g., perpendicular to the Z direction). The size of the top cross-section 403 is greater than the size of the bottom cross-section 405. The axis 407 is defined as a projection line extending from the center of the bottom cross-section 405 to the top cross-section 403 in the Z direction. The axis 407 may be located in a reference plane 409 extending in the Y direction and the Z direction. In other words, the reference plane 409 passes through the center of the bottom cross-section 405 and extends in the Y direction and the Z direction. The reference plane 409 may be aligned with Figure 2 The axes 407 in overlap because Figures 3A-3B A side view along the Y direction is provided. A central section 411 of the SNC structure 400 can be formed at the intersection of the reference plane 409 and the SNC structure 400. The central section 411 can be perpendicular to the X direction and can extend from the center of the bottom section 405 to the top section 403. In some embodiments, the top section 403 is asymmetric with respect to the reference plane 409 (and the central section 411). The top section 403 can be divided by the reference plane 409 (and the central section 411) into a portion 403a and another portion 403b. The portion 403a extends from the reference plane 409 (and the central section 411) in a first direction (e.g., the X direction), and the portion 403b extends from the reference plane 409 (and the central section 411) in a second direction opposite to the first direction. In some embodiments, along the first direction, the size of the portion 403a is larger than the size of the portion 403b.

[0069] The top portion 402 has a first side (eg, a right side, also referred to as a first side) on the SNC structure 400. Figure 2 ) and on the side surface 406 on the other side (eg, the left side, also referred to as the second side, as shown ... Figure 3B4 (shown in FIG. 4 ). The first side and the second side are opposite each other relative to a reference plane 409 (and a center cross-section 411). The bottom portion 404 has a side surface 410 on the first side and a side surface 412 on the second side. In some embodiments, a tangent plane to side surface 406 can have a smaller slope than a tangent plane to side surface 410 relative to the X-direction. In some embodiments, a tangent plane to side surface 406 can have a smaller slope than a tangent plane to side surface 408 relative to the X-direction. In some embodiments, the angle between axis 407 and the tangent plane to side surface 406 is within a range between 20 degrees and 70 degrees.

[0070] Figure 4 A method for forming a semiconductor device (eg, Figure 5A The semiconductor device 200 or Figure 5B Each SNC structure in the SNC structure array may be Figure 5A SNC structure 142, Figure 5A SNC Structure 318 or Figure 5A An example of an SNC structure 400 is shown.

[0071] Figure 2 A top view of an array 500 of SNC holes 502 is shown. Figure 5C Shown along Figure 5D 508 is adjacent to row 506, and row 510 is adjacent to row 508. It should be understood that the opening shape of the SNC hole 502 is not limited to the following: Figure 5C The elliptical or oval shapes shown may include any suitable shape, such as square, rectangular or circular. It should also be understood that although Figure 5D An SNC aperture array having only three rows is shown, but any suitable number of rows may be included in the SNC aperture array.

[0072] In some embodiments, dielectric layer 504 may be formed over a transistor array (not shown). For example, the transistor array may include transistors such as Figure 5Dtransistors. Each SNC hole 502 can be formed on top of a corresponding transistor in the array of transistors and can extend in the Z-direction to a terminal (source or drain) of the corresponding transistor. In some embodiments, the SNC holes 502 of the array 500 can be formed by etching the dielectric layer 504. For example, the SNC holes 502 can be formed by a reactive ion etching (RIE) process. The RIE process can etch the dielectric layer 504 by applying an ion beam to the dielectric layer 504 at a zero angle of incidence with respect to the Z-direction. In other words, the SNC holes 502 of the array 500 can be formed by directing the ion beam toward the dielectric layer 504 in a direction perpendicular to the top surface 512 of the dielectric layer 504 during the same RIE process. The formed SNC holes 502 can expose a terminal (source or drain) of each transistor in the array of transistors. Each SNC hole 502 has an inner side surface 514 and a bottom surface 516.

[0073] At least one row of SNC holes 502 of the array 500 can be modified by a first directional ion beam etching (IBE) process. Figure 5C A top view of the array 500 modified by the first directional IBE process is shown. Figure 5C A side view of a cross-section of the modified array 500 along the cut line BB’ is shown. For example, as Figure 5E and Figure 5F shown, the SNC holes in row 506 and row 510 are modified, and the modified SNC holes are now referred to as SNC holes 502a. As Figure 5E shown, each SNC hole 502a in row 506 and row 510 is formed from a corresponding SNC hole 502 by creating an inner side surface 518a (e.g., a chamfer) between the inner side surface 514 and the top surface 512 of the dielectric layer 504. The inner side surface 518a can be formed by the first directional IBE process that applies an ion beam to the dielectric layer 504 at an angle of incidence θ1 with respect to the Z-direction. The inner side surface 518a is on a first side (e.g., the right side) of a top portion 520a of the SNC hole 502a because the ion beam is directed toward the first side. In some embodiments, a tangent plane of the inner side surface 518a is perpendicular to the angle of incidence of the ion beam in the first directional IBE process. In some embodiments, an angle between the Z-direction (or the reference plane 524) and the inner side surface 518a is in a range between 20 degrees and 70 degrees.

[0074] In some embodiments, to prevent the first directional IBE process from modifying the SNC holes 502 of row 508, row 508 can be covered by a mask (e.g., a mask 519a as Figure 5F shown) during the first directional IBE process.

[0075] AsFigure 5E As shown, each SNC hole 502a has an opening (also referred to as a top section) 521a. Opening 521a is divided into a portion 522a and a portion 523a by a reference plane 524 of the SNC hole 502a. In each SNC hole, reference plane 524 can be defined as a plane passing through the center of the bottom surface 516 of the SNC hole and extending in the Z and Y directions. Each SNC hole 502a (and 502) can have a central section 526 located at the intersection of reference plane 524 and the SNC hole 502a. Central section 526 can be perpendicular to the X direction and can extend from the center of the bottom surface 516 to the opening 521a. Opening 521a is also divided into portion 522a and portion 523a by central section 526. Opening 521a is asymmetrical relative to reference plane 524 (and central section 526). Portion 522a of opening 521a extends from reference plane 524 (and central section 526) in a first direction (e.g., the X direction). Portion 523a of opening 521a extends from reference plane 524 (and central section 526) in a second direction opposite the first direction. Along the first direction, a dimension of portion 522a is greater than a dimension of portion 523a.

[0076] In some embodiments, row 508 of array 500 can be modified by a second directional IBE process. Figure 5E A top view of the array 500 as modified by the second directional IBE process is shown. Figure 5D The modified array 500 is shown along Figure 5F The side view of the cross section of the cutting line C-C'. Figure 4 As shown, each SNC aperture 502b in row 508 is formed by creating an inner surface 518b (e.g., a chamfer) between the inner surface 514 and the top surface 512 of the dielectric layer 504. The inner surface 518b can be formed by a second directional IBE process that applies an ion beam to the dielectric layer 504 at an incident angle θ2 relative to the Z direction. The inner surface 518b is located on the second side (e.g., the left side) of the top portion 520b of the SNC aperture 502b because the ion beam in the second directional IBE process is directed toward the second side. The incident angle θ2 used in the second directional IBE process can be the same as or different from the incident angle θ1 used in the first directional IBE process. In some embodiments, the tangent plane of the inner surface 518b is perpendicular to the incident angle of the ion beam in the second directional IBE process. In some embodiments, the angle between the Z direction (or the reference plane 524 and the central section 526) and the tangent plane of the inner surface 518b is in a range between 20 degrees and 70 degrees.

[0077] In some embodiments, to prevent the second directional IBE process from modifying the SNC holes 502a of the rows 506 and 510, each of the rows 506 and 510 can be masked (eg, Figure 1B The mask 519b) shown in FIG.

[0078] In some embodiments, the first directional IBE process and the second directional IBE process may use high energy inert ions (eg, argon or xenon).

[0079] like Figure 5E As shown, each SNC hole 502b has an opening (also referred to as a top section) 521b. Opening 521b is divided into a portion 522b and a portion 523b by reference plane 524 (and center section 526) of SNC hole 502b. Opening 521b is asymmetrical relative to reference plane 524 (and center section 526). Portion 522b of opening 521b extends from reference plane 524 (and center section 526) in a first direction (e.g., the X direction). Portion 523b of opening 521a extends from reference plane 524 (and center section 526) in a second direction opposite to the first direction. Along the first direction, portion 523b is larger than portion 522b.

[0080] The SNC structure can be formed by filling one or more conductive materials into the SNC holes of the array 500 (e.g., the SNC holes 502a in rows 506 and 510 and the SNC holes 502b in row 508). The one or more conductive materials may include W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. Figures 5A-5F The inner surface 518a and Figure 6 The inner surface 518b of the SNC structure (eg, Figure 2 The top portion of the SNC structure (as shown) can have an asymmetric structure and can expand or extend in the horizontal direction (e.g., in the XY plane). Such a top portion can serve as a landing pad for a storage structure to be formed on top of the SNC structure. The landing pad can accommodate lateral offsets between the location of the storage structure and the location of the SNC structure (e.g., as shown). Figures 3A-3B As shown), and thus can provide a reliable connection between the storage structure and the SNC structure and allow the storage structure to have a larger CD.

[0081] In some embodiments, two separate directional IBE processes may be performed (e.g. Figure 2As shown in FIG, the SNC holes in two adjacent rows can be expanded to opposite sides. For example, the SNC holes in the even-indexed rows (e.g., row 506) can be expanded to one side, and the SNC holes in the odd-indexed rows (e.g., row 508) can be expanded to the opposite side. It can be understood that Figure 4 The SNC holes and fabrication methods shown are for illustrative purposes only, and any suitable variations may be applied in practice depending on the pattern and structure of the transistor array and memory structure array connected by the SNC structure. In some embodiments, the SNC holes in the even-indexed rows (e.g., rows 506 and 510) are expanded to one side, and the SNC holes in the odd-indexed rows (e.g., row 508) are not expanded. In other words, the second directional IBE process can be skipped, and a cover mask (e.g., mask 519a) is applied to the SNC holes in the odd-indexed rows in the first directional IBE process. In some other embodiments, only one directional IBE process (e.g., the first directional IBE process) is performed, and the SNC holes (in both the even-indexed and odd-indexed rows) are expanded to the same side. That is, the second directional IBE process can be skipped, and no cover mask is used in the first directional IBE process.

[0082] Figures 5A-5F A flow chart of an exemplary process 600 is shown. Process 600 may be performed, for example, to form a SNC structure in a semiconductor device (eg, a DRAM). The semiconductor device may be, for example, Figures 5A-5F The semiconductor device 200 or Figure 6 The semiconductor device 300. The SNC structure can be Figure 2 SNC structure 142, SNC structure 318 of FIG. 3 or Figures 5A-5F The SNC structure 400 is similar or identical to that of FIG. Figure 5E Process 600 may include forming Figure 5D It should be understood that the operations shown in process 600 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some operations may be performed simultaneously or in parallel. Figure 5D The order shown is different from the order in which it is executed.

[0083] At operation 602, a vertical transistor (eg, Figure 5E an array of vertical transistors 126) and a dielectric layer (e.g., Figure 5F dielectric layer 504).

[0084] At operation 604, an SNC hole array is formed in the dielectric layer. The SNC hole array includes a first row ( Figure 5Fof the SNC hole array. Each SNC hole of the SNC hole array extends along a second direction (e.g., the Z direction) that is perpendicular to the first direction, and has a top portion and a bottom portion along the second direction. The bottom portion is disposed on top of a respective vertical transistor of the array of vertical transistors.

[0085] In some implementations, the array of storage node contact holes is formed using the same RIE process with a zero angle of incidence with respect to the second direction.

[0086] At operation 606, for each storage node contact hole of the first row of storage node contact holes, a first inner side surface (e.g., inner side surface 518a) is formed on a first side (e.g., the right side) of the top portion of the storage node contact hole. Figure 5C The slope of the tangent plane of the first inner side surface with respect to the X direction is less than the slope of the tangent plane of a second inner side surface (e.g., inner side surface 514) on the first side of the bottom portion of the storage node contact hole.

[0087] In some implementations, the first inner side surface of each of the first row of storage node contact holes is formed using a first directional IBE process with a first angle of incidence (e.g., shown as θ1) that is perpendicular to the first inner side surface. Figure 5E

[0088] In some implementations, the array of storage node contact holes further includes a second row of storage node contact holes adjacent to the first row of storage node contact holes. The process 600 further includes, for each storage node contact hole of the second row of storage node contact holes, forming a third inner side surface on a first side of the top portion of the storage node contact hole. The slope of the tangent plane of the third inner side surface with respect to the X direction is less than the slope of the tangent plane of a fourth inner side surface on the first side of the bottom portion of the storage node contact hole. The tangent plane of the third inner side surface and the tangent plane of the first inner side surface have the same slope with respect to the X direction. The third inner side surface of each of the second row of storage node contact holes is formed during the first directional IBE process.

[0089] In some other implementations, the array of storage node contact holes further includes a second row (e.g., row 508) of storage node contact holes adjacent to the first row of storage node contact holes. The process 600 further includes, for each storage node contact hole of the second row of storage node contact holes, forming a third inner side surface (e.g., inner side surface 518b) on a second side (e.g., the left side) of the top portion of the storage node contact hole. Figure 7 Figure 7 ​​The slope of the tangent plane of the third inner surface is smaller than the slope of the tangent plane of the fourth inner surface (e.g., inner surface 514) on the second side of the bottom portion of the storage node contact hole relative to the X direction. The second side is opposite to the first side. In some embodiments, the third inner surface of each of the second row of storage node contact holes is formed during the second directional IBE process using a second incident angle perpendicular to the third inner surface (e.g., as shown in FIG. 1 ). Figure 2 In some embodiments, the openings of the second row of storage node contact holes are covered during the first directional IBE process (e.g., by Figures 3A-3B The mask 519a is formed, and the openings of the first row of storage node contact holes are covered during the second directional IBE process (eg, by Figure 4 mask 519b).

[0090] Figure 7 FIG2 shows a block diagram of an exemplary system 700. According to one or more embodiments of the present disclosure, the system 700 may have one or more semiconductor devices (e.g., memory devices). The system 700 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. ​ As shown, system 700 may include a host device 708 and a memory system 702 having one or more memory devices 704 and a memory controller 706. Host device 708 may include a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. Host device 708 may be configured to send data to or receive data from one or more memory devices 704.

[0091] The memory device 704 may be any memory device disclosed herein, such as ​ and ​ The memory device (eg, DRAM device) shown in or including ​A memory device of the illustrated SNC structure. In some embodiments, the memory device 704 comprises NAND flash memory. A memory controller 706 (also referred to as a controller circuit) is coupled to the memory device 704 and to a host device 708. According to embodiments of the present disclosure, the memory device 704 can include a plurality of electrically conductive interconnects that pass through a cap layer and contact electrically conductive pads in an electrically conductive pad layer, and the memory controller 706 can be coupled to the memory device 704 by at least one of the plurality of electrically conductive interconnects. The memory controller 706 is configured to control the memory device 704. For example, the memory controller 706 can be configured to operate the plurality of channel structures via word lines. The memory controller 706 can manage data stored in the memory device 704 and communicate with the host device 708.

[0092] In some embodiments, the memory controller 706 is designed / configured to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 706 is designed / configured to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which is used as data storage for mobile devices such as smartphones, tablets, laptops, etc. and enterprise storage arrays. The memory controller 706 can be configured to control operations of the memory device 704, such as read, erase, and program (or write) operations. The memory controller 706 can also be configured to manage various functions with respect to data stored or to be stored in the memory device 704, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 706 is also configured to handle error correction codes (ECC) with respect to data read from or written to the memory device 704. The memory controller 706 can also perform any other suitable functions, such as formatting the memory device 704.

[0093] The memory controller 706 can communicate with external devices (e.g., the host device 708) according to a particular communication protocol. For example, the memory controller 706 can communicate with external devices by at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a firewire protocol, etc.

[0094] The memory controller 706 and one or more memory devices 704 can be integrated into various types of memory devices, e.g., included in the same package, such as a Universal Flash Storage (UFS) package or an eMMC package. That is, the memory system 702 can be implemented and packaged into different types of end electronic products. In one example as shown, the memory controller 706 and a single memory device 704 can be integrated into a memory card 702. The memory card 702 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. ​

[0095] The implementations of the subject matter and the actions and operations described in this disclosure can be implemented in digital electronic circuitry, in tangibly-embodied computer software or firmware, in computer hardware, including the structures disclosed in this disclosure and their structural equivalents, or in combinations of one or more thereof. Implementations of the subject matter described in this disclosure can be implemented as one or more computer programs, e.g., one or more modules of computer program instructions, encoded on a computer program carrier of a non-transitory storage medium, for execution by, or to control the operation of, data processing apparatus. The carrier can be a tangible non-transitory computer storage medium. Alternatively or additionally, the carrier can be a propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, generated to encode information for transmission to suitable receiver apparatus for execution by a data processing apparatus. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more thereof. The computer storage medium is not a propagated signal.

[0096] Note that references to “one embodiment,” “an embodiment,” “example embodiment,” “some embodiments,” etc., in this disclosure indicate that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment can not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that

[0097] ​Generally, the terminology can be understood at least in part based on a usage in accordance with a context in which the terminology is used. For example, the terminology "one or more" as used herein, depending at least in part upon a context in which the terminology is used, can be used to describe any feature, structure, or characteristic in a singular sense or can be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as "a" or "an," as used herein, depending at least in part upon a context in which the terms are used, can be understood to convey a singular usage or a plural usage. Further, terms, such as "based on" or "derived from," as used herein, can be understood as not necessarily requiring a set of exclusive factors, and can instead allow for additional influencing factors, not necessarily specifically described or not specifically described.

[0098] It should be readily understood that the meaning of "on," "over," and "above" in the present disclosure should be construed in the broadest sense, such that "on" means not only directly on something but also includes the meaning of being on something with intervening features or layers therebetween. Further, "over" or "above" means not only the meaning of being over or above something but can also include the meaning of being over or above something with no intervening features or layers therebetween (i.e., directly over something).

[0099] Further, to facilitate description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and the like, can be used herein for describing an element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms can be intended to encompass different orientations of the device in use or in an operation step, in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein can be interpreted accordingly.

[0100] As used herein, the term "substrate" refers to a material to which subsequent layers of material are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where the semiconductor device is formed, so unless otherwise specified, the semiconductor device is formed on the top side of the substrate. The bottom surface is opposite the top surface, so the bottom side of the substrate is opposite the top side of the substrate. The substrate itself can be patterned. The material added to the top of the substrate can be patterned or can remain unpatterned. Further, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-N+ conductive material, such as glass, plastic, or sapphire wafer.

[0101] As used herein, the term“layer” refers to a portion of material that includes a region having a thickness. A layer can extend over an entire underlying or overlying structure, or can have an area less than the area of the underlying or overlying structure. Further, a layer can be a region of a homogenous or inhomogenous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer can be between, or at, any pair of horizontal planes between a top surface and a bottom surface of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above and / or below. A layer can include multiple layers. For example, an interconnect layer can include one or more conductive and contact layers (in which contacts, interconnect lines, and / or vertical interconnect accesses (VIA) are formed) and one or more dielectric layers.

[0102] As used herein, the term“nominal / nominally” refers to a desired or target value for a characteristic or parameter of a component or process step, as well as a range of values above and / or below the desired value, set during a design phase of a product or process. As used herein, a range of values can be due to minor variations in manufacturing processes or tolerances. As used herein, the term“about” indicates a value for a given quantity that can vary based on the particular technological node associated with the subject semiconductor device. Based on a particular technological node, the term“about” can indicate a value for a given quantity that varies, for example, within 10-30% of the stated value (e.g., ±10%, ±20%, or ±30% of the stated value).

[0103] In the present disclosure, the term“horizontal / horizontally / laterally / laterally” refers to nominally parallel to a lateral surface of a substrate, and the term“vertical” or“vertically” refers to nominally perpendicular to a lateral surface of a substrate.

[0104] As used herein, the term“3D memory” refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as“memory strings,” such as NAND strings) in a lateral orientation on a substrate, such that the memory strings extend in a vertical direction relative to the substrate.

[0105] The present disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, a first feature can be formed over or on a second feature, which can include embodiments where the first feature and the second feature are in direct contact, and can also include embodiments where additional features can be formed between the first feature and the second feature such that the first feature and the second feature can not be in direct contact. In addition, the present disclosure can repeat certain

[0106] The foregoing description of implementations has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to be limited to the precise form disclosed. Many modifications and variations are possible in light of the teaching and guidance provided. It is intended that the disclosed implementations be limited only by the claims and equivalents thereof.

[0107] While the present disclosure contains many specific embodiments, these should not be construed as limiting the scope of the claims that will be determined solely by the claims and equivalents thereof. Certain features of the disclosure described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment can also be implemented separately or in any suitable subcombination. Moreover, although features can be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination and the claim can be directed to a subcombination or subcombination of a subcombination.

[0108] Similarly, while operations are described herein as being performed in a certain order, this is not intended to be limiting. In some cases, certain operations can be performed in different orders or omitted, and still achieve desirable results. In some cases, multiple tasks can be performed at the same time, or performed sequentially. Additionally, the separation of various system modules and components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems generally can be integrated together in a single software product or packaged into multiple software products.

[0109] Particular implementations of the subject matter have been described. Other implementations are within the scope of the following claims. For example, the acts recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes described in the accompanying figures do not necessarily require the particular order or ordering shown, and in some instances, parallel processing or tasking can be advantageous.

[0110] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, and should only be defined in accordance with the following claims and their equivalents.

Claims

1. A semiconductor device comprising: A memory cell array comprising a first row of memory cells arranged along a first direction, wherein: at least one memory cell in the first row of memory cells includes a first vertical transistor, a first storage node contact structure, and a first storage structure stacked along a second direction perpendicular to the first direction; The first storage node contact structure includes a first top portion in contact with the first storage structure and a first bottom portion in contact with the first vertical transistor; and A first top cross-section of the first top portion is asymmetrical.

2. The semiconductor device according to claim 1, wherein: the first top cross-section of the first top portion being asymmetric with respect to a first central cross-section of the first storage node contact structure; the first central cross-section being perpendicular to the first direction and extending from a center of a first bottom cross-section of the first bottom portion to the first top cross-section; the first top cross-section comprising a first portion extending from the first central cross-section along the first direction and a second portion extending from the first central cross-section along a fourth direction opposite the first direction; and Along the first direction, a size of the first portion of the first top cross-section is greater than a size of the second portion of the first top cross-section.

3. The semiconductor device according to claim 2, wherein: The memory cell array further includes a second row of memory cells adjacent to the first row of memory cells; at least one memory cell in the second row of memory cells includes a second vertical transistor, a second storage node contact structure, and a second storage structure stacked along the second direction; the second storage node contact structure comprising a second top portion in contact with the second storage structure and a second bottom portion in contact with the second vertical transistor; a second top cross-section of the second top portion being asymmetric with respect to a second central cross-section of the second storage node contact structure; the second center cross-section being perpendicular to the first direction and extending from a center of a second bottom cross-section of the second bottom portion to the second top cross-section; the second top cross-section comprising a first portion extending from the second central cross-section along the first direction and a second portion extending from the second central cross-section along the fourth direction; and Along the first direction, a dimension of the second portion of the second top cross-section is greater than a dimension of the first portion of the second top cross-section.

4. The semiconductor device according to any one of claims 1 to 3, wherein The first vertical transistor is coupled to the first storage structure through the first storage node contact structure.

5. The semiconductor device according to any one of claims 1 to 4, wherein The first storage node contact structure includes at least one of metal, silicide, or doped silicon.

6. The semiconductor device according to any one of claims 1 to 5, wherein The first vertical transistor includes one of a single-gate structure, a double-gate structure, a triple-gate structure, and a gate-all-around (GAA) structure.

7. The semiconductor device according to any one of claims 1 to 6, wherein: The memory cell array is coupled to peripheral circuitry via conductive bonding contacts included in the bonding layer; and The bonding layer also includes a dielectric material that electrically isolates the conductive bonding contacts.

8. A semiconductor device comprising: A memory cell array comprising a first row of memory cells arranged along a first direction, wherein: at least one memory cell in the first row of memory cells includes a first vertical transistor, a first storage node contact structure, and a first storage structure stacked along a second direction perpendicular to the first direction; The first storage node contact structure includes a top portion in contact with the first storage structure and a bottom portion in contact with the first vertical transistor; and With respect to the first direction, a slope of a tangent plane of a side surface of the top portion of the first storage node contact structure on a first side is smaller than a slope of a tangent plane of a side surface of the bottom portion on the first side.

9. The semiconductor device according to claim 8, wherein: With respect to the first direction, a slope of the tangent plane of the side surface of the top portion of the first storage node contact structure on the first side is smaller than a slope of the tangent plane of the side surface of the top portion on the second side; and The first side and the second side are opposite to each other with respect to a third direction perpendicular to the first direction and the second direction.

10. The semiconductor device according to claim 8 or claim 9, wherein: A size of a cross-section of the top portion of the first storage node contact structure is larger than a size of a cross-section of the bottom portion of the first storage node contact structure.

11. The semiconductor device according to any one of claims 8 to 10, wherein An angle between the side surface of the top portion of the first storage node contact structure on the first side and the first direction varies from 20 degrees to 70 degrees.

12. The semiconductor device according to any one of claims 9 to 11, wherein: The memory cell array further includes a second row of memory cells adjacent to the first row of memory cells; at least one memory cell in the second row of memory cells includes a second vertical transistor, a second storage node contact structure, and a second storage structure stacked along the second direction; the second storage node contact structure comprising a top portion in contact with the second storage structure and a bottom portion in contact with the second vertical transistor; and With respect to the first direction, a slope of a tangent plane of a side surface of the top portion of the second storage node contact structure on the second side is smaller than a slope of a tangent plane of a side surface of the bottom portion of the second storage node contact structure on the second side.

13. The semiconductor device according to any one of claims 8 to 12, wherein The first vertical transistor is coupled to the first storage structure through the first storage node contact structure.

14. The semiconductor device according to any one of claims 8 to 13, wherein The first storage node contact structure includes at least one of metal, silicide, or doped silicon.

15. A method comprising: forming a vertical transistor array and a dielectric layer over the vertical transistor array; forming a storage node contact hole array in the dielectric layer, wherein the storage node contact hole array includes a first row of storage node contact holes arranged along a first direction, each storage node contact hole in the storage node contact hole array extends along a second direction perpendicular to the first direction and has a top portion and a bottom portion along the second direction, and the bottom portion is disposed on a top portion of a corresponding vertical transistor in the vertical transistor array; and For each storage node contact hole in the first row of storage node contact holes, a first inner surface is formed on a first side of the top portion of the storage node contact hole, wherein a slope of a tangent plane of the first inner surface is smaller than a slope of a tangent plane of a second inner surface on the first side of the bottom portion of the storage node contact hole relative to the first direction.

16. The method according to claim 15, wherein Forming the storage node contact hole array includes: The storage node contact hole array is formed by the same reactive ion etching (RIE) process using a zero incident angle with respect to the second direction.

17. The method according to claim 15 or claim 16, wherein: Forming the first inner surface of each storage node contact hole in the first row of storage node contact holes includes: The first inner side surface of each storage node contact hole in the first row of storage node contact holes is formed by a first directional ion beam etching (IBE) process using a first incident angle perpendicular to the first inner side surface.

18. The method according to any one of claims 15 to 17, wherein The storage node contact hole array further includes a second row of storage node contact holes adjacent to the first row of storage node contact holes, and wherein the method further includes: For each storage node contact hole in the second row of storage node contact holes, a third inner surface is formed on the first side of a top portion of the storage node contact hole, wherein a slope of a tangent plane of the third inner surface is smaller than a slope of a tangent plane of a fourth inner surface on the first side of a bottom portion of the storage node contact hole with respect to the first direction, wherein: The tangent plane of the third inner surface and the tangent plane of the first inner surface have the same slope relative to the first direction; and The third inner side surface of each storage node contact hole in the second row of storage node contact holes is formed during the first directional IBE process.

19. The method according to any one of claims 15 to 17, wherein The storage node contact hole array further includes a second row of storage node contact holes adjacent to the first row of storage node contact holes, and wherein the method further includes: For each storage node contact hole in the second row of storage node contact holes, a third inner surface is formed on a second side of a top portion of the storage node contact hole, wherein a slope of a tangent plane of the third inner surface is smaller than a slope of a tangent plane of a fourth inner surface on a second side of a bottom portion of the storage node contact hole relative to the first direction, wherein the second side is opposite to the first side.

20. The method of claim 19, wherein: The third inner side surface of each storage node contact hole in the second row of storage node contact holes is formed during a second directional IBE process using a second incident angle perpendicular to the third inner side surface; During the first directional IBE process, the openings of the second row of storage node contact holes are covered; and During the second directional IBE process, the openings of the first row of storage node contact holes are covered.

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