Semiconductor device and manufacturing method thereof

Abstract

Provided is a semiconductor device. A semiconductor device includes a substrate having active regions and isolation regions between the active regions, bit line structures disposed on the active regions, spacer structures disposed on sidewalls of the bit line structures, buried contacts disposed between the bit line structures, barrier layers disposed on the buried contacts and on sidewalls of the spacer structures, a semiconductor device includes a buried contact, a metal silicide layer disposed on the buried contact, a metal nitride layer disposed on the metal silicide layer, and a landing pad disposed on the metal nitride layer. The semiconductor device has the advantages of seamless filling and lower contact resistance.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device and a method of fabricating the same. BACKGROUND

[0002] Electronic devices are increasingly demanded to be thinner and lighter, which also drives semiconductor devices to be increasingly required to be smaller in size and higher in integration. These high-integration semiconductor devices result in less space available for elements to be disposed. For example, a landing pad is a common element applied in a dynamic random access memory (DRAM) cell to serve as an electrical interconnection function. As the node of the DRAM cell becomes smaller, the aspect ratio of the contact hole becomes higher, which results in voids in the contact in filling the contact hole, which increases the resistance of the contact and reduces the current, thus affecting the performance of the DRAM cell. SUMMARY

[0003] One embodiment of the present disclosure provides a semiconductor device, including a substrate having active regions and isolation regions between the active regions, a bit line structure disposed on the active regions, a spacer structure disposed on sidewalls of the bit line structure, a buried contact disposed between the bit line structure, a barrier layer disposed on the buried contact and on sidewalls of the spacer structure, a metal silicide layer disposed on the buried contact, a metal nitride layer disposed on the metal silicide layer, and a landing pad disposed on the metal nitride layer.

[0004] In some embodiments, sidewalls of the buried contact contact the plurality of spacer structures.

[0005] In some embodiments, the metal silicide layer includes a lower portion embedded in the buried contact and an upper portion protruding from the buried contact.

[0006] In some embodiments, sidewalls of the upper portion contact the barrier layer.

[0007] In some embodiments, a top surface of the upper portion is higher than a top surface of the buried contact.

[0008] In some embodiments, a width of the metal silicide layer is less than a width of the buried contact.

[0009] In some embodiments, sidewalls of the metal nitride layer contact the barrier layer, and an interface exists between the metal nitride layer and the barrier layer.

[0010] In some embodiments, the buried contact includes polysilicon, the metal silicide layer is a titanium silicide layer, the metal nitride layer is a titanium nitride layer, and the landing pad includes tungsten.

[0011] Another embodiment of the disclosure provides a method of fabricating a semiconductor device, including forming a bit line structure on an active region of a substrate; forming a spacer structure on sidewalls of the bit line structure; forming a buried contact between the bit line structure; forming a barrier layer on a top surface of the buried contact and on sidewalls of the spacer structure; removing a portion of the barrier layer on the top surface of the buried contact to expose the top surface of the buried contact; forming a metal silicide layer on the buried contact; forming a metal nitride layer on the metal silicide layer; and forming a landing pad on the metal nitride layer.

[0012] In some embodiments, forming the barrier layer includes performing an advanced sequential flow deposition process.

[0013] In some embodiments, the advanced sequential flow deposition process includes performing a plurality of cycles, each cycle including flowing carbon tetrachloride gas into a chamber; flowing a first purge gas to remove excess carbon tetrachloride gas from the chamber; flowing ammonia gas into the chamber; and flowing a second purge gas to remove excess ammonia gas from the chamber.

[0014] In some embodiments, forming the metal silicide layer includes performing a selective deposition process to deposit a metal on the top surface of the buried contact, and then the deposited metal reacts with silicon material in the buried contact.

[0015] In some embodiments, the selective deposition process also deposits a metal layer on the metal silicide layer.

[0016] In some embodiments, the method further includes performing a nitridation process to convert the metal layer to a metal nitride layer.

[0017] In some embodiments, the buried contact includes polysilicon, the metal silicide layer is a titanium silicide layer, the metal nitride layer is a titanium nitride layer, and the landing pad includes tungsten. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to make the purpose, features, advantages, and embodiments of the disclosure more obvious and easy to understand, the detailed description of the accompanying drawings is as follows:

[0019] Figure 1 A schematic diagram of a layout of a semiconductor device according to some embodiments of the disclosure.

[0020] Figures 2 to 9 Cross-sectional schematic diagrams of different manufacturing stages of a method of fabricating a semiconductor device according to some embodiments of the disclosure. DETAILED DESCRIPTION

[0021] Embodiments of the present disclosure will be described below with reference to the accompanying drawings, wherein like elements are generally denoted by like reference numerals. The present disclosure is not limited to the embodiments described below, which are presented as examples. The following detailed description includes specific details for the purpose of providing a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without these specific details. In some instances, well-known structures and elements have not been described in detail or have been shown in block diagram form in order to avoid obscuring the present disclosure. In addition, for the purpose of clarity, the description set forth in this specification can not identify a specific technique or methodology as a prior art reference to the technical disclosure. Furthermore, the description set forth in this specification is not intended to limit the scope or application of the present disclosure in that the description is intended to encompass any modification, alteration, or equivalent arrangement not expressly described herein but which are within the scope and spirit of the present disclosure. It should be appreciated that those skilled in the art can readily combine the elements of the following detailed description with the present disclosure to produce further embodiments without departing from the scope and spirit of the present disclosure. In addition, the drawings are not drawn to scale, but are merely intended for illustrative purposes.

[0022] When an element is referred to as being "on" another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In addition, the drawings are merely schematic and are not drawn to scale. The same reference numerals in different drawings represent the same or similar elements.

[0023] Reference will now be made to Figure 1 FIG. 1 is a schematic diagram of a layout of a semiconductor device according to some embodiments of the present disclosure. The semiconductor device 100 includes a plurality of active areas AA. In some embodiments, the active areas AA have a short axis and a long axis, and the active areas AA are substantially elliptical in a top view. In some embodiments, the long axis of the active areas AA extends along a diagonal direction along the X-axis.

[0024] A plurality of word lines WL are disposed to pass through the active areas AA and extend along the X-axis direction. The word lines WL are parallel to each other. In addition, the word lines WL can be spaced apart from each other at equal intervals.

[0025] A plurality of bit lines BL are disposed on the word lines WL and can extend along the Y-axis direction. Similarly, the bit lines BL are parallel to each other. In addition, the bit lines BL can be further connected to the corresponding active areas AA by direct contacts DC. In some embodiments, each active area AA is electrically connected to one direct contact DC.

[0026] A plurality of buried contacts BC are formed between adjacent two bit lines BL, respectively. In some embodiments, the buried contacts BC are spaced apart along the Y-axis direction.

[0027] A plurality of landing pads LP are disposed on the buried contacts BC and cover at least a portion of the corresponding bit lines BL. The landing pads LP are electrically connected to the buried contacts BC. The landing pads LP further electrically connect the lower electrodes (not shown) of the capacitors disposed thereon to the corresponding active areas AA. The landing pads LP and the buried contacts BC together act as contact plugs that electrically connect the capacitors to the active areas AA. The capacitors and the corresponding transistors (including the active areas AA) can be considered as 1T1C memory cells.

[0028] Referring to Figures 2 to 9 , Figures 2 to 9 are cross-sectional schematic views of different fabrication stages of a method of fabricating a semiconductor device according to some embodiments of the present disclosure, and the cross-sectional plane passes through lines A-A shown in Figure 1 .

[0029] Embodiments of the present disclosure provide a plurality of operational steps. The order in which some or all of these operational steps are described is not intended to be construed as a limitation, unless explicitly stated. Embodiments of the present disclosure can be adapted, modified and / or extended in various ways, some of which have been described already. It is to be understood that any feature described in relation to an embodiment of the present disclosure can be implemented in any other embodiment of the present disclosure unless the context clearly dictates otherwise. Furthermore, unless explicitly stated, any feature described in relation to one embodiment of the present disclosure can also be implemented in any other embodiment of the present disclosure.

[0030] Referring to Figure 2 , a method of fabricating a semiconductor device begins at step S10, in which a plurality of bit line structures 120 are formed on a substrate 102.

[0031] The substrate 102 can include a plurality of isolation regions 104 and a plurality of active regions 106. The substrate 102 can be, for example, a silicon substrate (e.g., a single crystalline silicon substrate, a polycrystalline silicon substrate, or an amorphous silicon substrate). Alternatively, the substrate 102 can be a silicon substrate doped with other semiconductor elements, such as germanium. In some embodiments, the substrate 102 can include semiconductor alloys, such as SiGe, SiGeC, GaInP, etc. In some embodiments, the substrate 102 can include semiconductor compounds, such as GaAs, SiC, InP, InAs, etc. In addition, in some embodiments, the substrate 102 can include a silicon-on-insulator structure. The active regions 106 can be doped regions in the substrate 102, and the active regions 106 are separated from each other by the isolation regions 104.

[0032] The isolation region 104 can be formed by a shallow trench isolation technique. The isolation region 104 can include a material including at least one of silicon oxide, silicon nitride, silicon oxynitride, for example. The isolation region 104 can include a single layer of dielectric, a double layer of dielectric, or a multi-layer of dielectric. For example, the isolation region 104 can be a double layer structure including silicon oxide and silicon nitride. For example, the isolation region 104 can be a triple layer structure including silicon oxide, silicon nitride, and silicon oxynitride.

[0033] The isolation layer 108 is formed on the substrate 102 and covers the upper surfaces of the isolation region 104 and the active regions 106 of the substrate 102. The isolation layer 108 includes at least one opening to expose at least one of the active regions 106 of the substrate 102. The opening is further filled with a conductive material to form a direct contact 110, also referred to as a bit line contact. In some embodiments, the direct contact 110 is electrically connected to a corresponding active region 106, and a portion of the active region 106 serves as a source of a transistor.

[0034] A plurality of bit line structures 120 are formed on the substrate 102. In some embodiments, the bit line structures 120 are regularly arranged on the substrate 102 with the same pitch. The bit line structure 120 includes two portions arranged along a vertical direction of the substrate 102 (i.e., along the Z-axis direction). In some embodiments, the bit line structure 120 includes a conductor layer 122 in a lower portion and an insulating cap layer 124 in an upper portion.

[0035] The conductor layer 122 and the insulating cap layer 124 are formed by forming a conductive material layer and an insulating cap layer material layer on the substrate 102, where the insulating cap layer material layer is formed on the conductive material layer. In some embodiments, the insulating cap layer material layer and the conductive material layer are etched simultaneously to form the conductor layer 122 and the insulating cap layer 124. In this way, the plurality of bit line structures 120 including the conductor layer 122 and the insulating cap layer 124 can be separated in a first direction (e.g., the X-axis direction), and the plurality of bit line structures 120 are arranged in parallel in a second direction (e.g., the Y-axis direction). In other embodiments, the insulating cap layer material layer can be etched to form a mask pattern on the conductive material layer, and the conductive material layer is etched using the patterned insulating cap layer material layer as a mask to form the conductor layer 122.

[0036] In some embodiments, the conductor layer 122 includes at least one conductive material, such as a doped semiconductor, a metal, a conductive metal nitride, a conductive metal silicide, etc. In some embodiments, the conductor layer 122 can be a stack structure. For example, the conductor layer 122 can be a stack including a doped semiconductor, a metal, a conductive metal nitride, etc., such as a stack of W, WN, and / or TiN, etc. The conductor layer 122 is electrically connected to the direct contact 110. In some embodiments, the insulating cap layer 124 includes silicon nitride. The vertical length (i.e., the length along the Z-axis direction) of the insulating cap layer 124 can be greater than the vertical length of the conductor layer 122.

[0037] Referring to Figure 3 The method of fabricating a semiconductor device proceeds to step S12, in which a plurality of spacer structures 130 are formed on the sidewalls of the bit line structures 120, and a plurality of buried contacts 140 are formed between the bit line structures 120.

[0038] The spacer structures 130 are disposed along the sidewalls of the bit line structures 120. The spacer structures 130 can be a single layer structure or a multi-layer structure. In some embodiments, the spacer structures 130 can include silicon nitride, silicon oxide, or a combination thereof. In some embodiments, the spacer structures 130 can include a sacrificial layer, which can be removed in a subsequent process to form air gaps in the spacer structures 130. In some embodiments, the spacer structures 130 can be fabricated by any suitable process, such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, etc.

[0039] After the spacer structures 130 are formed on the sidewalls of the bit line structures 120, the buried contacts 140 are then formed between the bit line structures 120 and the spacer structures 130 thereon. The buried contacts 140 can also be referred to as capacitor contacts. The formation of the buried contacts 140 includes performing an etching process to form a recess, such that a portion of the isolation region 104 of the substrate 102 and a portion of the active region 106 of the substrate 102 are exposed via the recess. In some embodiments, the recess and the space thereon are also referred to as a contact hole 150.

[0040] A deposition process is then performed to fill the exposed portion of the isolation region 104 of the substrate 102 and the exposed portion of the active region 106 of the substrate 102 with a first conductive material, and to continue filling the contact hole 150. A back-etching process is then performed to remove a portion of the first conductive material, leaving behind the first conductive material as the buried contacts 140 between the bit line structures 120. The sidewalls of the upper sections of the spacer structures 130 are exposed after the back-etching process is performed.

[0041] In some embodiments, the height of the buried contact 140 can be greater than the height of the conductor layer 122 of the bit line structure 120. That is, the top surface 140T of the buried contact 140 can be higher than the top surface 122T of the conductor layer 122 of the bit line structure 120. In some embodiments, the material of the buried contact 140 is a silicon-containing material. For example, the material of the buried contact 140 can be doped polysilicon.

[0042] Referring to Figure 4 , the method of fabricating the semiconductor device proceeds to step S14, in which a barrier layer 160 is conformally deposited on the structure as shown in FIG. 1C. In some embodiments, the barrier layer 160 is deposited on the sidewall 130W of the spacer structure 130 and on the top surface 140T of the buried contact 140. In other words, the barrier layer 160 is blanket deposited on the upper section of the contact hole 150. Figure 3

[0043] The barrier layer 160 is preferably deposited with a uniform thickness. The barrier layer 160 can be deposited by an advanced sequential flow deposition (ASFD) process, which has the advantage of good step coverage capability. The barrier layer 160 can include a metal layer, a metal nitride layer, or a combination thereof. The metal layer includes, for example, Ti, Ta, or a combination thereof. The metal nitride layer includes, for example, TiN, TiAlN, TaN, or a combination thereof. In some embodiments, the barrier layer 160 is a TiN layer.

[0044] In some embodiments, the advanced sequential flow deposition process used to form the barrier layer 160 includes one or more cycles. One cycle of the advanced sequential flow deposition process includes: flowing carbon tetrachloride (CCl4) gas into the chamber; flowing a purge gas to remove excess carbon tetrachloride gas in the chamber; flowing ammonia (NH3) gas into the chamber; and flowing a purge gas to remove excess ammonia gas in the chamber.

[0045] In some embodiments, the advanced sequential flow deposition process includes repeating the cycle multiple times, and the thickness of the barrier layer 160 can be determined by the number of cycles performed by the advanced sequential flow deposition process. After the advanced sequential flow deposition process is performed, the barrier layer 160 with a uniform thickness is obtained on the sidewall 130W of the spacer structure 130, on the top surface 140T of the buried contact 140, and on the top surfaces of the bit line structure 120 and the spacer structure 130.

[0046] Referring to Figure 5 ​The method of fabricating the semiconductor device proceeds to step S16, where a portion of the barrier layer 160 on the top surface 140T of the buried contact 140 is removed. In some embodiments, a directional etch-back process is performed to remove a portion of the barrier layer 160 on the top surface 140T of the buried contact 140. The top surface 140T of the buried contact 140 is exposed after the directional etch-back process is performed, while the sidewall 130W of the spacer structure 130 is still covered by the barrier layer 160. In some embodiments, a portion of the barrier layer 160 on the top surface of the bit line structure 120 and the spacer structure 130 is also removed in the directional etch-back process, and the top surface of the bit line structure 120 and the spacer structure 130 is exposed after the directional etch-back process is performed.

[0047] Referring to Figure 6 The method of fabricating the semiconductor device proceeds to step S18, where a metal silicide layer 170 is formed at the exposed top surface of the buried contact 140, and then a metal layer 180 is formed on the metal silicide layer 170. The metal silicide layer 170 is fabricated by chemical vapor deposition. The process of chemical vapor deposition includes introducing a metal-containing precursor along with a carrier gas, such as an inert gas, into a chamber. In some embodiments, the metal-containing precursor is a titanium-containing precursor. The titanium is deposited on the top surface of the buried contact 140 and reacts with the polysilicon material in the buried contact 140 to form the metal silicide layer 170, such as a titanium silicide layer, on the buried contact 140. Also, the amount of the metal-containing precursor introduced into the chamber is greater than the amount required to form the metal silicide layer 170. That is, the amount of the metal-containing precursor introduced into the chamber is sufficient not only to form the metal silicide layer 170, but also to form a thin metal layer 180, such as a titanium layer, on the metal silicide layer 170 after the metal silicide layer 170 is formed. In some embodiments, the deposition of titanium is a selective deposition. That is, the titanium is deposited only on the buried contact 140, but not on the barrier layer 160.

[0048] Referring to Figure 7 The method of fabricating the semiconductor device proceeds to step S20, where a nitridation process is performed to convert the previously deposited thin metal layer 180 (see Figure 6 ) into a metal nitride layer 190, such as a titanium nitride layer, on the metal silicide layer 170.

[0049] Referring to Figure 8 The method of fabricating the semiconductor device proceeds to step S22, where a second conductive material 200 is deposited to fill the contact hole 150 (see Figure 7The second conductive material 200 is different in material from the first conductive material of the buried contact 140. For example, the first conductive material of the buried contact 140 can be doped polysilicon, while the second conductive material 200 can be a metal such as tungsten. The second conductive material 200 not only fills the contact hole 150, but further covers the top surface of the bit line structure 120.

[0050] As discussed in the foregoing Figures 4 to 8 The barrier layer 160 disposed on the sidewall of the spacer structure 130 is deposited by an advanced sequential flow deposition process, which has good step coverage, as discussed in the foregoing. Thus, the barrier layer 160 can have a uniform thickness, and overhang phenomenon, such as a barrier layer thickness at the top of the contact hole being greater than the barrier layer thickness at the bottom of the contact hole when a chemical vapor deposition is used to deposit the barrier layer, can be avoided. In this way, the contact hole 150 can be free from being partially enclosed or capped by the barrier layer 160, and the inner diameter of the contact hole 150 can thus be kept uniform from bottom to top. In this way, the second conductive material 200 can seamlessly fill the contact hole 150.

[0051] In addition, the layers between the second conductive material 200 and the buried contact 140 include a metal silicide layer 170 on the buried contact 140 and a metal nitride layer 190 on the metal silicide layer 170. Compared to the case where the second conductive material 200 is formed directly on the buried contact 140, the addition of the metal silicide layer 170 and the metal nitride layer 190 between the two can greatly reduce the contact resistance of the layer stack in the contact hole 150. Further, the metal silicide layer 170, such as a titanium silicide layer, plays an important role in reducing the contact resistance between the buried contact 140, such as a polysilicon material, and the metal nitride layer 190, such as a titanium nitride layer. The metal nitride layer 190 under the second conductive material 200 not only serves as part of the contact, but can also be used to prevent diffusion of the second conductive material 200.

[0052] Continuing to refer back to Figure 8 In each contact hole 150, the buried contact 140 is disposed at the bottom of the contact hole 150, and a portion of the buried contact 140 extends into the substrate 102 and contacts the isolation region 104 and the active region 106. The side surface of the buried contact 140 contacts the spacer structure 130. The barrier layer 160 is disposed on the buried contact 140 and on the sidewall of the contact hole 150.

[0053] The metal silicide layer 170 is disposed on the buried contact 140, and a portion of the metal silicide layer 170 is surrounded by the buried contact 140. The metal silicide layer 170 includes an upper portion 172 embedded in the buried contact 140 and a lower portion 174 protruding from the buried contact 140. The bottom surface of the upper portion 172 of the metal silicide layer 170 is in contact with the side surface of the buried contact 140, and the side surface of the lower portion 174 of the metal silicide layer 170 is in contact with the barrier layer 160. The top surface 174T of the lower portion 174 is higher than the top surface 140T of the buried contact 140. The width Wl of the metal silicide layer 170 is smaller than the width W2 of the buried contact 140.

[0054] The metal nitride layer 190 is disposed on the metal silicide layer 170. The side surface of the metal nitride layer 190 is in contact with the barrier layer 160. The width W3 of the metal nitride layer 190 is equal to the width Wl of the metal silicide layer 170. The width W3 of the metal nitride layer 190 is smaller than the width W2 of the buried contact 140. Since the metal nitride layer 190 and the barrier layer 160 are fabricated by different process steps, there is an interface between the metal nitride layer 190 and the barrier layer 160.

[0055] Referring to Figure 9 , the method of fabricating the semiconductor device proceeds to step S24, and an etching process is performed to define a plurality of landing pads 210. The etching process includes first forming a mask pattern (not shown) on the second conductive material 200 (see Figure 8 ). Then, the second conductive material 200 is etched with the mask pattern as a mask. In some embodiments, portions of the bit line structure 120 and the spacer structure 130 on the sidewalls thereof are also removed in this etching process. After the etching process is completed, the landing pads 210 are defined, and the landing pads 210 are separated by openings therebetween. In some embodiments, the landing pads 210 cover the top surfaces of the bit line structure 120 and are in contact with the insulating cap layer 124.

[0056] According to some embodiments of the present disclosure, the contact structure, including the landing pads 210, the metal nitride layer 190, the metal silicide layer 170, and the buried contact 140, fabricated by the above process steps, can provide the advantages of seamless filling and lower contact resistance.

[0057] Although the present disclosure has been disclosed with reference to embodiments, it is not intended to limit the present disclosure. Any person skilled in the art can make various modifications and improvements without departing from the spirit and scope of the present disclosure, and the scope of protection of the present disclosure is defined by the appended claims.

[0058]

Symbol Description

[0059] 100: semiconductor device

[0060] 102: substrate

[0061] 104: isolation region

[0062] 106: active region

[0063] 108: isolation layer

[0064] 110: direct contact

[0065] 120: bit line structure

[0066] 122: conductor layer

[0067] 122T: top surface

[0068] 124: insulating cap layer

[0069] 130: spacer structure

[0070] 130W: sidewall

[0071] 140: buried contact

[0072] 140T: top surface

[0073] 150: contact hole

[0074] 160: barrier layer

[0075] 170: metal silicide layer

[0076] 172: upper portion

[0077] 174: lower portion

[0078] 174T: top surface

[0079] 180: metal layer

[0080] 190: metal nitride layer

[0081] 200: second conductive material

[0082] 210: landing pad

[0083] AA: active region

[0084] BC: buried contact

[0085] BL: bit line

[0086] DC: direct contact

[0087] LP: landing pad

[0088] S10, S12, S14, S16, S18, S20, S22, S24: steps

[0089] WL: word line

[0090] W1, W2, W3: width

[0091] X, Y, Z: axes

Claims

1. A semiconductor device, characterized in that: Include: a substrate comprising a plurality of active regions and a plurality of isolation regions between the plurality of active regions; a plurality of bit line structures disposed on the plurality of active regions; a plurality of spacer structures disposed on sidewalls of the plurality of bit line structures; a buried contact disposed between the plurality of bit line structures; a barrier layer disposed on the buried contact and on sidewalls of the plurality of spacer structures; a metal silicide layer disposed on the buried contact; a metal nitride layer, disposed on the metal silicide layer; as well as A landing pad is disposed on the metal nitride layer. 2 . The semiconductor device of claim 1 , wherein sidewalls of the buried contact contact the plurality of spacer structures. 3 . The semiconductor device according to claim 1 , wherein the metal silicide layer comprises a lower portion and an upper portion, the lower portion being embedded in the buried contact, and the upper portion being protruding from the buried contact. The semiconductor device according to claim 3 , wherein a sidewall of the upper portion contacts the barrier layer. The semiconductor device according to claim 3 , wherein a top surface of the upper portion is higher than a top surface of the buried contact. 6 . The semiconductor device according to claim 1 , wherein a width of the metal silicide layer is smaller than a width of the buried contact. 7 . The semiconductor device according to claim 1 , wherein a sidewall of the metal nitride layer contacts the barrier layer, and an interface exists between the metal nitride layer and the barrier layer. 8 . The semiconductor device according to claim 1 , wherein the buried contact comprises polysilicon, the metal silicide layer is a titanium silicide layer, the metal nitride layer is a titanium nitride layer, and the landing pad comprises tungsten.

9. A method for manufacturing a semiconductor device, characterized in that: Include: forming a plurality of bit line structures on a plurality of active regions of the substrate; forming a plurality of spacer structures on sidewalls of the plurality of bit line structures; forming buried contacts between the plurality of bit line structures; forming a barrier layer on a top surface of the buried contact and on sidewalls of the plurality of spacer structures; removing a portion of the barrier layer on the top surface of the buried contact to expose the top surface of the buried contact; forming a metal silicide layer on the buried contact; forming a metal nitride layer on the metal silicide layer; as well as A landing pad is formed on the metal nitride layer.

10. The method of claim 9, wherein forming the barrier layer comprises performing an advanced sequential flow deposition process.

11. The method of claim 10, wherein the advanced sequential flow deposition process comprises performing a plurality of cycles, each of the cycles comprising: introducing carbon tetrachloride gas into the chamber; introducing a first purge gas to remove excess carbon tetrachloride gas in the chamber; introducing ammonia gas into the chamber; and A second purge gas is introduced to remove excess ammonia gas in the chamber.

12. The method of claim 9, wherein forming the metal silicide layer comprises performing a selective deposition process to deposit metal on the top surface of the buried contact, followed by the deposited metal reacting with silicon material in the buried contact.

13. The method of claim 12, wherein the selective deposition process further deposits a metal layer on the metal silicide layer.

14. The method according to claim 13, wherein The method further includes performing a nitridation process to convert the metal layer into the metal nitride layer. 15 . The method of claim 9 , wherein the buried contact comprises polysilicon, the metal silicide layer is a titanium silicide layer, the metal nitride layer is a titanium nitride layer, and the landing pad comprises tungsten.

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