Memory device and manufacturing method thereof

Abstract

The invention discloses a memory device and a manufacturing method thereof. The memory device comprises a semiconductor substrate, a floating gate and an erase gate. The floating gate and the erase gate are arranged on the semiconductor substrate, and the erase gate comprises a main body part and a first branch part. The main body part extends along a first horizontal direction, and the first branch part extends along a second horizontal direction and is connected with the main body part. A first portion of the floating gate is under the first branch in the vertical direction.

Description

TECHNICAL FIELD

[0001] The present invention relates to a memory device and a method of fabricating the same, and more particularly to a memory device with an erase gate and a method of fabricating the same. BACKGROUND

[0002] Semiconductor memory is a semiconductor device used for storing data or data in a computer or electronic product, which can be classified as volatile memory and non-volatile memory. The non-volatile memory is widely used because of its characteristic of not losing stored data due to interruption of power supply. As the function of computer microprocessor becomes more and more powerful, the requirement for memory (e.g. embedded memory) is also increasing, and the fabrication method and structure of embedded memory are easily affected by other devices on the chip and need to be integrated in the design. Therefore, how to improve the operating performance of the memory device by changing the structure or / and fabrication method has been the goal of the related industry. SUMMARY

[0003] The present invention provides a memory device and a method of fabricating the same, which improves the operating performance of the memory device by using an erase gate with a branch portion.

[0004] One embodiment of the present invention provides a memory device, which includes a semiconductor substrate, a floating gate and an erase gate. The floating gate and the erase gate are disposed on the semiconductor substrate, and the erase gate includes a main portion and a first branch portion. The main portion extends along a first horizontal direction, and the first branch portion extends along a second horizontal direction and is connected to the main portion. A first portion of the floating gate is located below the first branch portion in a vertical direction.

[0005] One embodiment of the present invention provides a method of fabricating a memory device, which includes the following steps. A semiconductor substrate is provided, and a floating gate and an erase gate are formed on the semiconductor substrate. The erase gate includes a main portion and a first branch portion. The main portion extends along a first horizontal direction, and the first branch portion extends along a second horizontal direction and is connected to the main portion. A first portion of the floating gate is located below the first branch portion in a vertical direction. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 FIG. 1 is a schematic diagram of a memory device according to a first embodiment of the present invention;

[0007] Figure 2 FIG. 2 is a schematic diagram of a cross section of the memory device according to the first embodiment of the present invention;

[0008] Figure 3 FIG. 3 is another schematic diagram of a cross section of the memory device according to the first embodiment of the present invention.

[0009] Figure 4 schematic cross-sectional view of a memory device according to a first embodiment of the present invention;

[0010] Figure 5 schematic cross-sectional view of a memory device according to a first embodiment of the present invention;

[0011] Figures 6 to 12 schematic cross-sectional view of a memory device according to a first embodiment of the present invention;

[0012] Figure 7 schematic cross-sectional view of a memory device according to a first embodiment of the present invention; Figure 6 schematic cross-sectional view of a memory device according to a first embodiment of the present invention;

[0013] Figure 8 schematic cross-sectional view of a memory device according to a first embodiment of the present invention; Figure 6 schematic cross-sectional view of a memory device according to a first embodiment of the present invention;

[0014] Figure 9 schematic cross-sectional view of a memory device according to a first embodiment of the present invention; Figure 8 schematic cross-sectional view of a memory device according to a first embodiment of the present invention;

[0015] Figure 10 schematic cross-sectional view of a memory device according to a first embodiment of the present invention; Figure 9 schematic cross-sectional view of a memory device according to a first embodiment of the present invention;

[0016] Figure 11 schematic cross-sectional view of a memory device according to a first embodiment of the present invention; Figure 10 schematic cross-sectional view of a memory device according to a first embodiment of the present invention;

[0017] Figure 12 schematic cross-sectional view of a memory device according to a first embodiment of the present invention. Figure 11 schematic cross-sectional view of a memory device according to a first embodiment of the present invention.

[0018] Figure 13 schematic cross-sectional view of a memory device according to a second embodiment of the present invention.

[0019] Legend

[0020] 10: semiconductor substrate

[0021] 10A: active region

[0022] 10BS: bottom surface

[0023] 12: isolation structure

[0024] 14: dielectric layer

[0025] 16: patterned material layer

[0026] 18: dielectric layer

[0027] 20: dielectric layer

[0028] 22: gap sub

[0029] 24: patterned mask layer

[0030] 26: dielectric layer

[0031] 28: dielectric layer

[0032] 30: dielectric layer

[0033] 32: dielectric layer

[0034] 34: dielectric layer

[0035] 36: dielectric layer

[0036] 38: dielectric layer

[0037] 40: dielectric layer

[0038] 91: removal fabrication process

[0039] 92: etching fabrication process

[0040] 101: memory device

[0041] 102: memory device

[0042] BL: bit line region

[0043] BP: branch portion

[0044] BP1: first branch portion

[0045] BP2: second branch portion

[0046] CT1: contact structure

[0047] CT2: contact structure

[0048] CT3: contact structure

[0049] D1: first horizontal direction

[0050] D2: second horizontal direction

[0051] D3: vertical direction

[0052] EG: erase gate

[0053] F1: first portion

[0054] F2: second portion

[0055] F3: third portion

[0056] FG: floating gate

[0057] H1: first portion

[0058] H2: second portion

[0059] HM: patterned mask layer

[0060] L1: length

[0061] L11: length

[0062] L12: length

[0063] L13: length

[0064] L2: length

[0065] MP: main part

[0066] SL: source line region

[0067] TS1: top surface

[0068] TS2: top surface

[0069] WL: word line structure DETAILED DESCRIPTION

[0070] The following detailed description of the application discloses sufficient information to enable those skilled in the art to practice the application. The embodiments described below are exemplary and not limiting. It is apparent to a person of ordinary skill in the art that various changes and modifications can be made that will affect the form and details of the application while staying within the spirit and scope of the application.

[0071] Before further description of the embodiments, the following terminology used throughout the specification will first be addressed.

[0072] The terms "on," "over," and "above" are to be interpreted in the broadest context to mean not only "directly on" something but also to include the meaning of being on something with other intervening features or layers therebetween, and "over" or "above" something not only means "over" or "above" something but also can include the meaning of being "over" or "above" something without other intervening features or layers therebetween (i.e., directly on something).

[0073] The use of ordinal terms such as "first," "second," etc., in the specification and claims to modify a claim element does not imply and should not be construed as implying, any order or sequence among or between such claim elements and does not imply and should not be construed as implying any priority of one claim element over another. The use of ordinal terms in the specification and claims is merely to distinguish one claim element from another having the same name.

[0074] The term "etching" is generally used herein to describe a process for patterning a material so that at least a portion of the material remains after the etching is complete. When "etching" a material, at least a portion of the material may remain after the etching is complete. In contrast, when "removing" a material, substantially all of the material may be removed during the process. However, in some embodiments, "removing" may be considered a broad term to include etching.

[0075] The terms "forming" or "disposing" are used hereinafter to describe the act of applying a layer of material to a substrate. These terms are intended to describe any feasible layer formation technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0076] See also Figures 1 to 5 . Figure 1 is a schematic diagram of a memory device 101 according to a first embodiment of the present invention, Figure 2 is a schematic cross-sectional view of the memory device of this embodiment, Figure 3 is another cross-sectional schematic diagram of the memory device of this embodiment, Figure 4 is another cross-sectional view of the memory device of this embodiment, and Figure 5 FIG. 1 is a partial enlarged schematic diagram of the memory device of this embodiment. Figure 1 and Figure 5 is a schematic top view of a memory device, Figure 2 Can be considered as Figure 1 The cross-sectional view shown by the A-A' section line in FIG. Figure 3 Can be considered as Figure 1 The cross-sectional view shown by the BB' section line in FIG. Figure 4 Can be considered as Figure 1 The cross-sectional view is shown along the CC' section line in FIG. 1 , and in order to more clearly show the structural features in the top view, some components in the cross-sectional view are not shown in the top view. Figures 1 to 5As shown, the memory device 101 includes a semiconductor substrate 10, a floating gate FG, and an erase gate EG. The floating gate FG and the erase gate EG are disposed above the semiconductor substrate 10, and the erase gate EG includes a main portion MP and a branch portion BP (e.g., a first branch portion BP1). The main portion MP extends along a first horizontal direction D1, and the first branch portion BP1 extends along a second horizontal direction D2 and is connected to the main portion MP. A first portion F1 of the floating gate FG is located below the first branch portion BP1 in a vertical direction D3. By the design of the erase gate EG with the branch portion BP, the size of the region where the edge of the floating gate FG and the edge of the erase gate EG are electrically coupled to each other or / and F-N tunneling is increased, so that the programming speed and the erase speed of the memory device 101 are improved or / and the operating voltage of the memory device 101 is reduced to improve the operating window of the memory device 101.

[0077] In some embodiments, the memory device 101 can include a plurality of floating gates FG disposed apart from each other, and the erase gate EG can include a plurality of branch portions BP, and each branch portion BP can extend along the second horizontal direction D2 and be directly connected to the main portion MP. Some of the floating gates FG can be respectively located on two opposite sides of the erase gate EG in the second horizontal direction D2, some of the branch portions BP can be respectively located on two opposite sides of the main portion MP in the second horizontal direction D2, the erase gate EG can have a fishbone shape in a top view of the memory device 101, and the first horizontal direction D1 can be substantially orthogonal to the second horizontal direction D2, but not limited thereto. In the top view of the memory device 101, each floating gate FG can be disposed corresponding to two branch portions BP and partially overlap with the two branch portions BP in the vertical direction D3, respectively, and the two branch portions BP corresponding to the same floating gate FG can be regarded as the first branch portion BP1 and the second branch portion BP2, respectively. Therefore, the erase gate EG can include the second branch portion BP2 extending along the second horizontal direction D2 and connected to the main portion MP, and a second portion F2 of the floating gate FG can be located below the second branch portion BP2 in the vertical direction D3.

[0078] Further, the vertical direction D3 can be considered as a thickness direction of the semiconductor substrate 10, and the semiconductor substrate 10 can have an upper surface and a bottom surface 10BS opposite to each other in the vertical direction D3, and the floating gate FG and the erase gate EG can be disposed on one side of the upper surface. A horizontal direction (e.g., the first horizontal direction D1 or / and the second horizontal direction D2) substantially orthogonal to the vertical direction D3 can be substantially parallel to the upper surface or / and the bottom surface 10BS of the semiconductor substrate 10, but is not limited thereto. Further, in the present disclosure, a distance in the vertical direction D3 between a relatively higher position or / and component and the bottom surface 10BS of the semiconductor substrate 10 can be greater than a distance in the vertical direction D3 between a relatively lower position or / and component and the bottom surface 10BS of the semiconductor substrate 10, a lower portion or bottom of a component can be closer to the bottom surface 10BS of the semiconductor substrate 10 in the vertical direction D3 than an upper portion or top of the component, a component above another component can be considered as being relatively farther away from the bottom surface 10BS of the semiconductor substrate 10 in the vertical direction D3, and a component below another component can be considered as being relatively closer to the bottom surface 10BS of the semiconductor substrate 10 in the vertical direction D3, but is not limited thereto. It is worth mentioning that an upper surface of a component in the present disclosure can include a topmost surface of the component in the vertical direction D3, and a bottom surface of a component can include a bottommost surface of the component in the vertical direction D3, but is not limited thereto. Further, a condition that a specific component is disposed between two other components in a certain direction in the present disclosure can include, but is not limited to, a condition that the component is sandwiched between the two components in the direction.

[0079] In some embodiments, the memory device 101 can further include a patterned mask layer HM disposed over the semiconductor base 10, the floating gates FG are partially disposed between the patterned mask layer HM and the semiconductor base 10 in the vertical direction D3, and the patterned mask layer HM can include a first portion H1 and a second portion H2. The first portion H1 can extend along the first horizontal direction D1, and the second portion H2 can extend along the second horizontal direction D2 and is connected to the first portion H1. In some embodiments, the memory device 101 can include two patterned mask layers HM located on two opposite sides of the erase gate EG in the second horizontal direction D2, each patterned mask layer HM can include a plurality of second portions H2 directly connected to the first portion H1, and each second portion H2 can extend from an edge of the first portion H1 along the second horizontal direction D2 toward the main portion MP of the erase gate EG. In a top view of the memory device 101, each first portion H1 can be disposed corresponding to a plurality of floating gates FG and partially overlap in the vertical direction D3, each second portion H2 can be disposed corresponding to one floating gate FG and partially overlap in the vertical direction D3, and each second portion H2 can be sandwiched between two branch portions BP (e.g., the first branch portion BP1 and the second branch portion BP2) of the erase gate EG in the first horizontal direction D1.

[0080] In some embodiments, a portion of the floating gate FG can be exposed through the patterned mask layer HM and the gap sub-layer 120 formed on the sidewall of the patterned mask layer HM. Figures 1 to 5The position of the second portion H2 of the patterned mask layer HM is defined such that it affects the relative sizes of the first portion Fl and the second portion F2 of the floating gate FG. For example, in the top view of the memory device 101, when the center line of the second portion H2 in the first horizontal direction Dl overlaps with the center line of the corresponding floating gate FG in the first horizontal direction Dl, the length Ll l of the first portion Fl of the floating gate FG in the first horizontal direction Dl can be substantially equal to the length L12 of the second portion F2 of the floating gate FG in the first horizontal direction Dl. Conversely, when an alignment offset occurs in the fabrication process of forming the patterned mask layer HM, the length Ll l of the first portion Fl of the floating gate FG in the first horizontal direction Dl can be different from the length L12 of the second portion F2 of the floating gate FG in the first horizontal direction Dl. In addition, the length L2 of the second portion H2 of the patterned mask layer HM in the first horizontal direction Dl can be less than the length Ll of the floating gate FG in the first horizontal direction Dl, a third portion F3 of the floating gate FG can be disposed under the main portion MP of the erase gate EG in the vertical direction D3, and the length L13 of the third portion F3 of the floating gate FG in the first horizontal direction Dl can be substantially equal to the length Ll of the floating gate FG in the first horizontal direction Dl. Thus, the length L13 of the third portion F3 in the first horizontal direction Dl can be greater than the length Ll l of the first portion Fl in the first horizontal direction Dl, the length L12 of the second portion F2 in the first horizontal direction Dl, and the length L2 of the second portion H2 of the patterned mask layer HM in the first horizontal direction Dl, respectively.

[0081] In some embodiments, the semiconductor substrate 10 can include a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, or a semiconductor substrate formed of other suitable semiconductor material or / and structure. In addition, the memory device 101 can further include an isolation structure 12 disposed in the semiconductor substrate 10 to define an active region 10A in the semiconductor substrate 10, so the active region 10A can be a portion of the semiconductor substrate 10 and have the same material composition as the semiconductor substrate 10. The isolation structure 12 can include a single layer or multiple layers of insulating material, such as can include an insulating liner and an insulating gapfill material disposed on the insulating liner, but is not limited thereto. In some embodiments, the active region 10A can include a first portion extending along a first horizontal direction Dl and a plurality of second portions interleaved with the first portion and extending along a second horizontal direction D2, the floating gate FG can be disposed on the second portions of the active region 10A, and the erase gate EG can be disposed on the active region 10A and the isolation structure 12. In some embodiments, the floating gate FG and the erase gate EG can be formed of polysilicon or other suitable conductive material, the floating gate FG can have an electrically floating characteristic without being directly connected to other conductive material, and the patterned mask layer HM can include a nitride insulating material (such as silicon nitride) or other suitable insulating material. In some embodiments, an upper surface TS1 of the erase gate EG can be substantially coplanar with an upper surface TS2 of the patterned mask layer HM, and the memory device 101 can not have an additional control gate, and the erase gate EG with the branch portion BP can replace the control gate for a programming operation (such as can utilize a portion of the erase gate EG overlapping the floating gate FG in a vertical direction D3 to generate an electrical coupling), but is not limited thereto.

[0082] In some embodiments, the memory device 101 can further include a source line region SL, a bit line region BL, a word line structure WL, a dielectric layer 14, a dielectric layer 18, a dielectric layer 26, a dielectric layer 30, a dielectric layer 32, a dielectric layer 34, a dielectric layer 36, a dielectric layer 38, a dielectric layer 40, and a plurality of contact structures (e.g., a contact structure CT1, a contact structure CT2, and a contact structure CT3). The source line region SL and the bit line region BL can be disposed in the semiconductor base 10, the source line region SL can be disposed in the vertical direction D3 corresponding to the erase gate EG, and the source line region SL and the bit line region BL can be doped regions, such as N-type heavily doped regions, formed in the semiconductor base 10, but the application is not limited thereto. The dielectric layer 14, the dielectric layer 18, the dielectric layer 26, the dielectric layer 30, the dielectric layer 32, the dielectric layer 34, and the dielectric layer 36 can include oxide dielectric materials or other suitable dielectric materials. A portion of the dielectric layer 14 can be located between the floating gate FG and the semiconductor base 10 in the vertical direction D3, the dielectric layer 18 can be located between the patterned mask layer HM and the floating gate FG in the vertical direction D3, the dielectric layer 30 can be disposed between the erase gate EG and the source line region SL, and the dielectric layer 32 can be partially located between the erase gate EG and the floating gate FG and partially located between the erase gate EG and the patterned mask layer HM. The word line structure WL and the dielectric layer 26 can be located on the dielectric layer 14, and the dielectric layer 26 can be partially located between the word line structure WL and the floating gate FG and partially located between the word line structure WL and the patterned mask layer HM. The dielectric layer 36 can cover the word line structure WL, the dielectric layer 26, the patterned mask layer HM, and the erase gate EG, the dielectric layer 38 can cover the bit line region BL and the sidewall of the word line structure WL, and the dielectric layer 34 can be located between the dielectric layer 38 and the word line structure WL. The dielectric layer 40 can cover the dielectric layer 36 and the dielectric layer 38, and the contact structure CT1, the contact structure CT2, and the contact structure CT3 can be electrically connected to the erase gate EG, the word line structure WL, and the bit line region BL, respectively, by penetrating the corresponding dielectric layers. The dielectric layer 38 can include nitride dielectric materials or other suitable dielectric materials, and the dielectric layer 40 can include single-layer or multi-layer dielectric materials, such as oxide dielectric materials, nitride dielectric materials, oxynitride dielectric materials, or other suitable dielectric materials. The word line structure WL can include polysilicon or other suitable conductive materials, and each contact structure can include a barrier layer and a low-resistance material disposed on the barrier layer. The low-resistance material can include materials with relatively low resistivity, such as copper, aluminum, tungsten, etc., and the barrier layer can include titanium nitride, tantalum nitride, or other suitable conductive barrier materials, but the application is not limited thereto.

[0083] In some embodiments, the memory device 101 can include two patterned mask layers HM, two word line structures WL, and two bit line regions BL disposed on two opposite sides of the erase gate EG in the second horizontal direction D2, respectively, and a plurality of floating gates FG can be disposed on two opposite sides of the erase gate EG in the second horizontal direction D2, respectively. In addition, one floating gate FG and the erase gate EG, the word line structure WL, the source line region SL, the bit line region BL, the dielectric layer 26, the dielectric layer 30, and the dielectric layer 32 corresponding to the floating gate FG can form one memory cell, and adjacent memory cells in the first horizontal direction D1 or / and in the second horizontal direction D2 can share one erase gate EG, but the application is not limited thereto. In some embodiments, the memory device 101 can be regarded as an eflash structure, and the absence of a control gate in the memory device 101 can improve the process integration between the memory device 101 and other elements formed on the semiconductor substrate 10, but the application is not limited thereto. In addition, the design of the erase gate EG with the branch portion BP in the present application can also be applied to other types of memory devices as needed.

[0084] Please refer to Figures 6 to 12 and Figures 1 to 5 . Figures 6 to 12 The manufacturing method of the memory device of one embodiment of the present application is schematically shown in the following figures: Figure 7 is a top view, Figure 6 is a schematic view after Figure 8 is a schematic view after Figure 6 is a schematic view after Figure 9 is a schematic view after Figure 8 is a schematic view after Figure 10 is a schematic view after Figure 9 is a schematic view after Figure 11 is a schematic view after Figure 10 is a schematic view after Figure 12 is a schematic view after Figure 11 In some embodiments, Figure 3 may be regarded as a schematic view after Figure 12 but the application is not limited thereto. In addition, in order to more clearly show the structural features in the top view Figure 7 , some components in Figure 6 are not shown in the top view. As Figures 1 to 5As shown, the fabrication method of the present embodiment can include the following steps. A semiconductor substrate 10 is provided, and a floating gate FG and an erase gate EG are formed over the semiconductor substrate 10. The erase gate EG includes a main portion MP and a first branch portion BP1, the main portion MP extends along a first horizontal direction D1, and the first branch portion BP1 extends along a second horizontal direction D2 and is connected to the main portion MP. A first portion F1 of the floating gate FG is located below the first branch portion BP1 in a vertical direction D3.

[0085] Further, the fabrication method of the present embodiment can include, but is not limited to, the following steps. As shown in FIG. 1C, a dielectric layer 14, a patterned material layer 16, and a dielectric layer 18 can be formed over the semiconductor substrate 10, and a patterned mask layer HM and a dielectric layer 20 can be formed over the semiconductor substrate 10 after the formation of the patterned material layer 16. In some embodiments, an isolation structure 12 can be formed in the semiconductor substrate 10 to define an active region 10A in the semiconductor substrate 10, and the isolation structure 12 can be formed by forming a trench in the semiconductor substrate 10 and filling the trench with an insulating material. In addition, the dielectric layer 14, the dielectric layer 18, and a material layer sandwiched between the dielectric layer 14 and the dielectric layer 18 can be patterned by the fabrication process of forming the trench, so that the material layer sandwiched between the dielectric layer 14 and the dielectric layer 18 can be patterned to become the patterned material layer 16, and the patterned material layer 16 can be disposed substantially corresponding to the active region 10A in the vertical direction D3, but the present embodiment is not limited thereto. In addition, the patterned mask layer HM can include the first portion H1 and the second portion H2 as described above, the second portion H2 can be formed over the active region 10A and the patterned material layer 16 in the vertical direction D3, and the first portion H1 can be formed over the isolation structure 12 and the patterned material layer 16 in the vertical direction D3. Therefore, the patterned mask layer HM can be partially formed over the patterned material layer 16 and partially formed over the isolation structure 12 in the vertical direction D3. Figure 6 Figure 7 As shown, a gap sub 22 can be formed on the sidewall of the patterned mask layer HM, and the gap sub 22 can include an oxide dielectric material or other suitable dielectric material. In some embodiments, a portion of the dielectric layer 18 and the dielectric layer 20 can be removed by an etching fabrication process (for example, but not limited to, a dry etching fabrication process) for forming the gap sub 22 to expose a portion of the patterned material layer 16, but the present embodiment is not limited thereto. Then, as shown in FIG. 1E, a dielectric layer 24 can be formed over the semiconductor substrate 10, and the dielectric layer 24 can be formed by a deposition fabrication process (for example, but not limited to, a chemical vapor deposition fabrication process) or other suitable fabrication process. In some embodiments, the dielectric layer 24 can be formed by a deposition fabrication process (for example, but not limited to, a chemical vapor deposition fabrication process) or other suitable fabrication process, and the dielectric layer 24 can be formed to cover the gap sub 22 and the patterned material layer 16.

[0086] As shown, a gap sub 22 can be formed on the sidewall of the patterned mask layer HM, and the gap sub 22 can include an oxide dielectric material or other suitable dielectric material. In some embodiments, a portion of the dielectric layer 18 and the dielectric layer 20 can be removed by an etching fabrication process (for example, but not limited to, a dry etching fabrication process) for forming the gap sub 22 to expose a portion of the patterned material layer 16, but the present embodiment is not limited thereto. Then, as shown in FIG. 1E, a dielectric layer 24 can be formed over the semiconductor substrate 10, and the dielectric layer 24 can be formed by a deposition fabrication process (for example, but not limited to, a chemical vapor deposition fabrication process) or other suitable fabrication process. In some embodiments, the dielectric layer 24 can be formed by a deposition fabrication process (for example, but not limited to, a chemical vapor deposition fabrication process) or other suitable fabrication process, and the dielectric layer 24 can be formed to cover the gap sub 22 and the patterned material layer 16. Figure 6 Figure 8 As shown, a gap sub 22 can be formed on the sidewall of the patterned mask layer HM, and the gap sub 22 can include an oxide dielectric material or other suitable dielectric material. In some embodiments, a portion of the dielectric layer 18 and the dielectric layer 20 can be removed by an etching fabrication process (for example, but not limited to, a dry etching fabrication process) for forming the gap sub 22 to expose a portion of the patterned material layer 16, but the present embodiment is not limited thereto. Then, as shown in FIG. 1E, a dielectric layer 24 can be formed over the semiconductor substrate 10, and the dielectric layer 24 can be formed by a deposition fabrication process (for example, but not limited to, a chemical vapor deposition fabrication process) or other suitable fabrication process. In some embodiments, the dielectric layer 24 can be formed by a deposition fabrication process (for example, but not limited to, a chemical vapor deposition fabrication process) or other suitable fabrication process, and the dielectric layer 24 can be formed to cover the gap sub 22 and the patterned material layer 16. Figure 8 Figure 9 ​​​As shown, a removal fabrication process 91 can be performed to remove a portion of the spacer 22, and another portion of the spacer 22 can remain on the sidewall of the second portion H2 of the patterned mask layer HM after the removal fabrication process 91. In some embodiments, a patterned mask layer 24 can be formed on the semiconductor substrate 10 before the removal fabrication process 91 is performed, and the patterned mask layer 24 can cover the spacer 22 on the sidewall of the second portion H2 of the patterned mask layer HM and at least a portion of the patterned mask layer HM. In some embodiments, the removal fabrication process 91 can include an etching fabrication process (such as, but not limited to, a wet cleaning process), the patterned mask layer 24 can serve as an etching mask for the etching fabrication process, and the patterned mask layer 24 can include a patterned photoresist or other suitable mask material. As shown, Figure 9 As shown, Figure 10 After the removal fabrication process 91, the patterned mask layer 24 can be removed, and an etching fabrication process 92 can be performed on the patterned material layer 16 using the patterned mask layer HM and the spacer 22 (such as the spacer 22 on the sidewall of the second portion H2 of the patterned mask layer HM) as masks, and at least a portion of the patterned material layer 16 can be etched by the etching fabrication process 92 to become the floating gate FG. In other words, the removal fabrication process 91 is performed before the etching fabrication process 92, and the projected pattern of the floating gate FG in the vertical direction D3 can be affected by the shape and formation position of the patterned mask layer HM and the spacer 22. It is worth mentioning that the method used to form the floating gate FG in the present disclosure can include, but is not limited to, the steps shown above, and other suitable methods can be used to form the floating gate FG according to design requirements. Figures 6 to 10 As shown,

[0087] As shown, Figure 11 After the floating gate FG is formed, a dielectric layer 26 can be formed on the sidewall of the patterned mask layer HM and the floating gate FG, and the dielectric layer 26 can be considered as a spacer formed on the sidewall. In some embodiments, the dielectric layer 26 can be formed by forming a dielectric material and performing a back-etching process on the dielectric material, and the dielectric layer 28 can be formed on the patterned mask layer HM. Then, as shown, Figure 11 As shown, Figure 12 The spacer 22, the portion of the dielectric layer 26, the portion of the dielectric layer 28, and the portion of the dielectric layer 14 remaining on the sidewall of the second portion H2 of the patterned mask layer HM can be removed to expose a portion of the active region 10A. Then, as shown, Figure 3 and Figure 1As shown, the erase gate EG, source line region SL, bit line region BL, word line structure WL, dielectric layer 30, dielectric layer 32, dielectric layer 34, dielectric layer 36, dielectric layer 38, dielectric layer 40 and a plurality of contact structures can be formed to form the memory device 101. In other words, the spacers 22 remaining on the sidewalls of the second portion H2 of the patterned mask layer HM can be Figure 10 In some embodiments, the method of forming the erase gate EG and the word line structure WL may include performing a planarization process (such as but not limited to a chemical mechanical polishing process) on the conductive material (such as but not limited to polysilicon) formed on the semiconductor substrate 10, and Figure 12 The dielectric layer 28, a portion of the patterned mask layer HM, and a portion of the dielectric layer 26 shown in the figure can be removed by this planarization process, so the upper surface TS1 of the erase gate EG, the upper surface TS2 of the patterned mask layer HM, and the upper surface of the word line structure WL can be substantially coplanar, but not limited to this.

[0088] The following describes various embodiments of the present invention. To simplify the description, the following description focuses on the differences between the embodiments and does not repeat the similarities. In addition, the same elements in the various embodiments of the present invention are labeled with the same reference numerals to facilitate comparison between the various embodiments.

[0089] See also Figure 13 . Figure 13 FIG. 1 is a schematic diagram of a memory device 102 according to a second embodiment of the present invention. Figure 13 As shown, in the memory device 102, the length L11 of the first portion F1 of the floating gate FG in the first horizontal direction D1 may be different from the length L12 of the second portion F2 of the floating gate FG in the first horizontal direction D1. For example, when the formation position of the patterned mask layer HM is toward Figure 13 When the offset is below Figure 13 The length L11 of the first portion F1 in the first horizontal direction D1 may be greater than Figure 13 The length L12 of the second portion F2 in the first horizontal direction D1 is, but is not limited to, a length L12. Furthermore, the floating gate FG is affected by the formation position of the patterned mask layer HM. The length L1 of the floating gate FG in the first horizontal direction D1 can be considered the maximum length of the floating gate FG in the first horizontal direction D1. The length L13 of the third portion F3 of the floating gate FG in the first horizontal direction D1 can be less than the length L1, but is not limited to this.

[0090] In summary, in the memory device and the manufacturing method thereof, the size of the region where the edge of the floating gate and the edge of the erase gate are electrically coupled or / and F-N tunneling is increased by the branch of the erase gate, so that the programming speed and the erase speed of the memory device are improved or / and the operating voltage of the memory device is relatively reduced to improve the operating tolerance range or / and the operating performance of the memory device.

[0091] The above merely provides the preferred embodiments of the present application, and all equivalent changes and modifications made according to the claims of the present application should be within the scope of the present application.

Claims

1. A memory device comprising: semiconductor substrates; A floating gate is disposed on the semiconductor substrate; as well as An erase gate is disposed on the semiconductor substrate, wherein the erase gate comprises: a main body extending along a first horizontal direction; as well as The first branch portion extends along the second horizontal direction and is connected to the main portion, wherein the first portion of the floating gate is located below the first branch portion in the vertical direction.

2. The memory device of claim 1 , wherein the erase gate further comprises: The second branch portion extends along the second horizontal direction and is connected to the main body portion, wherein the second portion of the floating gate is located below the second branch portion in the vertical direction. 3 . The memory device of claim 2 , wherein a length of the first portion of the floating gate in the first horizontal direction is different from a length of the second portion of the floating gate in the first horizontal direction.

4. The memory device of claim 2 , further comprising: A patterned mask layer is disposed on the semiconductor substrate, wherein the floating gate is partially disposed between the patterned mask layer and the semiconductor substrate in the vertical direction, and the patterned mask layer comprises: a first portion extending along the first horizontal direction; and The second portion extends along the second horizontal direction and is connected to the first portion of the patterned mask layer, wherein the second portion of the patterned mask layer is sandwiched between the first branch portion and the second branch portion of the erase gate in the first horizontal direction. 5 . The memory device of claim 4 , wherein a length of the second portion of the patterned mask layer in the first horizontal direction is smaller than a length of the floating gate in the first horizontal direction. 6 . The memory device of claim 4 , wherein the third portion of the floating gate is disposed below the main portion of the erase gate in the vertical direction.

7. The memory device of claim 6, wherein a length of the third portion of the floating gate in the first horizontal direction is greater than a length of the first portion of the floating gate in the first horizontal direction and a length of the second portion of the floating gate in the first horizontal direction. 8 . The memory device of claim 6 , wherein a length of the third portion of the floating gate in the first horizontal direction is greater than a length of the second portion of the patterned mask layer in the first horizontal direction. 9 . The memory device of claim 4 , wherein an upper surface of the erase gate is coplanar with an upper surface of the patterned mask layer.

10. The memory device of claim 1, wherein the first horizontal direction is orthogonal to the second horizontal direction.

11. A method for manufacturing a memory device, comprising: providing a semiconductor substrate; forming a floating gate on the semiconductor substrate; as well as An erase gate is formed on the semiconductor substrate, wherein the erase gate comprises: a main body extending along a first horizontal direction; as well as The first branch portion extends along the second horizontal direction and is connected to the main portion, wherein the first portion of the floating gate is located below the first branch portion in the vertical direction.

12. The method for manufacturing a memory device according to claim 11 , wherein the method of forming the floating gate comprises: forming a patterned material layer on the semiconductor substrate; After the patterned material layer is formed, forming a patterned mask layer on the semiconductor substrate, wherein the patterned mask layer is partially formed on the patterned material layer in the vertical direction; forming spacers on sidewalls of the patterned mask layer; as well as An etching process is performed on the patterned material layer using the patterned mask layer and the spacer as masks, wherein at least a portion of the patterned material layer is etched by the etching process to form the floating gate.

13. The method for manufacturing a memory device according to claim 12 , wherein the patterned mask layer comprises: a first portion extending along the first horizontal direction; as well as The second portion extends along the second horizontal direction and is connected to the first portion of the patterned mask layer.

14. The method for fabricating a memory device according to claim 13 , wherein the method for forming the floating gate further comprises: Before the etching process, a removal process is performed to remove a portion of the spacer, wherein another portion of the spacer remains on the sidewall of the second portion of the patterned mask layer after the removal process.

15. The method for manufacturing a memory device according to claim 14, further comprising: After the etching process and before the erase gate is formed, the other portion of the spacer remaining on the sidewall of the second portion of the patterned mask layer is removed. 16 . The method for fabricating a memory device as claimed in claim 13 , wherein a length of the second portion of the patterned mask layer in the first horizontal direction is smaller than a length of the floating gate in the first horizontal direction.

17. The method for manufacturing a memory device according to claim 13 , wherein the erase gate further comprises: The second branch portion extends along the second horizontal direction and is connected to the main body portion, wherein the second portion of the floating gate is located below the second branch portion in the vertical direction. 18 . The method for manufacturing a memory device according to claim 17 , wherein the second portion of the patterned mask layer is sandwiched between the first branch portion and the second branch portion of the erase gate in the first horizontal direction. 19 . The method for fabricating a memory device according to claim 17 , wherein a length of the first portion of the floating gate in the first horizontal direction is different from a length of the second portion of the floating gate in the first horizontal direction. 20 . The method for manufacturing a memory device according to claim 11 , wherein the first horizontal direction is perpendicular to the second horizontal direction.

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