A planar gate IGBT device and a manufacturing method thereof

Abstract

The present application relates to the technical field of semiconductor, and especially relates to a planar gate IGBT device and a manufacturing method thereof, which comprises a substrate, a doped region and a gate region, and a P-type floating region corresponding to the doped region; the gate region is located on the substrate; the doped region is located on the substrate and below the gate region and at both ends of the gate region; the doped region comprises an N+ source region and a P-type body region, the N+ source region is located in the P-type body region, and the surface of the N+ source region, the surface of the P-type body region and the surface of the substrate are located on the same horizontal plane; the P-type floating region is located in the substrate, below the gate region, between the doped regions and in a specified area beside the corresponding P-type body region, and the P-type floating region is close to the P-type body region and not in contact with the P-type body region. Through the structural arrangement of the device, the on-state voltage drop of the planar gate IGBT device is reduced, and the reliability and practicability of the planar gate IGBT device are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a planar gate IGBT device and a manufacturing method thereof. BACKGROUND

[0002] In power system applications, planar gate IGBT (Insulated Gate Bipolar Transistor) devices are widely used in low-frequency power electronic devices such as frequency converters, motor drives, and industrial controls due to their high withstand voltage and large current carrying capacity. In planar gate IGBTs, the JFET resistance similar to MOSFET devices hinders the further optimization of the on-state voltage drop of the IGBT device, resulting in a problem of high on-state voltage drop of the planar gate IGBT. Then, the trench gate IGBT that eliminates the JFET resistance significantly reduces its on-state voltage drop, making the trench gate IGBT a mainstream design.

[0003] However, in high-voltage IGBT applications above 3300V, the reliability risk of the trench gate IGBT is greater than that of the planar gate IGBT. This is because the bottom of the trench of the trench gate IGBT concentrates the electric field, which is more susceptible to high-voltage impact, thereby damaging the gate oxide layer and causing device damage and circuit failure. Therefore, in high-voltage planar gate IGBT applications, the high on-state voltage drop of the planar gate IGBT is an urgent problem to be solved. SUMMARY

[0004] The present application provides a planar gate IGBT device and a manufacturing method thereof, which solves the technical problem of high on-state voltage drop of the planar gate IGBT in high-voltage planar gate IGBT applications in the prior art, reduces the on-state voltage drop of the planar gate IGBT device, optimizes the trade-off between the on-state voltage drop and the blocking voltage of the high-voltage planar gate IGBT, and improves the reliability and practicality of the planar gate IGBT device.

[0005] In a first aspect, the present application provides a planar gate IGBT device, comprising: a substrate, a doped region and a gate region, and a P-type floating region corresponding to the doped region one by one.

[0006] The gate region is located above the substrate.

[0007] The doped region is located on the substrate and below the gate region and at both ends of the gate region; the doped region comprises: an N+ source region and a P-type body region, the N+ source region is located within the P-type body region, the surface of the N+ source region, the surface of the P-type body region and the surface of the substrate are located on the same horizontal plane.

[0008] The P-type floating region is located in the substrate, under the gate region, between the doped regions, and in a designated area beside the corresponding P-type body region, the P-type floating region is close to the P-type body region and is not in contact with the P-type body region, so as to realize low on-state voltage drop of the planar gate IGBT device.

[0009] Optionally, the gate region comprises a gate oxide layer, a thick oxide layer, and a gate polysilicon layer.

[0010] The gate oxide layer and the thick oxide layer are located on the surface of the substrate, and the gate oxide layer is located on both sides of the thick oxide layer.

[0011] The gate polysilicon layer is located above the gate oxide layer and the thick oxide layer.

[0012] The gate polysilicon layer is in a curved shape with a groove, and the groove of the gate polysilicon layer covers the thick oxide layer.

[0013] Optionally, the horizontal area of the designated area is the area between the adjacent side of the P-type body region and the designated side of the thick oxide layer, wherein the adjacent side of the P-type body region is one side of the P-type body region adjacent to another doped region, and the designated side of the thick oxide layer is the side closest to the P-type body region.

[0014] Optionally, the vertical area of the designated area is the area between the surface of the P-type body region and the bottom of the P-type body region to 15 um below.

[0015] Optionally, the doping concentration of the P-type floating region is less than the doping concentration of the P-type body region.

[0016] Optionally, further comprising an N-type carrier storage layer.

[0017] The N-type carrier storage layer corresponds to the doped region one by one, the doped region is located in the N-type carrier storage layer, and the surface of the N-type carrier storage layer is located in the same horizontal plane as the surface of the substrate.

[0018] In the presence of the N-type carrier storage layer, the P-type floating region is not in contact with the N-type carrier storage layer.

[0019] Optionally, further comprising an emitter metal layer, the emitter metal layer is located above the substrate and the gate region, and covers the gate region and the doped region.

[0020] Optionally, further comprising a dielectric layer, the dielectric layer is located on the gate region and below the emitter metal layer, and covers the gate region to isolate the gate region and the emitter metal layer.

[0021] Optionally, further comprising: an N-type field termination layer, a P-type collector layer and a collector metal layer;

[0022] The N-type field termination layer is located below the substrate;

[0023] The P-type collector layer is located below the N-type field termination layer;

[0024] The collector metal layer is located below the P-type collector layer.

[0025] Based on the same inventive concept, in a second aspect, the present application further provides a manufacturing method of a planar gate IGBT device, for manufacturing the planar gate IGBT device as described in the first aspect, the method comprising:

[0026] forming a gate region above a substrate;

[0027] forming the doped regions on the substrate and below the gate region, the doped regions being located at both ends of the gate region; the doped regions comprising: N+ source regions and P-type body regions, the N+ source regions being located within the P-type body regions, the surface of the N+ source regions, the surface of the P-type body regions and the surface of the substrate being located at the same level;

[0028] forming the P-type floating regions within the substrate and below the gate region, the P-type floating regions also being located between the doped regions and at a designated area laterally to the corresponding P-type body regions, the P-type floating regions being close to the P-type body regions and not in contact with the P-type body regions, so as to achieve a low on-state voltage drop of the planar gate IGBT device.

[0029] The one or more technical solutions in the embodiments of the present application have at least the following technical effects or advantages:

[0030] In the planar gate IGBT device structure of the embodiments of the present application, the P-type floating regions are arranged in the designated areas laterally to the P-type body regions of each doped region located on the substrate and below the gate region. In this way, the junction curvature of the P-type body regions and the electric field intensity below the gate oxide layer of the silicon surface of the substrate (especially at the step where the thick oxide layer and the gate oxide layer meet) are significantly reduced, the front carrier concentration of the planar gate IGBT device is greatly improved, the on-state voltage drop of the planar gate IGBT device is reduced, and the blocking voltage is not sacrificed. Through the arrangement of the P-type floating regions, the trade-off between the on-state voltage drop and the blocking voltage of the high-voltage planar gate IGBT is also optimized, and the reliability and practicability of the planar gate IGBT device are improved. BRIEF DESCRIPTION OF DRAWINGS

[0031] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments with reference made to the accompanying drawings. The drawings are for purposes of illustration only and are not intended to be limiting in

[0032] Figure 1 A structural schematic diagram of a planar gate IGBT device in an embodiment of the present application is shown;

[0033] Figure 2 A curve schematic diagram of a cell width and saturation voltage of a comparative device in an embodiment of the present application is shown;

[0034] Figure 3 A curve schematic diagram of a structural depth and front surface carrier concentration of a planar gate IGBT device in an embodiment of the present application is shown;

[0035] Figure 4 A curve schematic diagram of a voltage and current between a collector and an emitter of a planar gate IGBT device in an embodiment of the present application is shown;

[0036] Figure 5 A structural schematic diagram of implanting a P-type floating region on a substrate in an embodiment of the present application is shown;

[0037] Figure 6 A structural schematic diagram of forming a P-type floating region on a substrate in an embodiment of the present application is shown;

[0038] Figure 7 A structural schematic diagram of forming a thick oxide layer and implanting an N-type carrier storage layer in an embodiment of the present application is shown;

[0039] Figure 8 A structural schematic diagram of thermally growing a gate oxide layer after the thick oxide layer and forming a gate polysilicon in an embodiment of the present application is shown;

[0040] Figure 9 A structural schematic diagram of forming a P-type body region, an N+ source region and an emitter metal layer in an embodiment of the present application is shown;

[0041] Figure 10 A step flow schematic diagram of a manufacturing method of a planar gate IGBT device in an embodiment of the present application is shown;

[0042] In the drawings, 110, substrate; 120, doped region; 130, gate region; 140, N-type carrier storage layer; 150, P-type floating region; 160, emitter metal layer; 170, N-type field termination layer; 180, P-type collector layer; 190, collector metal layer; 111, dielectric layer;

[0043] 121, N+ source region; 122, P-type body region;

[0044] 131, gate oxide layer; 132, gate polysilicon; 133, thick oxide layer. DETAILED DESCRIPTION

[0045] Exemplary embodiments of the present disclosure will be described in greater detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it is understood that the present disclosure can be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0046] Embodiment One

[0047] The first embodiment of the present application provides a planar gate IGBT device, as shown in FIG. 1, comprising a substrate 110, a doped region 120 and a gate region 130, and a P-type floating region 150 corresponding to the doped region 120. The gate region 130 is located above the substrate 110. The doped region 120 is located on the substrate 110 and below the gate region 130, and at both ends of the gate region 130. The doped region 120 comprises an N+ source region 121 and a P-type body region 122. The N+ source region 121 is located within the P-type body region 122, and the surface of the N+ source region 121, the surface of the P-type body region 122 and the surface of the substrate 110 are located at the same level. Figure 1 The P-type floating region 150 is located within the substrate 110, below the gate region 130, between the doped regions 120, and in a designated area corresponding to the side of the P-type body region 122. The P-type floating region 150 is close to the P-type body region 122 and is not in contact with the P-type body region 122, so as to achieve a low on-state voltage drop of the planar gate IGBT device.

[0048] It should be noted that the planar gate IGBT device of the present embodiment is particularly suitable for high voltage applications, i.e. high voltage IGBT applications above 3300V, and can also be used in low voltage applications. The planar gate IGBT device of the present embodiment uses N-type single crystal silicon material as the material of the substrate 110, which serves as the drift region of the IGBT device. The substrate 110 is an N-type lightly doped substrate. The N+ source region 121 is an N-type heavily doped source region. The shape of the P-type floating region 150 is not limited and can be set according to actual needs. For example, the P-type floating region 150 can be point-shaped or square-shaped.

[0049]

[0050] ​In the planar gate IGBT device structure of the embodiment, a P-type floating region 150 is arranged in a designated area beside the P-type body region 122 of each doped region 120 located on the substrate 110 and below the gate region 130. This significantly reduces the junction curvature of the P-type body region 122 and the electric field intensity below the gate oxide layer of the silicon substrate 110 surface, greatly increases the front carrier concentration of the planar gate IGBT device, reduces the on-state voltage drop of the planar gate IGBT device, and does not sacrifice the blocking voltage. By arranging the P-type floating region 150, the trade-off between the on-state voltage drop and the blocking voltage of the high-voltage planar gate IGBT is optimized, and the reliability and practicability of the planar gate IGBT device are improved.

[0051] Next, the structure of the planar gate IGBT device of the embodiment will be described in detail in combination with Figure 1 the drawings.

[0052] The gate region 130 includes a gate oxide layer 131, a gate polysilicon 132, and a thick oxide layer 133. The gate oxide layer 131 and the thick oxide layer 133 are located on the surface of the substrate, and the gate oxide layer 131 is located on both sides of the thick oxide layer 133. The gate polysilicon 132 is located above the gate oxide layer 131 and the thick oxide layer 133. Among them, the gate polysilicon 132 is in a curved shape with a groove, and the groove of the gate polysilicon 132 covers the thick oxide layer 133.

[0053] Specifically, the gate oxide layer 131 and the thick oxide layer 133 are both oxide layers, and the thick oxide layer 133 includes a field oxide layer and a gate oxide layer. The gate oxide layer 131 is a single-pass gate oxide layer. By arranging the gate oxide layer 131 and the thick oxide layer 133, a thin-thick oxide layer is formed.

[0054] The doped region 120 is located at both ends of the gate region 130, as Figure 1 shown, the left doped region 120 is located at the left end of the gate region 130, and the right doped region 120 is located at the right end of the gate region 130. Each end of the gate region 130 (i.e. each end of the gate oxide layer 131 and the gate polysilicon 132 of the gate region 130) covers part of the N+ source region 121 and the P-type body region 122 of the corresponding doped region 120. For example, the left end of the gate region 130 covers part of the N+ source region 121 and the P-type body region 122 of the left doped region 120, and by analogy, the right end of the gate region 130 covers part of the N+ source region 121 and the P-type body region 122 of the right doped region 120.

[0055] The material of the gate polysilicon 132 is polysilicon, and the materials of the gate oxide layer 131 and the thick oxide layer 133 are silicon dioxide. The gate polysilicon 132 has a "hat" shape in the gate oxide layer 131, that is, a curved shape with a groove. Especially in high-voltage applications, the gate polysilicon 132 has this shape, which has the effect of reducing the Miller capacitance, thereby reducing the switching loss, and the thick oxide layer can withstand a higher electric field, ensuring the service life of the gate oxide layer 131 in high-voltage use conditions, making the device more reliable, and having the effects of voltage resistance, etc. The groove formed by the gate polysilicon 132 covers the thick oxide layer 133.

[0056] Each doped region 120 is provided with a corresponding P-type floating region 150. The P-type floating region 150 is located between the doped regions 120 and in a designated area on the side of the corresponding P-type body region 122, and the P-type floating region 150 is close to the P-type body region 122 and does not contact the P-type body region 122. The designated area of the P-type floating region 150 corresponds to the designated area of the P-type body region 122 of each doped region 120, and the horizontal area of the designated area of the P-type body region 122 (i.e., the designated area of the P-type body region 122 corresponding to the P-type floating region 150) is the area between the adjacent side of the P-type body region 122 and the designated side of the thick oxide layer 133. Among them, the adjacent side of the P-type body region 122 is the side of the P-type body region 122 adjacent to the P-type body region 122 of another doped region 120. The designated side of the thick oxide layer 133 is the side of the thick oxide layer 133 closest to the P-type body region 122. The vertical area of the designated area is the area between the surface of the P-type body region 122 and the bottom of the P-type body region 122 to 15um below.

[0057] Specifically, in the embodiment, the P-type floating region 150 is provided in the designated area of the P-type body region 122 corresponding to the doped region 120, and the P-type floating region 150 is provided in the designated area of the P-type body region 122 corresponding to the doped region 120. Figure 1In the embodiment, for the P-type body region 122 of the left doped region 120, the horizontal region of the specified region of the P-type body region 122 (i.e. the specified region of the left P-type body region 122 corresponding to the P-type floating region 150) is the region between the adjacent side of the left P-type body region 122 and the specified side of the thick oxide layer 133. The adjacent side of the left P-type body region 122 is the side of the left P-type body region 122 adjacent to the P-type body region 122 of the right doped region 120, i.e. the right side of the left P-type body region 122. The specified side of the thick oxide layer 133 is the side of the thick oxide layer 133 closest to the left P-type body region 122, i.e. the left side of the thick oxide layer 133. Similarly, for the P-type body region 122 of the right doped region 120, the horizontal region of the specified region of the P-type body region 122 (i.e. the specified region of the right P-type body region 122 corresponding to the P-type floating region 150) is the region between the adjacent side of the right P-type body region 122 and the specified side of the thick oxide layer 133. The adjacent side of the right P-type body region 122 is the side of the right P-type body region 122 adjacent to the P-type body region 122 of the left doped region 120, i.e. the left side of the right P-type body region 122. The specified side of the thick oxide layer 133 is the side of the thick oxide layer 133 closest to the right P-type body region 122, i.e. the right side of the thick oxide layer 133.

[0058] The vertical region of the specified region of the P-type body region 122 of the left doped region 120 is the region between the surface of the left P-type body region 122 and the bottom of the left P-type body region 122 to 15um or 10um below. The boundary of the bottom of the left P-type body region 122 to 15um or 10um below is the boundary of the bottom of the left P-type body region 122 vertically spaced 15um or 10um from the substrate 110. Similarly, the vertical region of the specified region of the P-type body region 122 of the right doped region 120 is the region between the surface of the right P-type body region 122 and the bottom of the right P-type body region 122 vertically 15um or 10um from the substrate 110.

[0059] By limiting the position of the P-type floating region 150 corresponding to the P-type body region 122 of each doped region 120, the P-type floating region 150 is as close as possible to the corresponding P-type body region 122 without contacting the P-type body region 122. In this way, through the P-type floating region 150, the effect of reducing the junction curvature of the P-type body region 122 and the electric field intensity under the gate oxide layer of the silicon substrate 110 (especially at the step where the thick oxide layer 133 and the gate oxide layer 131 meet) is achieved, which improves the surface carrier concentration of the planar gate IGBT device and achieves the purpose of reducing the on-state voltage drop of the planar gate IGBT device.

[0060] Furthermore, the doping concentration of the P-type floating region 150 is lower than that of the P-type body region 122 to achieve a low on-state voltage drop. The doping concentration of the P-type floating region 150 cannot exceed that of the P-type body region 122. Increasing the doping concentration of the P-type floating region 150, while improving the reduction of the electric field (i.e., higher blocking voltage), introduces a problem of a rapid increase in the on-state voltage drop. This increase in on-state voltage drop is due to the increased doping concentration of the P-type floating region 150, which narrows the electron current path. Therefore, the doping concentration of the P-type floating region 150 should not be set too high.

[0061] The planar gate IGBT device in this embodiment further includes an N-type carrier storage layer 140. The N-type carrier storage layer 140 corresponds one-to-one with the doped region 120, with the doped region 120 located within the N-type carrier storage layer 140. The surface of the N-type carrier storage layer 140 and the surface of the substrate 110 are on the same horizontal plane. In the presence of the N-type carrier storage layer 140, the P-type floating region 150 is not in contact with the N-type carrier storage layer 140.

[0062] Specifically, such as Figure 1 As shown, the doped region 120 on the left is located in the N-type carrier storage layer 140 on the left, and the doped region 120 on the right is located in the N-type carrier storage layer 140 on the right. The surface of the N-type carrier storage layer 140 and the surface of the substrate 110 are on the same horizontal plane. In the presence of the N-type carrier storage layer 140, in a designated region of the P-type body region 122 of each doped region 120, the P-type floating region 150 does not contact the N-type carrier storage layer 140, that is, the P-type floating region 150 is not located in the N-type carrier storage layer 140, so as to avoid the formation of a PN junction between the P-type floating region 150 and the N-type carrier storage layer 140, thereby avoiding the introduction of PNP parasitic transistors in the electron and hole paths, that is, avoiding the formation of a PNP parasitic transistor by the P-type floating region 150 + N-type carrier storage layer 140 + P-type body region 122. By setting the P-type floating region 150, the peak electric field at the junction curvature of the P-type body region 122 and below the gate oxide layer on the surface of the silicon substrate 110 (especially at the step where the thick oxide layer 133 and the gate oxide layer 131 meet) is reduced, thereby reducing the impact of the N-type carrier storage layer 140 on the breakdown voltage. This improves the doping concentration margin of the N-type carrier storage layer 140 and significantly reduces the on-state voltage drop of the planar gate IGBT device. Furthermore, combining the P-type floating region 150 and the N-type carrier storage layer 140 makes the planar gate IGBT device more suitable for high-voltage IGBT applications, improving the reliability and practicality of the planar gate IGBT device in high-voltage applications, and also improving the doping concentration margin of the N-type carrier storage layer 140. The increased doping concentration margin of the N-type carrier storage layer 140 can reduce the on-state voltage drop without increasing the turn-off loss.

[0063] The planar gate IGBT device of the embodiment further comprises an emitter metal layer 160. The emitter metal layer 160 is located above the substrate 110 and the gate region 130, and the emitter metal layer 160 covers the gate region 130 and the doped region 120. The material of the emitter metal layer 160 includes but is not limited to aluminum, copper, gold.

[0064] The planar gate IGBT device of the embodiment further comprises a dielectric layer 111. The dielectric layer 111 is located above the gate region 130 and below the emitter metal layer 160, and the dielectric layer 111 covers the gate region 130, i.e. the dielectric layer 111 covers the gate oxide layer 131 and the gate polysilicon 132 of the gate region 130, so as to isolate the gate region 130 and the emitter metal layer 160. The material of the dielectric layer 111 is boron-doped and phosphorus-doped oxide layer. The dielectric layer 111 is an ILD (InterLayer Dielectric) dielectric layer, which plays a role of electrical isolation, and can also improve the signal transmission speed and reduce the power consumption, and provides physical support for the emitter metal layer 160 and ensures the stability of the structure.

[0065] The planar gate IGBT device of the embodiment further comprises an N-type field termination layer 170, a P-type collector layer 180 and a collector metal layer 190. The N-type field termination layer 170 is located below the substrate 110, the P-type collector layer 180 is located below the N-type field termination layer 170, and the collector metal layer 190 is located below the P-type collector layer 180. The P-type collector layer 180 is a P-type heavily doped collector layer. The material of the collector metal layer 190 includes but is not limited to aluminum, titanium, nickel, silver.

[0066] The structural principle of the planar gate IGBT device of the embodiment is as follows:

[0067] The P-type floating region 150 is set in a designated region of each P-type body region 122, i.e. the P-type floating region 150 is set in a lateral direction of the curvature of the PN junction formed in each P-type body region 122, and the doping concentration of the P-type floating region 150 is smaller than the doping concentration of the P-type body region 122. The P-type floating region 150 is not in contact with the N-type carrier storage layer 140, and the P-type floating region 150 is capacitively coupled with the surrounding substrate 110 to form an adaptive electric potential. The center of the electric potential attracts a part of the potential lines at the curvature of the PN junction of the P-type body region 122 and under the gate oxide layer on the surface of the silicon substrate 110 (especially at the step where the thick oxide layer 133 and the gate oxide layer 131 meet), thereby reducing the peak electric field at the curvature of the PN junction of the P-type body region 122 and under the gate oxide layer on the surface of the silicon substrate 110 (especially at the step where the thick oxide layer 133 and the gate oxide layer 131 meet), and reducing the impact of the N-type carrier storage layer 140 on the withstand voltage. This effectively moderates the electric field intensity at the curvature of the PN junction of the P-type body region 122 and under the gate oxide layer on the surface of the silicon substrate 110 (especially at the step where the thick oxide layer 133 and the gate oxide layer 131 meet), improves the margin of the doping concentration of the N-type carrier storage layer 140 for the planar gate IGBT device, and thus improves the front carrier concentration of the planar gate IGBT device to reduce the on-state voltage drop, and enhances the reliability and practicability of the planar gate IGBT device, and is compatible with the existing process.

[0068] In addition, the P-type floating region 150 is floating and located in a lateral direction of the P-type body region 122, and does not introduce a PNP parasitic tube under the emitter metal layer 160. The existence of the PNP parasitic tube hinders the removal of holes when the IGBT device is turned off. Therefore, the planar gate IGBT device structure of the present embodiment does not affect the turn-off capability.

[0069] The P-type floating region 150 is floating and located near the curvature of the PN junction of the P-type body region 122, and does not introduce a PNP parasitic tube formed by the P-type floating region 150 + the N-type carrier storage layer 140 + the P-type body region 122 on the surface of the silicon substrate 110. The PNP parasitic tube can intensify the JFET effect of the device, and significantly increase the on-state voltage drop. Therefore, the P-type floating region 150 in the planar gate IGBT device structure of the present embodiment has little effect on the increase of the on-state voltage drop.

[0070] In the following, the planar gate IGBT device of the present embodiment (i.e. the planar gate IGBT device with the P-type floating region 150 + the N-type carrier storage layer 140) is compared and analyzed with a comparative planar gate IGBT device. The comparative planar gate IGBT device is a planar gate IGBT device without the P-type floating region 150 and with the N-type carrier storage layer 140, and the rest of the structure is consistent with the planar gate IGBT device of the present embodiment.

[0071] In power system applications, planar gate IGBT devices operate at frequencies of only a few hundred hertz, requiring low on-state voltage drop. In unavoidable parasitic inductance in power systems leads to significant voltage overshoot during high-current turn-off, necessitating high blocking voltage capability. This necessitates the use of a high-resistivity substrate (110) for IGBT fabrication. In high-voltage applications, to achieve even lower on-state voltage drop, larger IGBT cell widths combined with carrier storage layer designs are employed. While larger cell widths reduce JFET resistance and thus lower on-state voltage drop to some extent, [further issues arise]. Figure 2 The graph showing the relationship between cell width and saturation voltage for the comparative devices indicates that when the cell width (Pitch) exceeds 70µm, the effect of reducing the on-state voltage drop tends to saturate, meaning the saturation voltage (Vcesat) on the vertical axis approaches saturation. Furthermore, larger cell widths require larger chip areas. However, when the carrier storage layer concentration exceeds 1e16cm⁻¹... -3 This will cause the junction curvature of the P-type body region 122 and the local electric field concentration under the gate oxide layer on the surface of the silicon substrate 110, reducing the blocking voltage of the IGBT device.

[0072] like Figure 3 As shown, the solid line represents the planar gate IGBT device of this embodiment, and the dashed line represents the comparative device. Figure 3 The horizontal axis represents the structural depth of the substrate 110 of the device, and the vertical axis represents the front-side carrier concentration of the device. At the same structural depth, the front-side carrier concentration of the device in this embodiment is greater than that of the comparative device. Figure 3 In the diagram, the inflection point of the curve resembling a trough indicates the location of the PN junction formed in the P-type body region 122. For example... Figure 4 As shown, the solid line represents the planar gate IGBT device of this embodiment, and the dashed line represents the comparative device. Figure 4 The horizontal axis represents the voltage Vce between the collector and emitter of the device, and the vertical axis represents the current Ic of the device at the corresponding voltage. Under the same current, the voltage of the device in this embodiment is lower than that of the comparative device.

[0073] These descriptions, through the device structure of this embodiment, specifically by introducing a P-type floating region 150 with a lower doping concentration than the P-type body region 122 at the side position of the junction bend, effectively reduce the junction curvature of the P-type body region 122 and the electric field strength below the gate oxide layer on the silicon substrate 110 surface. This allows for the use of a higher doping concentration N-type carrier storage layer 140, further increasing the front-side carrier concentration of the planar gate IGBT device, thereby reducing the on-state voltage drop. Furthermore, with the same cell size, the device structure of this embodiment can significantly increase the N-type carrier concentration of the N-type carrier storage layer 140 and weaken the drop in the blocking voltage of the IGBT device, optimizing the trade-off between the on-state voltage drop and blocking voltage of the planar gate IGBT device in high-voltage applications, and achieving a low on-state voltage drop.

[0074] Below, in conjunction with Figure 1 The fabrication process of the planar gate IGBT device in this embodiment is described below:

[0075] like Figure 5 As shown, a P-type floating region 150 is implanted on substrate 110. The P-type floating region 150 is made of boron (B), boron fluoride (BF2), or a combination of B and BF2. The implantation energy range of the P-type floating region 150 is 20~2000 keV, and the implantation dose range is 1e12~1e13 cm⁻¹. -2 .

[0076] like Figure 6 As shown, the substrate 110 is epitaxially grown through a thermal process, and the epitaxial layer grown on the substrate 110 is ( Figure 6 The doping concentration of region A is consistent with that of substrate 110. The doping concentration of epitaxial layer A may also be inconsistent with that of substrate 110 or set according to actual needs. The thickness of the epitaxial layer grown on substrate 110 ranges from 3 to 15 μm, and the P-type floating region 150 is formed into a dotted shape during the thermal process.

[0077] like Figure 7 As shown, a thick oxide layer, 133, is grown on the substrate 110, particularly in the middle of the cell. The thickness of the thick oxide layer 133 ranges from 1.2 to 3 μm. Next, the N-type carrier storage layer 140 is implanted. Phosphorus ion implantation can be used to form the N-type carrier storage layer 140, with an implantation energy range of 20–2500 keV and an implantation dose range of 1e¹²–2e¹³ cm⁻¹. -2 .like Figure 8 As shown, a thermally grown gate oxide layer 131 has a thickness ranging from 80 nm to 120 nm. An N-type high-doping concentration ranging from 1e19 to 1e21 cm⁻¹ is also deposited. -3The polysilicon is etched to form a gate polysilicon 132 with a groove shape.

[0078] like Figure 9 As shown, in the N-type carrier storage layer 140, the P-type body region 122 and the N+ source region 121 are implanted and pushed into the well. Next, a dielectric layer 111 is deposited, followed by contact hole etching and metal deposition to form the emitter metal layer 160, thus obtaining the emitter. Finally, conventional substrate 110 bottom surface thinning, implantation, annealing, and metal deposition processes are performed, forming an N-type field-terminating layer 170 under the substrate 110, a P-type collector layer 180 under the N-type field-terminating layer 170, and a collector metal layer 190 under the P-type collector layer 180, to achieve the desired result. Figure 1 The complete structure shown.

[0079] While maintaining compatibility with existing processes, by introducing a P-type floating region 150 with a lower doping concentration than the P-type body region 122 at the side of the junction bend, the junction curvature of the P-type body region 122 and the electric field strength below the gate oxide layer on the silicon substrate 110 surface can be effectively mitigated. This also increases the margin of the planar gate IGBT device for the carrier concentration of the N-type carrier storage layer 140, thereby increasing the front-side carrier concentration of the planar gate IGBT device and reducing the on-state voltage drop. The structure of the planar gate IGBT device in this embodiment can be realized without complex fabrication processes, achieving cost reduction and efficiency improvement.

[0080] Example 2

[0081] Based on the same inventive concept, the second embodiment of the present invention also provides a method for fabricating a planar gate IGBT device, used to fabricate a planar gate IGBT device as shown in Embodiment 1, such as... Figure 10 As shown, the manufacturing method includes:

[0082] S201, a gate region is formed on the substrate;

[0083] S202, the doped region is formed on the substrate and below the gate region, the doped region being located at both ends of the gate region; the doped region includes: an N+ source region and a P-type body region, the N+ source region being located within the P-type body region, and the surface of the N+ source region, the surface of the P-type body region and the surface of the substrate being located on the same horizontal plane.

[0084] S203, the P-type floating region is formed in the substrate and below the gate region. The P-type floating region is also located between the doped regions and in a designated area to the side of the corresponding P-type body region. The P-type floating region is close to the P-type body region and is not in contact with the P-type body region, so as to achieve a low on-state voltage drop of the planar gate IGBT device.

[0085] Since the manufacturing method of the planar gate IGBT device introduced in the embodiment is the manufacturing method adopted by the planar gate IGBT device in Embodiment One of the present application, the specific implementation of the manufacturing method of the planar gate IGBT device of the present embodiment and its various forms of changes can be understood by those skilled in the art based on the planar gate IGBT device introduced in Embodiment One of the present application. Therefore, how the manufacturing method of the planar gate IGBT device realizes the planar gate IGBT device in Embodiment One of the present application will not be introduced in detail here. As long as those skilled in the art implement the manufacturing method adopted by the planar gate IGBT device in Embodiment One of the present application, it belongs to the scope of the present application.

[0086] Those skilled in the art will appreciate that although preferred embodiments of the application have been described, modifications and alterations can be made to the embodiments by those skilled in the art once they have the benefit of the present disclosure. Accordingly, the appended claims are intended to include within their scope all such modifications and alterations as fall within the scope of the present application.

[0087] Obviously, various modifications and changes can be made to the present application by those skilled in the art without departing from the spirit and scope of the present application. Thus, it is intended that the present application embrace all such modifications and changes as fall within the scope of the appended claims and their equivalents.

Claims

1. A planar gate IGBT device, characterized in that, include: The substrate, the doped region, and the gate region, and the P-type floating region corresponding to each of the doped regions; The substrate is made of N-type single-crystal silicon. The gate region is located on the substrate; The doped region is located on the substrate, below the gate region, and at both ends of the gate region; The doped region includes an N+ source region and a P-type body region, wherein the N+ source region is located within the P-type body region, and the surface of the N+ source region, the surface of the P-type body region, and the surface of the substrate are located on the same horizontal plane. The P-type floating region is located within the substrate, below the gate region, between the doped regions, and in a designated area to the side of the corresponding P-type body region. The P-type floating region is close to the P-type body region but not in contact with it, thereby achieving a low on-state voltage drop for the planar gate IGBT device. The vertical region of the designated area is the area between the surface of the P-type body region and the bottom of the P-type body region to 15µm below it. The horizontal region of the designated area is the area between the adjacent side of the P-type body region and the designated side of the thick oxide layer. The adjacent side of the P-type body region is the side of the P-type body region adjacent to another doped region, and the designated side of the thick oxide layer is the side of the thick oxide layer closest to the P-type body region. The gate region includes: a gate oxide layer, a thick oxide layer, and a gate polysilicon layer; The gate oxide layer and the thick oxide layer are located on the surface of the substrate, with the gate oxide layer located on both sides of the thick oxide layer; The gate polysilicon is located on the gate oxide layer and the thick oxide layer; The gate polysilicon is curved with grooves, and the grooves of the gate polysilicon cover the thick oxide layer so that the thick oxide layer can withstand a higher electric field and realize the high voltage application of the device.

2. The planar gate IGBT device as described in claim 1, characterized in that, The doping concentration of the P-type floating region is less than the doping concentration of the P-type body region.

3. The planar gate IGBT device as described in any one of claims 1 to 2, characterized in that, Also includes: N-type carrier storage layer; The N-type carrier storage layer corresponds one-to-one with the doped region, the doped region is located within the N-type carrier storage layer, and the surface of the N-type carrier storage layer and the surface of the substrate are on the same horizontal plane. In the presence of the N-type carrier storage layer, the P-type floating region is not in contact with the N-type carrier storage layer.

4. The planar gate IGBT device as described in claim 1, characterized in that, Also includes: Emitter metal layer; the emitter metal layer is located above the substrate and the gate region, and the emitter metal layer covers the gate region and the doped region.

5. The planar gate IGBT device as described in claim 4, characterized in that, Also includes: A dielectric layer is located on the gate region and below the emitter metal layer, the dielectric layer covering the gate region to isolate the gate region and the emitter metal layer.

6. The planar gate IGBT device as described in claim 1, characterized in that, Also includes: N-type field termination layer, P-type collector layer and collector metal layer; The N-type field termination layer is located beneath the substrate; The P-type collector layer is located below the N-type field termination layer; The current collector metal layer is located below the P-type current collector layer.

7. A method for fabricating a planar gate IGBT device, characterized in that, The method for manufacturing a planar gate IGBT device as described in any one of claims 1 to 6 includes: A gate region is formed on the substrate; The doped region is formed on the substrate and below the gate region, and the doped region is located at both ends of the gate region; the doped region includes an N+ source region and a P-type body region, the N+ source region is located within the P-type body region, and the surface of the N+ source region, the surface of the P-type body region and the surface of the substrate are located on the same horizontal plane. The P-type floating region is formed within the substrate and below the gate region. The P-type floating region is also located between the doped regions and in a designated area to the side of the corresponding P-type body region. The P-type floating region is close to the P-type body region but not in contact with it, so as to achieve a low on-state voltage drop of the planar gate IGBT device.

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