Method for optimizing characteristics of metal oxide semiconductor field effect transistor

Abstract

The invention discloses a method for optimizing the characteristics of a metal oxide semiconductor field effect transistor (MOSFET), which is particularly suitable for manufacturing a trench gate power MOSFET. The method aims at solving the contradiction between gate deep concave etching and groove corner shoulder collapse which are needed for preventing gate-source electric leakage (IGSS) failure and influence on an injection profile. The method comprises the following steps: after a gate conductive layer is formed, performing first shallow etchback; after the first etch-back, ion implantation of the P body region and the N + region is carried out; and finally, after the injection is completed, carrying out second deeper etch-back. Through the two-step etch-back process, the first shallow etch-back effectively protects the corner of the trench, which is conducive to optimizing the junction depth of the P body region / N + region, stabilizing the threshold voltage (VTH) and inhibiting the short channel effect; and the second time of deep back etching ensures thorough removal of grid electrode residues, so that IGSS failure is effectively prevented. The method improves the performance and reliability of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and particularly relates to a method for optimizing characteristics of a metal oxide semiconductor field effect transistor. BACKGROUND

[0002] Power MOSFETs, especially trench-gate power MOSFETs (such as shield-gate trench MOSFETs, SGT MOSFETs), are key devices in the field of power electronics. With the development of technology, in order to improve the integration and performance of devices, the pitch size of trench-gate power MOSFETs is continuously reduced. However, the reduction of the pitch size leads to the further compression of the width of the mesa structure in the trench structure of the device.

[0003] In the manufacturing process, for example, when the field oxide or the gate oxide is grown, due to process factors (such as stress in the oxidation process, difference in oxidation rate at the top corner, etc.), the corners of the trench structure, especially the top corner of the mesa structure, are prone to uneven consumption of the oxide layer or structural collapse, forming a so-called “slump”. This “slump” will affect the uniformity and doping distribution of the subsequent ion implantation step, such as the implantation profile of the P-well and the N-well (or N+ source region).

[0004] In addition, when forming the gate structure, an etch back (or recess) step is usually required for the deposited gate conductive layer (such as doped polysilicon, Gate Poly). One important purpose of performing the gate polysilicon etch back is to remove the polysilicon that may be left between the device cell region and the terminal structure (such as the source poly linkup region), in order to prevent these residual polysilicon from connecting the gate and the source, thereby avoiding the gate-source-drain short (IGSS) failure. In order to ensure complete removal, the etch back step usually requires a certain over-etch (OE) amount, resulting in a relatively deep recess (for example, the recess depth is more than 0.1 microns) of the top surface of the gate polysilicon relative to the top surface of the mesa structure.

[0005] However, research has found (for example, through process simulation) that in the presence of "shoulder collapse", a deeper gate poly recess depth can significantly affect the implant profile of the P-well and N+ region. Specifically, a deeper recess makes it easier for implant ions to enter the channel region, resulting in a deeper junction depth of the N+ region and P-well. A deeper N+ region junction depth can shorten the effective channel length, potentially triggering short channel effects and increasing channel leakage; at the same time, changes in the N+ region / P-well junction depth can affect the gate's control over the channel, leading to an increase in the threshold voltage (VTH) of the device, and even potentially making the device difficult to turn on normally, thereby degrading the device's switching characteristics.

[0006] Therefore, the prior art faces a dilemma: on the one hand, sufficient gate poly etch-back depth is needed to avoid the risk of IGSS failure, and on the other hand, a deeper etch-back depth can worsen the implant profile in the presence of "shoulder collapse", leading to problems such as difficult junction depth control, threshold voltage drift, and short channel effects.

[0007] In view of this, there is an urgent need to propose a new MOSFET manufacturing process that can ensure effective removal of gate poly residue, avoid IGSS failure, optimize the implant profile of the P-well and N+ region, control the junction depth, stabilize the threshold voltage, and suppress short channel effects, especially in high-density, small-size trench gate power MOSFET devices. SUMMARY

[0008] The present application aims to solve the technical problems faced in existing semiconductor manufacturing processes, particularly in the manufacture of trench gate power metal-oxide-semiconductor field-effect transistors (MOSFETs). As device cell pitch size continues to shrink, the mesa width in the trench structure is compressed, and at the same time, during the growth of the field oxide layer or the gate oxide layer, "shoulder collapse" phenomena can easily occur at the corners of the trench. This structural defect can severely affect the ion implant profile of the subsequent P-body and N+ source regions, leading to uneven doping distribution and difficult junction depth control.

[0009] On the other hand, in order to prevent the gate conductive layer (such as poly silicon) from remaining between the cell region and the termination structure after etch-back (Recess / Etch Back), and to avoid the resulting gate-source-drain leakage (IGSS) failure, a deeper etch-back is usually required, for example, making the top of the gate poly silicon below the mesa structure surface by more than 0.1 microns. However, research has shown that in the presence of "shoulder collapse", this depth of etch-back can further worsen the implant profile of the P-body and N+ regions, leading to a deeper junction depth. A deeper N+ region junction depth can shorten the effective channel length, triggering short channel effects and channel leakage; at the same time, changes in the P-body / N+ region junction depth can affect the gate's control over the channel, leading to an increase or drift in the threshold voltage (VTH), affecting the normal switching characteristics of the device.

[0010] Therefore, there is a dilemma in the prior art: deep etching is needed to avoid IGSS failure, but this will destroy the implant profile of the critical doping region, especially in small size devices and in the presence of process defects (such as "shoulder collapse"). There is an urgent need for a MOSFET manufacturing method that can ensure good implant profile control (optimize junction depth and VTH, suppress short channel effect) and effectively prevent IGSS failure at the same time.

[0011] To achieve the above object and other related objects, the present application provides a method for optimizing the characteristics of a metal oxide semiconductor field effect transistor, comprising:

[0012] Step one, providing a semiconductor substrate, a trench structure is formed on the semiconductor substrate, the trench structure includes a mesa structure and a groove;

[0013] Step two, forming a field dielectric layer on the sidewall and bottom of the groove;

[0014] Step three, depositing a source conductive layer to fill the groove where the field dielectric layer is formed;

[0015] Step four, etching the source conductive layer and the field dielectric layer to define a source structure in the groove and expose part of the sidewall and top surface of the mesa structure;

[0016] Step five, forming an isolation dielectric layer above the source structure and part of the sidewall of the exposed mesa structure, wherein the top surface of the isolation dielectric layer is lower than the top surface of the mesa structure, thereby leaving a space above the isolation dielectric layer in the groove for forming a gate structure;

[0017] Step six, forming a gate dielectric layer on the inner wall of the groove above the isolation dielectric layer and the upper sidewall and top surface of the mesa structure;

[0018] Step seven, depositing a gate conductive layer to fill the remaining space in the groove above the isolation dielectric layer defined by the gate dielectric layer;

[0019] Step eight, first etching the gate conductive layer and the gate dielectric layer thereunder, so that the gate conductive layer has a first recess depth on the top surface of the mesa structure region;

[0020] Step nine, after the first etching, implanting P-type dopants into the mesa structure to form a P body region;

[0021] Step ten, after implanting the P-type dopants, implanting N-type dopants into the mesa structure to form an N+ region;

[0022] Step eleven, after implanting the N-type dopant, performing a second etch-back to the gate conductive layer so that the gate conductive layer has a second recess depth on the top surface of the mesa structure region, the second recess depth is greater than the first recess depth.

[0023] Preferably, the metal oxide semiconductor field effect transistor is a trench gate power MOSFET.

[0024] Preferably, in step three, the source conductive layer is a source polysilicon layer.

[0025] Preferably, in step seven, the gate conductive layer is a gate polysilicon layer.

[0026] Preferably, in step eight, the first recess depth is such that the top surface of the gate conductive layer is flush with or slightly lower than the top surface of the mesa structure.

[0027] Preferably, in step eight, the first recess depth is in the range of 270 angstroms to 330 angstroms.

[0028] Preferably, in step nine, the implanting P-type dopant includes at least one P-body implant.

[0029] Preferably, the P-body implant includes: a first P-body implant using boron as dopant, implant energy in the range of 36 kiloelectron-volts to 44 kiloelectron-volts, implant dose in the range of 5.4E12 atoms per square centimeter to 6.6E12 atoms per square centimeter; and a second P-body implant using boron as dopant, implant energy in the range of 40.5 kiloelectron-volts to 49.5 kiloelectron-volts, implant dose in the range of 3.6E12 atoms per square centimeter to 4.4E12 atoms per square centimeter.

[0030] Preferably, in step nine, further comprising: a halo implant using boron as dopant, implant energy in the range of 31.5 kiloelectron-volts to 38.5 kiloelectron-volts, implant dose in the range of 9E12 atoms per square centimeter to 1.1E13 atoms per square centimeter.

[0031] Preferably, after step nine, before step ten or after step ten, further comprising a step of performing the P-body region anneal.

[0032] Preferably, in the step of performing the P-body region anneal, the anneal temperature is in the range of 900 degrees Celsius to 1100 degrees Celsius, and the anneal time is in the range of 27 seconds to 33 seconds.

[0033] Preferably, in step ten, the N-type dopant is arsenic (As) or phosphorus (P).

[0034] Preferably, in step ten, the implantation energy of the implantation of N-type dopant is in the range of 40.5 keV to 49.5 keV, and the implantation dose is in the range of 4.5E15 atoms / cm2 to 5.5E15 atoms / cm2.

[0035] Preferably, in step eleven, the second recess depth is in the range of 990 angstroms to 1210 angstroms

[0036] Preferably, the method is used to prevent MOSFET short channel effect and optimize its threshold voltage.

[0037] As described above, the method for optimizing the characteristics of a metal oxide semiconductor field effect transistor of the present application has the following beneficial effects:

[0038] 1. Precise control of implantation profile and junction depth: the first shallow etch effectively protects the trench corner region, significantly reduces the impact of "shoulder collapse" on the subsequent P body region and N+ region ion implantation profile, so that the junction depth can be precisely controlled, avoiding the problems caused by over-deep junction, and the doping profile is closer to the ideal state.

[0039] 2. Optimize threshold voltage (VTH): by precisely controlling the junction depth of the P body region and the N+ region, the control ability of the gate on the channel is improved, so that the threshold voltage of the device is more stable, and it is easier to match the design target value, avoiding the problem of excessive VTH or drift caused by out-of-control junction depth, ensuring the normal opening and working of the device.

[0040] 3. Suppress short channel effect: by preventing the N+ region from being too deep, the effective channel length is maintained, thereby effectively suppressing the short channel effect and reducing the sub-threshold leakage current and off-state leakage of the device.

[0041] Effectively prevent IGSS failure: the second deep etch step ensures the reliable removal of the gate conductive layer residue between the cell region and the terminal structure, completely eliminates the IGSS leakage risk caused by the connection of the polysilicon residue to the gate and source, and improves the reliability and yield of the device.

[0042] 4. Process decoupling and compatibility: the method ingeniously decouples the two conflicting process requirements of protecting the implantation profile (which requires shallow etching) and preventing IGSS (which requires deep etching), and meets them respectively through timing arrangement. The process steps of the method are compatible with the existing mainstream MOSFET manufacturing process, and are easy to implement.

[0043] In summary, the method provided by the present application significantly improves the implantation control of the key doped region without sacrificing the IGSS performance, optimizes the threshold voltage and short channel characteristics of the device, and provides an effective technical approach for manufacturing small-size trench gate power MOSFET with high performance and high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 Shown is a schematic diagram of the process flow of the present invention;

[0045] Figure 2 It is a schematic diagram showing the first etching back of the gate conductive layer according to the present invention;

[0046] Figure 3 Shown is a schematic diagram of forming a P body region and an N+ region according to the present invention;

[0047] Figure 4 It is a schematic diagram showing the second etching back of the gate conductive layer according to the present invention. DETAILED DESCRIPTION

[0048] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] An embodiment of the present application provides a method for optimizing the characteristics of a metal oxide semiconductor field effect transistor (MOSFET), aiming to solve the problems in the prior art, especially in the manufacture of small-size trench gate power MOSFETs, caused by the contradiction between the "collapsed shoulder" problem of the trench corner and the need for deep etching of the gate polysilicon, resulting in deformation of the P body region / N+ region injection profile, difficulty in controlling the junction depth, threshold voltage drift, and short channel effect.

[0050] See also Figure 1 , the method comprises the following steps:

[0051] Step 1: Provide a semiconductor substrate 101 on which a groove structure is formed. The groove structure includes a platform structure and a groove. This is particularly important for manufacturing high-density, small cell pitch devices. As the device size decreases, the width of the platform structure is compressed, making subsequent process control more challenging.

[0052] In some embodiments, the semiconductor substrate 101 may be a silicon substrate, such as a P-type or N-type doped silicon wafer, or may be a structure including an epitaxial layer.

[0053] In some embodiments, the MOSFET is a trench gate power MOSFET, such as a shielded gate trench (SGT) MOSFET.

[0054] Step two, form a field dielectric layer 102 on the sidewall and bottom of the recess; the field dielectric layer 102 is usually used to provide electrical isolation in the non-active area of the device or the bottom of the recess, such as a silicon oxide layer formed by thermal oxidation or chemical vapor deposition (CVD) etc.

[0055] Step three, deposit a source conductive layer 103 to fill the recess formed with the field dielectric layer 102; the source conductive layer 103 can be used as the source connection part of the device, or as a shield electrode in the shield gate structure.

[0056] In some embodiments, the source conductive layer 103 is a source polysilicon layer, such as doped or undoped polysilicon formed by low pressure chemical vapor deposition (LPCVD) etc.

[0057] Step four, etch the source conductive layer 103 and the field dielectric layer 102, such as by anisotropic dry etching process, to define the source structure in the recess and expose part of the sidewall and top surface of the mesa structure, to create conditions for the formation of the gate dielectric layer 105 and the gate conductive layer 106 and the channel region.

[0058] Step five, form an isolation dielectric layer 104 on the source structure and part of the sidewall of the exposed mesa structure, such as a silicon oxide, silicon nitride or a combination layer, to reliably electrically isolate the source structure from the subsequently formed gate structure. The top surface of the isolation dielectric layer 104 is lower than the top surface of the mesa structure, leaving a space in the recess above the isolation dielectric layer 104 for forming the gate structure.

[0059] Step six, form a gate dielectric layer 105 on the inner wall of the recess above the isolation dielectric layer 104 and the upper sidewall and top surface of the mesa structure; the gate dielectric layer 105 is a core component of the MOSFET device, and its quality and thickness directly affect the threshold voltage, transconductance, leakage and reliability of the device. A high-quality silicon oxide layer is usually used, such as formed by a precisely controlled thermal oxidation process.

[0060] In some embodiments, the thickness of the gate dielectric layer 105 can be adjusted according to the design requirements of the device.

[0061] Step seven, deposit a gate conductive layer 106 to fill the remaining space in the recess above the isolation dielectric layer 104 defined by the gate dielectric layer 105; the gate conductive layer 106 will serve as the gate to control the turn-on and turn-off of the MOSFET.

[0062] In some embodiments, the gate conductive layer 106 is a doped polysilicon layer, such as N-type heavily doped polysilicon, to obtain a lower gate resistance. It can be deposited by CVD etc. and in-situ doped or subsequently ion implanted doped.

[0063] Step eight, perform a first etch-back of the gate conductive layer 106 and the gate dielectric layer 105 thereunder, to form a structure as shown in FIG. 6, for example, using a plasma dry etching process, so that the gate conductive layer 106 has a first recessed depth on the top surface of the mesa structure region; this step is one of the key innovations of the present method. Unlike the conventional process which etches the gate polysilicon to a deeper position in one step, this step performs a shallower etch-back. Figure 2

[0064] In some embodiments, in step eight, the first recessed depth is such that the top surface of the gate conductive layer 106 is flush with or slightly lower than the top surface of the mesa structure. This shallower etch-back depth is significant: first, it enables the gate conductive layer 106 to act as a protective cap over the trench corner during subsequent ion implantation, especially for the regions where the "shoulder collapse" problem exists, effectively blocking excessive scattering or implantation of the implantation ions into the deep trench sidewall, thus preserving the steepness of the subsequent P body and N+ implantation profiles and the predetermined junction depth; second, an appropriate etch-back amount (e.g. including a small amount of over-etching) helps to remove any potential residue or native oxide layer on the top of the mesa structure, ensuring uniformity and cleanliness of the subsequent implantation.

[0065] In some embodiments, in step eight, the first recessed depth is in the range of 270 angstroms to 330 angstroms , for example 300 angstroms.

[0066] Step nine, after the first etch-back, implant P-type dopants into the mesa structure to form a P body region; due to the shallow first etch-back depth, the protective effect of the gate conductive layer 106 on the trench corner is fully realized, and when P-type dopant implantation is performed at this time, a P body doping profile closer to the ideal design and less affected by "shoulder collapse" can be obtained. This is crucial for accurately controlling the threshold voltage (VTH) and channel length of the device, and helps to avoid problems such as VTH drift or device failure to turn on due to improper control of P body junction depth.

[0067] In some embodiments, in step nine, implanting the P-type dopants includes at least one P body implantation. Multiple implantations of different energies and doses can be designed as needed to optimize the doping concentration gradient of the P body region.

[0068] ​In some embodiments, in step nine, the P-body implant includes: a first P-body implant using boron (B) as dopant, implant energy in a range of 36 kiloelectronvolt (keV) to 44 kiloelectronvolt (keV), for example 40 kiloelectronvolt (keV), implant dose in a range of 5.4E12 atoms / cm2to 6.6E12 atoms / cm2, for example 6E12 atoms / cm2; and a second P-body implant using boron (B) as dopant, implant energy in a range of 40.5 kiloelectronvolt (keV) to 49.5 kiloelectronvolt (keV), for example 40 kiloelectronvolt (keV), implant dose in a range of 3.6E12 atoms / cm2to 4.4E12 atoms / cm2, for example 4E12 atoms / cm2.

[0069] In some embodiments, in step nine, further includes: a halo implant using boron (B) as dopant, implant energy in a range of 31.5 kiloelectronvolt (keV) to 38.5 kiloelectronvolt (keV), for example 35 kiloelectronvolt (keV), implant dose in a range of 9E12 atoms / cm2to 1.1E13 atoms / cm2, for example 1E13 atoms / cm2. The halo implant is usually used to form a counter-doped region near the channel close to the source / drain region, which can effectively suppress the short channel effect and improve the off-state characteristics of the device.

[0070] In some embodiments, after step nine, before or after step ten, further includes a step of P-body anneal. Anneal, for example rapid thermal anneal (RTA), is a necessary process step to activate the implanted P-type dopants to make them electrically active by occupying substitutional sites in the silicon lattice, and to repair the lattice damage caused to the semiconductor substrate 101 during ion implantation, to restore the crystal structure.

[0071] In some embodiments, in the step of P-body anneal, the anneal temperature is in a range of 900 degrees Celsius (°C) to 1100 degrees Celsius (°C), and the anneal time is in a range of 27 seconds (s) to 33 seconds (s), for example the anneal temperature is 1000 degrees Celsius and the anneal time is 30 seconds.

[0072] Step ten, after the implantation of P-type dopants (usually after the P-body implant and related anneal are completed), N-type dopants are implanted into the mesa structure to form N+ regions, forming a structure as shown in Figure 3 The N+ regions usually serve as the source regions of the MOSFET, and require high concentration of N-type doping to form a good ohmic contact and reduce the source resistance. Similar to the P-body region implant, due to the protection of the first shallow etch, the implant profile and junction depth of the N+ regions can also be better controlled, avoiding the risk of exacerbating the short channel effect and increasing the channel leakage due to excessively deep junction depth.

[0073] In some embodiments, in step ten, the N-type dopant is arsenic (As) or phosphorus (P).

[0074] In some embodiments, in step 10, the N-type dopant is implanted at an injection energy in the range of 40.5 kiloelectronvolts (keV) to 49.5 kiloelectronvolts (keV), for example, 45 keV, and at an injection dose in the range of 4.5E15 atoms / cm2 to 5.5E15 atoms / cm2, for example, 5E15 atoms / cm2. The higher injection dose ensures low sheet resistance of the N+ source region. After the N+ implant, a corresponding annealing step is typically required to activate the dopant and repair damage.

[0075] Step 11: After the N-type dopant is implanted (and usually after all related implantation and annealing steps are completed), the gate conductive layer 106 is etched back for the second time to form a Figure 4 In the structure shown, for example, a dry etch process is continued, resulting in a second recess depth of the gate conductive layer 106 at the top surface of the mesa structure region, which is greater than the first recess depth. This is the second key step in the method of the present invention. The depth of this etch-back is significantly greater than the first etch-back. Its primary purpose is to increase the recess depth of the gate conductive layer 106 to a sufficient depth to completely remove any remaining "filaments" or connections in the gate conductive layer 106 between the device cell active area and the terminal structure (e.g., the source polysilicon connection region). This residual is one of the main causes of gate-source leakage current (IGSS) failures. By performing this deep etch-back, the risk of IGSS can be effectively eliminated, improving device yield and long-term reliability. Crucially, since the implant profiles of the P-body and N+ regions have already been formed under the protection of the first shallow etch-back, this deep etch-back operation will no longer adversely affect these critical doping profiles. Therefore, by cleverly dividing the gate etch-back into two steps and performing ion implantation between the two steps, the present method successfully decouples the seemingly conflicting requirements of protecting the implant profile and preventing IGSS failures.

[0076] In some embodiments, in step 11, the second recess depth is 990 angstroms. to 1210 angstroms The depth is sufficient to meet the requirement of removing residual polysilicon, for example, the recess depth reaches more than 0.1 micron (1000 angstroms).

[0077] In summary, by adopting the above-mentioned optimized process flow including two-step gate etch-back and ion implantation of the P-body region and the N+ region between the two etch-backs, the method provided in the embodiment of the present application brings significant beneficial effects:

[0078] 1. Improved implant profile control: The first light etch effectively protects the trench corner, making the P body and N+ region implant junction depth less susceptible to "shoulder collapse" and over-deepening, resulting in a steeper doping profile closer to the design target.

[0079] 2. Optimized device characteristics: Precise control of junction depth helps stabilize and optimize the threshold voltage (VTH) of the device, preventing excessive VTH that can lead to difficult turn-on, while maintaining effective channel length to effectively suppress short channel effects and reduce channel leakage. This helps improve the switching performance and energy efficiency of the device.

[0080] 3. Prevention of IGSS failure: The second deep etch ensures complete removal of gate poly residue, effectively avoiding accidental connection between the gate and source, significantly reducing the risk of IGSS leakage.

[0081] 4. Improved reliability and yield: By simultaneously addressing implant control and IGSS issues, the overall stability and yield of device manufacturing are improved, reducing production costs.

[0082] This method has good process compatibility and is easy to integrate into existing semiconductor manufacturing processes, especially suitable for the production of advanced trench gate power MOSFET devices with high performance and reliability requirements.

[0083] It should be noted that the diagrams provided in the embodiments only illustrate the basic concept of the application in a schematic manner, and only show the components related to the application in the diagrams, not according to the number, shape and size of the components when actually implemented. The actual implementation of each component may be arbitrarily changed in terms of type, number and proportion, and the component layout pattern may be more complex.

[0084] The above embodiments only illustratively explain the principles and effects of the application, and are not intended to limit the application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed by the application should be covered by the claims of the application.

Claims

1. A method for optimizing the characteristics of a metal oxide semiconductor field effect transistor, characterized in that: At least: Step 1: providing a semiconductor substrate, wherein a groove structure is formed on the semiconductor substrate, and the groove structure includes a boss structure and a groove; Step 2: forming a field dielectric layer on the sidewall and bottom of the groove; Step 3: depositing a source conductive layer to fill the groove formed with the field dielectric layer; Step 4: etching the source conductive layer and the field dielectric layer to define a source structure in the groove and expose a portion of the sidewall and top surface of the boss structure; Step 5: forming an isolation dielectric layer above the source structure and on the exposed sidewalls of the mesa structure, wherein a top surface of the isolation dielectric layer is lower than a top surface of the mesa structure, thereby leaving space for forming a gate structure within the groove and above the isolation dielectric layer; Step 6: forming a gate dielectric layer on the inner wall of the groove above the isolation dielectric layer and on the upper sidewall and top surface of the boss structure; Step 7: depositing a gate conductive layer to fill the remaining space in the groove defined by the gate dielectric layer and located above the isolation dielectric layer; Step eight, performing a first etching back on the gate conductive layer and the gate dielectric layer thereunder, so that the gate conductive layer has a first recess depth on the top surface of the boss structure region; Step 9: After the first etch-back, injecting P-type dopants into the boss structure to form a P-body region; Step 10: After injecting the P-type dopant, injecting an N-type dopant into the boss structure to form an N+ region; Step 11: After injecting the N-type dopant, perform a second etching back on the gate conductive layer so that the gate conductive layer has a second recessed depth on the top surface of the boss structure region, and the second recessed depth is greater than the first recessed depth.

2. The method for optimizing the characteristics of a metal oxide semiconductor field effect transistor according to claim 1, wherein: The metal oxide semiconductor field effect transistor is a trench gate power MOSFET.

3. The method for optimizing the characteristics of a metal oxide semiconductor field effect transistor according to claim 1, wherein: In step three, the source conductive layer is a source polysilicon layer.

4. The method for optimizing the characteristics of a metal oxide semiconductor field effect transistor according to claim 1, wherein: In step seven, the gate conductive layer is a gate polysilicon layer.

5. The method for optimizing the characteristics of a metal oxide semiconductor field effect transistor according to claim 1, wherein: In step eight, the first recess depth is such that the top surface of the gate conductive layer is flush with or slightly lower than the top surface of the boss structure.

6. The method for optimizing the characteristics of a metal oxide semiconductor field effect transistor according to claim 5, wherein: In step eight, the depth of the first recess is in a range of 270 angstroms to 330 angstroms.

7. The method for optimizing the characteristics of a metal oxide semiconductor field effect transistor according to claim 1, wherein: In step nine, the implanting of P-type dopants includes at least one P-body region implantation.

8. The method for optimizing the characteristics of a metal oxide semiconductor field effect transistor according to claim 7, wherein: The P body injection includes: a first P body injection, using boron as a dopant, an injection energy in the range of 36 keV to 44 keV, and an injection dose in the range of 5.4E12 atoms / cm2 to 6.6E12 atoms / cm2; and a second P body injection, using boron as a dopant, an injection energy in the range of 40.5 keV to 49.5 keV, and an injection dose in the range of 3.6E12 atoms / cm2 to 4.4E12 atoms / cm2.

9. The method for optimizing the characteristics of a metal oxide semiconductor field effect transistor according to claim 8, wherein: Step nine further includes: halo implantation, using boron as a dopant, with an implantation energy ranging from 31.5 keV to 38.5 keV and an implantation dose ranging from 9E12 atoms / cm2 to 1.1E13 atoms / cm2.

10. The method for optimizing the characteristics of a metal oxide semiconductor field effect transistor according to claim 1 or 7, wherein: After step nine, before step ten, or after step ten, the method further includes a step of annealing the P body region.

11. The method for optimizing characteristics of a metal oxide semiconductor field effect transistor according to claim 10, wherein: In the step of annealing the P body region, the annealing temperature is in the range of 900 degrees Celsius to 1100 degrees Celsius, and the annealing time is in the range of 27 seconds to 33 seconds.

12. The method for optimizing characteristics of a metal oxide semiconductor field effect transistor according to claim 1, wherein: In step ten, the N-type dopant is arsenic or phosphorus.

13. The method for optimizing characteristics of a metal oxide semiconductor field effect transistor according to claim 1 or 12, wherein: In step ten, the implantation energy of the N-type dopant is in the range of 40.5 keV to 49.5 keV, and the implantation dose is in the range of 4.5E15 atoms / cm2 to 5.5E15 atoms / cm2.

14. The method for optimizing characteristics of a metal oxide semiconductor field effect transistor according to claim 1, wherein: In step eleven, the second recess has a depth ranging from 990 angstroms to 1210 angstroms.

15. The method for optimizing characteristics of a metal oxide semiconductor field effect transistor according to claim 1, wherein: The method is used to prevent the short channel effect of MOSFET and optimize its threshold voltage.

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