Heterojunction device with hole absorption layer and preparation process

Abstract

The heterojunction device comprises a substrate layer, a buffer layer, a heterojunction structure, a regulation and control layer, a gate contact layer, the hole absorption layer and a metal electrode, the buffer layer is arranged on the substrate layer, and the heterojunction structure comprises a first semiconductor layer and a second semiconductor layer. A heterojunction is formed between the first semiconductor layer and the second semiconductor layer, the regulation and control layer is arranged on the second semiconductor layer, the gate contact layer is arranged on the regulation and control layer, the hole absorption layer is located on one side of the regulation and control layer and used for absorbing holes and restraining negative effects of the regulation and control layer on two-dimensional electron gas, and the metal electrode is arranged on the gate contact layer and used for absorbing the holes. The method is used for electrical connection and control. The hole absorption layer is introduced into the adjacent region of the regulation and control layer in the device, so that the inhibition effect of the regulation and control layer on two-dimensional electron gas generation of a heterojunction structure interface is effectively weakened, and the conduction capability and the electron migration efficiency of the device are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to a heterojunction device with a hole absorption layer and a preparation process. BACKGROUND

[0002] GaN-based heterojunction devices (HEMTs) have shown great application prospects in various fields due to their excellent high-frequency and high-power characteristics. GaN materials have excellent wide bandgap, high electron mobility, and thermal stability, making them have great advantages in high-performance applications such as radio frequency amplifiers, power conversion, 5G communication, and electric vehicles. With the advancement of technology, GaN heterojunction devices are increasingly used in high-temperature and high-pressure environments, becoming the core of modern electronic devices. In order to further improve the performance of the device, especially the gate control ability and the regulation of carrier injection, optimizing the generation and stability of two-dimensional electron gas (2DEG) has become a key research.

[0003] In GaN heterojunction devices, the p-GaN layer is often used as a gate control layer in GaN heterojunction devices, which can effectively adjust the threshold voltage and improve the gate control ability of the device. It has significant advantages in improving the device turn-off characteristics and gate response speed, especially in high-frequency applications. However, the p-GaN layer also brings some limitations: since the p-GaN layer is a p-type doped material, it forms a depletion region between the p-GaN layer and the AlGaN layer, which inhibits the generation of 2DEG. The stability of 2DEG is the key to the high performance of GaN devices, and the introduction of p-GaN affects the generation of 2DEG at the AlGaN / GaN interface, limiting the performance of the device under high power and high frequency. Therefore, how to enhance the gate control while reducing the inhibitory effect of p-GaN on the generation of 2DEG has become a problem to be solved in the design of GaN heterojunction devices. SUMMARY

[0004] In order to solve the above technical problems, the present application provides a heterojunction device with a hole absorption layer and a preparation process.

[0005] The technical solution of the present application to solve the above technical problems is as follows: a heterojunction device with a hole absorption layer, comprising: a substrate layer; a buffer layer disposed on the substrate layer; a heterojunction structure comprising a first semiconductor layer and a second semiconductor layer, a heterojunction being formed between the first semiconductor layer and the second semiconductor layer; a control layer disposed on the second semiconductor layer for adjusting the gate threshold voltage; a gate contact layer disposed on the control layer; a hole absorption layer, located on one side of the control layer, comprising fixed negative charge centers for absorbing holes and inhibiting the negative effect of the control layer on the two-dimensional electron gas; a metal electrode, disposed on the gate contact layer, for electrical connection and control.

[0006] Further, the second semiconductor layer has a first ohmic contact electrode and a second ohmic contact electrode at two ends respectively, and the metal electrode is located between the first ohmic contact electrode and the second ohmic contact electrode.

[0007] Further, a first insulating layer is disposed between the first ohmic contact electrode and the control layer, and a second insulating layer is disposed between the hole absorption layer and the second ohmic contact electrode, and the hole absorption layer is located between the second insulating layer and the control layer.

[0008] Further, the hole absorption layer is an n-type doped semiconductor layer, and the negative charge centers are composed of fixed negative charges after donor doping ionization.

[0009] Further, the substrate layer is selected from one or more superimposed structures of Si, Al2O3, HfO2, Ga2O3, CrO or MgO.

[0010] Further, the buffer layer is one of SiC, AlN, GaN or AlGaN.

[0011] Further, the first semiconductor layer, the second semiconductor layer, the control layer and the gate contact layer are all ternary-pentatomic compound semiconductors, and the material components or types of the first semiconductor layer and the second semiconductor layer are different.

[0012] Further, the first semiconductor layer is one of GaN, InN, AlGaN, InGaN, InAlGaN or AlN; and the second semiconductor layer is one of GaN, InN, AlGaN, InGaN or AlN.

[0013] The application also provides a preparation process of a heterojunction device with a hole absorption layer, comprising the following steps: S1: sequentially depositing a buffer layer and a first semiconductor layer on a substrate layer by organic chemical deposition (MOCVD); S2: depositing a second semiconductor layer on the first semiconductor layer by organic chemical deposition (MOCVD), atomic layer epitaxy deposition (ALD) or molecular beam epitaxy deposition (MBE) to form a heterojunction structure; S3: using alcohol, acetone and deionized water to clean Al x Ga 1-xThe N / GaN heterojunction is ultrasonically cleaned, dried by nitrogen blowing, ion-etched by BCl3 gas to form an ohmic contact area, and an ohmic contact electrode is formed by electron beam evaporation, and rapid annealing is performed at 850°C in an N2 atmosphere for about 30 seconds; S4: depositing a regulation layer and a gate contact layer on the heterojunction structure by organic chemical deposition (MOCVD), and etching; S5: forming a metal electrode on the gate contact layer by electron beam evaporation; S6: depositing an n-type doped Si layer as a hole absorption layer on the side of the regulation layer on the heterojunction structure by organic chemical deposition (MOCVD) or atomic layer epitaxy deposition (ALD), and etching; S7: forming a high-dielectric-constant first insulating layer and a second insulating layer on the heterojunction structure by magnetron sputtering, plasma-enhanced chemical vapor deposition or atomic layer epitaxy deposition (ALD), and performing rapid annealing at 300-1200°C for 1-10 minutes.

[0014] Further, in step S6, a layer of Si material is selectively deposited on the surface of the Al x Ga 1-x N layer along the gate sidewall region by organic chemical deposition (MOCVD), atomic layer epitaxy deposition (ALD) or other thin film technology to form a hole absorption layer. After deposition, the Si layer is patterned by reactive ion etching to only retain the structure layer in the target area.

[0015] The heterojunction device with a hole absorption layer provided by the present application has the following beneficial effects: the hole absorption layer is introduced in the adjacent area of the regulation layer, effectively weakening the inhibitory effect of the regulation layer on the generation of 2DEG at the interface of the heterojunction structure, improving the conduction capacity and electron migration efficiency of the device; and the structure enhances the gate regulation performance while maintaining the electrical neutrality of the device in the non-working state, reducing the risk of leakage, and significantly improving the overall performance and reliability of the heterojunction device. In addition, the hole absorption layer is realized by n-type doping process, which has good process compatibility and is convenient for integrated application. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a structural schematic diagram of the present application; Figures 2-8 is a process flow diagram in the present application; Figures 1 to 8The reference numerals shown in the figures represent respectively: 101-first ohmic contact electrode, 102-second ohmic contact electrode, 103-metal electrode, 201-substrate layer, 202-buffer layer, 203-first semiconductor layer, 204-second semiconductor layer, 205-regulating layer, 206-gate contact layer, 207-hole absorption layer, 301-first insulating layer, 302-second insulating layer. DETAILED DESCRIPTION

[0017] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0018] like Figure 1 As shown, a heterojunction device with a hole absorption layer includes a substrate layer 201, a buffer layer 202, a heterojunction structure, a regulating layer 205, a gate contact layer 206, a hole absorption layer 207 and a metal electrode 103; The substrate layer 201 serves as a physical support base for the device, provides mechanical stability, and provides a basis for lattice matching for the subsequent epitaxial growth of the semiconductor layer. In this embodiment, the substrate layer 201 is selected from one or more stacked structures of Si, Al2O3, HfO2, Ga2O3, CrO, or MgO; The buffer layer 202 is provided on the substrate layer 201 to reduce the lattice mismatch and thermal expansion difference between the substrate layer 201 and the upper semiconductor material, thereby suppressing the generation of interface defects. In this embodiment, the buffer layer 202 is one of SiC, AlN, GaN or AlGaN. The heterojunction structure includes a first semiconductor layer 203 and a second semiconductor layer 204, and a heterojunction is formed between the first semiconductor layer 203 and the second semiconductor layer 204. The heterojunction structure spontaneously forms a 2DEG at the interface through the difference in the interface energy bands of the two different semiconductor materials, providing a high-mobility conductive channel for the device. The first semiconductor layer 203, the second semiconductor layer 204, the control layer 205 and the gate contact layer 206 are all Group III-V compound semiconductors, and the material composition or type of the first semiconductor layer 203 and the second semiconductor layer 204 are different, such as Al x Ga 1-x N / A y Ga 1-y N, where x and y are both in the range of 0 to 1. The first semiconductor layer 203 is one of GaN, InN, AlGaN, InGaN, InAlGaN or AlN; the second semiconductor layer 204 is one of GaN, InN, AlGaN, InGaN or AlN.

[0019] The modulation layer 205 is disposed on the second semiconductor layer 204, for adjusting the gate threshold voltage and enhancing the gate control ability. By means of doping (e.g. p-type doping GaN), a depletion region is formed to control the on and off of 2DEG.

[0020] The gate contact layer 206 is disposed on the modulation layer 205, which can protect the underlying semiconductor layer (modulation layer 205) from subsequent processes (e.g. etching, electrode preparation), and optimize the electric field distribution and heat dissipation.

[0021] The hole absorption layer 207 is disposed on one side of the modulation layer 205, which contains fixed negative charge centers for absorbing holes and inhibiting the negative impact of the modulation layer on 2DEG. In this embodiment, the hole absorption layer 207 is an n-type doped semiconductor layer, and the negative charge center is composed of fixed negative charges after the donor doping ions are ionized. By introducing electrons to form donor energy levels in the forbidden band, the ionization leaves behind negatively charged ions, forming negative charge centers, achieving the function of the hole absorption layer. When holes are injected, the hole absorption layer can absorb these holes to prevent their impact on the formation of 2DEG, while maintaining neutrality in the non-working state and not interfering with the normal operation of the device.

[0022] The metal electrode 103 is disposed on the gate contact layer 206 to achieve electrical connection and control of the device. In this embodiment, the material of the metal electrode 103 is selected from one of titanium, gold, nickel, platinum, rhenium, tungsten, silver, aluminum, titanium, molybdenum or indium.

[0023] In this embodiment, the second semiconductor layer 204 has a first ohmic contact electrode 101 and a second ohmic contact electrode 102 at both ends, and the metal electrode 103 is located between the first ohmic contact electrode 101 and the second ohmic contact electrode 102. The first ohmic contact electrode 101 and the second ohmic contact electrode 102 serve as the source and drain of the device, respectively, providing low-resistance current input and output paths. The electrode material of the first ohmic contact 101 and the second ohmic contact 102 includes one of gold, silver, aluminum, titanium, platinum, or indium.

[0024] The first insulating layer 301 is arranged between the first ohmic contact electrode 101 and the regulating layer 205, the second insulating layer 302 is arranged between the hole absorption layer 207 and the second ohmic contact electrode 102, and the hole absorption layer 207 is located between the second insulating layer 302 and the regulating layer 205. The first insulating layer 301 isolates the gate metal electrode 103 and the regulating layer 205, prevents the leakage current and optimizes the electric field distribution. The second insulating layer 302 isolates the hole absorption layer 207 and the second ohmic contact electrode 102, avoids the electrical interference between the hole absorption layer and the electrode. In general, in the embodiment, the hole absorption layer 207 captures the holes through the negative charge center, the second insulating layer 302 further isolates the hole absorption layer and the drain electrode, and prevents the leakage. Meanwhile, the first insulating layer 301 optimizes the gate electric field and improves the threshold voltage stability. Preferably, the first insulating layer 301 and the second insulating layer 302 are composed of one or more of Si3N4, SiN x , HfO2, Ga2O3, CrO, AlN, SiO2, Al2O3, TiO2, MgO, MnO and multi-element compound insulating materials AlHfO x , HfSiON.

[0025] The working principle of the scheme is that, in the device, a hole absorption layer 207 is arranged on the side of the regulating layer 205 and the heterojunction structure, so as to regulate the injection behavior of the holes and improve the formation condition of the 2DEG. The hole absorption layer 207 is an n-type doped semiconductor layer, which contains stable negative charge centers inside, can absorb the holes injected from the regulating layer 205 in the on state of the device, thereby reducing the accumulation of the holes near the interface of the heterojunction structure, and avoiding the adverse effects on the 2DEG density and distribution.

[0026] The hole absorption layer 207 effectively shields the downward diffusion path of the side hole by forming a built-in electric field or introducing donor state ionized charges, so that the 2DEG can be stably formed at the heterojunction interface of the heterojunction structure (AlGaN / GaN) and maintain a high carrier concentration. In addition, in the non-conduction or static state of the device, the hole absorption layer remains electrically neutral, does not cause additional leakage or parasitic effects, and ensures the static stability of the device.

[0027] Through the introduction of the structure, not only the gate control ability of the device is effectively improved, but also the adverse effects of the regulating layer 205 on the formation of the 2DEG are significantly reduced, thereby improving the on-state conduction ability and overall performance of the device.

[0028] In addition, the application also provides a preparation process of the heterojunction device with the hole absorption layer, which comprises the following steps: S1: sequentially depositing a buffer layer 202 and a first semiconductor layer 203 on a substrate layer 201 through organic chemical deposition (MOCVD); S2: depositing a second semiconductor layer 204 on the first semiconductor layer 203 by means of organic chemical deposition (MOCVD), atomic layer epitaxial deposition (ALD) or molecular beam epitaxial deposition (MBE) to form a heterojunction structure; S3: ultrasonic cleaning the Al x Ga 1-x N / GaN heterojunction with alcohol, acetone and deionized water respectively, and then blowing dry with nitrogen, and then performing ion etching with BCl3 gas to form an ohmic contact region, and then forming an ohmic contact electrode by means of electron beam evaporation, and then performing rapid annealing at 850°C in a N2 atmosphere for about 30 seconds; S4: depositing a regulating layer 205 and a gate contact layer 206 on the heterojunction structure by means of organic chemical deposition (MOCVD), and then performing etching; S5: forming a metal electrode 103 on the gate contact layer 206 by means of electron beam evaporation; S6: depositing an n-type doped Si layer as a hole absorption layer 207 on the regulating layer 205 side of the heterojunction structure by means of organic chemical deposition (MOCVD) or atomic layer epitaxial deposition (ALD), and then performing etching; In step S6, a layer of Si material is selectively deposited on the surface of the Al x Ga 1-x N layer along the gate sidewall region by means of organic chemical deposition (MOCVD), atomic layer epitaxial deposition (ALD) or other thin film technology, for forming a hole absorption layer, and after deposition, the Si layer is patterned by means of reactive ion etching, and only the structure layer in the target region is reserved; S7: forming a first insulating layer 301 and a second insulating layer 302 with high dielectric constant (k>6) on the heterojunction structure by means of magnetron sputtering, plasma enhanced chemical vapor deposition or atomic layer epitaxial deposition (ALD), and then performing rapid annealing at 300-1200°C for 1-10 minutes, as shown in FIG. 3. ε r Figure 8

[0029] The above merely provides the preferred embodiments of the present application, but should not be used to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.​​

Claims

1. A heterojunction device having a hole absorption layer, characterized in that: include: substrate layer (201); a buffer layer (202), disposed on the substrate layer (201); A heterojunction structure comprises a first semiconductor layer (203) and a second semiconductor layer (204), wherein a heterojunction is formed between the first semiconductor layer (203) and the second semiconductor layer (204); A regulating layer (205) is provided on the second semiconductor layer (204) and is used to regulate the gate threshold voltage; A gate contact layer (206) is provided on the regulating layer (205); A hole absorption layer (207), located on one side of the control layer (205), comprises a fixed negative charge center for absorbing holes and suppressing the negative impact of the control layer (205) on the two-dimensional electron gas; A metal electrode (103) is provided on the gate contact layer (206) and is used for electrical connection and control.

2. The heterojunction device with a hole absorption layer according to claim 1, wherein: The second semiconductor layer (204) has a first ohmic contact electrode (101) and a second ohmic contact electrode (102) at both ends, respectively; the metal electrode (103) is located between the first ohmic contact electrode (101) and the second ohmic contact electrode (102).

3. The heterojunction device with a hole absorption layer according to claim 2, wherein: A first insulating layer (301) is provided between the first ohmic contact electrode (101) and the regulating layer (205), a second insulating layer (302) is provided between the hole absorption layer (207) and the second ohmic contact electrode (102), and the hole absorption layer (207) is located between the second insulating layer (302) and the regulating layer (205).

4. The heterojunction device with a hole absorption layer according to claim 1, wherein: The hole absorption layer (207) is an n-type doped semiconductor layer, and the negative charge center is composed of fixed negative charges after donor doping and ionization.

5. The heterojunction device with a hole absorption layer according to claim 1, wherein: The substrate layer (201) is selected from one or more superimposed structures of Si, Al2O3, HfO2, Ga2O3, CrO or MgO.

6. The heterojunction device having a hole absorption layer according to claim 1, wherein: The buffer layer (202) is one of SiC, AlN, GaN or AlGaN.

7. The heterojunction device having a hole absorption layer according to claim 1, wherein: The first semiconductor layer (203), the second semiconductor layer (204), the regulating layer (205) and the gate contact layer (206) are all Group III-V compound semiconductors, and the first semiconductor layer (203) and the second semiconductor layer (204) have different material components or types.

8. The heterojunction device having a hole absorption layer according to claim 1, wherein: The first semiconductor layer (203) is one of GaN, InN, AlGaN, InGaN, InAlGaN or AlN; and the second semiconductor layer (204) is one of GaN, InN, AlGaN, InGaN or AlN.

9. A process for preparing a heterojunction device having a hole absorption layer according to any one of claims 1 to 8, characterized in that: The following steps are involved: S1: depositing a buffer layer (202) and a first semiconductor layer (203) in sequence on a substrate layer (201) by organic chemical deposition; S2: depositing a second semiconductor layer (204) on the first semiconductor layer (203) by organic chemical deposition, atomic layer epitaxial deposition, or molecular beam epitaxial deposition to form a heterojunction structure; S3: Al was purified by using alcohol, acetone and deionized water. x Ga 1-x The N / GaN heterojunction was ultrasonically cleaned, dried with nitrogen, and then ion-etched with BCl3 gas to form an ohmic contact area. The ohmic contact electrode was grown by electron beam evaporation and rapidly annealed in a CN2 atmosphere at 850° for about 30 seconds. S4: depositing a control layer (205) and a gate contact layer (206) on the heterojunction structure by organic chemical deposition, and performing etching; S5: forming a metal electrode (103) on the gate contact layer (206) by electron beam evaporation; S6: depositing an n-type doped Si layer as a hole absorption layer (207) on the side of the control layer (205) by organic chemical deposition or atomic layer epitaxial deposition on the heterojunction structure, and etching; S7: forming a first insulating layer (301) and a second insulating layer (302) with a high dielectric constant on the heterojunction structure by magnetron sputtering, plasma enhanced chemical vapor deposition or atomic layer epitaxial deposition, and performing rapid annealing at 300-1200° C. for 1-10 minutes.

10. The process for preparing a heterojunction device with a hole absorption layer according to claim 9, wherein: In step S6, at A1 x Ga 1-x On the surface of the N layer, along the gate sidewall area, a layer of Si material is selectively deposited by organic chemical deposition, atomic layer epitaxial deposition or other thin film technology to form a hole absorption layer. After deposition, the Si layer is patterned by reactive ion etching method to retain only the structural layer in the target area.

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