Insulated gate field effect transistor and preparation method thereof

Abstract

The embodiment of the invention provides an insulated gate field effect transistor. The insulated gate field effect transistor comprises a semiconductor layer, a gate oxide layer and a gate layer which are sequentially stacked along a first direction, the semiconductor layer is provided with a drift layer, a first doping type semiconductor layer and a second doping type semiconductor layer; the drift layer is provided with a first sub-region which is located on the side, away from the gate layer, of the gate oxide layer. The doping type of the second doping type semiconductor layer is the same as that of the drift layer and is different from that of the first doping type semiconductor layer; the insulated gate field effect transistor further comprises a first functional layer. The gate oxide layer is provided with a first surface in contact with the gate layer. The first functional layer is arranged between the first surface and the semiconductor layer; and the orthographic projection of the first functional layer on the semiconductor layer is located in the first sub-region. According to the insulated gate field effect transistor and the preparation method thereof provided by the embodiment of the invention, the stability of the insulated gate field effect transistor can be improved while the on-resistance is not influenced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to an insulated gate field effect transistor and a preparation method thereof. BACKGROUND

[0002] The MOS (Metal-Oxide-Semiconductor) insulated gate field effect transistor, also known as a metal-oxide-semiconductor field effect transistor, has higher input impedance than a junction field effect transistor, and has a simple manufacturing process, flexible and convenient use, and is very conducive to high integration, thus being widely concerned and researched by people. Compared with a Si MOSFET of the same power level, the SiC MOSFET has a significantly reduced on-resistance and switching loss, is suitable for a higher working frequency, and has greatly improved high-temperature stability due to its high-temperature working characteristics. However, because silicon carbide has better resistivity, the current of the SiC MOSFET in the on state is mainly concentrated in the region close to the channel surface, which increases the electric field intensity in the region below the gate of the SiC MOSFET, and the characteristics and manufacturing process of the silicon carbide material itself also cause the region below the gate of the SiC MOSFET to have a relatively large electric field intensity, thereby affecting the reliability of the SiC MOSFET. At present, how to take corresponding measures to reduce the potential breakdown risk and improve the stability of the device in response to the large electric field intensity below the gate of the SiC MOSFET has become a problem to be solved in the industry. SUMMARY

[0003] Therefore, to overcome at least part of the problems in the prior art, embodiments of the present application provide an insulated gate field effect transistor and a preparation method thereof, which can improve the stability of the insulated gate field effect transistor without affecting the on-resistance.

[0004] One embodiment of the present application provides an insulated gate field effect transistor, comprising a semiconductor layer, a gate oxide layer, and a gate layer which are sequentially stacked along a first direction; the semiconductor layer has a drift layer with a first sub-region located on a side of the gate oxide layer away from the gate layer, a first doped semiconductor layer located on an end of the drift layer close to the gate oxide layer, the first doped semiconductor layer comprising a second sub-region and a third sub-region which are separately located on opposite sides of the first sub-region, a second doped semiconductor layer comprising a fourth sub-region and a fifth sub-region, the fourth sub-region being surrounded by the second sub-region and exposed outside the second sub-region on a surface of the gate oxide layer close to the fourth sub-region, the fifth sub-region being surrounded by the third sub-region and exposed outside the third sub-region on a surface of the gate oxide layer close to the fifth sub-region, the second doped semiconductor layer having the same doping type as the drift layer and different from the first doped semiconductor layer, the first sub-region, the second sub-region, the third sub-region, the fourth sub-region, and the fifth sub-region all being connected to the gate oxide layer; the insulated gate field effect transistor further comprises a first functional layer, the gate oxide layer has a first surface in contact with the gate layer, the first functional layer is arranged between the first surface and the semiconductor layer, and a normal projection of the first functional layer on the semiconductor layer is located in the first sub-region.

[0005] In one embodiment, the first functional layer is located between the gate oxide layer and the first sub-region.

[0006] In one embodiment, the material of the first functional layer is the same as that of the gate oxide layer.

[0007] In one embodiment, the first functional layer comprises a first material layer and a second material layer which are sequentially stacked along the first direction, the first material layer is the same as the material of the gate oxide layer, and the second material layer is the same as the material of the gate layer.

[0008] In one embodiment, the gate oxide layer has a first oxide layer and a second oxide layer which are sequentially stacked along the first direction, and the first functional layer is located between the first oxide layer and the second oxide layer.

[0009] In one embodiment, the material of the first functional layer is the same as that of the gate layer.

[0010] In one embodiment, the first functional layer has a higher electric field strength than the gate oxide layer.

[0011] In one embodiment, the thickness of the first functional layer along the first direction is 100-1000 angstroms.

[0012] The embodiment of the present application also provides a preparation method of an insulated gate field effect transistor, comprising: sequentially forming a semiconductor layer, a gate oxide layer and a gate electrode layer; the semiconductor layer comprises a drift layer, the drift layer comprises a first sub-region, the first sub-region is located on a side of the gate oxide layer away from the gate electrode layer; a first doped semiconductor layer is located on an end of the drift layer close to the gate oxide layer; the first doped semiconductor layer comprises a second sub-region and a third sub-region separately arranged on opposite sides of the first sub-region; a second doped semiconductor layer comprises a fourth sub-region and a fifth sub-region; the fourth sub-region is surrounded by the second sub-region and the fourth sub-region is exposed outside the second sub-region close to a surface of the gate oxide layer; the fifth sub-region is surrounded by the third sub-region and the third sub-region is exposed outside the third sub-region close to the surface of the gate oxide layer; the second doped semiconductor layer has the same doping type as the drift layer and has a different doping type from the first doped semiconductor layer; the first sub-region, the second sub-region, the third sub-region, the fourth sub-region and the fifth sub-region are all connected with the gate oxide layer; a first functional layer is formed after the semiconductor layer is formed and before the gate oxide layer is formed, and a normal projection of the first functional layer on the semiconductor layer is located in the first sub-region.

[0013] In one embodiment, the sequentially forming the semiconductor layer, the gate oxide layer and the gate electrode layer specifically comprises: forming a first oxide layer on the semiconductor layer; the forming the first functional layer comprises: forming a functional material layer of the first functional layer on the first oxide layer, and etching the functional material layer to obtain the first functional layer; the sequentially forming the semiconductor layer, the gate oxide layer and the gate electrode layer further comprises: forming a second oxide layer on the first functional layer, so that the second oxide layer covers the first functional layer and the first oxide layer; the first oxide layer and the second oxide layer jointly constitute the gate oxide layer.

[0014] The above embodiment of the present application has at least one or more of the following beneficial effects: by arranging the first functional layer between the first surface of the gate oxide layer and the drift layer, the structural thickness between the gate electrode layer and the first sub-region can be increased through the first functional layer, so as to enhance the overall strength of the layers below the gate electrode layer. And by arranging the normal projection of the first functional layer on the drift layer in the first sub-region of the drift layer, the first functional layer will not cover the channel, so as to enhance the stability of the insulated gate field effect transistor without affecting the on-resistance Ron as much as possible. BRIEF DESCRIPTION OF DRAWINGS

[0015] The specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0016] Figure 1 A structure diagram of an insulated gate field effect transistor provided by an embodiment of the present application is shown.

[0017] Figure 2 A structure diagram of an insulated gate field effect transistor provided by another embodiment of the present application is shown.

[0018] Figure 3 A structure diagram of an insulated gate field effect transistor provided by yet another embodiment of the present application is shown.

[0019] Figure 4 A structure diagram corresponding to a step of a preparation method of an insulated gate field effect transistor provided by an embodiment of the present application is shown.

[0020] Figure 5 A structure diagram corresponding to another step of a preparation method of an insulated gate field effect transistor provided by an embodiment of the present application is shown.

[0021] Figure 6 A structure diagram corresponding to a step of a preparation method of an insulated gate field effect transistor provided by an embodiment of the present application is shown.

[0022] Figure 7 A structure diagram corresponding to another step of a preparation method of an insulated gate field effect transistor provided by an embodiment of the present application is shown.

[0023]

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] 100, insulated gate field effect transistor; 10, semiconductor layer; 11, drift layer; 111, first sub-region; 12, first doped semiconductor layer; 121, second sub-region; 122, third sub-region; 13, second doped semiconductor layer; 131, fourth sub-region; 132, fifth sub-region; 20, gate oxide layer; 201, first surface; 202, second surface; 21, first oxide layer; 22, second oxide layer; 30, gate layer; 40, first functional layer; 41, first material layer; 42, second material layer; 401, functional material layer. DETAILED DESCRIPTION

[0025] In order to make the above objectives, features and advantages of the present application more apparent, specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0026] In order to make ordinary skilled in the art better understand the technical solutions of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work should belong to the scope of protection of the present application.

[0027] It should be noted that the terms "first", "second" and the like in the description and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the terms thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in other than the order illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a list of steps or units need not be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to such processes, methods, products or devices.

[0028] It should also be noted that the division of the plurality of embodiments in the present application is only for the convenience of description, and should not constitute a special limitation. The features in various embodiments can be combined with each other and mutually quoted without contradiction.

[0029] With reference to Figure 1 An embodiment of the present application provides an insulated gate field effect transistor 100, comprising a semiconductor layer 10, a gate oxide layer 20 and a gate layer 30 which are sequentially stacked along a first direction. The semiconductor layer 10 has a drift layer 11, a first doped semiconductor layer 12 and a second doped semiconductor layer 13. The drift layer 11 has a first sub-region 111, which is located on the side of the gate oxide layer 20 away from the gate layer 30, such as Figure 1In the orientation shown, the first sub-region 111 is located below the gate oxide layer 20. The first doped semiconductor layer 12 is located at one end of the drift layer 11 near the gate oxide layer 20. The first doped semiconductor layer 12 includes a second sub-region 121 and a third sub-region 122, respectively, located on opposite sides of the first sub-region 111. The second doped semiconductor layer 13 includes a fourth sub-region 131 and a fifth sub-region 132. The fourth sub-region 131 is surrounded by the second sub-region 121, and the surface of the fourth sub-region 131 near the gate oxide layer 20 is exposed outside the second sub-region 121. The fifth sub-region 132 is surrounded by the third sub-region 122, and the surface of the third sub-region 122 near the gate oxide layer 20 is exposed outside the third sub-region 122. The second doped semiconductor layer 13 has the same doping type as the drift layer 11, but a different doping type from the first doped semiconductor layer 12. The first sub-region 111, the second sub-region 121, the third sub-region 122, the fourth sub-region 131, and the fifth sub-region 132 are all connected to the gate oxide layer 20. The insulated gate field effect transistor 100 further includes a first functional layer 40. The gate oxide layer 20 has a first surface 201 in contact with the gate layer 30. The first functional layer 40 is disposed between the first surface 201 and the semiconductor layer 10. The orthographic projection of the first functional layer 40 on the semiconductor layer 10 is located within the first sub-region 111.

[0030] like Figure 1 In the orientation shown, the first direction is from bottom to top. The drift layer 11 may also be referred to as an EPI layer or an epitaxial layer. The insulated gate field effect transistor 100 may be classified as an N-type field effect transistor or a P-type field effect transistor based on whether the doping type of the drift layer 11 semiconductor is N-type doped or P-type doped. For example, if the drift layer 11 is N-type doped, the insulated gate field effect transistor 100 is an N-type field effect transistor. When the drift layer 11 is N-type doped, the second doped semiconductor layer 13 is also N-type doped, and the first doped semiconductor layer 12 is P-type doped. When the drift layer 11 is P-type doped, the second doped semiconductor layer 13 is also P-type doped, and the first doped semiconductor layer 12 is N-type doped.

[0031] The gate oxide layer 20 may be made of silicon oxide, for example. Figure 1The gate oxide layer 20 is shown covering the first sub-region 111 and extending towards both sides of the first sub-region 111 to connect with the second sub-region 121, the third sub-region 122, the fourth sub-region 131 and the fifth sub-region 132. The fourth sub-region 131 and the fifth sub-region 132 form the source of the insulated gate field effect transistor 100. The gate layer 30, for example, a poly layer, forms the gate of the insulated gate field effect transistor 100. The insulated gate field effect transistor 100 is further provided with a substrate layer on the side of the drift layer 11 away from the gate oxide layer 20, and a drain layer below the substrate layer away from the drift layer 11. The insulated gate field effect transistor 100 can be a silicon carbide MOS, the substrate layer is for example a silicon carbide substrate, and the drift layer 11 is an N-type doped silicon carbide epitaxial layer. The drain has the same electrical property as the drift layer 11, for example, when the drift layer 11 is N-type doped, the drain is also an N electrode.

[0032] The first functional layer 40 is located between the first surface 201 and the semiconductor layer 10, which means that the first functional layer 40 is not higher than the gate oxide layer 20, i.e. the first functional layer 40 is located on the inner side of the gate oxide layer 20 close to the semiconductor layer 10, but not on the outer side of the gate oxide layer 20 away from the semiconductor layer 10. For example, referring to Figure 1 , the first functional layer 40 can be completely located below the gate oxide layer 20, i.e. the first functional layer 40 is located between the second surface 202 of the gate oxide layer 20 and the first sub-region 111, at this time the first functional layer 40 is in contact with the first sub-region 111. Or in another embodiment, referring to Figure 2 , the first functional layer 40 can be located inside the gate oxide layer 20, neither in contact with the semiconductor layer 10 nor in contact with the gate layer 30. The orthographic projection of the first functional layer 40 on the semiconductor layer 10 is within the first sub-region 111, i.e. the first functional layer 40 does not extend towards both sides to cover the second sub-region 121 and the third sub-region 122, i.e. the first functional layer 40 does not cover the channel.

[0033] In the related art, taking silicon carbide MOS as an example, the electric field intensity below the gate is large due to the material characteristics and manufacturing process. The above embodiments of the present application increase the material thickness between the corresponding gate layer 30 and the first sub-region 111 by arranging the first functional layer 40. For example, the thickness of the gate oxide layer 20 is about 600 angstroms, and the thickness of the first functional layer 40 is 300 angstroms. In the region where the first functional layer 40 is arranged, the thickness between the gate layer 30 below and the first sub-region 111 (or the semiconductor layer 10) is 900 angstroms. Therefore, the arrangement of the first functional layer 40 can enhance the overall strength of the layers below the gate layer 30, and has better breakdown resistance. In addition, the first functional layer 40 does not cover the channel. For the region where the first functional layer 40 is not arranged, the thickness between the gate layer 30 below and the semiconductor layer 10 is 600 angstroms. The stability of the insulated gate field effect transistor 100 can be improved without affecting the on-resistance Ron of the first functional layer 40.

[0034] In some embodiments, the material of the first functional layer 40 is the same as that of the gate oxide layer 20. That is, the first functional layer 40 can be a silicon oxide material. The material is easy to obtain by using the material and process used in the existing field effect transistor process, which can ensure lower production cost and difficulty. The thickness of the first functional layer 40 along the first direction can be 100-1000 angstroms (A) 1 angstrom = 10 -10 meters, and more specifically, 300-600 angstroms.

[0035] In some embodiments, referring to Figure 3 , the first functional layer 40 includes a first material layer 41 and a second material layer 42 stacked in sequence along the first direction. The first material layer 41 is the same as the material of the gate oxide layer 20, and the second material layer 42 is the same as the material of the gate layer 30. For example, the first material layer 41 is a silicon oxide material, and the second material layer 42 is a polysilicon material. On the one hand, the first material layer 41 and the second material layer 42 are selected from the material and process used in the existing field effect transistor process, which is easy to obtain and can ensure lower production cost and difficulty. On the other hand, the arrangement of the first functional layer 40 as the first material layer 41 and the second material layer 42 in a stacked structure can realize a double-gate structure. In actual application, the second material layer 42 can be floating or connected to the Source (ground) of the insulated gate field effect transistor 100, which can reduce the Cgd junction capacitance. Therefore, the above arrangement can improve the reliability while reducing the Cgd junction capacitance. The thickness of the first material layer 41 is, for example, 600-1000 angstroms, such as 600 angstroms, 800 angstroms, 1000 angstroms, etc. The thickness of the second material layer 42 is, for example, 3000-6000 angstroms, such as 3000 angstroms, 3500 angstroms, 3700 angstroms, 4000 angstroms, 4500 angstroms, 5000 angstroms, 6000 angstroms, etc.

[0036] In some embodiments, referring to Figure 2 , the gate oxide layer 20 has a first oxide layer 21 and a second oxide layer 22 stacked in sequence along the first direction. The first functional layer 40 is located between the first oxide layer 21 and the second oxide layer 22. The first oxide layer 21 and the second oxide layer 22 can have the same thickness, for example, 300-1000 angstroms. The first functional layer 40 is arranged between the first oxide layer 21 and the second oxide layer 22, so that the first functional layer 40 is not in contact with the first sub-region 111, and the limitation of the material of the first functional layer 40 is reduced.

[0037] In some embodiments, the material of the first functional layer 40 between the first oxide layer 21 and the second oxide layer 22 is the same as the material of the gate layer 30, so that an SGT (split gate) structure is formed in the insulated gate field effect transistor 100. In actual application, the first functional layer 40 can be floating or connected to the Source of the insulated gate field effect transistor 100, which can reduce the Cgd junction capacitance. Therefore, the above arrangement can enhance the reliability while reducing the Cgd junction capacitance. The thickness of the first functional layer 40 is 3000-6000 angstroms, for example, 3000 angstroms, 3500 angstroms, 3700 angstroms, 4000 angstroms, 4500 angstroms, 5000 angstroms, 6000 angstroms, etc.

[0038] In some embodiments, for the structure shown in Figure 1 or Figure 2 , the first functional layer 40 has a higher electric field strength than the gate oxide layer 20. For example, the gate oxide layer 20 is a silicon oxide material, and the first functional layer 40 can be selected as Si3N4 (silicon nitride), which has a higher electric field strength than the silicon oxide material. The material itself can be used to improve the electric field strength while enhancing the thickness. In some embodiments, the thickness of the first functional layer 40 in the first direction is 100-1000 angstroms, more specifically, 300-600 angstroms, for example, 300 angstroms, 400 angstroms, 450 angstroms, 500 angstroms, 600 angstroms, etc.

[0039] Referring to Figures 4 to 7 , the present embodiment also provides a preparation method of an insulated gate field effect transistor, which can prepare the insulated gate field effect transistor 100 provided in the foregoing embodiments. The preparation method comprises:

[0040] S1: sequentially forming a semiconductor layer 10, a gate oxide layer 20 and a gate electrode layer 30; the semiconductor layer 10 has a drift layer 11, the drift layer 11 has a first sub-region 111, the first sub-region 111 is located on a side of the gate oxide layer 20 away from the gate electrode layer 30; a first doped semiconductor layer 12 is located on an end of the drift layer 11 close to the gate oxide layer 20; the first doped semiconductor layer 12 includes a second sub-region 121 and a third sub-region 122 arranged on opposite sides of the first sub-region 111; a second doped semiconductor layer 13 includes a fourth sub-region 131 and a fifth sub-region 132; the fourth sub-region 131 is surrounded by the second sub-region 121 and the surface of the fourth sub-region 131 close to the gate oxide layer 20 is exposed outside the second sub-region 121; the fifth sub-region 132 is surrounded by the third sub-region 122 and the surface of the fifth sub-region 132 close to the gate oxide layer 20 is exposed outside the third sub-region 122; the second doped semiconductor layer 13 has the same doping type as the drift layer 11 and has a different doping type from the first doped semiconductor layer 12; the first sub-region 111, the second sub-region 121, the third sub-region 122, the fourth sub-region 131 and the fifth sub-region 132 are all connected to the gate oxide layer 20;

[0041] S2: forming a first functional layer 40; the first functional layer 40 is formed after the forming step of the semiconductor layer 10 is completed and before the forming step of the gate oxide layer 20 is completed, and the orthographic projection of the first functional layer 40 on the semiconductor layer 10 is located in the first sub-region 111.

[0042] The specific description of the semiconductor layer 10, the gate oxide layer 20 and the gate electrode layer 30 can refer to the description of the aforementioned insulated gate field effect transistor 100. For example, step S1 includes a step S11 of forming the semiconductor layer 10, for example, forming the drift layer 11, the first doped semiconductor layer 12 and the second doped semiconductor layer 13 of the semiconductor layer 10 on the substrate layer by ion implantation. Step S1 also includes a step S12 of forming the gate oxide layer 20 on the semiconductor layer 10, and a step S13 of forming the gate electrode layer 30 on the gate oxide layer 20.

[0043] The step S2 is performed after the forming step of the semiconductor layer 10 is completed and before the forming step of the gate oxide layer 20, that is, the step S2 can be inserted between the step S11 and the step S12, or the step S2 can be inserted in the step S12. The first functional layer 40 can be formed by deposition and etching processes.

[0044] For example, the step S12 includes a step S121 of forming a first oxide layer 21 on the semiconductor layer 10; Figure 4 The step S2 specifically includes forming a functional material layer 401 of the first functional layer 40 on the first oxide layer 21 Figure 5), and etching the functional material layer 401 to obtain the first functional layer 40 Figure 6

[0045] The step S12 further comprises a step S122 of forming a second oxide layer 22 on the first functional layer 40, so that the second oxide layer 22 covers the first functional layer 40 and the first oxide layer 21; the first oxide layer 21 and the second oxide layer 22 together constitute the gate oxide layer 20 Figure 7 ). The step execution sequence of the preparation method of the insulated gate field effect transistor is S11→S121→S2→S122→S13. The insulated gate field effect transistor 100 as shown in Figure 2 In the embodiment, the functional material layer 401 can be the same material as that of the gate oxide layer 20, or the same material as that of the gate layer 30, or a material with higher electric field strength than that of the gate oxide layer 20. The step sequence described above makes the selection of the functional material layer 401 less restricted, and the existing material can be used in the traditional process, so that the material is easy to obtain, and the preparation process is relatively simple.

[0046] Of course, in other embodiments, the step S2 specifically comprises forming a functional material layer 401 of the first functional layer 40 on the semiconductor layer 10, and etching the functional material layer 401 to obtain the first functional layer 40; the step S12 specifically comprises forming a gate oxide layer 20 on the semiconductor layer 10 and the first functional layer 40, so that the gate oxide layer 20 covers the first functional layer 40 and part of the semiconductor layer 10. The step execution sequence of the preparation method of the insulated gate field effect transistor is S11→S2→S12→S13, and the insulated gate field effect transistor 100 as shown in Figure 1 ) can be obtained. When the first functional layer 40 comprises a first material layer 41 and a second material layer 42, the insulated gate field effect transistor 100 as shown in Figure 3 The step sequence in the embodiment can make the gate oxide layer 20 more integral and better in quality, and enhance the stability of the product.

[0047] The preparation method of the insulated gate field effect transistor provided in the embodiments of the present application can be used to prepare the insulated gate field effect transistor 100 in the foregoing embodiments, and has the same effects as the insulated gate field effect transistor 100, which will not be described herein.

[0048] ​The above merely describes preferred embodiments of the present application, and is not intended to limit the present application in any form. Although the present application has been disclosed with the preferred embodiments as above, it is not intended to limit the present application. Any person skilled in the art, without departing from the technical solution of the present application, can make some changes or modifications to the above disclosed technical content to obtain equivalent embodiments with equivalent changes. However, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the technical solution of the present application, shall still fall within the scope of the technical solution of the present application.

Claims

1. An insulated gate field effect transistor, characterized in that: The invention comprises a semiconductor layer, a gate oxide layer, and a gate layer stacked in sequence along a first direction; the semiconductor layer has: a drift layer, the drift layer having a first sub-region, the first sub-region being located on a side of the gate oxide layer away from the gate layer; a first doped semiconductor layer located at one end of the drift layer close to the gate oxide layer; the first doped semiconductor layer includes a second sub-region and a third sub-region located on opposite sides of the first sub-region; The second doped semiconductor layer includes a fourth sub-region and a fifth sub-region; the fourth sub-region is surrounded by the second sub-region and a surface of the fourth sub-region close to the gate oxide layer is exposed outside the second sub-region; The fifth sub-region is surrounded by the third sub-region, and a surface of the third sub-region close to the gate oxide layer is exposed outside the third sub-region; The second doped semiconductor layer has the same doping type as the drift layer and a different doping type from the first doped semiconductor layer; The first sub-region, the second sub-region, the third sub-region, the fourth sub-region and the fifth sub-region are all connected to the gate oxide layer; The insulated gate field effect transistor also includes a first functional layer, the gate oxide layer has a first surface in contact with the gate layer; the first functional layer is arranged between the first surface and the semiconductor layer; and the orthographic projection of the first functional layer on the semiconductor layer is located in the first sub-region.

2. The insulated gate field effect transistor according to claim 1, wherein: The first functional layer is located between the gate oxide layer and the first sub-region.

3. The insulated gate field effect transistor according to claim 2, wherein: The material of the first functional layer is the same as that of the gate oxide layer.

4. The insulated gate field effect transistor according to claim 2, wherein: The first functional layer includes a first material layer and a second material layer sequentially stacked along the first direction. The first material layer is made of the same material as the gate oxide layer, and the second material layer is made of the same material as the gate layer.

5. The insulated gate field effect transistor according to claim 1, wherein: The gate oxide layer includes a first oxide layer and a second oxide layer sequentially stacked along a first direction; and the first functional layer is located between the first oxide layer and the second oxide layer.

6. The insulated gate field effect transistor according to claim 5, wherein: The material of the first functional layer is the same as that of the gate layer.

7. The insulated gate field effect transistor according to claim 1, wherein: The first functional layer has a higher electric field strength resistance than the gate oxide layer.

8. The insulated gate field effect transistor according to claim 7, wherein: The thickness of the first functional layer in the first direction is 100 to 1000 angstroms.

9. A method for preparing an insulated gate field effect transistor, characterized in that: The process includes sequentially forming a semiconductor layer, a gate oxide layer, and a gate layer; the semiconductor layer includes a drift layer, the drift layer includes a first sub-region, the first sub-region is located on a side of the gate oxide layer away from the gate layer; a first doped semiconductor layer is located at an end of the drift layer close to the gate oxide layer; the first doped semiconductor layer includes a second sub-region and a third sub-region respectively disposed on opposite sides of the first sub-region; and the second doped semiconductor layer includes a fourth sub-region and a fifth sub-region; the fourth sub-region is surrounded by the second sub-region, and a surface of the fourth sub-region close to the gate oxide layer is exposed outside the second sub-region; The fifth sub-region is surrounded by the third sub-region, and a surface of the third sub-region close to the gate oxide layer is exposed outside the third sub-region; the second doped semiconductor layer has the same doping type as the drift layer and a different doping type from the first doped semiconductor layer; the first sub-region, the second sub-region, the third sub-region, the fourth sub-region, and the fifth sub-region are all connected to the gate oxide layer; The process of forming a first functional layer is as follows: forming the first functional layer after the step of forming the semiconductor layer is completed and before the step of forming the gate oxide layer is completed, and making the orthographic projection of the first functional layer on the semiconductor layer located within the first sub-region.

10. The method for preparing an insulated gate field effect transistor according to claim 9, wherein: The process of sequentially forming a semiconductor layer, a gate oxide layer and a gate layer specifically includes: forming a first oxide layer on the semiconductor layer; The step of forming the first functional layer includes: forming a functional material layer of the first functional layer on the first oxide layer, and etching the functional material layer to obtain the first functional layer; The process of sequentially forming a semiconductor layer, a gate oxide layer, and a gate layer further includes: forming a second oxide layer on the first functional layer so that the second oxide layer covers the first functional layer and the first oxide layer; the first oxide layer and the second oxide layer together constitute the gate oxide layer.

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