An AI model-based power domain anti-hanging simulation verification method and system

Abstract

The application belongs to the chip field and discloses a power domain anti-hanging simulation verification method and system based on an AI model. An access relationship table of a power domain is acquired. A register mapping file of a power management unit (PMU) is parsed through an automatic script, and register configuration information of each power domain is extracted. Signal waveform data in a cross-domain access process between different power domains is collected, and the signal waveform contains timing constraint information. The register configuration information, the signal waveform data and the access relationship table are input into a pre-trained AI model, and register write sequences corresponding to each power domain and verification check logic are generated through the AI model. Based on the access relationship table, all possible access paths between power domains are traversed. For each access path, the register write sequences and the verification check logic generated by the AI model are called to perform joint simulation verification on a simulation platform. The application can realize automatic verification of power domain anti-hanging and improve verification efficiency.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of chips, and particularly relates to a power domain anti-hanging simulation verification method and system based on an AI model. BACKGROUND

[0002] With the continuous progress of integrated circuit technology, the integration and complexity of modern chips, especially 5G and AI chips, have increased dramatically. They usually contain multiple functional modules. In order to effectively manage power consumption, chips use a design architecture called multi-power domain. Under this architecture, the chip is divided into multiple independent power domains, and each domain can independently perform power-on, power-down, and switching of various low-power states (such as sleep).

[0003] However, this architecture introduces unprecedented verification challenges. The power states of various power domains are not completely independent, but there are complex dependencies and interaction protocols. The state switching (such as power-down) of one power domain will directly affect the access behavior of other domains. If not handled properly, for example, when one domain is in a power-down state and another domain tries to access it, or the timing of power state switching does not meet the requirements, it is easy to cause the entire system to hang, that is, the chip's partial or all functions stop responding, causing catastrophic consequences. Therefore, fully verifying the power management logic to prevent hanging is a key link to ensure the correctness and reliability of chip functions.

[0004] Currently, the industry generally uses traditional verification methods that are highly dependent on manual work when performing power domain anti-hanging verification. The main process and inherent shortcomings are as follows:

[0005] Manual analysis and design understanding: Verification engineers need to manually read and analyze thousands of pages of chip design specifications and register manuals to understand the relationships between various power domains, the functions of each register in the power management unit (PMU), and the handshake protocol for inter-domain communication.

[0006] Manual test case writing: Based on the above understanding, engineers use their personal experience to derive and write test scenarios, and manually write a large amount of test code to configure PMU registers, simulate various power state switching and inter-domain access.

[0007] Manual addition of check logic: Engineers need to manually write assertions and checker code and embed them into the simulation environment to monitor signal behavior and report errors when protocol violations occur.

[0008] Random test and manual debugging: usually supplemented with random test to stimulate potential errors. Once the hang or functional error is found in the simulation, the engineer needs to manually analyze the complex waveform chart to locate the root cause of the problem, which is extremely time-consuming.

[0009] The traditional method has low verification efficiency, the whole process is time-consuming and laborious, and manual operation is easy to introduce human error, which seriously slows down the project progress. Secondly, the coverage is insufficient, the experience of engineers is difficult to cover all extreme, complex cross-domain interaction scenarios, and traditional random test is difficult to systematically traverse all possible power state combinations and access paths, leaving verification blind spots and affecting chip quality. Moreover, due to high dependence on manpower and poor scalability, the verification quality is over-dependent on the experience of individual experts, and the knowledge is difficult to deposit and reuse. With the continuous growth of chip complexity, the number of power domains is increasing, and the interaction relationship is exponentially complex, so the traditional manual method cannot meet the requirements.

[0010] Therefore, the industry urgently needs to fully verify the power management logic to prevent hang and ensure the correctness and reliability of the chip function. SUMMARY

[0011] The purpose of the present application is to improve the verification efficiency of power domain hang prevention. Therefore, in a first aspect, the present application provides an AI model-based power domain hang prevention simulation verification method, which comprises:

[0012] Obtain an access relationship table, which is used to represent the access relationship between different power domains;

[0013] Parse the register mapping file of the power management unit PMU through an automatic script to extract the register configuration information of each power domain;

[0014] Collect signal waveform data in the cross-domain access process between different power domains, which contains timing constraint information;

[0015] Input the register configuration information, signal waveform data and access relationship table into a pre-trained AI model to generate register write sequences and verification check logic corresponding to each power domain through the AI model;

[0016] Based on the access relationship table, traverse all possible access paths between power domains;

[0017] For each access path, call the register write sequence and verification check logic generated by the AI model to perform joint simulation verification on the simulation platform.

[0018] In a possible implementation, the register configuration information includes register address, bit field, reset value and access permission.

[0019] In a possible implementation, the signal waveform data in the process of collecting cross-domain access between different power domains includes:

[0020] The signal waveform data includes a wake-up request signal waveform sent by the PMU domain to the accessed power domain, a power enable signal waveform sent by the PMU domain, a power good signal waveform returned by the accessed power domain, a clock good signal waveform returned by the accessed power domain, a reset release signal waveform returned by the accessed power domain, and a wake-up confirmation signal waveform returned by the accessed power domain to the PMU domain.

[0021] In a possible implementation, the inputting of the register configuration information, the signal waveform data, and the access relationship table into the pre-trained AI model and the generation of the register write sequence and the verification check logic corresponding to each power domain by the AI model include:

[0022] The register configuration information, the signal waveform data, and the access relationship table are input into the pre-trained AI model, the register of the shutoff power domain is configured by the AI model, and the shutoff power domain is set to the power-off state.

[0023] The register of the uninterrupted power domain is configured, and the uninterrupted power domain is set to access the shutoff power domain.

[0024] The register of the shutoff power domain is configured, and the shutoff power domain is set to return an error response signal.

[0025] It is determined whether the access signal of the uninterrupted power domain is hung up, and if so, an error is reported.

[0026] It is determined whether the shutoff power domain returns an error response signal error resp, and if not, an error is reported.

[0027] In a possible implementation, the inputting of the register configuration information, the signal waveform data, and the access relationship table into the pre-trained AI model and the generation of the register write sequence and the verification check logic corresponding to each power domain by the AI model include:

[0028] The register configuration information, the signal waveform data, and the access relationship table are input into the pre-trained AI model, the register of the shutoff power domain is configured by the AI model, and the shutoff power domain is set to the power-on state.

[0029] The register of the uninterrupted power domain is configured, and the uninterrupted power domain is set to access the shutoff power domain.

[0030] It is determined whether the shutoff power domain returns a correct response signal OK resp, and if not, an error is reported.

[0031] In a possible implementation, the AI model is trained in the following manner:

[0032] The historical verification data includes historical register configuration information, historical signal waveforms, and an access relationship table.

[0033] The historical verification data and verification result labels are input into the AI model to be trained, the verification result labels including success result identifiers or failure result identifiers recorded in previous simulation or hardware testing, and failure causes.

[0034] Based on the verification result labels and the output of the AI model to be trained, the parameters of the AI model are adjusted until a trained AI model is obtained.

[0035] In a possible implementation, the method further includes:

[0036] The register write sequence is run on a simulation platform.

[0037] Based on the verification check logic, the simulation process is monitored in real time and it is determined whether real-time signal waveforms conform to expected timing relationships.

[0038] If not, a verification report is generated and output, the verification report including assertion violation information and error type classification.

[0039] In a second aspect, an AI model-based power domain anti-hanging simulation verification system is provided, and the system includes:

[0040] An acquisition module is configured to acquire an access relationship table, the access relationship table being used to represent access relationships between different power domains.

[0041] An analysis module is configured to parse a register mapping file of a power management unit (PMU) through an automatic script, and extract register configuration information of each power domain.

[0042] A collection module is configured to collect signal waveform data in a cross-domain access process between different power domains, the signal waveforms including timing constraint information.

[0043] A generation module is configured to input the register configuration information, signal waveform data, and access relationship table into a pre-trained AI model, and generate register write sequences and verification check logic corresponding to each power domain through the AI model.

[0044] A traversal module is configured to traverse all possible access paths between power domains based on the access relationship table.

[0045] A joint simulation module is configured to, for each access path, call the register write sequences and verification check logic generated by the AI model to perform joint simulation verification on a simulation platform.

[0046] In a third aspect, the present application provides a computer program product comprising instructions which, when executed on a computer, cause the computer to implement any of the above described methods.

[0047] In a fourth aspect, the present application provides a computer-readable storage medium having stored therein a computer program which, when executed by a processor, implements any of the above described methods.

[0048] In the embodiments of the present application, an access relationship table is acquired, the access relationship table being used to represent the access relationship between different power domains; a register mapping file of a power management unit (PMU) is parsed by an automatic script to extract register configuration information of each power domain; signal waveform data in a cross-domain access process between different power domains is collected, the signal waveform containing timing constraint information; the register configuration information, the signal waveform data and the access relationship table are input to a pre-trained AI model to generate register write sequences corresponding to each power domain and verification check logic by the AI model; based on the access relationship table, all possible access paths between power domains are traversed; for each access path, the register write sequences and the verification check logic generated by the AI model are called to perform joint simulation verification on a simulation platform. The automatic verification of the power domain anti-hanging can be realized, and the verification efficiency is improved. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1 A flowchart of a power domain anti-hanging simulation verification provided by the embodiments of the present application is shown;

[0050] Figure 2 An access relationship representation provided by the embodiments of the present application is shown;

[0051] Figure 3 An access logic relationship between power domains provided by the embodiments of the present application is shown;

[0052] Figure 4 Another flowchart of a power domain anti-hanging simulation verification provided by the embodiments of the present application is shown. DETAILED DESCRIPTION

[0053] The present application will be described in detail by embodiments below.

[0054] With the continuous progress of integrated circuit technology, the integration and complexity of modern chips, especially 5G and AI chips, have increased dramatically. Typically, a modern chip contains multiple functional modules. In order to effectively manage power consumption, the chip adopts a design architecture called Multi-Power Domain. Under this architecture, the chip is divided into multiple independent power domains, and each domain can independently perform power-on, power-down, and switching between various low-power states (such as sleep).

[0055] However, this architecture introduces unprecedented verification challenges. The power states of various power domains are not completely independent, but there are complex dependencies and interaction protocols. The state switching (such as power-down) of one power domain directly affects the access behavior of other domains. If not handled properly, for example, when one domain is in a power-down state and another domain tries to access it, or the timing of power state switching does not meet the requirements, it is easy to cause the entire system to hang, i.e., the chip's partial or full functionality stops responding, causing catastrophic consequences. Therefore, fully verifying the power management logic to prevent hanging is a key step to ensure the correctness and reliability of the chip's functionality.

[0056] Currently, the industry generally uses traditional verification methods that rely heavily on manual work when verifying power domain anti-hanging. The main process and inherent shortcomings are as follows:

[0057] Manual analysis and design understanding: Verification engineers need to manually read and analyze thousands of pages of chip design specifications and register manuals to understand the relationships between various power domains, the functions of each register in the Power Management Unit (PMU), and the handshake protocols for inter-domain communication.

[0058] Manual test case writing: Based on the above understanding, engineers use their personal experience to derive and write test scenarios, and manually write a large amount of test code to configure PMU registers, simulate various power state switching and inter-domain access.

[0059] Manual addition of checking logic: Engineers need to manually write assertions and checker code and embed them into the simulation environment to monitor signal behavior and report errors when protocol violations occur.

[0060] Dependence on random testing and manual debugging: Random testing is usually used to trigger potential errors. Once a hang or functional error is found in the simulation, engineers need to manually analyze complex waveforms to locate the root cause of the problem, which is extremely time-consuming.

[0061] The traditional method has low verification efficiency, the whole process is time-consuming and laborious, manual operation is prone to human error, and seriously slows down the project progress. Secondly, the coverage is insufficient, the experience of engineers is difficult to cover all extreme and complex cross-domain interaction scenarios, and traditional random testing is difficult to systematically traverse all possible power state combinations and access paths, leaving verification blind spots and affecting chip quality. Moreover, due to high dependence on manpower and poor scalability, the quality of verification depends too much on the experience of individual experts, and knowledge is difficult to deposit and reuse. With the continuous growth of chip complexity, the number of power domains is increasing, and the interaction relationship is exponentially complex, so the traditional manual method cannot meet the requirements.

[0062] Therefore, there is an urgent need in the industry to fully verify the power management logic to prevent hang-ups and ensure the correctness and reliability of the chip functions.

[0063] Based on this, in a first aspect, referring to Figure 1 The present application provides a power domain hang-up prevention simulation verification method based on an AI model, which comprises:

[0064] S101, an access relationship table is obtained, which is used to represent the access relationship between different power domains.

[0065] Referring to Figure 2 An access relationship table is provided, and each item vertically and each item horizontally represents each power domain. It can be known from the table that there is an access relationship between the AON M power domain and the AP_S power domain, and there is no access relationship between the AON M power domain and the AON_S power domain. Referring to Figure 3 An access logic diagram between power domains is provided. For access logic that is not available, such as the case where the power domain 1 cannot access the power domain 3, it is shown in the figure.

[0066] S102, the register mapping file of the power management unit PMU is parsed through an automatic script, and the register configuration information of each power domain is extracted.

[0067] The power management unit PMU stores the register configuration information of each power domain in the register mapping file in CSV (Comma-Separated Values, comma-separated value) format or Excel format, and the register configuration information includes register address, bit field, reset value and access permission, which is used to describe how to control the power domain. Among them, the bit field defines the function of the specific bit, the reset value is the default state automatically restored when the power domain is powered on or restarted, and the access permission defines how the register can be operated, including read-write, read-only and other different access permissions.

[0068] Taking the opening of the GPU power supply domain as an example, the automatic script parses the information of the GPU power supply control register from the.csv file, the address is: 0x1000_0000; the bit field is: bit[0] = 1, enabling the GPU power supply, bit[3:1]: selecting the voltage level (0: 0.7V, 1: 0.75V,..., 7: 1.0V), bit

[31] : power state (1: good, 0: abnormal); the reset value is: 0x0000_0000, the default is all 0, that is, the power supply is off; the access permission is: RW (read and write).

[0069] The embodiment of the application can eliminate the redundant operation of manually parsing the register manual by automatically parsing the registers related to the power supply domain in the PMU register mapping file, extracting the register address, bit field, reset value and access permission.

[0070] S103, collecting signal waveform data in the cross-domain access process between different power supply domains, the signal waveform containing timing constraint information.

[0071] The power supply domains with access relationship will generate signal waveform data with time sequence when accessing, indicating what signals are sent.

[0072] S104, inputting the register configuration information, signal waveform data and access relationship table into the pre-trained AI model, and generating register write sequence and verification check logic corresponding to each power supply domain through the AI model.

[0073] The pre-trained AI model can generate specific configurations of how to write the register based on the register configuration information, signal waveform data and access relationship table, simulate various scenarios of inter-domain access, and ensure that the access will not be wrong in this scenario. In addition, the AI model will also generate verification check logic for judging whether the test is passed.

[0074] S105, based on the access relationship table, traversing all possible inter-power supply domain access paths.

[0075] The system-level power supply domain access relationship traversal verification is performed.

[0076] S106, for each access path, calling the register write sequence and verification check logic generated by the AI model to perform joint simulation verification on the simulation platform.

[0077] The simulation platform can perform joint simulation verification based on the environment generated by the AI model.

[0078] In the embodiments of the present application, an access relationship table is acquired, the access relationship table being used to represent the access relationship between different power domains; a register mapping file of a power management unit (PMU) is parsed through an automatic script to extract register configuration information of each power domain; signal waveform data in a cross-domain access process between different power domains is collected, the signal waveform containing timing constraint information; the register configuration information, the signal waveform data and the access relationship table are input into a pre-trained AI model to generate register write sequences corresponding to each power domain and verification check logic through the AI model; based on the access relationship table, all possible access paths between power domains are traversed; for each access path, the register write sequences and the verification check logic generated by the AI model are called to perform joint simulation verification on a simulation platform. The power domain hang-up prevention can be automatically verified, and the verification efficiency is improved.

[0079] In a possible implementation, the step S103 can specifically include:

[0080] The signal waveform of the wake-up request signal sent by the PMU domain to the accessed power domain, the signal waveform of the power enable signal sent by the PMU domain, the signal waveform of the power good signal returned by the accessed power domain, the signal waveform of the clock good signal returned by the accessed power domain, the signal waveform of the reset release signal returned by the accessed power domain, and the signal waveform of the wake-up confirmation signal returned by the accessed power domain to the PMU domain are collected.

[0081] Taking an example of a CPU domain trying to access a GPU domain in a sleep state, the signal transmission relationship is described. Generally, it includes the signals sent by the control party (PMU), power handshake request (PMU controls the power-on wake-up of the GPU), pmu_gpu_pwr_en (PMU enables the power supply of the GPU), the PMU pulls up this signal to control the external power management chip to start supplying power to the GPU. The signals returned by the response party (GPU domain), gpu_pwr_ok (GPU power good), indicating that the core voltage of the GPU has been stabilized and established. This is an indicator of stable power supply, gpu_clk_ok (GPU clock good), indicating that the clock of the GPU has been stabilized. This is the basis for the normal operation of the synchronization logic, gpu_rst_n (GPU reset release), indicating that the internal logic of the GPU has been released from reset and can start running. Power handshake acknowledge (GPU wake-up response), the GPU pulls up this signal to inform the CPU that it is fully ready and can formally initiate data transmission. This is an ideal and successful handshake process. It defines the correct template for power domain wake-up, including the correct sequence and timing relationship between each signal, for example, ack must be pulled up after pwr_ok and clk_ok, and ack and req must be within 1000 clock cycles.

[0082] Of course, there will also be a failed handshake process, for example, the control party (PMU) sends a signal, power handshake request (PMU controls the GPU to wake up), pmu_gpu_pwr_en (PMU enables the power supply of the GPU), the PMU pulls up this signal to control the external power management chip to start supplying power to the GPU; Then the power domain starts, the power supply is stable, gpu_pwr_ok is pulled up, the clock is stable, gpu_clk_ok is pulled up, but the reset fails, gpu_rst_n is always low, eventually leading to wake-up timeout, ACK unresponsive, power handshake acknowledge is always low, CPU request suspension, and the system hangs here. In this fault waveform, due to some design defects, for example, reset control logic error, the reset signal gpu_rst_n of the GPU has not been released. The GPU logic cannot work, and naturally it cannot send the reply signal power handshake acknowledge.

[0083] In a possible implementation, the step S104 can specifically include:

[0084] Step one, input the register configuration information, signal waveform data and access relationship table into the pre-trained AI model, configure the registers of the shutdownable power domain through the AI model, and set the shutdownable power domain to a power-off state;

[0085] Step two, configure the registers of the unshutdownable power domain, and set the unshutdownable power domain to access the shutdownable power domain;

[0086] Step three, configure the registers of the shutdownable power domain, and set the shutdownable power domain to return an error response signal;

[0087] Step four, judge whether the access signal of the unshutdownable power domain is dead or not, and if yes, report an error;

[0088] Step five, judge whether the shutdownable power domain returns an error response signal error resp or not, and if no, report an error.

[0089] The AI model is mainly used to generate a configuration sequence that can effectively trigger various potential hanging scenarios, and the access of the shutdownable power domain will not be dead, so the shutdownable power domain can be set to a power-off state, and the unshutdownable power domain is set to access the shutdownable power domain. When the shutdownable power domain is in a power-off state, the expected behavior will return an error response error resp.

[0090] Step four and step five are verification check logic, which stipulates that a clear error reply must be received. When the power-off domain power is turned off, the output signal of the module must be isolated to 0; the internal state of the module should be maintained or cleared; after the power control signal (power_down_req) is pulled high, the isolation must be completed within a certain period.

[0091] In a possible implementation, the step S104 can specifically include:

[0092] Step one, input the register configuration information, signal waveform data and access relationship table into the pre-trained AI model, configure the registers of the power-off domain through the AI model, and set the power-off domain to the power-on state;

[0093] Step two, configure the registers of the power-continuous domain, and set the power-continuous domain to access the power-off domain.

[0094] Step three, determine whether the power-off domain returns a correct response signal OK resp, and if not, report an error.

[0095] Set the power-off domain to the power-on state, and let the power-continuous domain access the power-off domain. When the power-off domain is in the power-on state, the expected behavior request is processed normally.

[0096] Step three is the verification check logic. In order to realize the power domain anti-hanging, it is necessary to verify whether the power-off domain returns a correct response signal OK resp. If the power-continuous domain sends a write operation to the power-off domain first, and then sends a read operation, the verification check logic includes that the read and write operation instructions have been received and processed by the power-off domain; and the content obtained by the read operation is the same as the content written by the previous write operation, otherwise it is judged as a data corruption fault.

[0097] In a possible implementation, the AI model is trained in the following manner:

[0098] Obtain historical verification data, including historical register configuration information, historical signal waveform and access relationship table;

[0099] Input the historical verification data and verification result label into the AI model to be trained, train the AI model, and the verification result label includes the success result identifier or failure result identifier recorded in the previous simulation or hardware test, and the failure reason;

[0100] Based on the verification result label and the output of the AI model to be trained, adjust the parameters of the AI model until a trained AI model is obtained.

[0101] In a possible implementation, the method further includes:

[0102] running the register write sequence on a simulation platform;

[0103] based on the verification checking logic, monitoring the simulation process in real time and judging whether the real-time signal waveform conforms to the expected timing relationship;

[0104] If not, a verification report is generated and output, the verification report including assertion violation information and error type classification.

[0105] The register write sequence generated by the AI model may also fail in the simulation process, at which time the verification checking logic is based on to pull out the signal waveform in the simulation process for external checking. For problematic simulation, a verification report including assertion violation information and error type classification is generated and output. The register write sequence generated by the AI model is also added to the historical verification data again for iterative training of the AI model.

[0106] Referring to Figure 4 , a flowchart of a power domain anti-hanging simulation verification method provided by the present application.

[0107] The input of the AI model includes register configuration information, signal waveform, power domain basic information (including power domain name and voltage), and access relationship table. After the AI model is trained with historical verification data, the AI model outputs a verification environment and a checker, i.e., a register write sequence and verification checking logic, and finally EDA (electric design automatic) is used for joint simulation.

[0108] In a second aspect, the embodiments of the present application provide a power domain anti-hanging simulation verification system based on an AI model, the system comprising:

[0109] The acquisition module is configured to acquire an access relationship table, the access relationship table being used to represent the access relationship between different power domains.

[0110] The analysis module is configured to parse a register mapping file of a power management unit (PMU) through an automatic script, and extract register configuration information of each power domain.

[0111] The collection module is configured to collect signal waveform data in a cross-domain access process between different power domains, the signal waveform containing timing constraint information.

[0112] The generation module is configured to input the register configuration information, signal waveform data, and access relationship table into a pre-trained AI model, and generate, through the AI model, a register write sequence and verification checking logic corresponding to each power domain.

[0113] a traversal module configured to traverse all possible power domain inter-access paths based on the access relationship table;

[0114] a co-simulation module configured to, for each access path, invoke the register write sequence and the verification check logic generated by the AI model to perform co-simulation verification on a simulation platform.

[0115] In a third aspect, the present application provides a computer program product comprising instructions which, when executed on a computer, cause the computer to carry out the method of any of the preceding aspects.

[0116] In a fourth aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and the computer program, when executed by a processor, implements the method of any of the preceding aspects.

[0117] In the above embodiments, the implementation can be wholly or partially in software, hardware, firmware, or any combination thereof. When implemented by software, the implementation can be wholly or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed by a computer, the computer program instructions wholly or partially generate the processes or functions described in the embodiments of the present application. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center through a wired (for example, coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (for example, infrared, wireless, microwave, etc.) manner. The computer-readable storage medium can be any available medium accessible by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media. The available medium can be a magnetic medium (for example, floppy disk, hard disk, magnetic tape), an optical medium (for example, DVD), or a semiconductor medium (for example, Solid State Disk (SSD)), etc.

[0118] It is to be noted that, as used in this document, the terminology "first", "second", etc. is merely used to differentiate one entity or action from another, and does not necessarily imply any actual physical or logical relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0119] Each of the embodiments in the present specification is described in a related manner, and the same or similar parts among the embodiments can be referred to each other. Each of the embodiments focuses on the difference from other embodiments. In particular, for the system, computer program product, and computer readable storage medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiment.

[0120] The above only describes the preferred embodiments of the present application, and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An AI model-based power domain anti-hanging simulation verification method, characterized in that, The method comprises: acquiring an access relationship table, the access relationship table being used to represent an access relationship between different power supply domains; analyzing a register mapping file of a power management unit (PMU) through an automatic script to extract register configuration information of each power supply domain; collecting signal waveform data in a cross-domain access process between different power supply domains, the signal waveform containing timing constraint information; inputting the register configuration information, the signal waveform data and the access relationship table into a pre-trained AI model to generate register write sequences and verification check logic corresponding to each power supply domain through the AI model; based on the access relationship table, traversing all possible access paths between power supply domains; for each access path, calling the register write sequences and the verification check logic generated by the AI model to perform joint simulation verification on a simulation platform.

2. The method of claim 1, wherein, The register configuration information comprises register addresses, bit fields, reset values and access permissions.

3. The method of claim 1, wherein, The collection of signal waveform data in the cross-domain access process between different power supply domains comprises: collecting a wake-up request signal waveform sent by a PMU domain to an accessed power supply domain, a power supply enable signal waveform sent by the PMU domain, a power good signal waveform returned by the accessed power supply domain, a clock good signal waveform returned by the accessed power supply domain, a reset release signal waveform returned by the accessed power supply domain, and a wake-up confirmation signal waveform returned by the accessed power supply domain to the PMU domain.

4. The method of claim 1, wherein, The inputting of the register configuration information, the signal waveform data and the access relationship table into the pre-trained AI model to generate the register write sequences and the verification check logic corresponding to each power supply domain through the AI model comprises: inputting the register configuration information, the signal waveform data and the access relationship table into a pre-trained AI model to configure registers of a shut-down power supply domain through the AI model and set the shut-down power supply domain to a power-down state; configuring registers of an un-shut-down power supply domain and setting the un-shut-down power supply domain to access the shut-down power supply domain; configuring registers of the shut-down power supply domain and setting the shut-down power supply domain to return an error response signal; judging whether an access signal of the un-shut-down power supply domain is hung up, and if so, reporting an error; judging whether the shut-down power supply domain returns an error response signal error resp, and if not, reporting an error.

5. The method of claim 1, wherein, The inputting of the register configuration information, the signal waveform data and the access relationship table into the pre-trained AI model to generate the register write sequences and the verification check logic corresponding to each power supply domain through the AI model comprises: inputting the register configuration information, the signal waveform data and the access relationship table into a pre-trained AI model to configure registers of a shut-down power supply domain through the AI model and set the shut-down power supply domain to a power-up state; configuring registers of an un-shut-down power supply domain and setting the un-shut-down power supply domain to access the shut-down power supply domain; judging whether the shut-down power supply domain returns a correct response signal OK resp, and if not, reporting an error.

6. The method of claim 1, wherein, The AI model is trained in the following manner: acquiring historical verification data, including historical register configuration information, historical signal waveforms and an access relationship table; The historical verification data and a verification result label are input into an AI model to be trained, the verification result label including a success result label or a failure result label recorded in a previous simulation or hardware test, and a failure cause; Based on the verification result label and an output of the AI model to be trained, parameters of the AI model are adjusted until a trained AI model is obtained.

7. The method of claim 1, wherein, The method further comprises: running the register write sequence on a simulation platform; based on the verification check logic, monitoring a simulation process in real time and judging whether a real-time signal waveform conforms to an expected timing relationship; if not, generating and outputting a verification report, the verification report including assertion violation information and error type classification.

8. An AI model-based power domain anti-hanging simulation verification system, characterized in that, The system comprises: an acquisition module configured to acquire an access relationship table, the access relationship table being used to represent an access relationship between different power domains; an analysis module configured to analyze a register mapping file of a power management unit (PMU) through an automatic script, and extract register configuration information of each power domain; a collection module configured to collect signal waveform data in a cross-domain access process between different power domains, the signal waveform containing timing constraint information; a generation module configured to input the register configuration information, the signal waveform data, and the access relationship table into a pre-trained AI model, and generate register write sequences and verification check logic corresponding to each power domain through the AI model; a traversal module configured to traverse all possible access paths between power domains based on the access relationship table; a joint simulation module configured to, for each access path, call the register write sequences and the verification check logic generated by the AI model, and perform joint simulation verification on a simulation platform.

9. A computer program product comprising instructions, characterized in that, When it is run on a computer, it causes the computer to implement the method of any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the method of any one of claims 1-7.

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