Graphics processor, thread block allocation method, thread bundle assembly method, and chip

Abstract

The application discloses a graphics processor, a thread block allocation method, a thread bundle assembly method and a chip, and belongs to the chip field.The graphics processor comprises a first table generation unit, a thread block allocation unit and at least two cores.The first table generation unit is used for generating a first overlap table based on n first address regions; the first overlap table is sent to the thread block allocation unit; the i first address region is used for indicating a memory address expected to be accessed by the i thread block in the n thread blocks; the first overlap table is used for recording the overlap degree between any two first address regions; the thread block allocation unit is used for allocating the n thread blocks to the at least two cores based on the first overlap table and a first allocation principle; each core is allocated with m thread blocks; and the first allocation principle comprises that the overlap degree between the m first address regions corresponding to each core reaches a preset condition.The application can improve the cache hit rate.

Description

Technical Field

[0001] This application relates to the field of chips, and in particular to a graphics processor, a thread block allocation method, a thread bundle assembly method, and a chip. Background Technology

[0002] A graphics processing unit (GPU) is a typical multiprocessor system. Typically, one processor core in a GPU can access one L1 cache, while multiple processor cores share one L2 cache.

[0003] In related technologies, the thread distribution method of graphics processors mainly considers load balancing, so that the number of threads on each processor core is similar. However, these technologies do not consider whether the thread distribution method is cache-friendly, that is, they do not take into account the hit rate of the distributed threads on the accessed cache. Summary of the Invention

[0004] This application provides a graphics processor, a thread block allocation method, a thread bundle assembly method, and a chip. This application allocates thread blocks based on the degree of address overlap, which can improve the cache hit rate.

[0005] According to one aspect of this application, a graphics processor is provided, the graphics processor including a first table generation unit, a thread block allocation unit and at least two cores;

[0006] The first table generation unit is used to generate a first overlapping table based on n first address regions; and send the first overlapping table to the thread block allocation unit; the i-th first address region among the n first address regions is used to indicate the memory address that the i-th thread block in the n thread blocks is expected to access, and the first overlapping table is used to record the degree of overlap between any two first address regions;

[0007] The thread block allocation unit is used to allocate n thread blocks to at least two cores based on the first overlap table and the first allocation principle, so that each core is allocated m thread blocks. The first allocation principle includes that the overlap between the m first address regions corresponding to each core reaches a preset condition, where n and m are both positive integers greater than or equal to 2.

[0008] According to one aspect of this application, a graphics processor is provided, the graphics processor including a first core, the first core including a second table generation unit and a thread bundle assembly unit;

[0009] The second table generation unit is used to generate a second overlapping table based on p second address regions for the first thread block in the first core. The i-th second address region in the p second address regions is used to indicate the memory address that the i-th thread in the first thread block is expected to access. The second overlapping table is used to record the degree of overlap between any two second address regions. The second overlapping table is sent to the thread bundle assembly unit.

[0010] The thread bundle assembly unit is used to assemble p threads into at least two thread bundles based on a second overlap table and a second allocation principle, such that each thread bundle is allocated q threads. The second allocation principle includes that the overlap between the q second address regions corresponding to each thread bundle reaches a preset condition, where p and q are both positive integers greater than or equal to 2.

[0011] According to one aspect of this application, a thread block allocation method is provided, the method being executed by a graphics processor, the graphics processor including a first table generation unit, a thread block allocation unit, and at least two cores, the method comprising the following steps.

[0012] The first table generation unit generates a first overlapping table based on n first address regions; and sends the first overlapping table to the thread block allocation unit; the i-th first address region among the n first address regions is used to indicate the memory address that the i-th thread block in the n thread blocks is expected to access, and the first overlapping table is used to record the degree of overlap between any two first address regions;

[0013] The thread block allocation unit allocates n thread blocks to at least two cores based on the first overlap table and the first allocation principle, so that each core is allocated m thread blocks. The first allocation principle includes that the overlap between the m first address regions corresponding to each core reaches a preset condition, where n and m are both positive integers greater than or equal to 2.

[0014] According to one aspect of this application, a thread bundle assembly method is provided, the method being executed by a graphics processor, the graphics processor including a first core, the first core including a second table generation unit and a thread bundle assembly unit, the method including the following steps.

[0015] The second table generation unit generates a second overlapping table for the first thread block in the first core based on p second address regions. The i-th second address region in the p second address regions is used to indicate the memory address that the i-th thread in the p threads included in the first thread block is expected to access. The second overlapping table is used to record the degree of overlap between any two second address regions. The second overlapping table is sent to the thread bundle assembly unit.

[0016] The thread bundle assembly unit assembles p threads into at least two thread bundles based on the second overlap table and the second allocation principle, such that each thread bundle is allocated q threads. The second allocation principle includes that the overlap between the q second address regions corresponding to each thread bundle reaches a preset condition, where p and q are both positive integers greater than or equal to 2.

[0017] According to one aspect of this application, a chip is provided, the chip including the above-described graphics processor.

[0018] According to one aspect of this application, a server is provided, the server including the above-described graphics processor.

[0019] According to one aspect of this application, an electronic device is provided, which includes the aforementioned graphics processor.

[0020] The beneficial effects of the technical solutions provided in this application include at least the following:

[0021] In this application, n thread blocks are allocated to at least two cores based on the degree of overlap between the n first address regions corresponding to the n thread blocks. This ensures that the address overlap between the m thread blocks in each core reaches a preset condition. Consequently, when the m thread blocks access the cache, the addresses of the data they access have a high degree of overlap, meaning that the m thread blocks will access the same data more often. At this time, the cache can continuously retain this data, which is less likely to be replaced by other less frequently accessed data. Therefore, when accessing the cache, the data can be directly obtained from the cache without needing to retrieve it from the lower-level cache or main memory. In other words, the thread block allocation scheme provided in this application improves the cache hit rate. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of a thread set provided in one embodiment of this application.

[0024] Figure 2 This is a structural block diagram of a graphics processor provided in one embodiment of this application.

[0025] Figure 3 This is a schematic diagram of overlapping address regions provided in one embodiment of this application.

[0026] Figure 4This is a schematic diagram of an overlapping table provided in one embodiment of this application.

[0027] Figure 5 This is a schematic diagram of multiple second sub-address regions provided in one embodiment of this application.

[0028] Figure 6 This is a schematic diagram of a method for generating a first address region provided in an embodiment of this application.

[0029] Figure 7 This is a structural block diagram of the first core provided in one embodiment of this application.

[0030] Figure 8 This is a schematic diagram of an electronic device provided in one embodiment of this application.

[0031] Figure 9 This is a schematic diagram of the structure of a server provided in one embodiment of this application. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0033] First, some terms used in the embodiments of this application will be introduced:

[0034] A thread is the smallest unit of execution in a graphics processing unit (GPU). A GPU is a multi-core processor system, consisting of at least two cores. These cores are the most important components of the GPU and are the actual processor kernels. The tasks assigned to at least two cores of the GPU constitute a set of threads. This set of threads can be two-dimensional or three-dimensional. In a two-dimensional set, each thread has a unique (x, y) coordinate, while in a three-dimensional set, each thread has a unique (x, y, z) coordinate. For ease of explanation, we will use a two-dimensional thread set as an example below. Figure 1 The diagram shows a two-dimensional set of threads, where the X-axis coordinates range from 0 to 15, and the Y-axis coordinates also range from 0 to 15. Figure 1 The illustrated set of two-dimensional threads includes 256 two-dimensional threads.

[0035] A thread block is a combination of multiple threads; that is, a thread block includes multiple threads. Figure 1The thread set shown includes four thread blocks: thread block 0 consists of a square thread matrix formed by coordinates (0, 0) and (7, 7); thread block 1 consists of a square thread matrix formed by coordinates (8, 0) and (15, 7); thread block 2 consists of a square thread matrix formed by coordinates (0, 8) and (7, 15); and thread block 3 consists of a square thread matrix formed by coordinates (8, 8) and (15, 15). The corresponding partitioning method can be found in [reference needed]. Figure 1 During the operation of a graphics processing unit (GPU), threads within the same thread block are assigned to the same core, and a core can be allocated multiple thread blocks. Within a core, for a given thread block, the threads within that thread block are divided into multiple thread bundles.

[0036] In this application, the following data relationships are defined: Assume there are n thread blocks, the graphics processor includes at least two cores, each core is allocated m thread blocks, each thread block includes p threads, the p threads in each core are used to assemble at least two thread bundles, each thread bundle includes q threads, where n, m, p, and q are all positive integers greater than or equal to 2.

[0037] The address region refers to the memory address expected to be accessed. Memory, also known as main memory, has multiple levels of cache between the core and main memory to improve the efficiency of the graphics processing unit's core read / write operations. These typically include L1 cache and L2 cache. Each core has its own L1 cache, while multiple cores share a single L2 cache. In this application, a first address region and a second address region are defined. The first address region refers to the memory address expected to be accessed by a thread block, and the second address region refers to the memory address expected to be accessed by a thread.

[0038] Figure 2 The diagram illustrates a structural block diagram of a graphics processor provided in an exemplary embodiment of this application. The graphics processor includes a first table generation unit 201, a thread block allocation unit 202, and at least two cores 203.

[0039] The first table generation unit 201 will acquire n first address regions, each corresponding one-to-one with a thread block. Each first address region indicates the memory address expected to be accessed by a thread block; that is, the i-th first address region among the n first address regions indicates the memory address expected to be accessed by the i-th thread block. The first table generation unit 201 will generate a first overlap table based on the n first address regions. The first overlap table is used to record the degree of overlap between any two first address regions.

[0040] The first table generation unit 201 sends the first overlapping table to the thread block allocation unit 202. Optionally, such as... Figure 2As shown, the first table generation unit 201 sends the first overlapping table to the bus 205, and the bus 205 sends the first overlapping table to the thread block allocation unit 202. Based on the first overlapping table and the first allocation principle, the thread block allocation unit 202 allocates n thread blocks to at least two cores 203, so that each core is allocated m thread blocks. The first allocation principle includes that the overlap between the m first address regions corresponding to each core reaches a preset condition, and the m first address regions correspond one-to-one with the m thread blocks in each core. n and m are both positive integers greater than or equal to 2.

[0041] In one embodiment, the first allocation principle includes ensuring that the overlap between the m first address regions corresponding to each core reaches a first threshold, meaning that the first allocation principle simultaneously guarantees that the address overlap for each core reaches the first threshold. In another embodiment, the first allocation principle includes ensuring that the overlap between the m first address regions corresponding to each core reaches the maximum extent, whereby the first allocation principle aims to maximize the address overlap for each core.

[0042] In one embodiment, the first overlap table is used to record the number of address cells that intersect between any two first address regions, where each address cell includes a standard-sized address region. In another embodiment, the first overlap table is used to record the size of the intersecting address region between any two first address regions. For example, if one first address region is 0-31 and the other is 15-46, then the first overlap table is used to record the length of the intersecting address region 15-31, which is 16.

[0043] exist Figure 2 The diagram also shows the L1 cache 204, bus 205, at least two L2 caches 206, and main memory 207 corresponding to each core 203. In one embodiment, each core 203 accesses the corresponding L1 cache 204 based on the allocated m thread blocks, and if the target access data is not found in the L1 cache 204, it accesses the L2 cache 206 through data transfer via the bus 205; if the target access data is still not found in the L2 cache 206, it will access the main memory 207.

[0044] In this application, n thread blocks are allocated to at least two cores based on the degree of overlap between the n first address regions corresponding to the n thread blocks. This ensures that the address overlap between the m thread blocks in each core reaches a preset condition. Consequently, when the m thread blocks access the cache, the addresses of the data they access have a high degree of overlap, meaning that the m thread blocks will access the same data more often. At this time, the cache can continuously retain this data, which is less likely to be replaced by other less frequently accessed data. Therefore, when accessing the cache, the data can be directly obtained from the cache without needing to retrieve it from the lower-level cache or main memory. In other words, the thread block allocation scheme provided in this application improves the cache hit rate.

[0045] First overlapping table

[0046] As described above, the first table generation unit 201 generates a first overlapping table based on n first address regions. In one embodiment, the first overlapping table is used to record the number of address cells that intersect between any two first address regions. The address cells include standard-sized address regions; for example, the size of the address cells is fixed at 32 bits. Optionally, the size of the address cells can be an integer or a floating-point number.

[0047] In this application, the number of intersecting address cells is used as the degree of overlap, which is beneficial for measuring the degree of overlap between two first address regions. Furthermore, the first overlap table only needs to record the number of intersecting address cells, and the amount of data that the first overlap table needs to accommodate is small, which is beneficial for the transmission and storage of the first overlap table.

[0048] In one embodiment, the address grid type includes any one of a one-dimensional address grid, a two-dimensional address grid, and a three-dimensional address grid. A one-dimensional address grid refers to a rectangular address grid, and the address value range corresponding to a rectangular address grid is a one-dimensional range. A two-dimensional address region refers to a planar address grid, and the address value range corresponding to a planar address grid is a two-dimensional value range. A three-dimensional address region refers to a volumetric address grid, and the address value range corresponding to a volumetric address grid is a three-dimensional value range. In this application, the two-dimensional address grid is mainly used for description.

[0049] For example, refer to Figure 3 , Figure 3 This is a schematic diagram illustrating the overlap between the four first address regions. M0 represents the first address region corresponding to thread block 0, M1 represents the first address region corresponding to thread block 1, M2 represents the first address region corresponding to thread block 2, and M3 represents the first address region corresponding to thread block 3. By observing... Figure 3 It can be observed that the first address region M0 intersects with M1 by two address cells, while the first address region M2 intersects with M3 by four address cells.

[0050] For example, refer to Figure 4 , Figure 4 The first overlapping table is shown. Figure 4 The first overlapping table records the number of address cells that intersect between any two of the four first address regions. Figure 4 In the table, the M0 counter line records the number of address cells where the first address region M0 intersects with other address regions, the M1 counter line records the number of address cells where the first address region M1 intersects with other address regions, and so on. Specifically, by observing... Figure 4 It can be observed that the M0 and M1 count rows record that the first address region M0 intersects with M1 by two address cells, while the M2 and M3 count rows record that the first address region M2 intersects with M3 by four address cells.

[0051] In one embodiment, the first overlap table is further used to record the first cumulative overlap degree corresponding to each first address region. The first cumulative overlap degree refers to the sum of the overlap degrees between the first address region corresponding to the current thread block and the first address regions corresponding to non-current thread blocks among n thread blocks. Figure 4 As shown, Figure 4 The first overlapping table also includes a total count row, which records the total number of address cells that intersect with other first address regions for each first address region. The total count row also records the total number of address cells that each of the first address regions M0, M1, M2 and M3 overlaps with address regions other than itself.

[0052] In one embodiment, after the first table generation unit 201 generates the first overlapping table, it stores the first overlapping table in a reserved buffer area in the L2 cache 206. In the case of 1000 thread blocks and each count value in the first overlapping table is 1 byte in size, only a buffer area of ​​size 1000*1000 / 2==500KB is needed.

[0053] First distribution principle

[0054] As described above, the thread block allocation unit 202 allocates n thread blocks to at least two cores based on the first overlapping table and the first allocation principle, so that each core is allocated m thread blocks.

[0055] In one embodiment, the thread block allocation unit 202 selects thread blocks one by one from n thread blocks based on a first overlap table and a first selection principle to obtain a thread block sequence. The first selection principle includes that among the remaining unselected thread blocks, the first address region corresponding to the next selected thread block has the highest degree of overlap with the first address region corresponding to the previous selected thread block.

[0056] Indicative, continuing from the previous text Figure 3 and Figure 4 The example shown is in Figure 4 The first overlapping table shown includes first address areas M0 to M3. First, based on the total number of rows recorded, the first address area with the largest total number of overlapping cells is selected from the first address areas M0 to M3, namely the first address area M2 (M2 and M3 have the same total number of overlapping cells, so the first address area with the smaller number is selected).

[0057] Then, from the M2 counting row, from the remaining first address regions M0, M1 and M3, select the first address region with the most cells overlapping with M2, that is, the first address region M3;

[0058] Next, from the M3 counting row, from the remaining first address regions M0 and M1, select the first address region with the most overlapping cells with M3, that is, the first address region M0 (M0 and M1 have the same total number of overlapping cells, so the first address region M0 with the smaller number is selected).

[0059] Finally, select the remaining first address region M1 from the M0 count row.

[0060] That is, according to Figure 4 The first overlapping table shown identifies M2, M3, M0, and M1 in sequence, and the corresponding identified thread block sequence is [thread block 2, thread block 3, thread block 0, and thread block 1].

[0061] In one embodiment, the thread block allocation unit 202 starts from the first thread block in the thread block sequence and allocates m thread blocks to one core each time until at least two cores have been allocated. Illustratively, assuming that at least two cores consist of two cores, each core supporting two thread blocks, then starting from the first thread block in the thread block sequence [thread block 2, thread block 3, thread block 0, and thread block 1], i.e., thread block 2, every two thread blocks are allocated to one core; that is, thread block 2 and thread block 3 are allocated to one core, and thread block 0 and thread block 1 are allocated to the other core.

[0062] In this application, the method of allocating thread blocks based on the aforementioned first selection principle can ensure that the overlap of the first address regions corresponding to the m thread blocks allocated to each core is maximized, thereby improving the cache hit rate. It can be understood that the aforementioned first selection principle is a greedy algorithm. When selecting the next thread block, it always makes the best choice for the current thread block. The greedy algorithm provides a solution to quickly find the optimal solution, ensuring that the overlap of the m first address regions corresponding to each core is maximized.

[0063] In the example described above, the thread block allocation unit 202 also employs a second selection principle.

[0064] Based on a second selection principle, the thread block allocation unit 202 selects a first target thread block from among n thread blocks as the first thread block in the thread block sequence. The first target thread block is the thread block with the largest cumulative overlap among the n thread blocks. The first cumulative overlap refers to the sum of the overlap between the first address region corresponding to the current thread block and the first address regions corresponding to non-current thread blocks. The current thread block refers to the thread block currently being targeted. For n thread blocks, the first cumulative overlap corresponding to each thread block is considered specifically. In other words, the first cumulative overlap refers to the sum of the overlap between the first address region corresponding to the i-th thread block and the first address regions corresponding to non-i-th thread blocks among the n thread blocks.

[0065] This is the process by which the thread block allocation unit 202 determines the first thread block in the thread block sequence as M2 in the example above.

[0066] Understandably, the second selection principle provides a method to determine the first thread block, which is the thread block with the highest cumulative overlap. By combining the first and second selection principles, the overlap of the m first address regions corresponding to each core is maximized.

[0067] In one embodiment, the process of the first table generation unit 201 generating the first overlapping table and the process of the core 203 in the graphics processor running thread blocks are parallel. When the core 203 runs the previous set of thread blocks, the first table generation unit 201 can simultaneously calculate the first overlapping table corresponding to the next set of thread blocks.

[0068] Once all n first thread blocks have been allocated, each core will run its assigned thread block. If a target core is missing a thread block, a new thread block will be added from the pending thread blocks. Optionally, the reason for the missing thread block may be that the core has already finished executing the thread block.

[0069] In one embodiment, the thread block allocation unit 202 is further configured to determine a second target thread block from the thread blocks to be scheduled when the target core has fewer than m thread blocks running in at least two cores, and allocate the second target thread block to the target core; the second target thread block is the thread block with the largest first overlap among the thread blocks to be scheduled; wherein, the first overlap refers to the degree of overlap between the first address region corresponding to the current thread block and the first address region corresponding to the thread block running on the target core.

[0070] For example, if there are n thread blocks, the target core allocates thread block 0 and thread block 1. When the target core runs, it finishes executing thread block 1 but does not finish executing thread block 0. The target core will select the second target thread block from the thread blocks to be scheduled. Among the thread blocks to be scheduled, the second address region corresponding to the second target thread block has the greatest overlap with the second address region corresponding to thread block 0.

[0071] By using the supplementary thread blocks provided in this application, the m first address regions corresponding to the m thread blocks on the target core can always maintain a high degree of overlap, thereby ensuring a consistently high cache hit rate.

[0072] First address region and second address region

[0073] As described above, the first address region refers to the memory address that a thread block is expected to access. In one embodiment, the first address region includes at least one of a one-dimensional address region, a two-dimensional address region, and a three-dimensional address region. A one-dimensional address region refers to a strip-shaped address, a two-dimensional address region refers to a planar address, and a three-dimensional address region refers to a volumetric address. The degree of overlap between two address regions refers to the degree of overlap between address regions of the same type. In this application, a two-dimensional address region is mainly used as an example to illustrate the concept of the first address region.

[0074] In one embodiment, the first address region includes multiple first sub-address regions, meaning that a thread block will access the memory addresses corresponding to multiple first sub-address regions. The type of each first sub-address region can be any one of a one-dimensional address region, a two-dimensional address region, and a three-dimensional address region.

[0075] This application also relates to the memory address accessed by a thread, referred to as a second address region, which indicates the memory address that a thread expects to access. In one embodiment, the second address region includes at least one of a one-dimensional address region, a two-dimensional address region, and a three-dimensional address region. A one-dimensional address region refers to a strip-shaped address, a two-dimensional address region refers to a planar address, and a three-dimensional address region refers to a volumetric address. In this application, a two-dimensional address region is primarily used as an example for illustration.

[0076] In one embodiment, the second address region includes multiple second sub-address regions, meaning that a thread will access the memory addresses corresponding to multiple second sub-address regions. The type of each second sub-address region can be any one of a one-dimensional address region, a two-dimensional address region, and a three-dimensional address region.

[0077] For example, refer to Figure 5 , Figure 5Two threads are shown, namely thread (0,0) and thread (1,0). Thread (0,0) corresponds to four second sub-address regions, namely R0, R1, R2 and R3. Among them, R0 and R1 are one-dimensional address regions, and R2 and R3 are two-dimensional address regions. Thread (1,0) corresponds to four second sub-address regions, namely R0', R1', R2' and R3'. Among them, R0' and R1' are one-dimensional address regions, and R2' and R3' are two-dimensional address regions.

[0078] In one embodiment, the first table generation unit 201 is configured to, for any one of n thread blocks, determine the starting thread and the ending thread of the thread block; use the second address region corresponding to the starting thread as the starting address region in the first address region corresponding to the thread block; and use the second address region corresponding to the ending thread as the ending address region in the first address region corresponding to the thread block, thereby obtaining the first address region corresponding to the thread block. The second address region corresponding to the starting thread is used to indicate the memory address that the starting thread is expected to access, and the second address region corresponding to the ending thread is used to indicate the memory address that the ending thread is expected to access.

[0079] For example, if the second address region of the starting thread is 0-31 and the second address region of the ending thread is 96-127, then the first address region of the determined thread block is 0-127.

[0080] For example, Figure 6 A schematic diagram of the method for generating the first address region of a thread block is shown. Figure 6 The left half shows four thread blocks, including thread block 0, thread block 1, thread block 2 and thread block 3. Figure 6 Each thread block consists of a square thread matrix, and each thread matrix contains 16 threads. Figure 6 In the example of thread block 0, the first address area corresponding to thread block 0 includes two first sub-address areas. Furthermore, the starting thread (0,0) of thread block 0 corresponds to two second sub-address areas (R0 and R0'), and the ending thread (3,3) of thread block 0 corresponds to two second sub-address areas (R1 and R1').

[0081] The first sub-address region of thread block 0 is obtained based on the second sub-address region R0 as the starting address region and the second sub-address region R1 as the ending address region. Figure 6In the first sub-address region, the second sub-address region R0 includes the address range bounded by coordinates (0,0), (0,1), (1,0), and (1,0), the second sub-address region R1 includes the address range bounded by coordinates (4,2), (5,2), (4,3), and (5,3), and the first sub-address region includes the address range bounded by coordinates (0,0), (0,3), (5,0), and (5,3).

[0082] The other first sub-address region of thread block 0 is obtained based on the second sub-address region R0' as the starting address region and the second sub-address region R1' as the ending address region. Figure 6 In the first sub-address region, the second sub-address region R0' includes the address range bounded by coordinates (128, 32), (128, 33), (129, 32), and (129, 33), the second sub-address region R1' includes the address range bounded by coordinates (132, 34), (132, 35), (133, 34), and (133, 35), and the other first sub-address region includes the address range bounded by coordinates (128, 32), (128, 35), (133, 32), and (133, 35).

[0083] In one embodiment, in conjunction with reference Figure 2 The graphics processor (GPU) runs a computer program and outputs the second address region corresponding to the thread. Optionally, the GPU runs a computer program and extracts the second address region corresponding to a portion of the threads from the memory access addresses originally carried by some threads. The GPU sends the second address region corresponding to the portion of the threads to the first table generation unit 201 via bus 205. The first table generation unit 201 combines the second address regions to form the first address region corresponding to the thread block.

[0084] In one embodiment, the first address region corresponding to thread block k includes multiple first sub-address regions [k1, k2, ..., kk]. k The second address region corresponding to the starting thread of thread block k includes multiple second sub-address regions [k'1, k'2, ..., k']. k The second address region corresponding to the ending thread of thread block k includes multiple second sub-address regions [k''1, k''2, ..., k'']. k ], then the first sub-address region k k Based on the second sub-address region k' k Second sub-address region k'' k Obtained. First sub-address region k k Based on the second sub-address region k' k As the starting address region, and based on the second sub-address region k'' k It is obtained as the end address region.

[0085] Thread bundle assembly

[0086] As described above, the thread block allocation unit 202 will allocate n thread blocks to at least two cores 203, such that each of the at least two cores 203 is allocated m thread blocks. The following discussion will focus on the first core among the at least two cores 203. The first core is any one of the at least two cores 203, and it contains the first thread block, which includes p threads.

[0087] Figure 7 A structural block diagram of the first core is shown. Schematic, the first core includes a second table generation unit 701 and a thread bundle assembly unit 702. The second table generation unit 701 obtains p second address regions corresponding to p threads. Each of the p second address regions indicates a memory address that a thread is expected to access; that is, the i-th second address region among the p second address regions indicates the memory address that the i-th thread is expected to access. The second table generation unit 701 generates a second overlapping table based on the p second address regions. The second overlapping table records the degree of overlap between any two second address regions.

[0088] The second table generation unit 701 sends the second overlapping table to the thread bundle assembly unit 702. The thread bundle assembly unit 702, based on the second overlapping table and the second allocation principle, assembles p threads into at least two thread bundles, such that each thread bundle is allocated q threads. The second allocation principle includes that the overlap between the q second address regions corresponding to each thread bundle reaches a preset condition, and that the q second address regions correspond one-to-one with the q threads in each thread bundle, where p and q are both positive integers greater than or equal to 2.

[0089] In one embodiment, the second allocation principle includes ensuring that the overlap between the q second address regions corresponding to each thread bundle reaches a second threshold. In other words, the second allocation principle simultaneously guarantees that the overlap between the q second address regions corresponding to each thread bundle reaches the second threshold. In another embodiment, the second allocation principle includes ensuring that the overlap between the q second address regions corresponding to each thread bundle reaches its maximum. In this case, the second allocation principle aims to maximize the overlap between the q second address regions corresponding to each thread bundle.

[0090] In one embodiment, the second overlap table is used to record the number of address cells that intersect between any two second address regions, where each address cell includes a standard-sized address region. In another embodiment, the second overlap table is used to record the size of the intersecting address region between any two second address regions. For example, if one second address region is 0-31 and the other is 15-46, then the second overlap table is used to record the length of the intersecting address region 15-31, which is 16.

[0091] exist Figure 7 The diagram also shows a thread bundle scheduling unit 703. The thread bundle scheduling unit 703 schedules the execution order of the q thread bundles assembled by the thread bundle assembly unit 702. For example, if two thread bundles are assembled: thread bundle 0 and thread bundle 1, the thread bundle scheduling unit 703 may schedule the execution of threads in thread bundle 0 first, followed by the execution of threads in thread bundle 1; alternatively, the thread bundle scheduling unit 703 may schedule the execution of some threads in thread bundle 0 first, then some threads in thread bundle 1, and then return to continue executing threads in thread bundle 0.

[0092] exist Figure 7 The diagram also shows an arithmetic logic unit 704, which is used to execute the arithmetic logic of the threads according to the scheduled thread order. Figure 7 A read-write pipeline 705 is also shown, which is used to receive at least two thread bundles to read and write data from L1 cache 204. Figure 7 The diagram also shows a thread bundle read / write merging unit 706. The read / write pipeline 705 sends the memory access addresses of threads to the thread bundle read / write merging unit 706. The thread bundle read / write merging unit 706 combines the memory access addresses of threads belonging to the same thread bundle to obtain a thread bundle memory access address corresponding to that thread bundle. For example, it merges the memory access addresses 0-31 of thread 0 and the memory access addresses 15-45 of thread 1 into 0-45. The thread bundle read / write merging unit 706 combines at least two thread bundle memory addresses corresponding to at least two thread bundles. The thread bundle read / write merging unit 706 sends these at least two thread bundle memory addresses to the L1 cache 204. The L1 cache 204 reads and writes data according to the execution order scheduled by the thread bundle scheduling unit 703, based on these at least two thread bundle memory addresses.

[0093] In one embodiment, in conjunction with reference Figure 7The p second address regions required by the second table generation unit 701 to generate the second overlapping table are sent to the second table generation unit 701 by the read-write pipeline 705. The read-write pipeline 705 sends the p second address regions to the second table generation unit 701, and the second table generation unit 701 generates the second overlapping table based on the p second address regions. At this time, the read-write pipeline 705 outputs the p second address regions, utilizing the address output function of the read-write pipeline 705, which avoids using other hardware to output the p second address regions and reduces the hardware density on the graphics processor.

[0094] In one embodiment, the graphics processor runs a computer program and outputs the second address region corresponding to the thread. Optionally, the graphics processor runs a computer program and retrieves the second address region corresponding to the thread from the memory access addresses originally carried in the thread. The graphics processor then sends the second address region corresponding to the thread to the second table generation unit 701 through the read / write pipeline 705.

[0095] In this application, based on the degree of overlap between the p second address regions corresponding to p threads, at least two thread bundles are assembled from the p threads, such that the address overlap between the q threads in each thread bundle reaches a preset condition. As a result, the thread bundle memory access addresses output by the thread bundle read-write merging unit can be merged to a large extent, thereby reducing the transmission bandwidth of the L1 cache. At this time, the larger degree of merging of memory access addresses reduces the address that needs to be accessed, thereby increasing the L1 cache hit rate.

[0096] Second overlapping table

[0097] As described above, the second table generation unit 701 generates a second overlapping table based on p second address regions. In one embodiment, the second overlapping table is used to record the number of address cells that intersect between any two second address regions. Each address cell includes a standard-sized address region; for example, the size of each address cell is fixed at 32 bits. Optionally, the size of the address cells can be an integer or a floating-point number.

[0098] In this application, the number of intersecting address cells is used as the degree of overlap, which is beneficial for measuring the degree of overlap between two second address regions. Furthermore, the second overlap table only needs to record the number of intersecting address cells, and the amount of data that the second overlap table needs to accommodate is small, which is beneficial for the transmission and storage of the second overlap table.

[0099] In one embodiment, the address grid type includes any one of a one-dimensional address grid, a two-dimensional address grid, and a three-dimensional address grid. A one-dimensional address grid refers to a rectangular address grid, and the address value range corresponding to a rectangular address grid is a one-dimensional range. A two-dimensional address region refers to a planar address grid, and the address value range corresponding to a planar address grid is a two-dimensional value range. A three-dimensional address region refers to a volumetric address grid, and the address value range corresponding to a volumetric address grid is a three-dimensional value range. In this application, the two-dimensional address grid is mainly used for description.

[0100] For example, refer to Figure 3 , Figure 3 This can also be viewed as a schematic diagram of the overlap between the four second address regions, where M0 represents the second address region corresponding to thread 0, M1 represents the second address region corresponding to thread 1, M2 represents the second address region corresponding to thread 2, and M3 represents the second address region corresponding to thread 3. By observing... Figure 3 It can be observed that the second address region M0 intersects with M1 by two address cells, while the second address region M2 intersects with M3 by four address cells.

[0101] For example, refer to Figure 4 , Figure 4 This can also be seen as showing a second overlapping table. Figure 4 The second overlap table records the number of address cells that intersect between any two of the four second address regions. Figure 4 In the table, the M0 counter line records the number of address cells where the second address region M0 intersects with other address regions, the M1 counter line records the number of address cells where the second address region M1 intersects with other address regions, and so on. Specifically, by observing... Figure 4 It can be observed that the M0 and M1 count rows record that the second address region M0 intersects with M1 by two address cells, while the M2 and M3 count rows record that the second address region M2 intersects with M3 by four address cells.

[0102] In one embodiment, the second overlap table is further used to record the second cumulative overlap degree corresponding to each second address region. The second cumulative overlap degree refers to the sum of the overlap degrees between the second address region corresponding to the current thread and the second address regions corresponding to non-current threads out of p threads. Figure 4 As shown, Figure 4 The second overlap table also includes a total count row, which records the total number of address cells that intersect with other second address regions for each second address region. The total count row also records the total number of address cells that each of the second address regions M0, M1, M2, and M3 overlaps with address regions other than itself.

[0103] Second distribution principle

[0104] As described above, the thread bundle assembly unit 702 assembles p threads into at least two thread bundles based on the second overlapping table and the second allocation principle, such that each thread bundle is allocated q threads.

[0105] In one embodiment, the thread bundle assembly unit 702 selects threads one by one from p threads based on a second overlap table and a third selection principle to obtain a thread sequence. The third selection principle includes that among the remaining unselected threads, the second address region corresponding to the next selected thread has the highest degree of overlap with the second address region corresponding to the previous selected thread.

[0106] Indicative, continuing from the previous text Figure 3 and Figure 4 The example shown is in Figure 4 The second overlapping table shown includes second address areas M0 to M3. First, based on the total number of rows recorded, the second address area with the largest total number of overlapping cells is selected from the second address areas M0 to M3, namely the second address area M2 (M2 and M3 have the same total number of overlapping cells, so the second address area with the smaller number is selected).

[0107] Then, from the M2 counting row, from the remaining second address regions M0, M1 and M3, select the second address region with the most cells overlapping with M2, that is, the second address region M3;

[0108] Next, from the M3 counting row, from the remaining second address regions M0 and M1, select the second address region with the most overlapping cells with M3, that is, the second address region M0 (M0 and M1 have the same total number of overlapping cells, so the second address region with the smaller number M0 is selected).

[0109] Finally, the remaining second address region M1 is selected from the M0 count row.

[0110] That is, according to Figure 4 The second overlapping table shown identifies M2, M3, M0, and M1 in sequence, and the corresponding thread sequence is [Thread 2, Thread 3, Thread 0, and Thread 1].

[0111] In one embodiment, the thread bundle assembly unit 702 starts from the first thread in the thread sequence and assigns q threads to a thread bundle each time until at least two thread bundles have been assigned. Illustratively, assuming that at least two thread bundles comprise two thread bundles, each supporting two threads, then starting from the first thread in the thread sequence [thread 2, thread 3, thread 0, and thread 1], i.e., thread 2, every two threads are assigned to a thread bundle; that is, one thread bundle is assembled based on threads 2 and 3, and another thread bundle is assembled based on threads 0 and 1.

[0112] In this application, the thread bundle assembly method based on the above third selection principle can ensure that the overlap of the second address regions corresponding to the q threads in each thread bundle is maximized, thereby improving the cache hit rate. It can be understood that the above third selection principle is a greedy algorithm. When selecting the next thread, it always makes the best choice for the current thread. The greedy algorithm provides a solution to quickly find the optimal solution, ensuring that the overlap of the q second address regions corresponding to each thread bundle is maximized.

[0113] In the example described above, the thread bundle assembly unit 702 also employs the fourth selection principle.

[0114] The thread bundle assembly unit 702 selects a first target thread from p threads based on the fourth selection principle, making it the first thread in the thread sequence. The first target thread is the thread with the highest cumulative overlap among the p threads. The second cumulative overlap refers to the sum of the overlaps between the second address region corresponding to the current thread and the second address regions corresponding to non-current threads among the p threads. The current thread refers to the thread currently being targeted. For p threads, the second cumulative overlap is considered specifically for each thread. In other words, the second cumulative overlap is the sum of the overlaps between the second address region corresponding to the i-th thread and the second address regions corresponding to non-i-th threads among the p threads.

[0115] This is the process in the example above where the thread bundle assembly unit 702 determines that the first thread in the thread sequence is M2.

[0116] Understandably, the fourth selection principle provides a method to determine the first thread, which is the thread with the highest cumulative overlap. By combining the third and fourth selection principles, the overlap of the q second address regions corresponding to each thread bundle is maximized.

[0117] Thread beam scheduling

[0118] In related technologies, when performing thread bundle scheduling, the thread bundle that has existed the longest is executed first. Only after the longest-existing thread bundle has finished executing are other thread bundles executed. This scheduling method is unsuitable when there is a significant overlap in the memory access addresses of threads in the same order within at least two thread bundles, and the cache cannot simultaneously accommodate all the memory access addresses corresponding to a thread bundle.

[0119] For example, thread bundle 0 includes threads 0, 1, 2, and 3, with corresponding memory addresses R0, R1, R2, and R3, respectively; thread bundle 1 includes threads 0', 1', 2', and 3', with corresponding memory addresses R0', R1', R2', and R3', respectively; thread bundle 2 includes threads 0'', 1'', 2'', and 3'', with corresponding memory addresses R0'', R1'', R2'', and R3'', respectively; and thread bundle 3 includes threads 0''', 1''', 2''', and 3''', with corresponding memory addresses R0''', R1''', R2''', and R3''', respectively.

[0120] In related technologies, when accessing the cache, thread bundle 0 will be executed first, followed by thread bundle 1, thread bundle 2, and thread bundle 3 in sequence. At this point, when accessing the cache sequentially via the memory address, the following situation may occur:

[0121] Thread bundle 0: R0 (miss) → R1 (miss) → R2 (miss) → R3 (miss, replace R0);

[0122] Thread bundle 1: R0' (miss, replace R1) → R1' (miss, replace R2) → R2' (miss, replace R3) → R3' (miss);

[0123] Thread bundle 2: All misses;

[0124] Thread bundle 3: All misses;

[0125] In the scheduling above, when accessing memory address R0' corresponding to thread 0' in thread bundle 1, memory address R0 has already been replaced. Thread 0' in thread bundle 1 and thread 0 in thread bundle 0 are threads of the same order; they are the first threads in their respective thread bundles. If there is a large overlap between their corresponding memory addresses R0 and R0', scheduling at least two thread bundles using related techniques fails to utilize this overlap, resulting in cache misses and a low cache hit rate. Similarly, the same issue of unutilized memory address overlap exists for threads of other orders.

[0126] In one embodiment, the thread bundle scheduling unit 703 is configured to receive at least two thread bundles sent by the thread bundle assembly unit 702; and schedule at least two thread bundles based on the threads of the same order corresponding to the at least two thread bundles. Optionally, the scheduling order determined by the thread bundle scheduling unit 703 is as follows: after the threads of the same order in the at least two thread bundles have finished executing, the threads of the next order in the at least two thread bundles are then executed.

[0127] Continuing with the example above, the order of cache access using the thread beam scheduling scheme of this application is as follows:

[0128] Thread bundle 0: R0 (miss);

[0129] Thread bundle 1: R0' (partial hit);

[0130] Thread bundle 2: R0'' (partial hit);

[0131] Thread bundle 3: R0''' (partial hit);

[0132] Thread bundle 0: R1 (miss);

[0133] Thread bundle 1: R1' (partial hit);

[0134] Thread bundle 2: R1'' (partial hit);

[0135] Thread bundle 3: R1''' (partial hit);

[0136] …(The same applies to R2 and R3, and will not be listed further.)

[0137] In the above scheduling, after accessing the memory address R0 corresponding to thread bundle 0 in the cache, the memory address R0' corresponding to thread bundle 1 will be accessed, followed by the memory address R0'' corresponding to thread bundle 2, and then the memory address R0''' corresponding to thread bundle 3. In the thread bundle scheduling scheme provided in this application, for cases where the memory addresses corresponding to threads in the same order within at least two thread bundles have significant overlap, this characteristic can be utilized to improve the cache hit rate.

[0138] In one embodiment, a thread bundle includes q threads, and the second address region corresponding to one thread includes multiple second sub-address regions. A thread bundle scheduling unit 703 is configured to receive at least two thread bundles sent by a thread bundle assembly unit 702; and to schedule at least two thread bundles based on the second sub-address regions of the same order corresponding to the at least two thread bundles. Optionally, the scheduling order determined by the thread bundle scheduling unit 703 is: after the second sub-address regions of the same order are executed, the second sub-address regions of the next order are executed. In this case, thread bundles are not scheduled at the granularity of a single thread, but rather at the level of a second sub-address region corresponding to a single thread.

[0139] In one embodiment, the graphics processor runs a computer program and outputs the second address region corresponding to the thread. When scheduling at least two thread bundles consisting of p threads in the first thread block for the first thread block, the thread bundle scheduling unit 703 can use the second address regions corresponding to each of the p threads to determine whether there is a large overlap in the memory access addresses corresponding to the threads of the same order in the at least two thread bundles, and then decide whether to adopt the thread bundle scheduling scheme provided in this application.

[0140] Software program generates second address region

[0141] In one embodiment, the second address region corresponding to a thread includes multiple second sub-address regions. The graphics processor runs a computer program and outputs multiple second sub-address regions. Optionally, each second sub-address region includes at least two address segments. When the graphics processor runs the computer program, the computer program can select at least two address segments to form a second sub-address region. In one embodiment, the computer program selects at least two address segments with a high degree of overlap to form a second sub-address region. In this case, the cache hit rate corresponding to the memory access address within the second sub-address region can be improved.

[0142] In one embodiment, the thread bundle assembly unit 702 is further configured to reuse the thread bundle assembly method in the first thread block for the second thread block in the first core, and assemble at least two thread bundles in the second thread block. Specifically, the thread bundle assembly unit 702 reuses the arrangement order of p threads when assembling at least two thread bundles corresponding to the first thread block. For example, if the first thread block includes 256 threads, the first thread sequence determined by the thread bundle assembly unit 702 when assembling the thread bundles is [thread 5, thread 4, thread 101, thread 106, ..., thread 201].

[0143] The second thread block contains 256 threads. According to the order of the first thread sequence, the second thread sequence is determined as [thread 5, thread 4, thread 101, thread 106, ..., thread 201].

[0144] That is, the thread bundle assembly unit 702 is also used to assemble at least two thread bundles corresponding to the second thread block in the first core, according to the same thread order as the first thread block. In this application, for the second thread block other than the first thread block, the thread bundle assembly method corresponding to the first thread block can be reused, avoiding the reordering operation of the threads in the second thread block, thereby reducing performance overhead.

[0145] Figure 8A structural block diagram of an electronic device 800 provided in an exemplary embodiment of this application is shown. Optionally, the electronic device 800 includes a graphics processor provided in an embodiment of this application.

[0146] Optionally, the electronic device can be a portable mobile terminal, such as a smartphone, tablet, MP3 player (Moving Picture Experts Group Audio Layer III), MP4 player (Moving Picture Experts Group Audio Layer IV), laptop, or desktop computer. The electronic device 800 may also be referred to as a user device, portable terminal, laptop terminal, desktop terminal, or other names. Typically, the electronic device 800 includes a processor 801 and a memory 802.

[0147] Processor 801 may include one or more processing cores, such as a quad-core processor or an octa-core processor. Processor 801 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). Processor 801 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 801 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content required to be displayed on the screen. In some embodiments, processor 801 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0148] The memory 802 may include one or more computer-readable storage media, which may be non-transitory. The memory 802 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices.

[0149] In some embodiments, the electronic device 800 may optionally include: a peripheral device interface 803 and at least one peripheral device. Those skilled in the art will understand that... Figure 8 The structure shown does not constitute a limitation on the electronic device 800, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0150] This application also provides a processor, which includes a graphics processor as described in the above embodiments.

[0151] This application also provides a chip that includes the graphics processor described in the above embodiments.

[0152] This application also provides a graphics card that includes a graphics processor as described in the embodiments above.

[0153] This application also provides a server that includes a graphics processor as described in the embodiments above.

[0154] Figure 9 The diagram illustrates the structure of a server provided in an exemplary embodiment of this application. The server 900 includes a plurality of graphics processors 901, and at least one of the graphics processors 901 employs at least one of the thread block allocation scheme and thread bundle assembly scheme provided in this application.

[0155] This application also provides a computing cluster, which includes multiple servers, at least one of which includes the graphics processor described in the above embodiments.

Claims

1. A graphics processor, characterized in that, The graphics processor includes a first table generation unit, a thread block allocation unit, and at least two cores; The first table generation unit is used to generate a first overlapping table based on n first address regions; and send the first overlapping table to the thread block allocation unit; wherein, the i-th first address region among the n first address regions is used to indicate the memory address that the i-th thread block in the n thread blocks is expected to access, and the first overlapping table is used to record the degree of overlap between any two first address regions. The thread block allocation unit is used to allocate the n thread blocks to the at least two cores based on the first overlap table and the first allocation principle, so that each core is allocated m thread blocks. The first allocation principle includes that the overlap between the m first address regions corresponding to each core reaches a preset condition, where n and m are both positive integers greater than or equal to 2.

2. The graphics processor according to claim 1, characterized in that, The first allocation principle includes the first selection principle; The thread block allocation unit is used to select thread blocks one by one from the n thread blocks based on the first overlap table and the first selection principle to obtain a thread block sequence; the first selection principle includes that among the remaining unselected thread blocks, the first address region corresponding to the next selected thread block has the highest degree of overlap with the first address region corresponding to the previous selected thread block. The thread block allocation unit is used to allocate the m thread blocks to a core each time, starting from the first thread block in the thread block sequence, until at least two cores have been allocated.

3. The graphics processor according to claim 2, characterized in that, The first allocation principle also includes a second selection principle; The thread block allocation unit is used to select a first target thread block from the n thread blocks based on the second selection principle, and to use it as the first thread block in the thread block sequence. The first target thread block is the thread block with the largest cumulative overlap among the n thread blocks; The first cumulative overlap refers to the sum of the overlap between the first address region corresponding to the current thread block and the first address region corresponding to the non-current thread block among the n thread blocks.

4. The graphics processor according to any one of claims 1 to 3, characterized in that, The first table generation unit is used to, for any one of the n thread blocks, take the second address region corresponding to the starting thread of the thread block as the starting address region in the first address region corresponding to the thread block; In addition, the second address region corresponding to the ending thread of the thread block is used as the ending address region in the first address region corresponding to the thread block to obtain the first address region corresponding to the thread block; The second address region corresponding to the starting thread is used to indicate the memory address that the starting thread is expected to access, and the second address region corresponding to the ending thread is used to indicate the memory address that the ending thread is expected to access.

5. The graphics processor according to any one of claims 1 to 3, characterized in that, The thread block allocation unit is further configured to, when the number of thread blocks running on the target core in the at least two cores is less than the m thread blocks, determine a second target thread block from the thread blocks to be scheduled, and allocate the second target thread block to the target core; the second target thread block is the thread block with the largest first degree of overlap among the thread blocks to be scheduled; Wherein, the first degree of overlap refers to the degree of overlap between the first address region corresponding to the current thread block and the first address region corresponding to the thread block running on the target core.

6. The graphics processor according to any one of claims 1 to 3, characterized in that, The first overlapping table is used to record the number of address cells that intersect between any two first address regions, and the address cells include standard-sized address regions.

7. The graphics processor according to any one of claims 1 to 3, characterized in that, The first address region includes at least one first sub-address region, and the at least one first sub-address region includes at least one of a one-dimensional address region, a two-dimensional address region, and a three-dimensional address region.

8. A graphics processor, characterized in that, The graphics processor includes a first core, and the first core includes a second table generation unit and a thread bundle assembly unit; The second table generation unit is used to generate a second overlapping table based on p second address regions for the first thread block in the first core. The i-th second address region in the p second address regions is used to indicate the memory address that the i-th thread in the p threads included in the first thread block is expected to access. The second overlapping table is used to record the degree of overlap between any two second address regions. The second overlapping table is sent to the thread bundle assembly unit; The thread bundle assembly unit is used to assemble the p threads into at least two thread bundles based on the second overlap table and the second allocation principle, such that each thread bundle is allocated q threads. The second allocation principle includes that the overlap between the q second address regions corresponding to each thread bundle reaches a preset condition, where p and q are both positive integers greater than or equal to 2.

9. The graphics processor according to claim 8, characterized in that, The second allocation principle includes the third selection principle; The thread bundle assembly unit is used to select threads one by one from the p threads based on the second overlap table and the third selection principle to obtain a thread sequence; the third selection principle includes that among the remaining unselected threads, the second address region corresponding to the next selected thread has the highest degree of overlap with the second address region corresponding to the previous selected thread. The thread bundle assembly unit is used to assemble the q threads into a thread bundle each time, starting from the first thread in the thread sequence, to obtain the at least two thread bundles.

10. The graphics processor according to claim 9, characterized in that, The second allocation principle also includes a fourth selection principle; The thread bundle assembly unit is used to select a first target thread from the p threads based on the fourth selection principle, and to use it as the first thread in the thread sequence. The first target thread is the thread with the second highest cumulative overlap among the p threads; The second cumulative overlap refers to the sum of the overlap between the second address region corresponding to the current thread and the second address region corresponding to the non-current thread among the p threads.

11. The graphics processor according to any one of claims 8 to 10, characterized in that, The second overlapping table is used to record the number of address cells that intersect between any two second address regions, wherein the address cells include standard-sized address regions.

12. The graphics processor according to any one of claims 8 to 10, characterized in that, The first core also includes a thread beam scheduling unit; The thread bundle scheduling unit is used to receive the at least two thread bundles sent by the thread bundle assembly unit; and to schedule the at least two thread bundles based on the threads of the same order corresponding to the at least two thread bundles.

13. The graphics processor according to any one of claims 8 to 10, characterized in that, The first core also includes a read / write pipeline; the read / write pipeline is used to send the p second address regions to the second table generation unit.

14. The graphics processor according to any one of claims 8 to 10, characterized in that, The thread bundle assembly unit is further configured to reuse the thread bundle assembly method in the first thread block for the second thread block in the first core, and assemble at least two thread bundles in the second thread block.

15. The graphics processor according to any one of claims 8 to 10, characterized in that, The second address region includes at least one second sub-address region, and the at least one second sub-address region includes at least one of a one-dimensional address region, a two-dimensional address region, and a three-dimensional address region.

16. A thread block allocation method, characterized in that, The method is executed by a graphics processor, which includes a first table generation unit, a thread block allocation unit, and at least two cores. The method includes: The first table generation unit generates a first overlapping table based on n first address regions; and sends the first overlapping table to the thread block allocation unit; wherein, the i-th first address region among the n first address regions is used to indicate the memory address that the i-th thread block in the n thread blocks is expected to access, and the first overlapping table is used to record the degree of overlap between any two first address regions; The thread block allocation unit allocates the n thread blocks to the at least two cores based on the first overlap table and the first allocation principle, so that each core is allocated m thread blocks. The first allocation principle includes that the overlap between the m first address regions corresponding to each core reaches a preset condition, where n and m are both positive integers greater than or equal to 2.

17. A method for assembling thread bundles, characterized in that, The method is executed by a graphics processor, the graphics processor including a first core, the first core including a second table generation unit and a thread bundle assembly unit, the method including: The second table generation unit generates a second overlapping table for the first thread block in the first core based on p second address regions. The i-th second address region in the p second address regions is used to indicate the memory address that the i-th thread in the p threads included in the first thread block is expected to access. The second overlapping table is used to record the degree of overlap between any two second address regions. The second overlapping table is then sent to the thread bundle assembly unit. The thread bundle assembly unit assembles the p threads into at least two thread bundles based on the second overlap table and the second allocation principle, such that each thread bundle is allocated q threads. The second allocation principle includes that the overlap between the q second address regions corresponding to each thread bundle reaches a preset condition, where p and q are both positive integers greater than or equal to 2.

18. A chip, characterized in that, The chip includes a graphics processor as described in any one of claims 1 to 15.

19. A server, characterized in that, The server includes a graphics processor as described in any one of claims 1 to 15.

20. An electronic device, characterized in that, The electronic device includes a processor, the processor including a graphics processor as described in any one of claims 1 to 15.

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