Operation pulse signal control method of non-volatile memory cell

Abstract

The invention relates to an operation pulse signal control method of a nonvolatile memory cell. In step (a), a verification action is performed to obtain a first sub-state value of a memory cell. In step (b), one pulse of the operation pulse signal is generated to the memory cell. In step (c), a verification action is performed to obtain a second sub-state value of the memory cell. And when the second sub-state value represents that the memory cell does not reach the target storage state, defining an actual difference value equal to the difference between the second sub-state value and the first sub-state value, adjusting the next pulse according to the actual difference value, setting the first sub-state value to be equal to the second sub-state value, and returning to the step (b). And stopping providing the next pulse when the second sub-state value represents that the memory cell reaches the target storage state.

Description

Technical Field

[0001] The present invention relates to a control method for a non-volatile memory cell, and in particular to a method for controlling an operation pulse signal when the non-volatile memory cell performs a programming action or an erasing action. Background Art

[0002] As we all know, non-volatile memory can continue to store data even after power is lost. Therefore, non-volatile memory has been widely used in electronic products. Furthermore, non-volatile memory includes multiple non-volatile memory cells arranged in an array structure, and each non-volatile memory cell contains a floating gate transistor.

[0003] Depending on the number of times a nonvolatile memory cell can be programmed, it can be a multi-time programmable (MTP) memory cell. Alternatively, it can be a one-time programmable (OTP) memory cell. By applying an appropriate bias voltage to the array structure, any nonvolatile memory cell can be programmed, erased, or read. Summary of the Invention

[0004] The present invention relates to an operation pulse signal control method for a non-volatile memory cell, wherein the memory cell can be divided into multiple sub-states to correspond to the number of electrons stored in the memory cell. The operation pulse signal control method includes the following steps: (a) performing a verification action to obtain a first sub-state value of the memory cell; (b) generating a pulse of the operation pulse signal to the memory cell; (c) performing the verification action to obtain a second sub-state value of the memory cell; (d) when the second sub-state value represents that the memory cell has not reached a target storage state, defining an actual difference equal to the second sub-state value minus the first sub-state value; generating the next pulse according to the actual difference; setting the first sub-state value equal to the second sub-state value; and returning to step (b); and (e) when the second sub-state value represents that the memory cell has reached the target storage state, stopping providing the next pulse.

[0005] In order to better understand the above and other aspects of the present invention, preferred embodiments are given below with reference to the accompanying drawings for detailed description as follows: BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1Ais a schematic diagram of a non-volatile memory cell of the present invention;

[0007] Figure 1B A schematic diagram of bias voltage when programming a memory cell;

[0008] Figure 1C Schematic diagram of bias voltage when erasing a memory cell;

[0009] Figure 1D and Figure 1E FIG. 2 is a schematic diagram showing a bias voltage when a memory cell is read; FIG.

[0010] Figure 1F is a current comparator in the sensing circuit;

[0011] Figure 2A Schematic diagram of the operating pulse generator;

[0012] Figure 2B is a comparison table and the corresponding pulse height;

[0013] Figure 2C The operating pulse signal P generated by the operating pulse generator OP ;

[0014] Figure 3A A table of memory cell status classifications when programming actions are applied;

[0015] Figure 3B A table of memory cell status classifications when an erase operation is performed;

[0016] Figure 3C A flow chart of the operation pulse signal control method for performing an erase operation or a program operation according to the present invention;

[0017] Figure 4A Schematic diagram of the operating pulse generator;

[0018] Figure 4B This is a flow chart of the operation pulse signal control method of the present invention;

[0019] Figure 4C For the present invention Figure 4B An example of the pulse adjustment step (S458);

[0020] Figure 4D for Figure 4B and Figure 4C Practical examples of processes;

[0021] Figure 5A For the present invention Figure 4B Another example of the pulse adjustment step (S458);

[0022] Figure 5B To utilize Figure 4B and Figure 5A The first operation pulse signal P generated by the flow chart OP ;as well as

[0023] Figure 5C To utilize Figure 4B and Figure 5A The second operation pulse signal P generated by the flow chart OP .

[0024]

Explanation of symbols

[0025] 100: Memory Cell

[0026] 140: Sensing circuit

[0027] 150: Current Comparator

[0028] 200, 400: Operation pulse generator

[0029] 210, 410: Band-difference reference circuit

[0030] 220: Comparison Table

[0031] 230, 430: Controller

[0032] 420: Processor

[0033] 425: Flag register

[0034] S330~S339, S450~S459, S462~S486, S574, S586: Step Flow DETAILED DESCRIPTION

[0035] Please refer to Figure 1A , which is a schematic diagram of a non-volatile memory cell of the present invention. Hereinafter, the non-volatile memory cell is referred to as a memory cell. The memory cell 100 includes: a switch transistor M SW , select transistor M S , floating gate transistor M F , capacitor C1, capacitor C2. That is, the memory cell 100 is a memory cell with three transistors and two capacitors (3T2C memory cell). SW , select transistor M S With floating gate transistor M F The memory cell 100 is an MTP memory cell. Of course, the memory cell 100 can also be composed of p-type transistors.

[0036] Select transistor M SThe first source / drain terminal of the transistor M is connected to the source line (SL), and the transistor M is selected. S The gate terminal of the floating gate transistor M is connected to a select gate line (SGL). F The first source / drain terminal is connected to the selection transistor M S The second source / drain terminal of the switching transistor M SW The first source / drain terminal is connected to the floating gate transistor M F The second source / drain terminal of the switching transistor M SW The second source / drain terminal of the switch transistor M is connected to the bit line (BL). SW The gate terminal of the first capacitor C1 is connected to a word line (WL). The first terminal of the first capacitor C1 is connected to the floating gate transistor M F The floating gate 120 of the first capacitor C1 is connected to the control line (CL). In addition, the first end of the second capacitor C2 is connected to the floating gate transistor M. F The floating gate 120 of the capacitor C2 is connected to an erase line (EL).

[0037] Basically, by providing an appropriate bias voltage to the memory cell 100, the memory cell 100 can be programmed, erased, and read. Figure 1B , which is a schematic diagram of bias voltage when programming a memory cell. When programming a memory cell 100, a first operating voltage V OP1 To the control line CL and the erase line EL, provide a turn-on voltage V ON To the word line WL and the select gate line SGL, a ground voltage (0V) is provided to the bit line BL and the source line SL. For example, the first operating voltage V OP1 is 17V, the start voltage V ON is 2.0V, the first operating voltage V OP1 It is also called the programming voltage. Basically, during programming, the highest voltage provided to the memory cell 100 is the programming voltage.

[0038] exist Figure 1B Under the bias condition, transistor M is selected S With the switching transistor M SW At this time, FN tunneling effect (Fowler-Nordheim Tunneling effect, referred to as FN tunneling effect) occurs inside the memory cell 100, and electrons are transported from the floating gate transistor M FInjecting electrons into the floating gate 120 causes the memory cell 100 to enter a programming state. Generally speaking, when electrons are injected into the floating gate 120, the floating gate transistor M F Furthermore, the more electrons are injected into the floating gate 120, the higher the threshold voltage of the floating gate transistor M. F The higher the threshold voltage will be.

[0039] In addition, when programming, if the shutdown voltage V OFF To the word line WL and the select gate line SGL, the transistor M is selected. S With the switching transistor M SW When the device is turned off, the FN tunneling effect does not occur and electrons cannot be injected into the floating gate 120, so that the storage state of the memory cell 100 remains unchanged. OFF is 0V.

[0040] Please refer to Figure 1C , which is a schematic diagram of bias voltage when erasing the memory cell. When erasing the memory cell 100, a second operating voltage V OP2 To the erase line EL, provide a turn-on voltage V ON To the word line WL and the select gate line SGL, a ground voltage (0V) is provided to the control line CL, the bit line BL and the source line SL. For example, the second operating voltage V OP2 is 19V, the second operating voltage V OP2 It is also called the erase voltage. Basically, during the erase operation, the highest voltage provided to the memory cell 100 is the erase voltage.

[0041] exist Figure 1C Under the bias condition of , the memory cell 100 undergoes FN tunneling effect, and electrons are ejected from the floating gate 120 through the second capacitor C2 to the erase line EL, so that the memory cell 100 becomes erased. Similarly, when electrons exit the floating gate 120, the floating gate transistor M F Furthermore, the more electrons exit the floating gate 120, the greater the threshold voltage of the floating gate transistor M. F The threshold voltage will be lower.

[0042] Please refer to Figure 1D and Figure 1E , which is a schematic diagram of the bias voltage when performing a read operation on the memory cell. Figure 1F It is the current comparator in the sensing circuit.

[0043] like Figure 1D and Figure 1EAs shown, when the memory cell 100 is read, a third operating voltage V OP3 To the erase line EL and the control line CL, provide a turn-on voltage V ON To the word line WL and the select gate line SGL, provide a read voltage V READ To the bit line BL, provide the ground voltage (0V) to the source line SL. For example, the read voltage V READ Between 0V and 2V, the third operating voltage V OP3 Between 0V and 2V.

[0044] like Figure 1D As shown, in the memory cell 100 in the programmed state, the floating gate 120 stores electrons, so the floating gate transistor M F Therefore, during the reading operation, the third operating voltage V OP3 The floating gate transistor M is still not turned on by coupling to the floating gate 120. F , so the memory cell current (cell current, I CELL ) is almost equal to zero.

[0045] like Figure 1E As shown, in the erased state of the memory cell 100, the floating gate 120 does not store electrons, so the floating gate transistor M F Therefore, during the reading operation, the third operating voltage V OP3 The floating gate transistor M can be turned on by coupling to the floating gate 120. F , so the memory cell 100 generates a larger read current I CELL , for example, a memory cell current of 65μA I CELL , flows from the bit line BL to the source line SL.

[0046] In other words, the memory cell current I CELL Therefore, during the reading operation, the memory cell current I generated by the memory cell 100 can be used to determine the current level of the memory cell 100. CELL The size is used to determine the storage state of the memory cell 100. For example, Figure 1F As shown, a sensing circuit 140 is designed in the non-volatile memory, and the sensing circuit 140 includes a current comparator 150. One end of the current comparator 150 receives the memory cell current I CELL The other end of the current comparator 150 receives the reference current I REF , for example, the reference current I REF is 10μA. When the memory cell current I CELL Greater than the reference current I REF, the output signal Out of the current comparator 150 is at a first logic level (eg, a high logic level), indicating that the memory cell 100 is in an erased state. On the contrary, when the memory cell current I CELL Less than the reference current I REF , the output signal Out of the current comparator 150 is at a second logic level (eg, a low logic level), indicating that the memory cell 100 is in a programmed state.

[0047] In the above description, during the programming operation of the memory cell 100, a fixed first operating voltage V OP1 To the control line CL and the erase line EL. During the erase operation of the memory cell 100, a fixed second operating voltage V OP2 To the erase line EL.

[0048] Of course, the present invention can also design an operation pulse generator in the non-volatile memory. The operation pulse generator can provide an operation pulse signal (P OP ) to the memory cell 100. In the following description, the operation pulse signal P OP It is used for the erase operation of the memory cell 100. Of course, the operation pulse signal P OP It can also be applied to the programming operation of the memory cell 100 .

[0049] Please refer to Figure 2A , which shows a schematic diagram of an operating pulse generator. Figure 2B It is a lookup table and the corresponding pulse height. Figure 2C The operating pulse signal P generated by the operating pulse generator OP .

[0050] like Figure 2A As shown, the operating pulse generator 200 includes a bandgap reference circuit 210, a lookup table 220, and a controller 230. The controller 230 receives the reference voltage V outputted by the bandgap reference circuit 210. REF The controller 230 is further connected to the lookup table 220 to receive a multiple value N. The lookup table 220 is stored in a memory, and the multiple value N is a positive number.

[0051] Basically, the controller 230 can be configured to generate a voltage according to the reference voltage V REFAnd the multiple value N to generate the operating pulse signal P OP For example, the controller 230 includes a charge pump that can generate (N×V REF ) of the pulse height. In addition, in this embodiment, all pulses P1~P 15 They are set to have the same pulse period and pulse width.

[0052] For example, the pulse period of the first pulse P1 is (T1+T2), the pulse width is T1, and both T1 and T2 are 10 ms. Of course, in other embodiments, the pulse period and pulse width of each pulse can be set according to actual needs. For example, the pulse period and pulse width of each pulse can be set in the reference table 220 so that the controller 230 generates the corresponding operation pulse signal P OP .

[0053] like Figure 2B and Figure 2C As shown, the reference voltage V REF is 1.2V, and the operating pulse signal P OP It can include up to 15 pulses P1~P 15 When actually performing the erasing operation, the operating pulse signal P OP Can be less than 15 pulses (pulse) P1~P 15 .

[0054] According to the comparison table 220, the pulse heights of the first pulse P1 and the second pulse P2 generated by the operating pulse generator 200 are 14.4V (12×1.2V), the pulse heights of the third pulse P3 and the fourth pulse P4 are 15.6V, the pulse heights of the fifth pulse P5 and the sixth pulse P6 are 16.8V, the pulse heights of the seventh pulse P7 and the eighth pulse P8 are 18.0V, and the pulse heights of the ninth pulse P9 to the fifteenth pulse P1 are 18.0V. 15 The pulse height is 19.2V.

[0055] During the erase operation, after the controller 230 of the pulse generator 200 generates a pulse to the memory cell 100, the sensing circuit in the non-volatile memory can immediately perform a verification operation to determine whether the memory cell 100 has reached the erase state. If the memory cell 100 has not yet reached the erase state, the controller 230 continues to generate the next pulse. On the contrary, if the memory cell 100 has reached the erase state, the controller 230 receives an activated verification pass signal (S PASS), indicating that the erase operation is completed, the controller 230 stops generating the next pulse.

[0056] exist Figure 2C In the erase operation time period T1, the controller 230 of the operation pulse generator 200 generates a first pulse P1 to the erase line EL of the memory cell 100. Thereafter, a verification operation is performed in the erase operation time period T2. At this time, the current comparator 150 of the sensing circuit 140 receives the read current (or memory cell current I CELL ) to determine whether the memory cell 100 has reached the erase state. If the memory cell 100 has not reached the erase state, the controller 230 continues to generate the second pulse P2 to the erase line EL. On the contrary, if the memory cell 100 has reached the erase state, it means that the erase operation is completed, and the controller 230 no longer generates the second pulse P2. In other words, when the operating pulse signal P OP During the time period between the two pulses of , the sensing circuit 140 performs a verification operation. Basically, the manner in which the sensing circuit 140 performs the verification operation is similar to the reading operation, and will not be described in detail here.

[0057] like Figure 2C As shown, the controller 230 of the operating pulse generator 200 outputs the 11th pulse P 11 After that, at time point T A To time point T B Verification action is performed between the two and the verification passes the signal S PASS Therefore, the operation pulse generator 200 no longer generates the following four pulses P 12 ~P 15 That is, the operation pulse signal P OP Using 11 pulses P1~P 11 The erasing operation is completed.

[0058] From the above description, it can be seen that when the memory cell 100 is erased, the operating pulse generator 200 provides the operating pulse signal P OP The memory cell 100 undergoes FN tunneling, and electrons are ejected from the floating gate 120 through the second capacitor C2 to the erase line EL, so that the memory cell 100 enters an erase state.

[0059] Similarly, the present invention can also set another operation pulse signal multiple value N in the reference table 220 and apply it to the programming operation. The same operating principle applies. When the memory cell 100 performs the programming operation, the operation pulse generator 200 provides another operation pulse signal P OPTo the control line CL and the erase line EL. Therefore, FN tunneling effect occurs inside the memory cell 100, and electrons pass through the floating gate transistor M F The floating gate 120 is injected, so that the memory cell 100 is in a programmed state.

[0060] Compared to providing a fixed first operating voltage V OP1 and the second operating voltage V OP2 To the memory cell 100. Using the operation pulse signal P OP Performing programming and erasing operations on the memory cell 100 can improve programming efficiency and erasing efficiency.

[0061] However, in the operating pulse generator 200, the reference voltage V generated by the band difference reference circuit 210 is REF There may be variations to varying degrees, or a failure of the bandgap reference circuit 210 may occur. When the bandgap reference circuit 210 fails, the memory cell 100 may be damaged, or programming failure or erasing failure may occur.

[0062] by Figure 2B For example, due to process variation, the reference voltage V output by the band-gap reference circuit 210 may be REF Slightly reduce, for example, reduce to 1.15V. During the erase operation, the operating pulse signal P OP The maximum pulse height is only 18.4V (16×1.15V). OP If the pulse height is not high enough, all electrons may not be able to exit the floating gate 120, resulting in erase failure. OP If the pulse height is not high enough, the number of electrons injected into the floating gate 120 may be insufficient, resulting in programming failure.

[0063] In addition, due to process variations, the reference voltage V output by the band-gap reference circuit 210 may vary. REF Slightly increase, for example, to 1.30V. During the erase operation, the operating pulse signal P OP The maximum pulse height will reach 20.8V (16×1.30V). OP The pulse height of the operating pulse signal P is too high, and the voltage stress on the memory cell 100 is too high, causing the memory cell 100 to be damaged. OP The pulse height is too high, and the voltage stress on the memory cell 100 is too great, causing the memory cell 100 to be damaged.

[0064] In order to solve the problem of using the lookup table 220 to generate the operation pulse signal P OPThe present invention proposes an operation pulse signal P for a non-volatile memory cell. OP Control method. The present invention determines the state changes of the memory cell 100 before and after receiving a pulse, and dynamically adjusts the pulse height or pulse width of the next pulse based on the state changes. The present invention is described in detail below. In the following description, the erase operation of the memory cell 100 is used as an example. Of course, the present invention can also be applied to the programming operation of the memory cell 100.

[0065] As can be seen from the above description, when the memory cell 100 is in the programming state, the floating gate transistor M F The floating gate transistor M120 stores enough electrons, so the threshold voltage is high and it is not easy to turn on. F The floating gate 120 does not store electrons or stores relatively few electrons, so the threshold voltage is low and it is easy to turn on. Therefore, the present invention further distinguishes multiple sub-states between the programmed state and the erased state according to the amount of electrons stored in the memory cell 100.

[0066] Basically, the operation of the read operation is similar to that of the verification operation. During the verification operation, the present invention changes the third operating voltage V OP3 Furthermore, the sensing circuit is based on the memory cell current I CELL To divide the memory cell into one of the 8 sub-states. When verifying the action, similar to Figure 1D and Figure 1E In the bias mode, the source line SL of the memory cell 100 receives the ground voltage (0V), and the bit line BL receives the read voltage V READ , select gate line SGL and word line WL to receive turn-on voltage V ON , only the third operating voltage V OP3 will change.

[0067] Please refer to Figure 3A , which shows the memory cell status classification table when using programming action. Figure 3B , which shows a memory cell state classification table when an erase operation is performed.

[0068] like Figure 3A As shown, when the third operating voltage V OP3 is 2.4V and the memory cell current I generated by the memory cell 100 CELLWhen the voltage is less than 2 μA, the memory cell 100 is classified as the seventh sub-state (sub_ST=7), and the sub-state value is equal to 7. When the memory cell 100 is in the seventh sub-state (sub_ST=7), it means that the memory cell 100 is in the target storage state, that is, the programming state (PGM).

[0069] When the third operating voltage V OP3 is 2.4V and the memory cell current I generated by the memory cell 100 CELL When the third operating voltage V OP3 is 1.6V and the memory cell current I generated by the memory cell 100 CELL When the current is less than 2 μA, the memory cell 100 is classified as the sixth sub-state (sub_ST=6). The sub-state value is equal to 6, which means that the memory cell 100 has not reached the target storage state.

[0070] When the third operating voltage V OP3 is 1.6V and the memory cell current I generated by the memory cell 100 CELL When the third operating voltage V OP3 is 0.8V and the memory cell current I generated by the memory cell 100 CELL When the current is less than 2 μA, the memory cell 100 is classified as the fifth sub-state (sub_ST=5), and the sub-state value is equal to 5, which means that the memory cell 100 has not reached the target storage state.

[0071] When the third operating voltage V OP3 is 0.8V and the memory cell current I generated by the memory cell 100 CELL When the third operating voltage V OP3 is 0V and the memory cell current I generated by the memory cell 100 CELL When the current is less than 2 μA, the memory cell 100 is classified as the fourth sub-state (sub_ST=4). The sub-state value is equal to 4, which means that the memory cell 100 has not reached the target storage state.

[0072] When the third operating voltage V OP3 is 0V and the memory cell current I generated by the memory cell 100 CELL When the current is greater than 2 μA and less than 20 μA, the memory cell 100 is classified as the third sub-state (sub_ST=3). The sub-state value is equal to 3, which means that the memory cell 100 has not reached the target storage state.

[0073] When the third operating voltage V OP3 is 0V and the memory cell current I generated by the memory cell 100 CELLWhen the current is greater than 20 μA and less than 40 μA, the memory cell 100 is classified as the second sub-state (sub_ST=2). The sub-state value is equal to 2, which means that the memory cell 100 has not reached the target storage state.

[0074] When the third operating voltage V OP3 is 0V and the memory cell current I generated by the memory cell 100 CELL When the current is greater than 40 μA and less than 60 μA, the memory cell 100 is classified as the first sub-state (sub_ST=1). The sub-state value is equal to 1, which means that the memory cell 100 has not reached the target storage state.

[0075] When the third operating voltage V OP3 is 0V and the memory cell current I generated by the memory cell 100 CELL When the voltage is greater than 60 μA, the memory cell 100 is classified as sub-state 0 (sub_ST=0), and the sub-state value is equal to 0. When the memory cell 100 is in sub-state 0 (sub_ST=0), it means that the memory cell 100 is in the erased state (ERS), which means that the memory cell 100 has not reached the target storage state.

[0076] That is, during the verification operation, according to the third operating voltage V OP3 The memory cell current I CELL That is, the sub-state of the memory cell 100 can be determined.

[0077] like Figure 3B As shown, the word state classification table used for the erase action is similar to Figure 3A , only the numerical differences of the sub-states are different. The following explains it.

[0078] like Figure 3B As shown, the target storage state here is the erase state. When the third operating voltage V OP3 is 2.4V and the memory cell current I generated by the memory cell 100 CELL When the voltage is less than 2 μA, the memory cell 100 is classified as the 0th sub-state (sub_ST=0), and the sub-state value is equal to 0. When the memory cell 100 is in the 0th sub-state (sub_ST=0), it means that the memory cell 100 is in the programming state (PGM).

[0079] When the third operating voltage V OP3 is 2.4V and the memory cell current I generated by the memory cell 100 CELL When the third operating voltage V OP3 is 1.6V and the memory cell current I generated by the memory cell 100 CELLWhen the current is less than 2 μA, the memory cell 100 is classified as the first sub-state (sub_ST=1), and the sub-state value is equal to 1, which means that the memory cell 100 has not reached the target storage state.

[0080] When the third operating voltage V OP3 is 1.6V and the memory cell current I generated by the memory cell 100 CELL When the third operating voltage V OP3 is 0.8V and the memory cell current I generated by the memory cell 100 CELL When the current is less than 2 μA, the memory cell 100 is classified as the second sub-state (sub_ST=2), and the sub-state value is equal to 2, which means that the memory cell 100 has not reached the target storage state.

[0081] When the third operating voltage V OP3 is 0.8V and the memory cell current I generated by the memory cell 100 CELL When the third operating voltage V OP3 is 0V and the memory cell current I generated by the memory cell 100 CELL When the current is less than 2 μA, the memory cell 100 is classified as the third sub-state (sub_ST=3). The sub-state value is equal to 3, which means that the memory cell 100 has not reached the target storage state.

[0082] When the third operating voltage V OP3 is 0V and the memory cell current I generated by the memory cell 100 CELL When the current is greater than 2 μA and less than 20 μA, the memory cell 100 is classified as the fourth sub-state (sub_ST=4). The sub-state value is equal to 4, which means that the memory cell 100 has not reached the target storage state.

[0083] When the third operating voltage V OP3 is 0V and the memory cell current I generated by the memory cell 100 CELL When the current is greater than 20 μA and less than 40 μA, the memory cell 100 is classified as the fifth sub-state (sub_ST=5). The sub-state value is equal to 5, which means that the memory cell 100 has not reached the target storage state.

[0084] When the third operating voltage V OP3 is 0V and the memory cell current I generated by the memory cell 100 CELL When the current is greater than 40 μA and less than 60 μA, the memory cell 100 is classified as the sixth sub-state (sub_ST=6). The sub-state value is equal to 6, which means that the memory cell 100 has not reached the target storage state.

[0085] When the third operating voltage V OP3is 0V and the memory cell current I generated by the memory cell 100 CELL When the voltage is greater than 60 μA, the memory cell 100 is classified as the seventh sub-state (sub_ST=7), and the sub-state value is equal to 7. When the memory cell 100 is in the seventh sub-state (sub_ST=7), it means that the memory cell 100 has reached the target storage state, namely the erased state (ERS).

[0086] Please refer to Figure 3C , which shows a flow chart of the operation pulse signal control method when performing an erase operation or a programming operation of the present invention. When performing an erase operation, the target storage state is the erase state. Therefore, when the erase operation starts, a verification operation is first performed to obtain the sub-state value of the memory cell 100, and this sub-state value is set to BF (step S330) as the initial operation. In other words, the value stored in BF is the sub-state value of the memory cell 100 before the pulse is provided. Afterwards, a pulse is provided to the memory cell 100 (step S332). Then, a verification operation is performed again to obtain the sub-state value of the memory cell 100, and this sub-state value is set to AF (step S334). In other words, the value stored in AF is the sub-state value of the memory cell 100 after the pulse is provided.

[0087] Next, it is determined whether AF is equal to 7 (step S336). In other words, it is determined whether the memory cell 100 has reached the target storage state (erased state). If AF is equal to 7, it means that the memory cell 100 has reached the target storage state (erased state), and the erase operation is confirmed to be complete, and the erase operation ends.

[0088] On the other hand, if AF is not equal to 7, it means that the memory cell 100 has not yet reached the target storage state (erased state). At this time, the actual difference Z is defined as the difference between AF and BF (AF-BF), and the next pulse is adjusted according to the actual difference Z (step S338). Then, BF is set equal to AF (step S339), and step S332 is continued. In this embodiment, the actual difference Z represents the difference between the sub-states before and after the memory cell 100 receives a pulse. In addition, the present invention further adjusts the pulse height (N) and pulse width of the next pulse according to the actual difference Z. Of course, it is also possible to adjust only the pulse height of the next pulse or only the pulse width of the next pulse.

[0089] For example, when the actual difference Z is large, such as when the actual difference Z is greater than or equal to 3, it indicates that the pulse can cause a large change in the sub-state of the memory cell 100. Therefore, the pulse height or pulse width of the next pulse can be reduced. Conversely, when the actual difference Z is small, such as when the actual difference Z is less than or equal to 2, it indicates that the pulse causes a small change in the sub-state of the memory cell 100. In this case, the pulse height or pulse width of the next pulse can be increased or maintained.

[0090] Similarly, Figure 3C The flowchart of the operation pulse signal control method can also be applied to programming operations. In this case, the target storage state is the programming state. The detailed operation of the programming operation will not be repeated here.

[0091] When performing the erase operation, adjust the operating pulse signal P OP The pulse height of the pulse is taken as an example to introduce the operating pulse generator and the control method of the operating pulse signal of the present invention in detail. Figure 4A , which shows a schematic diagram of an operating pulse generator. Figure 4B This is a flow chart of the operation pulse signal control method of the present invention.

[0092] like Figure 4A As shown, the operating pulse generator 400 includes a band difference reference circuit 410, a processor 420 and a controller 430. The controller 430 receives the reference voltage V output by the band difference reference circuit 410. REF Furthermore, the processor 420 receives the sub-state signal Sub_ST to determine the sub-state value of the memory cell 100. Furthermore, the processor 420 generates a multiplier value N and a ratio value R to the controller 430. That is, during the verification operation, the processing circuit 420 can receive the sensing circuit 140 ( Figure 1F ) to confirm the sub-state of the memory cell 100. Furthermore, the processor 420 further includes a flag register 425 therein.

[0093] The controller 430 generates a voltage according to the reference voltage V REF And the multiple value N, the ratio value R to generate the operating pulse signal P OP For example, the controller 430 includes a charge pump that can generate (N×R×V REF In addition, when the sub-state signal Sub_ST is equal to the target storage state, the processor 420 may further activate the verification pass signal S PASS , causing the controller 430 to stop generating the next pulse.

[0094] like Figure 4B As shown, at the beginning of the erase operation, the processor 420 provides an initial multiple value N and an initial ratio value R (step S450). Next, a verification operation is performed to obtain the sub-state value of the memory cell 100, and this sub-state value is set to BF (step S451). Of course, steps S450 and S451 can be swapped.

[0095] Then, the controller 430 generates a pulse to the memory cell 100 according to the multiplication value N and the ratio value R (step S452 ). Next, a verification operation is performed to obtain the sub-state value of the memory cell 100 and the sub-state value is set to AF (step S454 ).

[0096] Next, it is determined whether AF is equal to 7 (step S456). That is, it is determined whether the memory cell 100 has reached the target storage state (erased state). If AF is equal to 7, it means that the memory cell 100 has reached the target storage state (erased state), and the processor 420 acts to verify the pass signal S PASS , indicating that the erase operation is completed, the controller 430 stops generating the next pulse and ends the erase operation.

[0097] Conversely, if AF is not equal to 7, it means that the memory cell 100 has not yet reached the target storage state (erased state). In this case, the actual difference Z is set equal to the difference between AF and BF (AF-BF), and the multiplication value N and the ratio value R are adjusted based on the actual difference Z (step S458). Next, BF is set equal to AF (step S459), and step S452 is performed.

[0098] From the above description, it can be seen that the present invention will determine the state change of the memory cell 100 before and after receiving a pulse, and then dynamically adjust the pulse height or pulse width of the next pulse according to the magnitude of the state change. The pulse adjustment step (step S458) of the present invention is introduced below using the adjustment of the pulse height as an example. Please refer to Figure 4C , which illustrates the present invention Figure 4B An example of the pulse adjustment step (S458).

[0099] When entering the pulse adjustment step (step S458), it is first determined whether flag register 425 has been set (step S462). The initial value of flag register 425 is "0," indicating that flag register 425 has not been set. A value of "1" stored in flag register 425 indicates that flag register 425 has been set. According to an embodiment of the present invention, when flag register 425 is set, it indicates that the pulse height of the current pulse is sufficient. Therefore, subsequent fine-tuning of the pulse height is sufficient to gradually achieve the target state of memory cell 100.

[0100] If the flag register 425 has not been set (step S462), a determination is made as to whether the actual difference Z is less than a predetermined difference X (step S464). If the actual difference Z is less than the predetermined difference X, this indicates that the pulse height of the previous pulse was insufficient to significantly change the state of the memory cell 100. Therefore, the multiplier value N and the ratio value R are increased (step S466) to increase the pulse height of the next pulse.

[0101] In addition, when the flag register 425 has not been set and the actual difference Z is greater than or equal to the preset difference X, it means that the pulse height of the previous pulse is sufficient to cause a significant change in the state of the memory cell 100. Therefore, it is only necessary to fine-tune the pulse height in the future, and allow the state of the memory cell 100 to gradually reach the target state. At this time, the flag register 425 is set (step S468). Then, when it is determined that the actual difference Z is equal to the preset difference X (step S470), the multiplier value N is maintained and the ratio value R is maintained (step S472). When it is determined that the actual difference Z is greater than the preset difference X (step S470), the multiplier value N is maintained and the ratio value R is reduced (step S474).

[0102] Furthermore, steps S468 and S470 can be swapped. That is, after first confirming that the actual difference Z is equal to the preset difference X (step S470), flag register 425 is set (step S468), and step S472 is performed. Alternatively, after first confirming that the actual difference Z is greater than the preset difference X (step S470), flag register 420 is set (step S468), and step S474 is performed. Furthermore, steps S468 and S472 can be combined into a single step. Similarly, steps S468 and S474 can be combined into a single step.

[0103] According to an embodiment of the present invention, after confirming in step S462 that the flag register 425 has been set, the pulse height of the next pulse is adjusted according to the actual difference Z (step S480). When the actual difference Z is less than the preset difference X, the multiplier value N is maintained and the proportional value R is increased (step S482). When the actual difference Z is equal to the preset difference X, the multiplier value N is maintained and the proportional value R is maintained (step S484). When the actual difference Z is greater than the preset difference X, the multiplier value N is maintained and the proportional value R is decreased (step S486).

[0104] The following Figure 4D A practical example Figure 4B and Figure 4C In the process. Figure 4D In the reference voltage V REFThe voltage is 1.3V, the initial multiple value N is 12, the initial ratio value R is 0.9, the preset difference value X is set to 2, the multiple value N increases by 1 each time, and the ratio value R increases or decreases by an offset (offset, 0) each time, for example, the offset is equal to 0.025.

[0105] like Figure 4D As shown, before the operating pulse generator 400 generates the first pulse P1, that is, before time t1, a verify operation is performed to confirm that the sub-state value of the memory cell 100 is 0 (programmed state) and BF is set to 0. Then, based on the multiplication value N (N=12) and the initial ratio value R (R=0.9), the operating pulse generator 400 generates the first pulse P1 with a pulse height of 14.04V (12×0.9×1.3V) to the memory cell 100 between time t1 and time t2. After time t2, a verify operation is performed again to confirm that the sub-state value of the memory cell 100 is 0 and AF is set to 0.

[0106] Because AF is equal to 0, the memory cell 100 has not yet reached the target storage state (erase state), and the erase operation is not yet complete. Therefore, the operating pulse generator 400 needs to adjust and generate a second pulse P2 to the memory cell 100. Furthermore, because the actual difference Z is equal to 0, which is less than the preset difference X (X=2), the multiplier value N is increased by 1 (to N=13), and the ratio value R is increased by 0.025 (to R=0.925), setting BF equal to AF. Next, based on the multiplier value N (N=13) and the ratio value R (R=0.925), the operating pulse generator 400 generates a second pulse P2 with a pulse height of 15.6325V (13×0.925×1.3V) to the memory cell 100 between time points t3 and t4. After time point t4, a verify operation is performed to confirm that the sub-state value of the memory cell 100 is 0, and AF is set equal to 0.

[0107] Because AF is equal to 0, the memory cell has not yet reached the target storage state (erase state), and the erase operation has not yet completed. Therefore, the operating pulse generator 400 needs to adjust and generate a third pulse P3 to the memory cell 100. Furthermore, because the actual difference Z is equal to 0, which is less than the preset difference X (X=2), the multiplier value N is increased by 1 (to N=14), and the ratio value R is increased by 0.025 (to R=0.95), setting BF equal to AF. Next, based on the multiplier value N (N=14) and the ratio value R (R=0.95), the operating pulse generator 400 generates a third pulse P3 with a pulse height of 17.29V (14×0.95×1.3V) to the memory cell 100 between time points t5 and t6. After time point t6, a verify operation is performed to confirm that the sub-state value of the memory cell 100 is 0, and AF is set equal to 0.

[0108] Since AF is equal to 0, the memory cell has not yet reached the target storage state (erase state), and the erase operation has not yet completed. Therefore, the operating pulse generator 400 needs to adjust and generate the fourth pulse P4 to the memory cell 100. Furthermore, since the actual difference Z is equal to 0, which is less than the preset difference X (X=2), the multiplier value N is increased by 1 (to N=15) and the ratio value R is increased by 0.025 (to R=0.975), setting BF equal to AF. Next, based on the multiplier value N (N=15) and the ratio value R (R=0.975), the operating pulse generator 400 generates the fourth pulse P4 with a pulse height of 19.0125V (15×0.975×1.3V) to the memory cell 100 between time points t7 and t8. After time point t8, a verify operation is performed to confirm that the sub-state value of the memory cell 100 is 3, and AF is set equal to 3.

[0109] Since AF is equal to 3, the memory cell has not yet reached the target storage state (erased state), and the erase operation has not yet ended. That is, the operating pulse generator 400 needs to adjust and generate the fifth pulse P5 to the memory cell 100. In addition, since the actual difference Z is equal to 3, which is greater than the preset difference X (X=2), the flag register 425 is set (Flag=1), indicating that a suitable pulse height has been found, and only fine-tuning of the pulse height is required in the future. Furthermore, since the actual difference Z is greater than the preset difference X (Z>X), the multiplier value N remains unchanged (N=15), and the proportional value R is reduced by 0.025 (becoming R=0.95), and BF is set equal to AF. Then, according to the multiplier value N (N=15) and the proportional value R (R=0.95), the operating pulse generator 400 operates at time point t9 and time point t 10 Between t and t, a fifth pulse P5 with a pulse height of 18.525V (15×0.95×1.3V) is generated to the memory cell 100. At time point t 10 Afterwards, a verification operation is performed to confirm that the sub-state value of the memory cell 100 is 5, and AF is set to 5.

[0110] Since AF is equal to 5, the memory cell has not yet reached the target storage state (erase state), and the erase operation has not yet ended. That is, the operating pulse generator 400 needs to adjust and generate the sixth pulse P6 to the memory cell 100. In addition, since the flag register 425 has been set (Flag=1) and the actual difference Z is equal to 2, which is equal to the preset difference X (X=2), the multiplier value N remains unchanged (N=15) and the ratio value R remains unchanged (R=0.95), and BF is set equal to AF. Then, according to the multiplier value N (N=15) and the ratio value R (R=0.95), the operating pulse generator 400 at time point t 11 At time t 12Between t and t, a sixth pulse P6 with a pulse height of 18.525V (15×0.95×1.3V) is generated to the memory cell 100. At time point t 12 Afterwards, a verification operation is performed to confirm that the sub-state value of the memory cell 100 is 6, and AF is set to 6.

[0111] Since AF is equal to 6, the memory cell has not yet reached the target storage state (erase state), and the erase operation has not yet ended. That is, the operating pulse generator 400 needs to adjust and generate the seventh pulse P7 to the memory cell 100. In addition, since the flag register 425 has been set (Flag=1) and the actual difference Z is equal to 1, which is less than the preset difference X (X=2), the multiplier value N remains unchanged (N=15), and the proportional value R increases (R=0.975), setting BF equal to AF. Then, according to the multiplier value N (N=15) and the proportional value R (R=0.975), the operating pulse generator 400 at time point t 13 At time t 14 Between t and t, a seventh pulse P7 with a pulse height of 19.0125V (15×0.975×1.3V) is generated to the memory cell 100. At time point t 14 After that, the verification operation is performed to confirm that the sub-state value of the memory cell 100 is 7, and AF is set to 7, indicating that the memory cell 100 has reached the target storage state (erased state). Therefore, the processor 420 performs the verification operation to pass the signal S PASS , indicating that the erase operation is completed, the controller 430 stops generating the next pulse and ends the erase operation.

[0112] Depend on Figure 4D The operation pulse signal P OP As can be seen, before the flag register 425 is set, the pulse heights of pulses P1-P4 rise rapidly and reach the appropriate pulse height for the erase operation. After the flag register 425 is set, the pulse heights of pulses P5-P7 change smoothly, allowing the memory cell 100 to gradually reach the target state.

[0113] certainly, Figure 4D The pulse widths of the pulses P1-P4 can also be selectively adjusted based on the contents of flag register 425. For example, before flag register 425 is set, the pulse widths of pulses P1-P4 are relatively narrow (e.g., 8 ms). After flag register 425 is set, the pulse widths of pulses P5-P7 are relatively wide (e.g., 12 ms). In other words, after flag register 425 of processor 420 is set, controller 430 can further increase the pulse widths of subsequent pulses.

[0114] according to Figure 4CIn the operation flow, the ratio value R is decreased in step S474 and step S486. In fact, an adjustment function of the ratio value R can also be set in this step so that the ratio value R can be increased or decreased.

[0115] Please refer to Figure 5A , which illustrates the present invention Figure 4B Another example of the pulse adjustment step (S458). Figure 4C The difference lies only in step S574 and step S586. Only step S574 and step S586 are described below, and the rest are not repeated here.

[0116] like Figure 5A As shown, during the pulse adjustment step (step S458), when it is confirmed that the actual difference Z is greater than the preset difference X, step S574 or step S586 is performed. When performing step S574 or step S586, the multiplication value N is maintained and the ratio value R is modified according to the adjustment function. Figure 5B and Figure 5C Let's introduce the operation pulse signal P generated by the two adjustment functions. OP , and applied to the erase action.

[0117] Please refer to Figure 5B , which is used Figure 4B and Figure 5A The first operation pulse signal P generated by the flow chart OP .exist Figure 5B In the reference voltage V REF The voltage is 1.3V, the initial multiplier value N is 12, the initial scale value R is 0.9, the preset difference value X is set to 2, and each time the multiplier value N increases by 1, the scale value R increases by an offset (O), that is, the value of the scale value R increases or decreases each time. For example, the offset is equal to 0.025. In addition, the adjustment function of the scale value R is [R+(YZ)×O]. According to the adjustment function, the modified scale value R is equal to the result of subtracting the actual difference value Z from the preset adjustment parameter (Y), multiplied by the offset O, and then added to the original scale value R. Among them, Y is the adjustment parameter, and the adjustment parameter Y can be used to change the adjustment range of the scale value R, and the adjustment parameter Y is pre-set in the processor 420. The following is an example of the adjustment parameter Y being 4.

[0118] Basically, in Figure 5B In the figure, the four pulses P1 to P4 before time point t8 are the same as Figure 4D Furthermore, after time point t8, a verification operation is performed to confirm that the sub-state value of the memory cell 100 is 3, and AF is set to 3.

[0119] Since AF is equal to 3, the memory cell has not yet reached the target storage state (erase state), and the erase operation has not yet ended. That is, the operating pulse generator 400 needs to adjust and generate the fifth pulse P5 to the memory cell 100. In addition, since the actual difference Z is equal to 3, which is greater than the preset difference X (X=2), the flag register 425 is set (Flag=1), indicating that a suitable pulse height has been found, and only fine-tuning of the pulse height is required subsequently. Furthermore, since the actual difference Z is greater than the preset difference X (Z>X), the multiplier value N remains unchanged (N=15). In addition, according to the adjustment function, the corrected proportional value R is 1, that is, [0.975+(4-3)×0.025]. Next, BF is set equal to AF. Afterwards, according to the multiplier value N (N=15) and the proportional value R (R=1), the operating pulse generator 400 operates at time point t9 and time point t 10 Between t and t, a fifth pulse P5 with a pulse height of 19.5V (15×1×1.3V) is generated to the memory cell 100. At time t 10 Afterwards, a verification operation is performed to confirm that the sub-state value of the memory cell 100 is 6, and AF is set to 6.

[0120] Since AF is equal to 6, the memory cell has not yet reached the target storage state (erased state), and the erase operation has not yet ended. That is, the operating pulse generator 400 needs to adjust and generate the sixth pulse P6 to the memory cell 100. In addition, since the flag register 425 has been set (Flag=1) and the actual difference Z is equal to 3, which is greater than the preset difference X (X=2), the multiplier value N remains unchanged (N=15). In addition, according to the adjustment function, the corrected proportional value R is 1.025, that is, [1+(4-3)×0.025]. Next, BF is set equal to AF. Afterwards, according to the multiplier value N (N=15) and the proportional value R (R=1.025), the operating pulse generator 400 is at time point t 11 At time t 12 Between t and t, a sixth pulse P6 with a pulse height of 19.9875V (15×1.025×1.3V) is generated to the memory cell 100. At time point t 12 After that, the verification operation is performed to confirm that the sub-state value of the memory cell 100 is 7, and AF is set to 7, indicating that the memory cell 100 has reached the target storage state (erased state). Therefore, the processor 420 performs the verification operation to pass the signal S PASS , indicating that the erase operation is completed, the controller 430 stops generating the next pulse and ends the erase operation.

[0121] Please refer to Figure 5C , which is used Figure 4B and Figure 5A The second operation pulse signal P generated by the flow chartOP .exist Figure 5C In the reference voltage V REF The initial multiplier N is 12, the initial scale R is 0.9, the default difference X is set to 2, and each time the multiplier N increases by 1, the scale R increases by 0.025. Furthermore, the adjustment function for scale R is [R + (YZ) × O]. The adjustment parameter Y is equal to the difference between the target storage state value and the current sub-state, that is, (7-AF).

[0122] Basically, in Figure 5C In the figure, the four pulses P1 to P4 before time point t8 are the same as Figure 4D Furthermore, after time point t8, a verification operation is performed to confirm that the sub-state value of the memory cell 100 is 3, and AF is set to 3.

[0123] Since AF is equal to 3, the memory cell has not yet reached the target storage state (erased state), and the erase operation has not yet ended. That is, the operating pulse generator 400 needs to adjust and generate the fifth pulse P5 to the memory cell 100. In addition, since the actual difference Z is equal to 3, which is greater than the preset difference X (X=2), the flag register 425 is set (Flag=1), indicating that a suitable pulse height has been found, and only fine-tuning of the pulse height is required subsequently. Since the actual difference Z is greater than the preset difference X (Z>X), the multiplier value N remains unchanged (N=15). In addition, according to the adjustment function, the corrected proportional value R is 1, that is, {0.975+[(7-3)-3]×0.025}. Next, BF is set equal to AF. Afterwards, according to the multiplier value N (N=15) and the proportional value R (R=1), the operating pulse generator 400 operates at time point t9 and time point t 10 Between t and t, a fifth pulse P5 with a pulse height of 19.5V (15×1×1.3V) is generated to the memory cell 100. At time t 10 Afterwards, a verification operation is performed to confirm that the sub-state value of the memory cell 100 is 6, and AF is set to 6.

[0124] Since AF is equal to 6, the memory cell has not yet reached the target storage state (erased state), and the erase operation has not yet ended. That is, the operating pulse generator 400 needs to adjust and generate the sixth pulse P6 to the memory cell 100. In addition, since the flag register 425 has been set (Flag=1) and the actual difference Z is equal to 3, which is greater than the preset difference X (X=2), the multiplier value N remains unchanged (N=15). In addition, according to the adjustment function, the corrected proportional value R is 0.95, that is, {1+[(7-6)-3]×0.025}=0.95. Then, BF is set equal to AF. Afterwards, according to the multiplier value N (N=15) and the proportional value R (R=0.95), the operating pulse generator 400 is at time point t 11 At time t 12 Between t and t, a sixth pulse P6 with a pulse height of 18.525V (15×0.95×1.3V) is generated to the memory cell 100. At time point t 12 After that, the verification operation is performed to confirm that the sub-state value of the memory cell 100 is 7, and AF is set to 7, indicating that the memory cell 100 has reached the target storage state (erased state). Therefore, the processor 420 performs the verification operation to pass the signal S PASS , indicating that the erase operation is completed, the controller 430 stops generating the next pulse and ends the erase operation.

[0125] Obviously, using Figure 5B and Figure 5C The control method of the operation pulse signal shown can use fewer pulses to complete the erase operation, allowing the memory cell 100 to reach the erase state, thereby improving the erase efficiency. Figure 4B 、 Figure 4C 、 Figure 5A The control flow also applies to programmed actions, and its operating principles will not be described in detail.

[0126] In the above embodiment, when a new action is started, the processor 420 provides the initial multiple value N and the initial ratio value R to the controller 430 to generate the first pulse P1. In fact, the processor 420 can determine the initial multiple value N and the initial ratio value R of the next new action based on the final multiple value N and the ratio value R of the previous action. Figure 4D For example, when the processor 420 provides the multiple value N (N=15) and the ratio value R (R=0.975) to the controller 430, the pulse generator 400 generates the last pulse (the seventh pulse P7) to the memory cell 100. After that, the processor 420 verifies the pass signal S PASS, indicating that the erase operation is complete, causing the controller 430 to stop generating the next pulse and end the erase operation. At this point, the multiplier value N (N=15) and the ratio value R (R=0.975) are the final multiplier value N and the final ratio value R of this operation.

[0127] At the start of the next new erase or program operation, the processor 420 can determine the initial multiplier value N and initial ratio value R based on the final multiplier value N and ratio value R of the previous operation. For example, assuming that the processor 420 internally sets an adjustment value T to (-1), the initial value N is 14, that is, [15 + (T) = 15 - 1]; the initial value R is 0.95, that is, [0.975 + (T) × (0.025) = 0.975 - 0.025], where 0.0025 is the offset. Alternatively, the adjustment value T can be set to zero, in which case the initial value N is 15 (15 + 0) and the initial value R is 0.975 (0.975 + 0 × 0.025).

[0128] In addition, the operation pulse signal control method of the present invention is not limited to Figure 1A The 3T2C memory cell 100 shown in FIG. The operation pulse signal control method of the present invention can also be applied to memory cells of other structures. For example, during programming, the first terminal of a memory cell of a specific structure receives a fixed programming voltage, and the programming voltage is the highest bias voltage. At this time, the operation pulse signal P can also be used. OP To replace the programming voltage and input the specific structure memory cell, and use the operation pulse signal P of the present invention OP The control method is used to program the memory cell of the specific structure. Similarly, during the erasing operation, a second end of the memory cell of the specific structure receives an erase voltage of a fixed value, and the erase voltage is the highest bias voltage. At this time, the operation pulse signal P can also be used. OP To replace the erase voltage and input the second end of the specific structure memory cell, and use the operation pulse signal P of the present invention OP The control method is used to perform an erase operation on the specific structure memory cell.

[0129] From the above description, it can be seen that the present invention proposes an operation pulse signal P for a non-volatile memory cell. OP Control method: The present invention determines the state change of the memory cell 100 before and after receiving a pulse, and dynamically adjusts the pulse height or pulse width of the next pulse according to the state change, thereby making the programming and erasing operations more efficient.

[0130] In summary, although the present invention has been disclosed above with reference to preferred embodiments, these are not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A method for controlling an operating pulse signal of a nonvolatile memory cell, wherein the memory cell can be divided into a plurality of sub-states corresponding to the number of electrons stored in the memory cell, the method comprising the following steps: (a) performing a verification operation to obtain a first sub-state value of the memory cell; (b) generating a pulse of the operation pulse signal to the memory cell; (c) performing the verification operation to obtain a second sub-state value of the memory cell; (d) when the second sub-state value indicates that the memory cell has not reached the target storage state, defining the actual difference value to be equal to the second sub-state value minus the first sub-state value; generating a next pulse according to the actual difference; setting the first sub-state value to be equal to the second sub-state value; and , return to step (b); and (e) When the second sub-state value represents that the memory cell has reached the target storage state, stop providing the next pulse.

2. The operation pulse signal control method as claimed in claim 1, wherein when a programming operation is performed on the memory cell, the target storage state is the programmed state of the memory cell; or when an erasing operation is performed on the memory cell, the target storage state is the erased state of the memory cell.

3. The operation pulse signal control method according to claim 1 , wherein the step (d) further comprises: The pulse width or pulse height of the next pulse is adjusted according to the actual difference.

4. The operation pulse signal control method according to claim 1, wherein step (b) further comprises: The pulse of the operation pulse signal is generated to the memory cell according to the multiplication value and the ratio value; wherein the pulse height of the pulse is equal to the multiplication value multiplied by the ratio value multiplied by the reference voltage.

5. The operation pulse signal control method according to claim 4, wherein step (d) further comprises the following steps: (d1) when the flag register has not been set and the actual difference is less than the preset difference, increasing the multiplication value and the ratio value; (d2) when the flag register has not been set and the actual difference is equal to the preset difference, setting the flag register, maintaining the multiplication value, and maintaining the ratio value; as well as (d3) When the flag register has not been set and the actual difference is greater than the preset difference, the flag register is set, the multiplication value is maintained, and the ratio value is reduced.

6. The operation pulse signal control method according to claim 5, wherein step (d) further comprises the following steps: (d4) when the flag register is set and the actual difference is less than the predetermined difference, maintaining the multiplication value and increasing the ratio value; (d5) when the flag register is set and the actual difference is equal to the preset difference, maintaining the multiplication value and maintaining the ratio value; as well as (d6) When the flag register is set and the actual difference is greater than the preset difference, the multiplication value is maintained and the ratio value is reduced.

7. The operation pulse signal control method according to claim 4, wherein step (d) further comprises the following steps: (d1) when the flag register has not been set and the actual difference is less than the preset difference, increasing the multiplication value and increasing the ratio value; (d2) when the flag register has not been set and the actual difference is equal to the preset difference, setting the flag register, maintaining the multiplication value, and maintaining the ratio value; (d3) when the flag register has not been set and the actual difference is greater than the predetermined difference, setting the flag register, maintaining the multiplication value, and generating the proportional value according to the adjustment function; (d4) when the flag register is set and the actual difference is less than the predetermined difference, maintaining the multiplication value and increasing the ratio value; (d5) when the flag register is set and the actual difference is equal to the preset difference, maintaining the multiplication value and maintaining the ratio value; as well as (d6) When the flag register is set and the actual difference is greater than the preset difference, the multiplication value is maintained and the proportional value is generated according to the adjustment function.

8. The operation pulse signal control method of claim 7 , wherein the adjustment function generates the corrected proportional value, and the adjustment function is [R + (YZ) × O], where R is the proportional value, Y is the adjustment parameter, Z is the actual difference, and O is an offset representing the increase or decrease value of the proportional value R each time. 9 . The operation pulse signal control method as claimed in claim 8 , wherein the adjustment parameter is equal to the target storage state value minus the second sub-state value.

10. The operation pulse signal control method as claimed in claim 1, wherein the memory cell comprises: a select transistor, wherein a first source / drain terminal of the select transistor is connected to a source line and a gate terminal of the select transistor is connected to a select gate line; a floating gate transistor, wherein a first source / drain terminal of the floating gate transistor is connected to a second source / drain terminal of the select transistor; a switch transistor, wherein a first source / drain terminal of the switch transistor is connected to a second source / drain terminal of the floating gate transistor, the second source / drain terminal of the switch transistor is connected to a bit line, and a gate terminal of the switch transistor is connected to a word line; a first capacitor, wherein a first terminal of the first capacitor is connected to the floating gate of the floating gate transistor, and a second terminal of the first capacitor is connected to a control line; as well as A second capacitor, wherein a first terminal of the second capacitor is connected to the floating gate of the floating gate transistor, and a second terminal of the second capacitor is connected to an erase line.

11. The operation pulse signal control method according to claim 10, wherein during programming, the source line and the bit line receive a ground voltage, the word line and the select gate line receive a turn-on voltage, and the control line and the erase line receive the operation clock signal.

12. The operation pulse signal control method according to claim 10, wherein during an erase operation, the source line, the bit line and the control line receive a ground voltage, the word line and the select gate line receive a turn-on voltage, and the erase line receives the operation clock signal.

13. The operation pulse signal control method as described in claim 10, wherein when performing the verification operation, the source line receives a ground voltage, the bit line receives a read voltage, the word line and the select gate line receive a turn-on voltage, and the erase line and the control line receive an operation voltage; and, based on the operation voltage and the memory cell current generated by the memory cell, it is determined whether the memory cell is in the first sub-state value or the second sub-state value.

14. The operation pulse signal control method according to claim 1 , wherein the operation pulse signal is provided by an operation pulse generator, and the operation pulse generator comprises: Differential reference circuit to provide reference voltage; a processor receiving a sub-state signal to determine the first sub-state value or the second sub-state value of the memory cell, wherein the processor provides a multiplication value and a ratio value according to the first sub-state value and the second sub-state value; a controller receiving the reference voltage, the ratio value, and the multiple value, and generating the next pulse of the operation pulse, wherein a pulse height of the next pulse is equal to the multiple value multiplied by the ratio value multiplied by the reference voltage; The processor selectively activates a verification pass signal according to the sub-state signal; and when the verification pass signal is activated, the controller stops providing the next pulse. 15 . The operation pulse signal control method as claimed in claim 14 , wherein the processor further includes a flag register, and when the flag register is set, the pulse width of the next pulse is increased.

Images