Method of manufacturing semiconductor device

Abstract

The embodiment of the invention relates to a method for manufacturing a semiconductor device. After a back surface of a semiconductor substrate (SB) is polished such that a thickness of a central portion of the semiconductor substrate is smaller than a thickness of a peripheral portion of the semiconductor substrate, a metal film including a film made of silver or copper is formed on the back surface of the semiconductor substrate. Thereafter, the dicing tape is bonded to the back surface of the semiconductor substrate through the metal film. The substrate material layer of the scribing belt is made of polyvinyl chloride. Further, after the peripheral portion is separated from the central portion and the dicing tape, the semiconductor substrate bonded to the dicing tape is diced. Thereafter, the semiconductor substrate adhered to the dicing tape is transported.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2024-065752 filed on April 15, 2024 including the specification, drawings and abstract is incorporated herein by reference in its entirety. Background Art

[0003] The present invention relates to a method for manufacturing a semiconductor device, and can be applied to a method for manufacturing a semiconductor device including a step of scribing a semiconductor wafer having a backside metal film, for example.

[0004] After attaching a dicing tape to the back surface of a semiconductor wafer, the semiconductor wafer can be divided into a plurality of semiconductor chips by dicing the semiconductor wafer.

[0005] The disclosed technologies are listed below.

[0006] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2016-192450.

[0007] [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2011-222843.

[0008] Patent Documents 1 and 2 disclose that after polishing the back surface of a semiconductor wafer, a dicing tape is attached to the back surface of the semiconductor wafer so that the thickness of the central portion of the semiconductor wafer is smaller than the thickness of the peripheral portion of the semiconductor wafer. Summary of the Invention

[0009] Typically, a gold (Au) film is used as the back surface electrode of a semiconductor chip. However, the present inventors are considering using a silver (Ag) film (a material that oxidizes more easily than a gold film) as the back surface electrode of a semiconductor chip. The cost of silver is lower than that of gold. Therefore, using a silver film instead of a gold film as the back surface electrode of a semiconductor chip can reduce the manufacturing cost of the semiconductor chip.

[0010] However, as mentioned above, silver is more susceptible to oxidation than gold. Furthermore, when a silver film oxidizes, the performance and reliability of a semiconductor device assembled using that semiconductor chip may deteriorate. Therefore, it is best to take measures to prevent oxidation of the back surface electrode, which is made of a material that oxidizes more easily than the gold film.

[0011] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0012] According to one embodiment, a method for manufacturing a semiconductor device includes: grinding the second main surface of a semiconductor wafer so that the thickness of the central portion of the semiconductor wafer is less than the thickness of the peripheral portion of the semiconductor wafer; forming a metal film on the second main surface of the semiconductor wafer, including a first metal film made of silver or copper; and adhering a dicing tape to the second main surface of the semiconductor wafer via the metal film. The method also includes separating the peripheral portion from the central portion and the dicing tape; dicing the semiconductor wafer adhered to the dicing tape; and transporting the diced semiconductor wafer adhered to the dicing tape. The dicing tape includes a base material layer and an adhesive layer on the base material layer. The base material layer is made of polyvinyl chloride.

[0013] According to one embodiment, oxidation of a back surface electrode of a semiconductor chip can be prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a process flow chart of a manufacturing process of a semiconductor device according to one embodiment.

[0015] Figure 2 is a plan view showing a semiconductor substrate used in a process of manufacturing a semiconductor device according to one embodiment.

[0016] Figure 3 It is along Figure 2 A cross-sectional view of a semiconductor substrate taken along line A1-A1.

[0017] Figure 4 is a cross-sectional view of the semiconductor substrate after the wiring structure forming step has been performed.

[0018] Figure 5 is a plan view showing the back surface of the wafer after the back surface grinding step has been performed.

[0019] Figure 6 It is along Figure 5 Cross-sectional view of line A1-A1.

[0020] Figure 7 is a cross-sectional view near the edge of the semiconductor substrate after the back surface grinding step has been performed.

[0021] Figure 8 This is an explanatory diagram of the back surface grinding step.

[0022] Figure 9 is a cross-sectional view of the wafer after the back surface metal film forming step has been performed.

[0023] Figure 10 is a cross-sectional view near the edge of the semiconductor substrate after the back surface metal film forming step has been performed.

[0024] Figure 11 is an enlarged partial cross-sectional view of the back surface of the semiconductor substrate and a metal film formed on the back surface of the semiconductor substrate.

[0025] Figure 12 is a plan view showing the wafer after the dicing tape bonding step has been performed.

[0026] Figure 13 It is along Figure 12 Cross-sectional view of line A1-A1.

[0027] Figure 14 is a cross-sectional view near the edge of a semiconductor substrate after a dicing tape bonding step has been performed.

[0028] Figure 15 is an enlarged partial cross-sectional view showing the back surface of the semiconductor substrate, a metal film formed on the back surface of the semiconductor substrate, and a dicing stripe formed on the metal film.

[0029] Figure 16 This diagram illustrates the steps for bonding the dicing tape.

[0030] Figure 17 yes Figure 16 An enlarged partial cross-sectional view of a portion of FIG.

[0031] Figure 18 This diagram illustrates the steps for bonding the dicing tape.

[0032] Figure 19 This is an explanatory diagram of the peripheral portion separation step.

[0033] Figure 20 yes Figure 19 An enlarged partial cross-sectional view of a portion of .

[0034] Figure 21 This is an explanatory diagram of the peripheral portion separation step.

[0035] Figure 22 is a plan view of the wafer after the peripheral portion separation step is completed.

[0036] Figure 23 This is a diagram illustrating the dicing steps.

[0037] Figure 24 This is a diagram illustrating the dicing steps.

[0038] Figure 25 It is a plan view of the wafer after the dicing step is completed.

[0039] Figure 26 It is along Figure 25 Cross-sectional view of line A1-A1.

[0040] Figure 27 is a cross-sectional view of an example of a semiconductor device assembled by using the obtained semiconductor chip.

[0041] Figure 28 It is an explanatory diagram of a pickup step for obtaining a semiconductor chip from a structure. DETAILED DESCRIPTION

[0042] In the following embodiments, for convenience, when necessary, they are divided into multiple parts or embodiments for explanation. Unless otherwise specified, they are not unrelated to each other; on the contrary, one is related to another as a modification, detail, supplementary explanation, etc. of part or all of another. In addition, in the following embodiments, when the number of elements (including the number of elements, numerical values, quantities, ranges, etc.) is mentioned, unless otherwise specified or clearly limited to a specific number in principle, the specific number is not restrictive and can be more or less than the specific number. In addition, in the following embodiments, constituent elements (including element steps, etc.) are not necessarily required, unless it is specifically specified or considered in principle that they are obviously required, it goes without saying. Similarly, in the following embodiments, when the shape, positional relationship, etc. of the parts are mentioned, unless it is specifically specified or considered in principle not to be, it is assumed that those that are substantially close to or similar to the shape, etc. are included. The same applies to the above-mentioned numerical values ​​and ranges.

[0043] Hereinafter, the embodiments will be described in detail based on the accompanying drawings. In all drawings used to illustrate the embodiments, components having the same functions are represented by the same reference numerals, and their repeated descriptions are omitted. In addition, in the following embodiments, the descriptions of the same or similar parts will not be repeated in principle unless otherwise required.

[0044] In the drawings used in this embodiment, hatching may be omitted even in cross-sectional views to facilitate understanding of the drawings, and hatching may be added even in plan views to facilitate understanding of the drawings.

[0045] (Example)

[0046] A method for manufacturing the semiconductor device of this embodiment will be described. Figure 1 1 is a process flow chart showing a method for manufacturing a semiconductor device according to this embodiment.

[0047] <Semiconductor Substrate Preparation Step>

[0048] Figure 2 1 is a plan view showing a semiconductor substrate SB used in the method for manufacturing the semiconductor device of the present embodiment. Figure 3 It is along Figure 2 A cross-sectional view of the semiconductor substrate SB taken along line A1-A1 in FIG.

[0049] like Figure 2and Figure 3 As shown, a semiconductor substrate (semiconductor wafer) SB ( Figure 1 The semiconductor substrate SB prepared in step S1 is a substantially disk-shaped semiconductor wafer. The semiconductor substrate SB may have a notch NT for identifying the plane orientation of the semiconductor substrate SB.

[0050] like Figure 2 As shown, the semiconductor substrate SB has a plurality of chip regions 1A and scribe areas 1B between adjacent chip regions 1A. The chip region 1A is an area in which a semiconductor chip is to be obtained, and in a plan view, each chip region 1A is surrounded by a scribe area 1B. That is, in the semiconductor substrate SB, a plurality of chip regions 1A are arranged in an array, and the area between adjacent chip regions 1A corresponds to the scribe area 1B. In the scribe step described later, the semiconductor substrate SB is cut (diced) along the scribe area 1B to separate the chip regions 1A, thereby obtaining semiconductor chips. In the stage of preparing the semiconductor substrate SB in step S1, the chip region 1A and the scribe area 1B are virtual areas, and there is no boundary between the chip region 1A and the scribe area 1B.

[0051] like Figure 3 As shown, the semiconductor substrate SB has a front surface SB1 as one of the main surfaces and a back surface SB2 as the other main surface opposite to the front surface SB1. The thickness of the semiconductor substrate SB prepared in step S1 is uniform. In the semiconductor substrate SB prepared in step S1, the entire front surface SB1 is flat, and the entire back surface SB2 is flat.

[0052] <Semiconductor Element Formation Step>

[0053] Next, semiconductor elements ( Figure 1 Examples of semiconductor elements include MISFETs (Metal Insulator Semiconductor Field Effect Transistors) or bipolar transistors. For example, trench gate MISFETs, LDMOSFETs (Laterally Diffused Metal Oxide Semiconductor Field Effect Transistors), or IGBTs (Insulated Gate Bipolar Transistors) can be formed on the semiconductor substrate SB as semiconductor elements.

[0054] <Wiring Structure Forming Step>

[0055] Next, if Figure 4 As shown, a wiring structure WR ( Figure 1 Step S3 in ). Figure 4 is a cross-sectional view of the semiconductor substrate SB after the wiring structure forming step of step S3, showing the same Figure 3 The corresponding cross section.

[0056] The wiring structure WR includes one or more insulating layers, one or more wiring layers, and a topmost protective film (protective insulating film, passivation film). The topmost wiring layer of the wiring structure WR contains multiple pads (pad electrodes). In the wiring structure WR, each pad is exposed through an opening in the protective film. In each chip region 1A, a predetermined circuit (integrated circuit) is formed by semiconductor elements formed within or on the surface of the semiconductor substrate SB and the wiring formed in the wiring structure WR.

[0057] Hereinafter, the semiconductor substrate SB and the entire portion of the wiring structure WR on the front surface SB1 of the semiconductor substrate SB are referred to as a wafer (semiconductor wafer) WF. The back surface of the wafer WF corresponds to the back surface SB2 of the semiconductor substrate SB. The front surface of the wafer WF corresponds to the front surface of the wiring structure WR on the front surface SB1 of the semiconductor substrate SB. The front surface of the wafer WF and the back surface of the wafer WF are located on opposite sides of each other.

[0058] <Back Surface Grinding Step>

[0059] Next, the back surface of the wafer WF (the back surface SB2 of the semiconductor substrate SB) is ground ( Figure 1 By performing the back surface grinding step of step S4, the thickness of the semiconductor substrate SB is reduced.

[0060] In steps S2 and S3, it is desirable to maintain a certain thickness of semiconductor substrate SB to prevent damage to the substrate. On the other hand, to minimize the size of semiconductor devices, it is desirable to reduce the thickness of the semiconductor chips obtained after the dicing step (described later). In this embodiment, the back surface grinding step of step S4 is performed after steps S2 and S3 to reduce the thickness of semiconductor substrate SB. Therefore, by maintaining the thickness of semiconductor substrate SB during steps S2 and S3, damage to the substrate SB can be prevented while also reducing the thickness of the semiconductor chips obtained after the dicing step (described later).

[0061] However, unlike this embodiment, if the back surface is ground uniformly in the back surface grinding step of step S4, Figure 4 If the entire back surface SB2 of the semiconductor substrate SB shown in FIG. 1 is ground and the entire thickness of the semiconductor substrate SB is uniformly thinned, the handleability of the wafer WF after the back surface grinding step in step S4 may be reduced. In addition, in this case, the wafer WF may be warped, and if warping occurs, the processing accuracy in the dicing step may be reduced.

[0062] Therefore, in this embodiment, if Figures 5 to 7 As shown, in the back surface grinding step of step S4 , the peripheral portion PR of the peripheral semiconductor substrate SB is hardly ground, but the central portion CT surrounded by the peripheral portion PR is selectively ground to be thinned.

[0063] Figure 5 4 is a plan view showing the back surface of the wafer (back surface SB2 of semiconductor substrate SB) after the back surface grinding step of step S4. Figure 6 It is along Figure 5 A cross-sectional view of line A1-A1 in FIG. Figure 6 , the wafer WF is shown with the back surface (the back surface SB2 of the semiconductor substrate SB) facing upward. Figure 5 Although it is a plan view, for ease of understanding, hatching in different directions is applied to the central portion CT and the peripheral portion PR. Figure 5 In FIG. 1 , a plurality of chip regions 1A of the semiconductor substrate SB are indicated by dotted lines. Figure 7 : is a cross-sectional view near the edge of the semiconductor substrate SB after the back surface grinding step of step S4. Figure 7 In the figure, the wiring structure WR is omitted. Figure 8 This is an explanatory diagram of the back surface grinding step.

[0064] In a plan view, the semiconductor substrate SB has a central portion CT and a peripheral portion PR continuously surrounding the central portion CT (see Figure 5 In the semiconductor substrate SB, a plurality of chip regions 1A are located in the central portion CT, and no chip region 1A is provided in the peripheral portion PR.

[0065] Before the back surface grinding step of step S4, the entire back surface SB2 of the semiconductor substrate SB is flat and the thickness of the semiconductor substrate SB is almost uniform. Therefore, before the back surface grinding step of step S4, the thickness of the central portion CT of the semiconductor substrate SB is the same as the thickness of the peripheral portion PR.

[0066] In the back surface grinding step of step S4, as Figure 6 and Figure 7 As shown, the back surface SB2 of the semiconductor substrate SB is ground so that the thickness T2 of the central portion CT is smaller than the thickness T1 of the peripheral portion PR (T1>T2). The planar shape of the central portion CT is preferably circular. The planar shape of the peripheral portion PR is preferably annular.

[0067] Here, the thickness of the central portion CT of the semiconductor substrate SB upon completion of the back surface grinding step in step S4 is referred to as thickness T2, and the thickness of the peripheral portion PR of the semiconductor substrate SB upon completion of the back surface grinding step in step S4 is referred to as thickness T1. The thickness T2 of the central portion CT corresponds to the distance from the front surface SB1 to the back surface SB2 of the semiconductor substrate SB in the central portion CT. The thickness T1 of the peripheral portion PR corresponds to the distance from the front surface SB1 to the back surface SB2 of the semiconductor substrate SB in the peripheral portion PR. The thickness T2 of the central portion CT is smaller than the thickness T1 of the peripheral portion PR (T1>T2). The thickness T2 of the central portion CT is, for example, greater than 50 micrometers and less than 150 micrometers, while the thickness T1 of the peripheral portion PR is, for example, greater than 700 micrometers and less than 775 micrometers. The difference between the thickness T1 of the peripheral portion PR of the semiconductor substrate SB and the thickness T2 of the central portion CT is, for example, greater than 550 micrometers and less than 725 micrometers.

[0068] In addition, if Figure 5 As shown, the width W1 of the peripheral portion PR is substantially constant regardless of the position of the peripheral portion PR except for the portion where the notch NT is formed. The width W1 of the peripheral portion PR is, for example, at least 4000 μm and not more than about 6000 μm.

[0069] Therefore, by increasing the thickness T1 of the peripheral portion PR surrounding the central portion CT, the peripheral portion PR can function as a reinforcement member to suppress warping of the semiconductor substrate SB. This improves the handleability of the wafer WF after the back surface grinding step in step S4 and can suppress or prevent warping of the wafer WF. On the other hand, by reducing the thickness T2 of the central portion CT where the plurality of chip regions 1A are located, the thickness of the semiconductor chips obtained after the dicing step described later can be reduced.

[0070] Below, refer to Figure 8 A specific example of the back surface grinding step of step S4 will be described.

[0071] First, if Figure 8 As shown in the upper part of the back surface grinding tape BT, the back surface grinding tape BT is attached to the surface of the wafer WF. The back surface grinding tape BT has the function of preventing grinding debris or cleaning water from contaminating the semiconductor elements or wiring layers of the wiring structure WR formed in or on the front surface SB1 of the semiconductor substrate SB during the back surface grinding process. The back surface grinding tape BT includes a resin film as a base material and an adhesive layer formed on one main surface of the resin film. The back surface grinding tape BT is attached to the front surface (the front surface of the wiring structure WR). The adhesive layer of the back surface grinding tape BT is brought into contact with the surface of the wafer WF.

[0072] Next, although Figure 8Although not shown in the figure, with the back surface grinding tape BT attached to the wafer WF, the entire back surface of the wafer WF is ground (preliminary grinding step). This reduces the overall thickness of the semiconductor substrate SB. This preliminary grinding step can be omitted.

[0073] Next, if Figure 8 As shown in the middle of FIG, with the back surface grinding tape BT attached to the wafer WF, the back surface of the wafer WF (the back surface SB2 of the semiconductor substrate SB) is ground using a grinding tool KG1 (such as a grindstone) (rough grinding step). At this time, the central portion CT of the semiconductor substrate SB is selectively ground until its thickness reaches a predetermined thickness.

[0074] Next, if Figure 8 As shown in the lower portion of FIG, with the back surface grinding tape BT attached to the wafer WF, the back surface of the wafer WF (the back surface SB2 of the semiconductor substrate SB) is ground using a grinding tool KG2, such as a grindstone (finish grinding step). At this time, the central portion CT of the semiconductor substrate SB is selectively ground until its thickness reaches the designed target thickness. The abrasive grains of the grinding tool KG2 are smaller in size than those of the grinding tool KG1.

[0075] By using a grinding tool KG1 with a large grain size for grinding in the rough grinding step, the total time required for the grinding process can be shortened. Then, by using a grinding tool KG2 with a small grain size for grinding in the subsequent fine grinding step, the flatness of the back surface SB2 of the central portion CT of the semiconductor substrate SB can be improved. Thus, it is possible to simultaneously achieve a reduction in the time required for the grinding step and an improvement in the flatness of the back surface SB2 of the central portion CT of the semiconductor substrate SB.

[0076] By selectively grinding the central portion CT of the semiconductor substrate SB in the back surface grinding step of step S4, a step surface (step side, step portion) DS1 is formed at the boundary between the central portion CT and the peripheral portion PR of the semiconductor substrate SB, and the thickness T2 of the central portion CT becomes thinner than the thickness T1 of the peripheral portion PR of the semiconductor substrate SB.

[0077] As described above, when the rough grinding step and the subsequent fine grinding step are performed in the back surface grinding step of step S4, as shown in FIG. Figure 7As shown, a small step portion DS2 is also formed at the boundary between the central portion CT and the peripheral portion PR, continuous with the step surface DS1. The height difference between the step portion DS2 and the central portion CT is smaller than the height difference between the peripheral portion PR and the central portion CT, and is also smaller than the thickness of the central portion CT. The height difference between the step portion DS2 and the central portion CT corresponds to the difference between the thickness T3 of the step portion DS2 and the thickness T2 of the central portion CT. The thickness T3 of the step portion DS2 is, for example, greater than 100 microns and less than 250 microns. Furthermore, the height difference of the step portion DS2 is, for example, greater than 50 microns and approximately 100 microns.

[0078] The step surface DS1 and the step portion DS2 are located at the boundary between the central portion CT and the peripheral portion PR. The back surface of the peripheral portion PR continues to the step surface DS1, and the back surface of the central portion CT continues to the step portion DS2. The step portion DS2 is interposed between the step surface DS1 and the back surface of the central portion CT. In other words, the step portion DS2 exists below the step surface DS1.

[0079] After that, in order to remove the grinding debris and the grinding liquid attached to the wafer WF, the wafer WF is cleaned. At this time, the back grinding tape BT is peeled off from the wafer WF and the surface of the wafer WF is also cleaned.

[0080] Therefore, the back surface grinding step of step S4 is performed.

[0081] Unlike this embodiment, if the entire semiconductor substrate SB is uniformly thinned, the wafer WF is likely to warp when the back grinding tape BT is peeled off. Figures 5 to 7 As shown, a peripheral portion PR thicker than the central portion CT exists around the central portion CT where the plurality of chip regions 1A are arranged. Therefore, even if the back grinding tape BT is peeled off from the wafer WF, the wafer WF can be prevented from warping.

[0082] Furthermore, from the perspective of suppressing wafer WF warpage, a larger thickness T1 of the peripheral portion PR is desirable. On the other hand, increasing the width W1 of the peripheral portion PR can also suppress wafer WF warpage, but increasing the width W1 of the peripheral portion PR reduces the number of semiconductor chips that can be obtained from a single wafer WF. Therefore, to suppress wafer WF warpage, it is preferable to increase the thickness T1 of the peripheral portion PR rather than increasing the width W1 of the peripheral portion PR. Therefore, from the perspective of increasing the number of semiconductor chips that can be obtained from a single wafer WF and improving manufacturing efficiency, the thickness T1 of the peripheral portion PR is preferably at least twice the thickness T2 of the central portion CT. Furthermore, when the thickness T2 of the central portion CT is 100 microns or less, the thickness T1 of the peripheral portion PR is even more preferably at least five times the thickness T2 of the central portion CT.

[0083] <Back Surface Metal Film Formation Step>

[0084] Next, if Figures 9 to 11 As shown, a metal film ME ( Figure 1 Step S5 in ). Figure 9 is a cross-sectional view of the wafer after performing the back surface metal film forming step of step S5, showing the same Figure 6 The corresponding cross section. Figure 10 is a cross-sectional view near the edge of the semiconductor substrate SB after performing the back surface metal film forming step of step S5, showing the same Figure 7 The corresponding cross section. Figure 10 In the figure, the wiring structure WR is omitted. Figure 11 1 is an enlarged partial cross-sectional view showing the back surface of the semiconductor substrate SB and the metal film ME formed on the back surface of the semiconductor substrate SB.

[0085] The metal film (back surface metal film, metal layer) ME is formed on almost the entire back surface of the wafer WF (the back surface SB2 of the semiconductor substrate SB). Although the metal film ME may not be formed on the step surface DS1, the metal film ME is formed on the entire back surface of the central portion CT of the semiconductor substrate SB. The metal film ME is also formed on the back surface of the peripheral portion PR, but the metal film ME is not necessarily formed on the back surface of the peripheral portion PR.

[0086] By forming the metal film ME on the back surface of the wafer WF in step S5 , the semiconductor chip obtained after the dicing step described later has a back surface electrode composed of the metal film ME.

[0087] The present inventors are considering using a silver (Ag) film (a metal film made of silver) instead of a gold (Au) film (a metal film made of gold) as the back surface electrode of a semiconductor chip. When a silver (Ag) film is used instead of a gold (Au) film as the back surface electrode of a semiconductor chip, the manufacturing cost of the semiconductor chip can be reduced.

[0088] The back surface electrode of the semiconductor chip obtained after the dicing step described later is composed of the metal film ME. Therefore, in this embodiment, the metal film ME includes not a gold (Au) film but a silver (Ag) film.

[0089] Specifically, the metal film ME is composed of a laminated film of multiple metal films, including a silver (Ag) film as the uppermost layer (top layer). Note that within the metal film ME, the layer in contact with the back surface SB2 of the semiconductor substrate SB is the lowermost layer (bottom layer) of the metal film ME, while the layer farthest from the back surface SB2 of the semiconductor substrate SB is the uppermost layer of the metal film ME. In this embodiment, the uppermost layer of the metal film ME is made of silver (Ag). In other words, the silver (Ag) film ME3 included in the metal film ME is the front surface (exposed surface) of the metal film ME.

[0090] For example, Figure 11 As shown, the metal film ME is composed of a laminated film of a titanium (Ti) film ME1 formed on and in contact with the back surface SB2 of the semiconductor substrate SB, a nickel (Ni) film ME2 formed on the titanium film ME1, and a silver (Ag) film ME3 formed on the nickel film ME2. The titanium film ME1 and the nickel film ME2 are interposed between the back surface SB2 of the semiconductor substrate SB and the silver (Ag) film ME3. The titanium film ME1 is interposed between the back surface SB2 of the semiconductor substrate SB and the nickel film ME2, and the nickel film ME2 is interposed between the titanium film ME1 and the silver (Ag) film ME3. The metal film ME can be formed, for example, by sputtering. When the metal film ME is formed by sputtering, as shown in FIG. Figure 10 As shown, the metal film ME is hardly formed on the step surface DS1. In this case, the metal film ME on the back surface of the central portion CT and the metal film on the back surface of the peripheral portion PR are not connected to each other.

[0091] In addition, after forming the metal film ME in step S5, the front surface of the metal film ME (the front surface of the silver film ME3) may be roughened to improve the adhesion between the metal film ME and the dicing tape DT in the dicing tape attaching step of step S6 described later.

[0092] Next, the combination of the wafer WF and the metal film ME formed on the back surface of the wafer WF is referred to as a wafer (semiconductor wafer) WF1. That is, the combination of the semiconductor substrate SB, the wiring structure WR on the front surface SB1 of the semiconductor substrate SB, and the metal film ME on the back surface SB2 of the semiconductor substrate SB corresponds to the wafer WF1. The back surface of the wafer WF1 corresponds to the front surface of the metal film ME formed on the back surface SB2 of the semiconductor substrate SB. The front surface of the wafer WF1 corresponds to the front surface of the wiring structure WR on the front surface SB1 of the semiconductor substrate SB. The front surface of the wafer WF1 corresponds to the front surface of the wiring structure WR on the front surface SB1 of the semiconductor substrate SB. Furthermore, the back surfaces of the wafer WF1 are located on opposite sides of each other. Note that the front surface of the metal film ME corresponds to the surface (main surface) opposite to the surface in contact with the back surface SB2 of the semiconductor substrate SB.

[0093] In addition, the combination of the peripheral portion PR of the semiconductor substrate SB, the wiring structure WR on the front surface of the peripheral portion PR, and the metal film ME on the back surface of the peripheral portion PR is hereinafter referred to as the peripheral portion PR1. The back surface of the peripheral portion PR1 corresponds to the front surface of the metal film ME on the back surface of the peripheral portion PR of the semiconductor substrate SB.

[0094] In addition, hereinafter, the entirety of the central portion CT of the semiconductor substrate SB, the wiring structure WR on the central portion CT, and the metal film ME on the back surface of the central portion CT will be referred to as the central portion CT1. The back surface of the central portion CT1 corresponds to the front surface of the metal film ME on the back surface of the central portion CT of the semiconductor substrate SB. In a plan view, the boundary between the central portion CT1 and the peripheral portion PR1 coincides with the boundary between the central portion CT and the peripheral portion PR.

[0095] <Dicing Tape Bonding Step>

[0096] Next, if Figures 12 to 15 As shown, a dicing tape (protective tape) DT is attached to the back surface of the wafer WF1 ( Figure 1 In other words, in step S6, the dicing tape DT is attached to the back surface SB2 of the semiconductor substrate SB through the metal film ME.

[0097] Figure 12 is a plan view showing the wafer after the bonding step of step S6. Figure 12 , the position of the boundary between the central portion CT1 and the peripheral portion PR1 of the wafer WF1 is indicated by a dotted line. Figure 13 It is along Figure 12 A cross-sectional view of line A1-A1. Figure 13 , wafer WF1 is shown with the back surface of wafer WF1 facing upward. Figure 14 is a cross-sectional view near the edge of the semiconductor substrate SB after the dicing tape bonding step of step S6, showing the same Figure 10 The corresponding cross section. Figure 14 In the figure, the wiring structure WR is omitted. Figure 15 1 is an enlarged partial cross-sectional view showing the back surface of the semiconductor substrate SB, the metal film ME formed on the back surface of the semiconductor substrate SB, and the dicing tape DT formed on the metal film ME.

[0098] like Figure 15As shown, the dicing tape DT has a base material layer (substrate layer) BS and an adhesive layer (bonding layer) NL formed on one main surface of the base material layer BS. That is, the dicing tape DT has a laminated structure including the base material layer BS and the adhesive layer NL. In the present embodiment, the base material layer BS is made of polyvinyl chloride (PVC). The adhesive layer NL is made of acrylic resin. The thickness of the base material layer BS is preferably greater than 70 microns and less than 100 microns. The thickness of the adhesive layer NL is preferably greater than 5 microns and less than 10 microns. The dicing tape DT is attached to the back surface (front surface of the metal film ME) of the wafer WF1 so that the adhesive layer NL of the dicing tape DT faces (contacts) the back surface (front surface of the metal film ME) of the wafer WF1.

[0099] Next, we will refer to Figures 16 to 18 A specific example of the dicing tape attachment of step S6 will be described. Figure 16 and Figure 18 This diagram illustrates the steps for bonding the dicing tape. Figure 17 It is magnified Figure 16 A partially enlarged cross-sectional view of a portion of the Figure 14 The corresponding cross section. Figure 17 In the figure, the wiring structure WR and the stage STG1 are omitted.

[0100] First, wafer WF1 is placed in a vacuum container (vacuum chamber, vacuum chamber) VC (i.e., "wafer WF1 placement step"). The vacuum container VC includes a stage STG1 and a container portion CB placed on the stage STG1. Wafer WF1 is placed on the stage STG1 so that the front surface (the front surface of the wiring structure WR) of wafer WF1 faces the front surface of the stage STG1. The back surface of wafer WF1 on the stage STG1 faces upward. Wafer WF1 on the stage STG1 is covered by the container portion CB, but wafer WF1 is separated from the inner surface of the container portion CB. Wafer WF1 is placed in the space surrounded by the stage STG1 and the container portion CB.

[0101] Next, with the wafer WF1 placed in the vacuum vessel VC, the interior of the vacuum vessel VC is depressurized (i.e., a "depressurization step"). This depressurization step can be performed by evacuating the interior of the vacuum vessel VC using a vacuum pump (not shown). As a result, the interior of the vacuum vessel VC is placed in a depressurized state (i.e., a "vacuum state").

[0102] Next, if Figure 16 As shown, the dicing tape DT is placed on the back surface of the wafer WF1 placed on the stage STG1 (i.e., the "dicing tape DT placement step"). At this time, the dicing tape DT is placed on the back surface of the wafer WF1 so that the adhesive layer NL of the dicing tape DT (see Figure 15) faces the back surface (the front surface of the metal film ME). To facilitate the handling of the dicing tape DT, the dicing tape DT may be held at its periphery by an annular support member (not shown) and placed on the back surface of the wafer WF1.

[0103] like Figure 16 and Figure 17 As shown, when the scribe tape DT is placed on the back surface of wafer WF1, the scribe tape DT contacts the back surface of wafer WF1 in peripheral portion PR1, but does not contact the back surface of wafer WF1 in central portion CT1, and the back surface of wafer WF1 is separated from the scribe tape DT. In other words, the scribe tape DT contacts the back surface (the front surface of metal film ME on the back surface of peripheral portion PR) but does not contact the back surface (the surface of metal film ME on the back surface of central portion CT). The back surface of wafer WF1 is separated from the back surface of central portion CT1 and from the back surface of central portion CT1. Therefore, step surface DS1 and step portion DS2 do not contact the scribe tape DT. A space SP1 exists between the back surface of wafer WF1 and scribe tape DT, surrounded by the back surface of central portion CT1 (the surface of metal film ME on the back surface of central portion CT), step surface DS1, the front surface of metal film ME on step portion DS2, and the scribe tape DT.

[0104] The step of placing the dicing tape DT is performed in the vacuum container VC under reduced pressure (i.e., "vacuum state"). Therefore, the space SP1 is also in a reduced pressure state (i.e., "vacuum state"). At this stage, the pressure in the space SP1 is the same as the pressure around the wafer WF1 (space SP2) where the dicing tape DT is placed.

[0105] Next, the interior of the vacuum container VC is opened to the atmosphere (ie, the "atmosphere release step"). Figure 18 The state after the atmospheric release step is performed is shown. This atmospheric release step can be performed by stopping the exhaust of the vacuum container VC by the exhaust vacuum pump (not shown) and opening a valve (not shown) connected to the opening portion of the vacuum container VC to introduce atmospheric air from outside the vacuum container VC. As a result, since the interior of the vacuum container VC reaches atmospheric pressure, the surrounding area of ​​the wafer WF1 where the dicing tape DT is placed (space SP2) quickly reaches atmospheric pressure. However, space SP1 is less likely to reach atmospheric pressure and is more likely to remain in a reduced pressure state. This is because the back surface (the front surface of the metal film ME on the back surface of the peripheral portion PR) is in contact with the dicing tape DT at the end of the peripheral portion PR1, making space SP1 a nearly sealed space. When atmospheric air flows into the vacuum container VC, it is difficult for atmospheric air to flow into space SP1.

[0106] When the atmospheric release step is performed, the dicing tape DT is deformed due to the pressure difference between the inside of the vacuum container VC (i.e., the "atmospheric pressure state") and the space SP1 (i.e., the "decompression state"), thereby compressing (shrinking) the space SP1. That is, when the atmospheric release step is performed, the pressure around the wafer WF1 (space SP2) where the dicing tape DT is placed becomes greater than the pressure in the space SP1, and due to the pressure difference between the space SP2 and the space SP1, Figure 18 A force in the direction of arrow YG shown in FIG. 1 (a force for pressing the dicing tape DT toward the wafer WF1) is applied to the dicing tape DT. As a result, as shown in FIG. Figure 18 As shown, the dicing tape DT is deformed to follow the shape of the back surface of the wafer WF1 so that the dicing tape DT is attached to the entire back surface of the wafer WF1. Specifically, the dicing tape DT is adhered to the back surface of the metal film ME on the peripheral portion PR1, the step surface DS1, the step portion DS2 (the front surface of the metal film ME on the back surface of the peripheral portion PR), and the surface of the metal film ME on the central portion CT1 (see FIG. Figure 14 and Figure 18 ) on the back surface (the surface of the metal film ME on the back surface of the central portion CT). In other words, the dicing tape DT is bonded to the surface of the metal film ME on the back surface of the peripheral portion PR, the front surface of the metal film ME on the back surface of the central portion CT, the step surface DS1, and the front surface of the metal film ME on the step portion DS2 (see Figure 14 and Figure 18 ). As a result, the dicing tape DT is pasted onto the entire back surface of the wafer WF1 so that no gap is formed between the back surface of the wafer WF1 and the dicing tape DT.

[0107] Subsequently, the wafer WF1 to which the dicing tape DT is attached is taken out from the vacuum container VC.

[0108] <Peripheral portion separation step>

[0109] Next, by cutting the wafer WF1 along the boundary between the central portion CT (CT1) and the peripheral portion PR (PR1), the central portion CT1 and the peripheral portion PR1 are separated from each other ( Figure 1 Step S7 in ).

[0110] Below, we will refer to Figures 19 to 22 A specific example of the peripheral separation step of step S7 will be described. Figure 19 and Figure 21 This is an illustration of the peripheral separation process. Figure 20 yes Figure 19 A partial enlarged cross-sectional view of a portion of the Figure 14 The corresponding cross section. Figure 20 In the figure, the wiring structure WR and the stage STG2 are omitted. Figure 22FIG. 1 is a plan view of the wafer WF1 at the stage where the peripheral separation process of step S7 is completed. Figure 22 In FIG. 1 , a plurality of chip regions 1A in the wafer WF1 are indicated by dotted lines.

[0111] First, if Figure 19 As shown, wafer WF1, with dicing tape DT attached, is placed on stage STG2 of the dicing apparatus. At this point, wafer WF1 is placed on stage STG2 with the front surface of wafer WF1 facing upward, and dicing tape DT contacts the upper surface of stage STG2. The upper surface of stage STG2 has a shape aligned with the back surface of wafer WF1 and has a step at a position corresponding to step surface DS1.

[0112] Next, if Figure 19 and Figure 20 As shown, the wafer WF1 is cut from the surface side along the boundary between the central portion CT (CT1) and the peripheral portion PR (PR1) using a blade (cutting edge) BR1 of a cutting device (i.e., a "cutting step"). In this cutting step, the wafer WF1 is cut so that the cutting lines describe a circular path. Furthermore, in this cutting step, the wafer WF1 is preferably cut slightly inside the boundary between the central portion CT (CT1) and the peripheral portion PR (PR1). In a plan view, the side closer to the center of the central portion CT (CT1) corresponds to the inside, and the side farther from the center of the central portion CT (CT1) corresponds to the outside.

[0113] Wafer WF1 is cut by rotating blade BR1, separating central portion CT1 from peripheral portion PR1, but dicing tape DT is not completely cut. Therefore, dicing tape DT below central portion CT1 and dicing tape DT below peripheral portion PR1 remain integrally connected and do not separate even after the cutting step.

[0114] Next, if Figure 21 As shown, the peripheral portion PR1 is peeled off from the dicing tape DT. For example, the peripheral portion PR1 may be peeled off from the dicing tape DT by using a pick-up tool (not shown), thereby peeling the peripheral portion PR1 off from the dicing tape DT.

[0115] Since the peripheral portion PR1 is separated from the central portion CT1 in the above-described cutting step, the peripheral portion PR1 can be separated from the dicing tape DT while the central portion CT is still attached to the dicing tape DT. This allows the peripheral portion PR1 to be selectively separated from the dicing tape DT.

[0116] In the cutting step, by cutting the wafer WF1 slightly inside the boundary between the central portion CT1 and the peripheral portion PR1 , a part of the central portion (outer periphery) can also be separated from the dicing tape DT together with the peripheral portion PR1 .

[0117] Therefore, in step S7 , the peripheral portion PR1 may be separated from the central portion CT1 and the dicing tape DT.

[0118] When the peripheral portion separation step of step S7 is completed, as shown in FIG. Figure 22 As shown, the central portion CT1 of wafer WF1 is bonded to dicing tape DT, but the peripheral portion PR1 is not present on dicing tape DT. Therefore, before the peripheral portion separation step in step S7, wafer WF1 integrally includes the peripheral portion PR1 and the central portion CT1. However, after the peripheral portion separation step in step S7 is completed, wafer WF1 includes only the central portion CT1 without the peripheral portion PR1. The central portion CT1 has a plurality of chip regions 1A.

[0119] <Dicing Step>

[0120] Next, the wafer WF1 (central portion CT1) bonded to the dicing tape DT is diced (cut) ( Figure 1 Step S8 in the process).

[0121] Reference Figures 23 to 25 A specific example of the dicing step in step S8 will be described. Figure 23 and Figure 24 It is an explanatory diagram of the dicing process in step S8. Figure 25 1 is a plan view of the wafer WF1 at a stage where the dicing process in step S8 is completed. Figure 26 It is along Figure 25 A cross-sectional view along line A1-A1.

[0122] First, if Figure 23 As shown, the wafer WF1 with the dicing tape DT attached thereto is placed on the stage STG3 of the dicing apparatus. At this time, the wafer WF1 is placed on the stage STG3 with the front surface of the wafer WF1 facing upward, and the dicing tape DT faces (contacts) the upper surface of the stage STG3.

[0123] Next, if Figure 24 and Figure 25 As shown, the rotating blade (cutting edge) BR2 of the scribing device is used to cut along the scribing area 1B (see the above Figure 2 ) The wafer WF1 is cut from the front surface side. As a result, the wafer WF1 is separated into a plurality of semiconductor chips CP and divided (individualized). Each individualized chip region 1A corresponds to a semiconductor chip CP.

[0124] Each semiconductor chip consists of a chip region 1A on a semiconductor substrate SB, a wiring structure WR on the chip region 1A, and a metal film ME on the back surface of the chip region 1A. During the dicing step, the cut surface of the wafer WF1 corresponds to the side surface of each semiconductor chip CP. The metal film ME of each semiconductor chip CP functions as a back surface electrode of the semiconductor chip CP.

[0125] Although the wafer WF1 is cut into a plurality of semiconductor chips CP by the rotary blade BR2, the dicing tape DT is not completely cut. Therefore, even after the dicing step, the dicing tape DT located below each semiconductor chip CP remains integrally connected without being separated.

[0126] Therefore, before the dicing step S8, the single wafer WF1 (central portion CT1) is in a state of being bonded to a single dicing tape DT, but after the dicing step S8 is completed, the dicing wafer WF1 is in a state of being bonded to a single dicing tape DT, that is, a state in which a plurality of semiconductor chips CP are bonded to a single dicing tape DT. The dicing wafer WF1 is a collection of a plurality of semiconductor chips CP.

[0127] Hereinafter, the dicing tape DT and the plurality of semiconductor chips CP (dicing wafer WF1 ) bonded to the dicing tape DT are collectively referred to as a structure KB.

[0128] <Storage Steps>

[0129] Next, store Figure 25 and Figure 26 The structure KB shown in FIG. 1 is not used until the transport step S10 described later is performed ( Figure 1 Step S9).

[0130] <Transportation (Shipping) Steps>

[0131] Next, the structure KB is transported (shipped) to the customer, etc. ( Figure 1 When the structure KB is shipped to the customer in step S10, the assembly process of subsequent step S12 is performed at the customer's factory, etc. If the assembly process of subsequent step S12 is performed at another factory of the company, the structure KB is shipped to the other factory of the company in step S10.

[0132] <Storage Steps>

[0133] The structure KB transported in the transport step of step S10 is stored until the assembly process of the next step S12 is performed ( Figure 1 Step S11).

[0134] <Semiconductor Device Assembly Process>

[0135] By assembling a semiconductor device (semiconductor package) using the semiconductor chip CP obtained from the structure KB ( Figure 1 Step S12).

[0136] Figure 27 1 is a cross-sectional view showing an example of a semiconductor device (semiconductor package) PKG assembled using the semiconductor chip CP obtained using the structure KB.

[0137] Figure 27 The semiconductor device PKG shown includes a die pad (chip mounting portion) DP, a semiconductor chip CP mounted on the die pad DP via a conductive bonding material BD1 such as solder, leads LD, bonding wires BW, a metal plate MP, and a sealing portion MR that seals these components.

[0138] The semiconductor chip CP is composed of a semiconductor substrate SB, a wiring structure WR formed on the surface of the semiconductor substrate SB, and a metal film ME formed on the bottom surface of the semiconductor substrate SB. The back surface of the semiconductor chip CP is composed of the surface of the metal film ME, and the metal film ME serves as the back surface electrode of the semiconductor chip CP. The wiring structure WR of the semiconductor chip CP has a plurality of pads (bonding pads) PD. Figure 27 In this case, a trench-gate MISFET or LDMOSFET is formed within the main surface of the semiconductor substrate SB of the semiconductor chip CP or within the semiconductor substrate SB, and the multiple pads PD of the semiconductor chip CP include a gate pad PDG and a source pad PDS. The gate pad PDG is electrically connected to the gate electrode of the trench-gate MISFET or LDMOSFET through the wiring within the wiring structure WR. The source pad PDS is electrically connected to the source region of the trench-gate MISFET or LDMOSFET through the wiring within the wiring structure WR, and the metal film ME is electrically connected to the drain region of the trench-gate MISFET or LDMOSFET, and can function as a back surface electrode of the drain.

[0139] The semiconductor chip CP is mounted on the die pad DP in an orientation opposite to the metal film ME via a conductive bonding material BD1 such as solder, so that the metal film ME of the semiconductor chip CP is electrically connected to the die pad DP via the conductive bonding material BD1 .

[0140] The gate pad PDG of the semiconductor chip CP is electrically connected to the lead LD via a bonding wire BW. The die pad DP and the lead LD are made of a metal material, such as copper (Cu) or a copper alloy. A portion of the lead LD can be exposed from the sealing portion MR and used as an external terminal (external terminal of the gate). The back side of the die pad DP can be exposed from the back side of the sealing portion MR and used as an external terminal (external terminal of the drain).

[0141] One end of the metal plate MP is electrically connected to the source pad PDS of the semiconductor chip CP via a conductive bonding material BD2 such as solder. The other end of the metal plate MP protrudes from the sealing portion MR, and this protrusion serves as an external terminal of the source. The other end of the metal plate MP can also be electrically connected to a lead of the source via a conductive bonding material. In this case, the lead of the source serves as an external terminal of the source.

[0142] The sealing portion MR is made of a resin material and may contain a filler.

[0143] Next, Figure 27 The assembly process of the semiconductor device PKG shown in FIG. Figure 1 An example of step S12) is described below.

[0144] In order to manufacture the semiconductor device PKG, it is necessary to prepare a lead frame having a die pad DP and leads LD.

[0145] Next, a semiconductor chip CP is obtained from the structure KB and placed on the die pad DP of the lead frame via the conductive bonding material BD1. In this case, the semiconductor chip CP is placed on the die pad DP via the conductive bonding material BD1, with the metal film ME of the semiconductor chip CP facing the die pad DP. The bonding material BD1 is then hardened. This completes the die bonding step.

[0146] Figure 28 This is an explanatory diagram of the picking-up step of the semiconductor chip CP from the structure KB. As described above, in the structure KB, a plurality of semiconductor chips CP are attached to a single dicing tape DT. For example, after irradiating the adhesive layer NL of the dicing tape DT of the structure KB with ultraviolet light, the structure KB is placed on a Figure 28 Then, as shown in the example Figure 28 As shown, the semiconductor chip CP is peeled off from the dicing tape DT and picked up using a pickup tool such as a collet (not shown). The picked up semiconductor chip CP is placed on the die pad DP of the lead frame via the conductive bonding material BD1 as described above.

[0147] After the die bonding step, a metal plate connection step and a wire bonding step are performed. In the metal plate connection step, one end of the metal plate MP is electrically connected to the source pad PDS of the semiconductor chip CP via a conductive bonding material BD2 (e.g., solder). In the wire bonding step, the gate pad PDG of the semiconductor chip CP and the lead LD are electrically connected via a bonding wire BW. The metal plate connection step and the wire bonding step can be performed in any order.

[0148] After the metal plate connecting step and the wire bonding step, a sealing portion forming step is performed to form the sealing portion MR.

[0149] After the sealing portion forming step, the lead frame cutting step is performed to separate the leads LD and the die pad DP from the lead frame. Thereafter, as needed, steps such as bending the leads LD and plating the exposed portions of the leads LD and the die pad DP are performed.

[0150] In this way, a semiconductor device PKG can be assembled.

[0151] Research Background

[0152] As described above, the inventors of the present application have been considering using a silver (Ag) film instead of a gold (Au) film as the back electrode of a semiconductor chip. Therefore, when forming a back metal film on the back surface of a semiconductor substrate, consideration is being given to forming a metal film including a silver (Ag) film. Using a silver (Ag) film instead of a gold (Au) film can reduce the manufacturing cost of a semiconductor chip. However, compared with a gold (Au) film, a silver (Ag) film is more easily oxidized. If the silver film constituting the back electrode is oxidized, there is a risk that the performance and reliability of a semiconductor device assembled using a semiconductor chip having an oxidized back electrode may decline. To this end, the following two measures have been taken.

[0153] As a first measure, after dicing a semiconductor wafer having a metal film formed on the back side, a plurality of semiconductor chips are obtained, and then the obtained semiconductor chips are stored in a chip tray or carrier tape. The chip tray or carrier tape containing the plurality of semiconductor chips is vacuum-packed in an aluminum bag for transportation (shipping). The aluminum bag vacuum packaging can prevent the silver film contained in the metal film on the back side from being oxidized.

[0154] The second measure is to store semiconductor wafers with a metal film formed on the back side of the wafers in a wafer box instead of dicing them. The wafer box containing the semiconductor wafers is then vacuum-packed in aluminum bags before transportation (shipping). Vacuum packaging in aluminum bags prevents oxidation of the silver film contained in the metal film on the back side.

[0155] However, when implementing the first measure, it is necessary to obtain a plurality of semiconductor chips from the diced semiconductor wafer and store the obtained semiconductor chips in a chip tray or a carrier tape. This operation may be very labor-intensive and may increase costs.

[0156] Furthermore, when implementing the first measure, a dedicated device (e.g., a die bonding device compatible with the chip tray or carrier tape) must be prepared in advance at the transportation destination (shipping destination) of the chip tray or carrier tape loaded with a plurality of semiconductor chips. Furthermore, when implementing the second measure, a dedicated device (e.g., a dicing device) must be prepared in advance at the transportation destination (shipping destination) of the semiconductor wafers loaded in the wafer cassette.

[0157] In addition, when the first and second measures are implemented, the high cost of packaging materials such as aluminum bags may lead to increased costs.

[0158] Therefore, in recent years, there has been an increasing demand (customer demand) for transporting (shipping) diced semiconductor wafers attached to dicing tape after the dicing step to customers, etc. This allows semiconductor chips to be picked up from the diced semiconductor wafers attached to the dicing tape at the destination of the diced semiconductor wafers (shipping destination) and quickly used for the die bonding step.

[0159] However, vacuum packaging the diced semiconductor wafers in aluminum bags is extremely difficult. Furthermore, as mentioned above, silver (Ag) films oxidize more easily than gold (Au) films. Therefore, when transporting diced semiconductor wafers in the diced tape, new measures are needed to prevent oxidation of the silver film contained in the metal film on the back of the semiconductor wafers.

[0160] <Main Features and Effects>

[0161] In this embodiment, in step S4, the back surface SB2 of the semiconductor substrate (semiconductor wafer) SB is ground so that the thickness of the central portion CT of the semiconductor substrate SB is smaller than the thickness of the peripheral portion PR surrounding the central portion CT. Then, in step S5, a metal film ME including a silver film ME3 is formed on the back surface SB2 of the semiconductor substrate SB. Then, in step S6, a dicing tape DT is attached to the metal film ME on the back surface SB2 of the semiconductor substrate SB. Thereafter, in step S7, the semiconductor substrate SB (wafer WF1) is cut to separate the peripheral portion PR (PR1) from the central portion CT (CT1) and the dicing tape DT. Then, in step S8, the semiconductor substrate SB (wafer WF1) attached to the dicing tape DT is diced. The diced semiconductor substrate SB (wafer WF1), attached to the dicing tape DT, is then shipped to a customer or the like in step S10. That is, in step S10, the structure KB is shipped to the customer or the like.

[0162] In order to prevent oxidation of the silver film ME3 contained in the metal film ME during the storage step of step S9, the transportation step of step S10, and the storage step of step S11 after the cutting step of step S8, it is effective to increase the adhesion between the dicing tape DT and the metal film ME. If the adhesion between the dicing tape DT and the metal film ME is high, air is less likely to be present between the metal film ME and the dicing tape DT, resulting in less exposure of the metal film ME to the air, thereby preventing oxidation of the metal film ME. As a result, oxidation of the silver film ME3 contained in the metal film ME is prevented.

[0163] In this embodiment, in step S4, the back surface SB2 of the semiconductor substrate SB is ground so that the thickness of the central portion CT of the semiconductor substrate SB is smaller than the thickness of the peripheral portion PR of the semiconductor substrate SB. This improves the handling of the wafer WF after the back grinding step of step S4, can suppress or prevent warping of the wafer WF, and can reduce the thickness of the semiconductor chips CP obtained after the dicing step.

[0164] However, if the back surface SB2 of the semiconductor substrate SB is polished so that the thickness of the central portion CT of the semiconductor substrate SB is smaller than that of the peripheral portion PR, improving the adhesion between the metal film ME on the back surface of the central portion CT of the semiconductor substrate SB and the dicing tape DT during the dicing tape attachment step is difficult without careful measures. This is because a step forms at the boundary between the central portion CT and the peripheral portion PR of the semiconductor substrate SB's back surface, easily creating a gap between the metal film ME on the back surface of the central portion CT of the semiconductor substrate SB and the dicing tape DT. If the adhesion between the dicing tape DT and the metal film ME is low and a gap exists between the dicing tape DT and the metal film ME, air will be trapped between the metal film ME and the dicing tape DT, making the metal film ME susceptible to oxidation.

[0165] Therefore, in this embodiment, a dicing tape DT having a base material layer BS made of polyvinyl chloride is used. Soft polyvinyl chloride is preferably used as the polyvinyl chloride for the base material layer BS. This allows the dicing tape DT to be tightly bonded to the entire back surface of the wafer WF1 during the dicing tape bonding step S6, and enhances the adhesion between the metal film ME on the back surface of the central portion CT of the semiconductor substrate SB and the dicing tape DT. This will be explained in more detail.

[0166] As described above, the dicing tape bonding step S6 includes the following steps: placing wafer WF1 within the vacuum container VC, reducing the pressure within the vacuum container VC, placing the dicing tape DT on top of wafer WF1, and opening the vacuum container VC to the atmosphere. The dicing tape DT placed on top of wafer WF1 remains separated from the metal film ME on the central portion CT of semiconductor substrate SB until the vacuum container VC is opened to the atmosphere. Subsequently, by opening the interior of the vacuum container VC to the atmosphere, the pressure difference between the dicing tape DT and wafer WF1 and the pressure surrounding wafer WF1 presses the dicing tape DT toward wafer WF1. As a result, the dicing tape DT deforms to conform to the back surface of wafer WF1 and adheres to the entire back surface of wafer WF1. This brings the dicing tape DT into contact with and adheres to the metal film ME on the back surface of the central portion of semiconductor substrate SB.

[0167] Unlike this embodiment, when a polyolefin film is used as the base material layer BS of the dicing tape DT, even if the dicing tape DT attempts to deform to conform to the back surface of the wafer WF1 when the vacuum container VC is opened to the atmosphere, it cannot accurately deform to the shape of the back surface of the wafer WF1, and a gap may form between the dicing tape DT and the back surface of the wafer WF1. This is because, for example, the elasticity of a polyolefin film is lower than that of a polyvinyl chloride film. Therefore, when a polyolefin film is used as the base material layer BS of the dicing tape DT, not only may a gap form between the dicing tape DT and the wafer WF1, but this gap may also widen.

[0168] In contrast, in this embodiment, since polyvinyl chloride film is used as the base material layer BS of the dicing tape DT, it deforms more easily than when polyolefin film is used. From a different perspective, polyvinyl chloride film has higher elasticity than polyolefin film. Therefore, in this embodiment, when the vacuum container VC is exposed to the atmosphere, the dicing tape DT can deform according to the shape of the back surface of the wafer WF1. Consequently, compared to when polyolefin film is used, the dicing tape DT contacts and adheres to the entire back surface of the wafer WF1, thereby suppressing the formation of a gap between the dicing tape DT and the back surface of the wafer WF1. Furthermore, even if a small gap forms between the dicing tape DT and the wafer WF1, the high elasticity of the polyvinyl chloride film suppresses its expansion compared to when polyolefin film is used. As a result, the dicing tape DT adheres to the entire back surface of the wafer WF1, enhancing the adhesion between the metal film ME on the back surface of the central portion CT of the semiconductor substrate SB and the dicing tape DT. As a result, since air is less likely to be present between the metal film ME and the dicing tape DT, the silver film ME3 included in the metal film ME can be prevented from being oxidized during the storage step after the dicing step S8, the transportation process step S10, and the storage step S11. In addition, the silver film ME3 included in the metal film ME can be prevented from being sulfurized after the dicing step S8, during the storage step S9, the transportation step S10, and the storage step S11.

[0169] The silver film changes color due to oxidation or sulfidation. The present inventors have confirmed that even when the structure KB is left in the atmosphere for a long period of time (e.g., about 8 months), the semiconductor chip is removed from the structure KB, and the metal film ME is observed, the silver film ME3 contained in the metal film ME does not change color, and the silver film ME3 contained in the metal film ME hardly undergoes oxidation or sulfidation.

[0170] Therefore, even if the metal film ME is placed in the atmosphere for a long time during the storage step of step S9, the transfer step of step S10 and the storage step of step S11 after the dicing step of step S8 can prevent the silver film ME3 contained in the metal film ME from being oxidized, and the silver film ME3 contained in the metal film ME from being sulfurized, thereby improving the performance and reliability of the semiconductor device manufactured using the semiconductor chip CP.

[0171] In addition, in the assembly process step S12, as Figure 28 As shown, once the semiconductor chip CP is taken out from the structure KB, the taken out semiconductor chip CP can be quickly (e.g., within 5 minutes) used for the die bonding step (placing the semiconductor chip CP on the die pad DP). This prevents the silver film ME3 contained in the metal film ME of the semiconductor chip CP obtained from the structure KB from being oxidized before the die bonding step.

[0172] Furthermore, in this embodiment, oxidation and sulfurization of the silver film ME3 included in the metal film ME in the structure KB can be prevented, thereby allowing the time required for each of the storage step S9, the transport step S10, and the storage step S11 to be set as desired without worrying about oxidation of the silver film ME3 included in the metal film ME. Therefore, after the dicing step S8, the transport step S10 and the assembly step S12 can be performed at desired times.

[0173] Furthermore, the surface of the metal film ME, namely the silver film ME3, is preferably roughened. This roughening process is performed after the metal film ME is formed in step S5 and before the dicing tape bonding step S6. Roughening the surface of the metal film ME further enhances the adhesion between the metal film ME and the dicing tape DT in the dicing tape bonding step S6. This makes it easier to prevent oxidation and sulfidation of the silver film contained in the metal film ME during the storage step S9, the transport step S10, and the storage step S11 after the dicing step S8.

[0174] As described above, by grinding the back surface SB2 of the semiconductor substrate SB in step S4 , a step (step surface DS1 ) is formed at the boundary between the central portion CT and the peripheral portion PR on the back surface SB2 of the semiconductor substrate SB.

[0175] In step S4, a plurality of steps may be formed at the boundary between the central portion CT and the peripheral portion PR on the back surface SB2 of the semiconductor substrate SB. Figure 7 In this case, two steps (step surface DS1 and step portion DS2) are formed at the boundary between the central portion CT and the peripheral portion PR on the back surface SB2 of the semiconductor substrate SB.

[0176] When multiple steps are formed at the boundary between the central portion CT and the peripheral portion PR, a gap is more likely to form between the back surface of the wafer WF1 and the dicing tape DT during the dicing tape attaching step S6 than when a single step is formed at the boundary between the central portion CT and the peripheral portion PR. In contrast, in this embodiment, since the dicing tape DT is made of polyvinyl chloride, the dicing tape DT can be adhered to the entire back surface of the wafer WF1 not only when a single step is formed at the boundary between the central portion CT and the peripheral portion PR, but also when multiple steps are formed at the boundary, thereby preventing the formation of a gap between the back surface of the wafer WF1 and the dicing tape DT. This prevents oxidation and sulfurization of the silver film contained in the metal film ME during the storage step S9, the transport step S10, and the storage step S11 after the dicing step.

[0177] Like silver (Ag), copper (Cu) is cheaper than gold (Au), but it is more easily oxidized than gold (Au). Therefore, even if the metal film ME includes a copper (Cu) film instead of the silver film ME3, the same problems and effects as those described in this embodiment will occur. Therefore, even if the metal film ME includes a copper (Cu) film instead of the silver film ME3, this embodiment can be applied. That is, in this embodiment, the metal film ME can include a copper (Cu) film instead of the silver film ME3.

[0178] As mentioned above, the invention made by the present inventors has been described in detail based on the embodiments. However, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: (a) preparing a semiconductor wafer having a first major surface and a second major surface opposite to the first major surface; (b) grinding the second main surface of the semiconductor wafer so that the thickness of a central portion of the semiconductor wafer is smaller than the thickness of a peripheral portion of the semiconductor wafer surrounding the central portion; (c) after (b), forming a metal film including a first metal film made of silver or copper on the second main surface of the semiconductor wafer; (d) bonding a dicing tape to the second main surface of the semiconductor wafer through the metal film; (e) after (d), dicing the semiconductor wafer, and separating the peripheral portion from the central portion and the dicing tape; (f) after (e), dicing the semiconductor wafer bonded to the dicing tape; as well as (g) after (f), transporting the semiconductor wafer bonded to the dicing tape and diced, (d) includes: (d1) placing the semiconductor wafer in a vacuum container; (d2) after (d1), decompressing the interior of the vacuum container; (d3) after (d2), placing the dicing tape on the second main surface of the semiconductor wafer so as to separate from the metal film; and (d4) after (d3), opening the interior of the vacuum container to the atmosphere, wherein the dicing tape comprises a base material layer and an adhesive layer on the base material layer, and The base material layer is made of polyvinyl chloride.

2. The method according to claim 1, wherein after (d3), the dicing tape is separated from the metal film on the central portion of the semiconductor wafer, and The dicing tape is brought into contact with the metal film on the central portion of the semiconductor wafer by opening the interior of the vacuum container to the atmosphere in (d4).

3. The method according to claim 2, wherein in (d), the dicing tape is bonded to the metal film on the second main surface of the semiconductor wafer so that the bonding layer of the dicing tape faces the metal film on the second main surface of the semiconductor wafer. The method according to claim 3 , wherein the adhesive layer is made of acrylic resin. The method according to claim 1 , wherein the first metal film is an uppermost layer of the metal film.

6. The method according to claim 1, further comprising: (a1) after (a) and before (b), forming a semiconductor element on the first main surface of the semiconductor wafer or within the semiconductor wafer; as well as (a2) After (a1) and before (b), forming a wiring structure on the first main surface of the semiconductor wafer. The method according to claim 1 , wherein the front surface of the metal film is roughened. 8 . The method according to claim 1 , wherein a thickness of the base material layer is 70 μm or greater and 100 μm or less. The method according to claim 1 , wherein the metal film does not include a gold film.

10. The method according to claim 1, further comprising: (g1) After (g), semiconductor chips are obtained from the semiconductor wafer adhered to the dicing tape and diced, and a die bonding step is performed by using the obtained semiconductor chips.

11. The method according to claim 1, wherein in (b), a step portion is formed at a boundary between the central portion and the peripheral portion by grinding the second main surface of the semiconductor wafer.

12. The method according to claim 1, wherein in (b), a plurality of step portions are formed at a boundary between the central portion and the peripheral portion by grinding the second main surface of the semiconductor wafer.

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