Metal shielding for stable tape frame substrate processing

Abstract

Embodiments of process kits for use in a substrate process chamber are provided herein. Process kit for a substrate process chamber, comprising: a covering configured to extend over an unprotected dicing tape of a tape frame substrate during use, having a central opening configured to expose a semiconductor wafer supported on the dicing tape during use; and a metal shield disposed adjacent to at least a portion of the lower surface of the covering, so that the metal shield at least partially lines the lower surface.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to substrate processing equipment.

Background Art

[0002] In semiconductor substrate processing, integrated circuits are formed on a substrate composed of silicon or other semiconductor materials. Generally, various material layers, either semiconducting, conductive, or insulating, are utilized to form the integrated circuits. After integrated circuit devices are formed on a semiconductor substrate, such as a 300 mm silicon substrate, the individual devices are separated from the semiconductor substrate by a process known as singulation or "dicing", in which the substrate is selected for subsequent processing and diced or "singulated" into individual devices called "chips" before being packaged into a product.

[0003] A substrate having a completed device on its upper side, which has been thinned and optionally metallized on the bottom side, is fixed to a dicing tape by an adhesive applied to the dicing tape. The dicing tape is fixed to a dicing ring of the completed device and is fixed together with the completed device to form a tape frame substrate. The ring supports the tape around the outer periphery of the tape frame substrate. After the dicing process is completed, the dicing tape continues to support the diced chips at the predetermined locations where they were diced from the semiconductor substrate. However, subsequent plasma processing of the tape frame substrate can cause etching of the unprotected dicing tape, which can lead to unwanted arcing between the tape frame substrate and processing chamber components such as process kits.

[0004] Therefore, the inventors have provided embodiments of an improved process kit herein.

Summary of the Invention

[0005] Embodiments of process kits for use in a substrate process chamber are provided herein. Process kit for a substrate process chamber, comprising: a covering configured to extend over an unprotected dicing tape of a tape frame substrate during use, having a central opening configured to expose a semiconductor wafer supported on the dicing tape during use; and a metal shield disposed adjacent to at least a portion of the lower surface of the covering, so that the metal shield at least partially lines the lower surface.

[0006] In some embodiments, a substrate support for a substrate process chamber includes a pedestal having a support surface configured to support a tape frame substrate, and having one or more electrodes disposed therein; and a process kit configured to cover a portion of the pedestal to define a gap between the lower surface of the process kit and the support surface, which extends over the unprotected dicing tape of the tape frame substrate during use and is sufficient to accommodate the dicing tape, wherein the process kit comprises a covering configured to extend over the unprotected dicing tape of the tape frame substrate during use, and having a central opening configured to expose a semiconductor wafer supported on the dicing tape during use; and a metal shield electrically connected to the pedestal and disposed adjacent to at least a portion of the lower surface of the covering, so that the metal shield at least partially lines the gap.

[0007] In some embodiments, the process chamber includes a chamber body having an internal space; a pedestal disposed in the internal space, having a support surface for a tape frame substrate and one or more electrodes disposed therein; a covering configured to extend over the unprotected dicing tape of the tape frame substrate during use, having a central opening configured to expose a semiconductor wafer supported on the dicing tape during use; and a metal shield electrically coupled to the pedestal and disposed adjacent to at least a portion of the lower surface of the covering, so that the metal shield at least partially lines the lower surface.

[0008] Other and further embodiments of this disclosure are described below.

[0009] Embodiments of the present disclosure, briefly summarized above and described in more detail below, can be understood by referring to exemplary embodiments of the present disclosure shown in the accompanying drawings. However, since the present disclosure may allow for other equally valid embodiments, the accompanying drawings are merely illustrative of general embodiments of the present disclosure and should not be considered limiting to the scope. [Brief explanation of the drawing]

[0010] [Figure 1] This is a schematic side view of a process chamber according to at least some embodiments of the present disclosure. [Figure 2] This figure shows a substrate 112 according to at least some embodiments of the present disclosure. [Figure 3] This is a schematic cross-sectional side view of a substrate support according to at least some embodiments of the present disclosure. [Figure 4] This is a schematic cross-sectional side view of a substrate support according to at least some embodiments of the present disclosure. [Figure 5] This is a schematic bottom view of a process kit according to at least some embodiments of the present disclosure. [Figure 6]This is a schematic bottom view of a process kit according to at least some embodiments of the present disclosure.

[0011] For ease of understanding, the same reference numerals are used to designate identical elements common to the figures where possible. The figures are not drawn to a fixed scale and may be simplified for clarity. Elements and features of one embodiment may be usefully incorporated into other embodiments without further description. [Modes for carrying out the invention]

[0012] A tape frame (TF) substrate generally contains multiple finished devices, dies, or chips fixed to a dicing tape. Once the dies are fixed, the TF substrate can proceed to further processing, for example, by being sent to an apparatus that can select individual dies from the dicing tape. However, subsequent plasma processing of the TF substrate can cause etching of the unprotected dicing tape. Therefore, a covering may be placed over the exposed dicing tape. However, gaps or cavities between the covering and the covered area of ​​the TF substrate can generate secondary plasma, which can ignite and cause unstable and unreproducible plasma processing of devices attached to the dicing tape.

[0013] A metal shielding ring is placed between the covering and the TF substrate. The metal shielding ring is electrically coupled to an RF source, such as an RF high-temperature pedestal of a plasma process chamber, or a separate RF power supply, and thus the metal shielding ring creates an equipotential region close to the gap between the clamp and the TF substrate, thereby reducing or preventing arcing in that region.

[0014] Figure 1 is a schematic side view of a plasma process chamber 100 according to at least some embodiments of the present disclosure. The plasma process chamber 100 includes a chamber body 102 defining an internal space 117 therein. A substrate support 122 includes a pedestal 110 having a support surface for supporting a substrate 112 or TF substrate which will be disposed on top of a substrate support 122 disposed in the internal space 117. The pedestal 110 may be an electrostatic chuck (ESC) having one or more electrodes 124 disposed therein, or a non-chucking substrate holder (not shown). A shield 114 may be disposed in the internal space 117 and may surround a processing volume 118. The chamber body 102 may be coupled to ground 115.

[0015] A gas supply 108 is coupled to the chamber body 102 and provides one or more process gases from the gas supply 108 to the processing volume 118 via a supply conduit 106. One or more process gases may be provided by a showerhead 104 disposed in the internal space 117. The process gas flow rate is controlled by a gas flow valve 144. In some embodiments, as shown in Figure 1, the plasma process chamber 100 is a capacitively coupled plasma chamber that forms plasma 116 in the processing volume 118 for processing a substrate 112 on a pedestal 110. The plasma process chamber 100 may be a chamber configured for surface activation, etching, deposition, etc.

[0016] Ions produced from one or more process gases by a plasma reaction are influenced by a first bias power supply 126 electrically connected to one or more electrodes 124 disposed in a pedestal 110. In some embodiments, a second bias power supply 128 is electrically connected to one or more electrodes 124. In some embodiments, the first bias power supply 126 generates RF power at a first frequency of approximately 400 kHz to approximately 15 MHz. In some embodiments, the first bias power supply 126 generates RF power at a first frequency of approximately 13.56 MHz. The first frequency allows for adjustment of the ionic energy of ions produced from the plasma and process gases based on a first level of power produced by the first bias power supply 126. In some embodiments, the first power level can be greater than 0 to approximately 2000 W.

[0017] In some embodiments, the second bias power supply 128 generates RF power at a second frequency of approximately 40 MHz to approximately 110 MHz. In some embodiments, the second bias power supply 128 generates RF power at a second frequency of approximately 60 MHz. The second frequency allows for adjustment of the ion density of ions produced from the plasma and process gas based on a second level of power produced by the second bias power supply 128. In some embodiments, the second power level can be greater than 0 to approximately 2000 W.

[0018] When the plasma and ions interact with the substrate 112, contaminants may form, which are removed from the plasma process chamber 100 by the pump 120. The pump 120 may also be used to maintain the process pressure within the plasma process chamber 100. In some embodiments, the process pressure may range from approximately 0.7 mTorr to approximately 20 mTorr. The plasma process chamber 100 may also have cooling and / or heating elements or channels 142 that allow temperature control of the substrate 112 during processing by the temperature controller 140. The plasma process chamber 100 may be a plasma chamber configured for processing tape frame substrates, as is part of a hybrid bonding process flow, as will be described in more detail below.

[0019] Figure 2 shows a substrate 112 according to at least some embodiments of the present disclosure. In some embodiments, the substrate 112 is generally a tape-frame substrate comprising a layer of dicing tape 202 surrounded by a tape frame 204. During use, a plurality of chiplets 206 may be attached to the dicing tape 202. The plurality of chiplets 206 are generally formed by a singulation process that dices a semiconductor wafer 210 into a plurality of chiplets 206 or dies. In some embodiments, the tape frame 204 is made from a metal, such as stainless steel. The tape frame 204 may have one or more notches 208 to facilitate alignment and handling. For a semiconductor wafer 210 having a diameter of 300 mm, the tape frame 204 may have a width of about 340 mm to about 420 mm and a length of about 340 mm to about 420 mm.

[0020] FIG. 3 shows a schematic cross-sectional side view of a substrate support 122 according to at least some embodiments of the present disclosure. A substrate 112 is disposed on the substrate support 122. During a plasma process, the dicing tape 202 can be exposed to the plasma 116 in the region between the semiconductor wafer 210 (or plurality of dielets 206) and the tape frame 204. The exposed region of the dicing tape 202 causes etching of the exposed or unprotected regions of the dicing tape 202, which leads to wear of the dicing tape 202 and contamination of the semiconductor wafer 210 (or plurality of dielets 206).

[0021] The substrate support 122 includes a process kit 310 disposed on the pedestal 110. The process kit 310 extends over the unprotected area of the dicing tape 202 during use and defines a gap 318 between the lower surface 312 of the process kit 310 and the support surface of the pedestal 110 sufficient to accommodate that area, and includes a covering 304 configured to cover a portion of the pedestal 110. The covering 304 is configured to extend over the unprotected dicing tape of the TF substrate during use and has a central opening configured to expose the semiconductor wafer 210 during use.

[0022] For example, the inner diameter of the covering 304 is slightly smaller than the outer diameter of the semiconductor wafer 210, for example, about 0.1 mm to about 2 mm smaller. In some embodiments, the covering 304 is made of quartz. In some embodiments, the covering 304 includes a body 322 and an inner lip 326 extending downward from the body 322. In some embodiments, the outer surface 342 of the inner lip 3) is disposed radially outward of the semiconductor wafer 210. The gap 318 between the covering 304 and the substrate 112 can be susceptible to secondary plasma and arcing.

[0023] The process kit 310 advantageously includes a metal shield 306 made of a conductive material and electrically connected to the pedestal 110. The covering 304 and the metal shield 306 are generally sized to accommodate the substrate 112. In some embodiments, the metal shield 306 is made of aluminum or copper. The metal shield 306 is disposed in the gap 318 between the covering 304 and the substrate 112. For example, the metal shield 306 is disposed adjacent to at least a portion of the lower surface 312 of the covering 304, so that the metal shield 306 at least partially lines the gap 318. The metal shield 306 advantageously provides an equipotential region in the gap 318, thereby substantially reducing or preventing the formation of secondary plasma or arcing in the gap 318. In some embodiments, the metal shield 306 includes an outer portion 352, a ledge 356 extending radially inward from the outer portion 352, and a lip 358 extending downward from the radially inward edge 362 of the ledge 356. In some embodiments, the metal shield 306 has a substantially uniform thickness.

[0024] In some embodiments, the distance 350 between the lower surface 364 of the outer portion 352 and the lower surface 366 of the lip 358 is less than about 2 mm. In some embodiments, the gap between the lip 358 of the metal shield 306 and the pedestal 110 is between about 0.2 mm and about 2 mm. In some embodiments, the outer surface 314 of the covering 304 is substantially coplanar with the outer surface of the metal shield 306. The inner diameter of the outer portion 352 of the metal shield 306 may be sized to be slightly larger than the outer diameter of the substrate 112. In some embodiments, as shown in Figure 3, the metal shield 306 is a separate component from the covering 304.

[0025] The pedestal 110 may include one or more substrate lift openings 315 for accommodating lift pins to selectively raise or lower the substrate 112. A lift assembly 324 having one or more actuators is coupled to the pedestal 110 and configured to selectively raise or lower the lift pins through the one or more substrate lift openings 315. The pedestal 110 may include one or more kit lift openings 317 for accommodating lift pins to selectively raise or lower the process kit 310. A lift assembly 320 having one or more actuators is coupled to the pedestal 110 and configured to selectively raise or lower the lift pins through the one or more kit lift openings 317.

[0026] FIG. 4 shows a schematic cross-sectional side view of a substrate support 122 according to at least some embodiments of the present disclosure. In some embodiments, as shown in FIG. 4, the metal shield 306 is coupled to the covering 304 in a suitable manner. For example, the metal shield 306 can be deposited on, coated on, fixed via an adhesive to, fastened to, etc. the covering 304. In some examples, the metal shield 306 includes a metal coating 402 applied on the lower surface 312 of the covering 304. In some embodiments, the metal coating 402 has a thickness of from about 100 microns to about 500 microns. In some embodiments, the metal coating 402 is applied to the lower surface of the body 322 and the radially outer surface 408 of the inner lip 326. In some embodiments, the metal coating 402 is applied to the lower surface of the body 322 and not to the lower surface 420 of the inner lip 326.

[0027] Figure 5 shows a schematic bottom view of the process kit 310 according to at least some embodiments of the present disclosure. Figure 6 shows a schematic bottom view of the process kit 310 according to at least some embodiments of the present disclosure. In some embodiments, as shown in Figure 5, the metal shield 306 includes a continuous annular shield. In some embodiments, as shown in Figure 6, the metal shield 306 includes a plurality of segments 610 arranged at regular intervals around the covering 304 and partially covering only the lower surface 410 of the body 322 of the covering 304. In some embodiments, the plurality of segments 610 cover about 30 percent or more of the total surface area of ​​the lower surface 410.

[0028] While the above applies to embodiments of the present disclosure, other and further embodiments of the present disclosure can be conceived without departing from its basic scope.

Claims

1. A process kit for a substrate process chamber, A covering configured to extend over an unprotected dicing tape on a tape frame substrate during use, having a central opening configured to expose a semiconductor wafer supported on the dicing tape during use, A metal shield disposed adjacent to at least a portion of the lower surface of the covering, wherein the metal shield at least partially lines the lower surface, and A process kit equipped with the following features.

2. The process kit according to claim 1, wherein the covering is made of quartz.

3. The process kit according to claim 1, wherein the metal shield includes an outer portion, a ledge extending radially inward from the outer portion, and a lip extending downward from the radially inward edge of the ledge.

4. The process kit according to claim 3, wherein the distance between the lower surface of the outer portion and the lower surface of the lip is less than approximately 2 mm.

5. The process kit according to claim 1, wherein the metal shield comprises a metal coating on the lower surface of the covering.

6. The process kit according to claim 5, wherein the metal coating has a thickness of about 100 microns to about 500 microns.

7. The process kit according to any one of claims 1 to 6, wherein the metal shield includes a continuous annular shield.

8. The process kit according to any one of claims 1 to 6, wherein the metal shield includes a plurality of segments arranged at regular intervals around the covering and partially covering the lower surface of the body of the covering.

9. A substrate support for a substrate process chamber, A pedestal having a support surface configured to support a tape frame substrate, and having one or more electrodes disposed on the pedestal, A process kit according to any one of claims 1 to 6, wherein the process kit is configured to cover a portion of the pedestal in order to define a gap between the lower surface of the process kit and the support surface that is sufficient to extend over the unprotected dicing tape of the tape frame substrate during use and to accommodate the dicing tape. A substrate support comprising...

10. The substrate support according to claim 9, wherein a metal shield is electrically connected to the pedestal, and so the metal shield at least partially lines the gap.

11. The substrate support according to claim 9, wherein the metal shield includes a plurality of segments arranged at regular intervals around the covering and partially covering the lower surface of the body of the covering.

12. The substrate support according to claim 9, wherein the covering includes a main body and an inner lip extending downward from the main body.

13. The substrate support according to claim 9, wherein the metal shield includes a continuous annular shield.

14. The substrate support according to claim 9, wherein the outer surface of the covering is substantially coplanar with the outer surface of the metal shield.

15. It is a process chamber, A chamber body having an internal space inside, A pedestal disposed in the internal space, having a support surface for a tape frame substrate and one or more electrodes disposed on the pedestal, A process kit according to any one of claims 1 to 6, wherein the metal shield of the process kit is coupled to the pedestal and disposed adjacent to at least a portion of the lower surface of the covering, so that the metal shield at least partially lines the lower surface. A process chamber equipped with a process chamber.

16. The process chamber according to claim 15, wherein the metal shield comprises a metal coating on the lower surface of the covering, the covering is made of quartz, and the metal shield includes a continuous annular shield.

17. The process chamber according to claim 15, wherein the metal shield is separate from the covering.

18. The process chamber according to claim 15, further comprising an RF power supply coupled to one or more electrodes in the pedestal.

19. The process chamber according to claim 15, wherein the metal shield is made of aluminum or copper.

20. The process chamber according to claim 15, wherein the metal shield includes an outer portion, a ledge extending radially inward from the outer portion, and a lip extending downward from the radially inward edge of the ledge, and the gap between the lip and the pedestal is between approximately 0.2 mm and approximately 2 mm.

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