Facilitating RFID tag assembly using integrated circuits with chamfered corners

Abstract

Ditching scribe lanes and widened regions on a wafer results in some corners of an RFID IC on the wafer being chamfered. The widened region increases a distance between adjacent ICs at their intersection, thereby reducing the likelihood of a tilted or rotating IC colliding with an adjacent IC. Further, the widened region allows a vision-based alignment system to operate from the back of a dicing tape to more accurately singulate ICs, reducing the likelihood of causing an IC to tilt or rotate during ejection of the RFID IC. The chamfered corners of the IC also reduce stress and brittleness of the IC at these regions, thereby reducing the likelihood of damage in a collision event.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 583,595, filed September 19, 2023. The disclosure of that provisional application is hereby incorporated herein by reference in its entirety. Background Technology

[0003] Radio Frequency Identification (RFID) systems typically include an RFID reader, also known as an RFID reader / writer or RFID interrogator, and an RFID tag. RFID systems can employ various methods to locate and identify objects to which the tag is attached. RFID systems are useful in product- and service-related industries for tracking objects being handled, inventoried, or transported. In such cases, an RFID tag is typically attached to an individual item or its packaging. RFID tags typically include, or are made of, a radio frequency (RF) integrated circuit (IC).

[0004] Semiconductor processing generally involves multiple photolithography, etching, electroplating, and doping operations to form an array of individual integrated circuit dies on a surface of a semiconductor substrate, such as a wafer. For RFID tag chip applications, the integrated circuit die density typically ranges from tens of thousands of dies per wafer. Each die is separated from other dies by a narrow, ineffective boundary called a scribe lane (the space between adjacent dies on a wafer). Once the wafer-level integrated circuit die fabrication and testing are complete, the individual dies are "unified".

[0005] Simulation can be achieved using a sawing process or a more modern approach using plasma cutting, which involves cutting along the scribe lines. While scribe lines used in mechanical sawing techniques can be tens of micrometers wide (e.g., 60 micrometers), wafers used in plasma cutting can have much narrower scribe lines, ranging from single-digit micrometers or smaller. As grain size decreases, plasma etching or similar techniques, along with the use of narrower scribe lines, allow for a substantial increase in the total grain area (e.g., an increase of 20% or more).

[0006] Some RFID ICs can be plasma diced while they are still on the wafer, on the dicing tape. After singulating the ICs, a direct-die-attach machine can be used to attach individual ICs directly from the dicing tape to a label inlay. Some direct-die-attach machines operate by using a pin to "eject" an individual IC for assembly. In these cases, the pin is aligned with a desired individual IC that is placed on the back of the dicing tape. The pin is then pressed against the dicing tape, deforming the tape to "eject" the desired IC by moving or pushing it relative to the other ICs on the wafer. The "ejected" IC is then directly attached to a label inlay or intermediate (e.g., a strip), for example, by using an adhesive.

[0007] If the pin is not precisely aligned with the center of an IC to be ejected, the pin can cause the IC to tilt during the ejection process. However, since the direct-die-attach process is generally pin-IC alignment from the back of the dicing tape, it can be difficult to "see through" the dicing tape to make accurate alignment.

[0008] When the streets are very narrow, as can be the case with plasma dicing, the diced ICs are very close to each other. During the ejection process, an ejected IC can tilt due to misalignment of the pin, as described above, or can rotate or shift due to uneven application of force, uneven release from the tape, or other reasons. A tilted or rotated IC can collide with a neighboring IC, causing damage to the tilted / rotated IC and / or the neighboring IC. The damage can be particularly evident at the corners of the IC, in part because the square corners are brittle. SUMMARY

[0009] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the DETAILED DESCRIPTION. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to determine the scope of the claimed subject matter.

[0010] The example pertains to a method for reducing IC damage during an integrated circuit (IC) ejection process. The method may include receiving a wafer containing uncut ICs mounted on a dicing tape. For a first plurality of parallel scribes between the ICs on the wafer, a second plurality of parallel scribes between the ICs on the wafer, the second plurality of parallel scribes being perpendicular to the first plurality of parallel scribes, and a plurality of widened regions located at the intersections of the first and second plurality of scribes, an area to be etched on the wafer may be defined. Each widened region may be configured such that at least one IC corner located at each intersection is chamfered during a wafer dicing process to reduce the incidence of IC-to-IC corner contact and damage during the ejection process. The method may also include trenching the first and second plurality of scribes. The method may further include trenching the widened regions to form a plurality of chamfered IC corners. Each widened region may be at least partially delimited by one or more chamfered IC corners. The method may then include ejecting a plurality of ICs from the dicing tape.

[0011] In other examples, an integrated circuit (IC) arrangement is configured to reduce IC damage during the IC ejection process. The arrangement may include multiple ICs mounted on a dicing tape. The arrangement may further include a first plurality of parallel trenches between the ICs and a second plurality of parallel trenches between the ICs, the second plurality of parallel trenches being perpendicular to the first plurality of parallel trenches. The arrangement may also include a plurality of open widening regions located at the intersection of the first and second plurality of trenches, wherein each open widening region is at least partially delimited by one or more chamfered IC corners, and is configured to reduce the incidence of IC-to-IC corner contact and damage during the ejection process.

[0012] In another example, a wafer is provided configured to reduce damage during the ejection process of an integrated circuit (IC). The wafer may include a plurality of ICs. The wafer may also include a first plurality of parallel runners between the ICs and a second plurality of parallel runners between the ICs, the second plurality of parallel runners being perpendicular to the first plurality of parallel runners. The wafer may further include a plurality of widened regions located at the intersections of the first and second plurality of runners, configured to increase an edge-to-edge spacing between the ICs at the intersections by chamfering at least one IC corner at each intersection during a wafer dicing process, thereby reducing the incidence of IC-to-IC corner contact and resulting damage during the IC ejection process.

[0013] These and other features and advantages will become apparent from a reading of the following detailed description and a review of the associated drawings. It should be understood that the foregoing general description and the following detailed description are illustrative only and do not limit the scope of the embodiments as described in the claims. Attached Figure Description

[0014] The following detailed description will be based on the accompanying drawings, wherein:

[0015] Figure 1 This is a block diagram of the components of an RFID system.

[0016] Figure 2 It is a simplified diagram showing the components of a passive RFID tag, such as those that can be used in... Figure 1 A tag used in the system.

[0017] Figure 3 It is a concept map used to explain Figure 1 The RFID system uses a half-duplex communication mode between its components.

[0018] Figure 4 It is a block diagram showing a detail of an RFID tag, such as... Figure 2 The RFID tag shown.

[0019] Figure 5A and 5B Example Figure 4 The block diagram shows the tag-to-reader pair and the signal path during reader-to-tag communication.

[0020] Figure 6 This example illustrates a process that begins with a blank (starting) chip and ends with a single IC.

[0021] Figure 7A This example illustrates how a direct die attach machine uses a pin to eject a specific IC onto a tag inlay or intermediate.

[0022] Figure 7B An example is given of how a misaligned ejector pin can cause the selected IC to collide with an adjacent IC during ejection, potentially damaging the IC.

[0023] Figure 8 Example: An intersection of two scribe lines and four ICs on a chip.

[0024] Figure 9 The examples illustrate various combinations of chamfering at the corners of ICs to create a widened area at the intersection of four ICs on a chip.

[0025] Figure 10The example illustrates various corner configurations for an IC.

[0026] Figure 11 According to an embodiment, a flowchart of a method is illustrated for unifying and attaching RFID ICs to an RFID tag or an RFID tag precursor, while using chamfered corners to reduce IC impact damage. Detailed Implementation

[0027] In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and specific embodiments or examples are shown by way of illustration. These embodiments or examples may be combined, other forms may be utilized, and structural changes may be made without departing from the spirit or scope of this disclosure. The following detailed description is therefore not intended to be limiting, and the scope of the invention is defined by the appended claims and their equivalents.

[0028] As used herein, “memory” refers to one of the following: ROM, RAM, SRAM, DRAM, NVM, EEPROM, FLASH, fuse, MRAM, FRAM, and other similar volatile and non-volatile information storage technologies. Some portions of the memory may be writable, while others may not. “Instruction” means a request to perform a single, explicit action on a tag (e.g., write data into memory). “Command” means a reader request to perform one or more actions on one or more tags, and includes one or more tag instructions preceded by a command identifier or command code that identifies the command and / or tag instructions. “Program” means a request to perform a set or sequence of instructions on a tag (e.g., read a value from memory, and lock a memory word if the read value is less than a threshold). “Protocol” means an industry standard for communication between a reader and a tag (and vice versa). One such protocol is the 860 MHz to 960 MHz Type 1 Gen 2 UHF RFID communication protocol (“Gen2 Protocol”) developed by GS1 EPCglobal, Inc., versions 1.2.0, 2.0, and 3.0 of which are hereby incorporated by reference. Another protocol is ISO / IEC 18000-63 Information Technology – Radio Frequency Identification for Article Management – ​​Part 63: Communication Parameters for Type C Air Interfaces from 860 MHz to 960 MHz (“ISO / IEC 18000-63”), which is also hereby incorporated by reference.

[0029] In cases where the scribe lanes on a wafer are very narrow, such as in plasma-cut wafers, the cut ICs are very close to each other. During the ejection process, an ejected IC may tilt, rotate, and / or shift, for example, due to misalignment of the ejector pins, uneven force applied to the IC, and / or uneven release of the IC from the scribe line. This IC may collide with adjacent ICs, causing damage. This damage can be particularly noticeable at the corners of the IC, partly because the corners are fragile.

[0030] The exemplary implementation offers numerous technical advantages. Manufacturing yield can be increased due to reduced damage to the IC during the unitization process. Furthermore, a costly, high-accuracy alignment system is not required, and further reduction in IC size can be tolerated without increasing IC damage during unitization.

[0031] Figure 1 This is a simplified diagram of the components of a typical RFID system 100 in conjunction with an embodiment. An RFID reader 110 and a nearby RFID tag 120 communicate via RF signals 112 and 126. When data is sent to tag 120, reader 110 generates RF signal 112 by encoding the data, modulating the encoded data into an RF waveform, and transmitting the modulated RF waveform as RF signal 112. Tag 120 can then receive RF signal 112, demodulate the encoded data from RF signal 112, and decode the encoded data. Similarly, when data is sent to reader 110, tag 120 generates RF signal 126 by encoding the data, modulating the encoded data into an RF waveform, and causing the modulated RF waveform to be transmitted as RF signal 126. Data transmitted between reader 110 and tag 120 can be represented by symbols, also known as RFID symbols. If desired, a symbol can be a separator, a calibration value, or implemented to represent binary data, such as "0" and "1". After being processed by reader 110 and tag 120, the symbol can be regarded as a value, a number, or any other suitable data representation type.

[0032] The RF waveforms transmitted by reader 110 and / or tag 120 may be within a suitable frequency range, such as close to 900 MHz, 13.56 MHz, or similar frequencies. In some embodiments, RF signals 112 and / or 126 may include non-propagating RF signals, such as reactive near-field signals or similar signals. RFID tag 120 may be active or battery-assisted (i.e., self-powered), or passive. In the latter case, RFID tag 120 may harvest power from RF signal 112.

[0033] Figure 2This is a simplified diagram of an RFID tag 220, which can be used as follows: Figure 1 Label 120. Label 220 may be formed on a substantially planar inlay or substrate 222, and may be implemented in any suitable manner. Label 220 includes a circuit that may be implemented as an IC 224. In some embodiments, IC 224 is fabricated using complementary metal-oxide-semiconductor (CMOS) technology. In other embodiments, IC 224 may be fabricated using other technologies, such as bipolar junction transistor (BJT) technology, metal-semiconductor field-effect transistor (MESFET) technology, and other technologies as will be well known to those skilled in the art. IC 224 is disposed on inlay 222.

[0034] Tag 220 also includes an antenna for transmitting and / or interacting with RF signals. In some embodiments, the antenna may be metal etched, deposited, and / or printed on inlay 222; conductive cores formed with or without substrate 222; non-metallic conductive (such as graphene) patterning on substrate 222; a first antenna inductively, capacitively, or current-coupled to a second antenna; or may be fabricated using a number of other methods available for forming an antenna to receive RF waves. In some embodiments, the antenna may even be formed in IC 224. Regardless of the antenna type, IC 224 is connected via appropriate IC contacts ( Figure 2 (Not shown) Electrically coupled to the antenna. The term “electrically coupled” as used herein may mean a direct electrical connection, or it may mean a connection comprising one or more intermediate circuit blocks, elements, or devices. The “electrical” part of the term “electrically coupled” as used herein shall mean a coupling that is one or more of ohmic / current, capacitive, and / or inductive. Similarly, the terms “electrically isolated” or “electrically decoupled” as used herein mean, at least to the extent possible, the absence of one or more types of electrical coupling (e.g., current, capacitive, and / or inductive). For example, electrically isolated components are current-isolated, capacitively isolated, and / or inductively isolated from each other. Of course, there will be some unavoidable stray capacitive or inductive coupling between electrically isolated components, but the purpose of isolation is to minimize such stray coupling when compared to an electrically coupled path.

[0035] IC 224 is shown with a single antenna port and includes two IC contacts electrically coupled to two antenna segments 226 and 228, which are shown herein forming a dipole. Many other embodiments may use any number of connection ports, contacts, antennas, and / or antenna segments. Antenna segments 226 and 228 are depicted as separate from IC 224, but in other embodiments, these antenna segments may alternatively be formed on IC 224. The tag antenna according to the embodiments can be designed in any form and is not limited to a dipole. For example, the tag antenna may be a patch, a slot, a loop, a coil, a horn, a helix, a monopole, a microstrip, a stripline, or any other suitable antenna.

[0036] Schematic diagram 250 illustrates a top and side view of a tag 252 formed using a strip. Tag 252 differs from tag 220 in that it includes a substantially planar strip substrate 254 with strip contacts 256 and 258. IC 224 is mounted on the strip substrate 254 such that IC contacts on IC 224 are electrically coupled to strip contacts 256 and 258 via appropriate connections (not shown). The strip substrate 254 is then placed on an inlay 222 such that strip contacts 256 and 258 are electrically coupled to antenna sections 226 and 228. The strip substrate 254 can be attached to the inlay 222 by crimping, an interface layer, one or more adhesives, or any other suitable means.

[0037] Schematic Figure 260 illustrates a side view of an alternative arrangement of the strip substrate 254 placed on the insert 222. Instead of having the surface including the strip contacts 256 / 258 facing the surface of the insert 222, the strip substrate 254 is positioned with its strip contacts 256 / 258 facing away from the surface of the insert 222. The strip contacts 256 / 258 can then be capacitively coupled to the antenna sections 226 / 228 through the strip substrate 254, or electrically coupled using a through-hole formed by pressing the strip contacts 256 / 258 to the antenna sections 226 / 228. In some embodiments, the positions of the strip substrate 254 and the insert 222 can be reversed, with the strip substrate 254 mounted below the insert 222 and the strip contacts 256 / 258 electrically coupled to the antenna sections 226 / 228 through the insert 222. Of course, in other embodiments, the strip contacts 256 / 258 can be electrically coupled to the antenna section 226 / 228 via both the inlay 222 and the strip substrate 254.

[0038] During operation, the antenna couples to an RF signal in the environment and propagates the signal to IC 224. IC 224 can harvest power based on the incoming signal and its internal state and respond as appropriate. If IC 224 uses backscatter modulation, it can generate a response signal (e.g., signal 126) from an RF signal in the environment (e.g., signal 112) by modulating the reflectivity of the antenna. Electrically coupling and decoupling the IC contacts of IC 224 modulates the reflectivity of the antenna, thus altering the admittance or impedance of a shunt or series-connected circuit element coupled to the IC contacts. If IC 224 is capable of transmitting a signal (e.g., having its own power supply, coupled to an external power supply, and / or harvesting sufficient power for signal transmission), IC 224 can respond by transmitting response signal 126. Figure 2 In one embodiment, antenna segments 226 and 228 are separate from IC 224. In other embodiments, the antenna segments may alternatively be formed on IC 224.

[0039] An RFID tag, such as tag 220, is typically attached to or associated with an individual article or article package. An RFID tag may be attached to an article or package after it has been manufactured, may be partially manufactured and then attached to the article or package, and may be completed once attached to the article or package, or the manufacturing process of the article or package may include the manufacture of the RFID tag. In some embodiments, the RFID tag may be integrated into the article or package. In this case, a portion of the article or package may serve as a tag component. For example, a conductive portion of the article or package may serve as a tag antenna section or contact. A non-conductive portion of the article or package may serve as a tag substrate or inlay. If the article or package includes an integrated circuit or other circuit system, a portion of that circuit system may be configured to operate as part or all of an RFID tag IC. Therefore, "RFID IC" does not necessarily refer to an article, but more generally means an article containing an RFID IC and an antenna capable of interacting with RF waves and receiving and responding to RFID signals. Because the boundaries between ICs, tags, and items are often blurred, the terms “RFID IC,” “RFID tag,” “tag,” or “tag IC” used in this article may refer to ICs, tags, or even items, as long as the referenced element is capable of RFID functionality.

[0040] Figure 1 The components of the RFID system can communicate with each other in any number of modes. One such mode is called full-duplex, in which the reader 110 and the tag 120 can transmit simultaneously. In some embodiments, the RFID system 100 may be capable of full-duplex communication. Another such mode, which is more suitable for passive tags, is called half-duplex, and is described below.

[0041] Figure 3 It is a concept map 300, used to explain Figure 1 The RFID system uses half-duplex communication between components, in which tag 120 is implemented as a passive tag. This explanation is implemented with reference to a timeline and also with reference to the human metaphors of "talking" and "listening." The actual technical implementation of "talking" and "listening" is described at this time.

[0042] In half-duplex communication mode, the RFID reader 110 and the RFID tag 120 take turns speaking and listening to each other. As seen on the timeline, reader 110, designated as "R During the interval of “T”, the speaker speaks to tag 120, and tag 120 speaks to tag 120 during the interval designated as “T”. The "R" signal is given to the reader 110 during intervals. For example, a sample R... The T interval occurs during time interval 312, during which reader 110 speaks (block 332) and tag 120 listens (block 342). A subsequent sample T... The R interval occurs during time interval 326, during which reader 110 listens (block 336) and tag 120 speaks (block 346). Interval 312 may belong to a different duration than interval 326, but here, the durations are shown to be approximately equal only for illustrative purposes.

[0043] During interval 312, reader 110 transmits, for example, Figure 1 The signal 112 is a signal (block 352), while the tag 120 receives the reader signal (block 362), processes the reader signal to extract data, and collects power from the reader signal. When the reader signal is received, the tag 120 does not backscatter (block 372), and therefore the reader 110 does not receive a signal from the tag 120 (block 382).

[0044] During interval 326, also known as a backscattering time interval or backscattering period, reader 110 does not transmit a data-bearing signal. Instead, reader 110 transmits a continuous wave (CW) signal, which is a carrier wave that is generally not encoded with information. The CW signal provides tag 120 with the energy to be acquired and a waveform that tag 120 can modulate to form a backscattering response signal. Therefore, during interval 326, tag 120 does not receive a signal with encoded information (block 366), but instead modulates the CW signal (block 376) to produce a backscattering response signal. Figure 2 A backscattered signal of the signal 126. Tag 120 can generate a backscattered signal by modulating the CW signal by adjusting its antenna reflectivity, as described above. Reader 110 then receives and processes the backscattered signal (block 386).

[0045] Figure 4 It is a block diagram showing a detail of an RFID IC, such as Figure 2 IC 224. Circuit 424 can be implemented in an IC, such as IC 224. Circuit 424 implements at least two IC contacts 432 and 433, which are suitable for coupling to an antenna section, such as... Figure 2 Antenna sections 226 / 228 are included. When two IC contacts form a signal input from an antenna and a signal echo sent to that antenna, it is typically referred to as an antenna port. IC contacts 432 and 433 can be implemented in any suitable manner, such as by conductive pads, bumps, or the like. In some embodiments, circuitry 424 implements more than two IC contacts, particularly when multiple antenna ports are configured and / or coupled to multiple antennas.

[0046] Circuit 424 includes a signal routing section 435, which may include signal wiring, a signal routing bus, a receive / transmit switch, and the like, for routing signals between components of circuit 424. IC contacts 432 / 433 may be current-, capacitively, and / or inductively coupled to signal routing section 435. For example, optional capacitors 436 and / or 438 may capacitively couple IC contacts 432 / 433 to signal routing section 435, thereby decoupling IC contacts 432 / 433 from signal routing section 435 and other components of circuit 424.

[0047] In some cases, capacitive coupling (and the resulting current decoupling) between IC contacts 432 and / or 433 and components of circuit 424 is desirable. For example, in some RFID tag embodiments, IC contacts 432 and 433 may be currently connected to terminals of a tuning circuit on the tag. In these embodiments, current decoupling of IC contacts 432 and 433 prevents a DC short circuit from forming between the IC contacts through the tuning circuit.

[0048] Capacitors 436 / 438 may be implemented within circuit 424 and / or partially or entirely outside circuit 424. For example, a dielectric or insulating layer on the surface of the IC containing circuit 424 may serve as the dielectric in capacitors 436 and / or 438. As another example, a dielectric or insulating layer on the surface of a tag substrate (e.g., inlay 222 or strip substrate 254) may serve as the dielectric in capacitors 436 / 438. Metal or conductive layers disposed on both sides of the dielectric layer (i.e., between the dielectric layer and the IC, and between the dielectric layer and the tag substrate) may then serve as terminals of capacitors 436 / 438. The conductive layers may include IC contacts (e.g., IC contacts 432 / 433), antenna segments (e.g., antenna segments 226 / 228), or any other suitable conductive layer.

[0049] Circuit 424 includes a rectifier and a PMU (Power Management Unit) 441, which harvests energy from the RF signal incident on antenna sections 226 / 228 to power the reader-to-tag circuit. T) and tag to reader (T) R) Circuitry that supplies power to IC 424 during one or both intervals. The rectifier and PMU 441 may be implemented in any manner known in the art and may include one or more components configured to convert an alternating current (AC) or time-varying signal into a direct current (DC) or substantially time-invariant signal.

[0050] Circuit 424 also includes a demodulator 442, a processing block 444, a memory 450, and a modulator 446. The demodulator 442 demodulates the RF signal received via IC contacts 432 / 433 and can be implemented in any suitable manner, such as using a chip, amplifier, and other similar components. The processing block 444 receives the output from the demodulator 442, performs operations such as command decoding, memory interfacing, and other related operations, and can generate an output signal for transmission. The processing block 444 can be implemented in any suitable manner, such as by means of a combination of one or more of a processor, memory, decoder, encoder, and other similar components. The memory 450 stores data 452 and can be at least partially implemented as permanent or semi-permanent memory, such as non-volatile memory (NVM), EEPROM, ROM, or other memory types configured to retain data 452 even when circuit 424 is not powered. Processing block 444 can be configured to read data from memory 450 and / or write data to memory 450.

[0051] Modulator 446 generates a modulated signal from the output signal generated by processing block 444. In one embodiment, modulator 446 generates the modulated signal by driving the load presented by the antenna sections(s) coupled to IC contacts 432 / 433 to form a backscattered signal as described above. In another embodiment, modulator 446 includes and / or uses a transmitter to generate and transmit the modulated signal via the antenna sections(s) coupled to IC contacts 432 / 433. Modulator 446 can be implemented in any suitable manner, such as using a switch, driver, amplifier, and other similar components. Demodulator 442 and modulator 446 can be separate components, combined in a single transceiver circuit, and / or part of processing block 444.

[0052] In some embodiments, particularly those with more than one antenna port, circuitry 424 may include multiple demodulators, rectifiers, PMUs, modulators, processing blocks, and / or memories.

[0053] Figure 5A Show Figure 4 The components of circuit 424, version 524-A, have been further modified to emphasize one R. T interval (e.g.: Figure 3 A signal operation during the time interval 312). In R During the T interval, demodulator 442 demodulates an RF signal received from IC contacts 432 / 433. The demodulated signal is provided to processing block 444 as C_IN, which in some embodiments may include a received symbol stream. Rectifier and PMU 441 may be active, for example, harvesting power from an incident RF waveform and supplying power to demodulator 442, processing block 444, and other circuit components. During the T interval, modulator 446 does not actively modulate a signal and is effectively decoupled from the RF signal. For example, signal routing segment 435 can be configured to decouple modulator 446 from the RF signal, or an impedance of modulator 446 can be adjusted to decouple it from the RF signal.

[0054] Figure 5B Show Figure 4 The components of circuit 424, version 524-B, have been further modified to emphasize a T. R interval (e.g.: Figure 3 A signal operation during a time interval of 326. In T During the R interval, processing block 444 outputs a signal C_OUT, which may include a symbol stream for transmission. Modulator 446 then generates a modulated signal from C_OUT and transmits the modulated signal via antenna sections coupled to IC contacts 432 / 433, as described above. In T During the R interval, the rectifier and PMU 441 can be active, while the demodulator 442 can actively demodulate a signal. In some embodiments, the demodulator 442 can be active during the T interval. During the R interval, the signal is decoupled from the RF signal. For example, the signal routing segment 435 can be configured to decouple the demodulator 442 from the RF signal, or an impedance of the demodulator 442 can be adjusted to decouple it from the RF signal.

[0055] In a typical embodiment, demodulator 442 and modulator 446 are operable to demodulate and modulate signals according to a protocol, such as the Gen2 protocol described above. In embodiments where circuitry 424 includes multiple demodulators, modulators, and / or processing blocks, each may be configured to support different protocols or different sets of protocols. A protocol partially specifies symbol encoding and may include a set of modulation, rate, timing, or any other parameters associated with data communication. A protocol may be a variant of an internationally approved protocol such as the Gen2 protocol, for example including fewer or additional commands required compared to the approved protocol, and so on. In some examples, additional commands may sometimes be referred to as custom commands.

[0056] Figure 6 This example illustrates a process that begins with a blank (starting) chip and ends with a single IC.

[0057] Schematic diagram 610 illustrates a starter wafer 612. The starter wafer 612 may be made of a semiconductor material, such as silicon. Silicon is sometimes doped with p-type or n-type impurities to improve its electronic properties, serving as a substrate for operation, as desired. The starter wafer 612 has a top surface 614 and a bottom surface 616 opposite to the top surface 614. Typically, circuitry for RFID ICs can be fabricated on the top surface 614, as described below.

[0058] Schematic diagram 620 illustrates a processed wafer 622, which includes integrated circuits (ICs) 624 separated from each other by scribe lines 626. The processed wafer 622 is derived from the fabrication of IC 624 on a starting wafer 612. IC 624 is fabricated using semiconductor manufacturing machines typically operated by a foundry. IC 624 is formed on the original surface of top surface 614, located both below and above the original surface in layers. Additionally, other materials are deposited on top surface 614, such as gate stacks for CMOS devices, interconnect layers (metal lines), devices on the silicon surface such as MIM (metal-insulator-metal) capacitors, and a circuit passivation layer, sometimes also referred to as a dielectric, as well as many other potential structures and layers. Thus, the processed wafer 622 acquires a new top surface 628, which is elevated from the original surface.

[0059] In the simplified diagram 620, only a few of these ICs 624 are shown for illustrative purposes. In practice, IC manufacturers attempt to produce as many of these ICs 624 as possible on a single processed wafer to increase the IC yield per wafer and thereby reduce the cost of individual ICs. The number of ICs on a wafer can be increased by (a) reducing the IC size and / or (b) reducing the width of the scribe lines between ICs.

[0060] Schematic diagram 630 is a representation of how IC 624 on wafer 622 is separated from each other in a process called "singleification". Singleification can be performed by cutting the processed wafer 622 along scribe lines 626 to form scribe line trenches 632. The scribe line trenches 632 may extend partially or entirely through the full height of the processed wafer. Generally, scribe line trench formation (or "trenching") occurs after IC fabrication, although in some cases, the trenches may be formed before or during IC fabrication. The size of a trench may depend on the specific technology or singleification technique used. In some cases, the sidewalls of the scribe line trench may be coated with a passivation layer. Singleification can be accomplished by mechanical sawing, laser cutting, or plasma cutting, among other methods. The resulting single-unit ICs 634 typically contain one of the individual ICs 624. The size of each single-unit IC (e.g., 634) is therefore determined in part by the size of the individual IC (e.g., 624). A single RFID IC can be attached to an RFID tag or RFID tag precursor (e.g., a tag inlay or intermediate).

[0061] As described in this article, RFID ICs on a chip can be individualized to separate individual ICs from each other. Before individualization, the chip can be mounted to a dicing tape, typically located on the back of the chip, so that the individualized IC is attached to the dicing tape. After individualization, the chip mounted on the dicing tape can be provided to a direct die attacher, which is assembled to attach the specific RFID IC on the chip to a tag inlay or intermediate.

[0062] Figure 7A This example illustrates how a direct die attach machine uses a pin to eject a specific IC onto a tag inlay or intermediate.

[0063] Figure 700A shows a simplified diagram of a direct die attach machine. The direct die attach machine holds a single-chip assembly mounted on the front side of a dicing tape 706, represented by single-chip ICs 708A, 708B, and 708C. Specifically, the direct die attach machine may use a vacuum cover 704 to hold the back side of the dicing tape 706. To attach a selected RFID IC, such as RFID IC 708B, to a tag insert or intermediary 712, the direct die attach machine first aligns a pin 702 located on the back side of the dicing tape 706 with the center of the selected IC 708B. Once aligned, the direct die attach machine presses the pin against the back side of the dicing tape 706, deforming the tape to eject IC 708B by moving or pushing it relative to adjacent ICs on the dicing tape 706 (e.g., ICs 708A and 708C). The ejected IC 708B can then be attached to a tag insert / intermediate 712, for example, using an adhesive 710. This process is called a direct die-attach RFID tag assembly process. The tag insert or intermediate 712 can also be called an RFID tag or an RFID tag precursor. Although this process is described with reference to ejecting the selected RFID IC 708B, multiple ICs can be ejected at once.

[0064] As mentioned above, increasing the yield of an IC from a wafer can involve reducing the IC size and / or reducing the scribe line width between ICs. In some cases, this results in very narrow scribe line trenches, leading to very small gaps between an IC ejected during a direct die attachment process and adjacent ICs. If a pin is not precisely aligned with a selected IC, the resulting tilt of the IC will cause it to collide with an adjacent IC, potentially damaging the IC involved in the collision.

[0065] Figure 7B An example is given of how a misaligned ejector pin can cause the selected IC to collide with an adjacent IC during ejection, potentially damaging the IC.

[0066] Schematic diagram 700B illustrates a selected IC 724 ejected from IC 708 during a direct die attachment process. The ejector pin 702 is not properly aligned with the center of IC 724, causing IC 724 to tilt during ejection. As a result, the selected IC 724 collides with an adjacent IC (at collision point 722), potentially damaging both the selected IC 724 and the adjacent IC.

[0067] Even when a ejector pin is correctly aligned with an IC to be ejected, the narrow scribe grooves can still cause the IC to rotate or shift (e.g., due to uneven force application, uneven adhesive release, or similar reasons), resulting in collisions with adjacent ICs and subsequent damage.

[0068] Furthermore, narrow scribe lines and grooves can make precise needle alignment more difficult. Direct die attachment processes generally involve needle-IC alignment from the back of the dicing tape. An alignment system may struggle to fully penetrate the dicing tape for accurate alignment, and if the system uses scribe lines or grooves to guide alignment, narrow scribe lines can exacerbate the difficulty. Additionally, larger ICs can tolerate a greater degree of misalignment at the top of the die before tilting significantly enough to damage the IC, while smaller RFID ICs cannot tolerate such a large amount of misalignment before tilting significantly enough to damage the IC.

[0069] As mentioned above, the yield of an IC chip depends in part on the IC size and the scribe line width. As the IC size or scribe line width decreases, the IC yield increases. However, such reductions in size and width can increase the likelihood of IC damage, thereby reducing IC yield. For example, in the direct die-attach process described above, the reduced IC size and scribe line width increase the probability of collisions and IC damage during ejection, resulting in a decrease in IC yield. Collision-based IC damage can be particularly noticeable at the corners of the IC.

[0070] Figure 8 This example illustrates the intersection of two scribe lines and four ICs on a chip. Simplified diagram 800 shows the intersection of two scribe lines 804 and 806 between four ICs 802A to 802D. When scribe lines 804 and 806 are narrow, the adjacent ICs 802A to 802D are also very narrowly spaced. In this situation, if an ejected IC tilts or rotates, its edges and corners may collide with the edges and corners of adjacent ICs (potential corner collision 808). Damage to ICs can be particularly noticeable at IC corners compared to IC edges, partly due to increased brittleness of the corners compared to straight edges. In some cases, a tilted or rotated IC can damage multiple adjacent ICs.

[0071] According to some examples, the corners of ICs at the intersection of engravings can be chamfered to create a widened area (e.g., relative to the width of the engraving) at the intersection after trenching. This widened area increases the edge-to-edge spacing between adjacent ICs at the intersection, reducing the likelihood of corner collisions and damage, and potentially improving visibility for vision-based alignment systems. In this disclosure, a chamfered corner refers to a corner or corner region that is more rounded or obtuse than a right angle. Similarly, chamfering a corner means reducing the sharpness of the corner. For example, chamfering an IC corner may involve transforming one corner of an IC into two or more vertices. For a rectangular IC, chamfering an IC corner can transform a right-angled IC corner into two or more obtuse-angled corners, thereby transforming the rectangular IC into a polygonal IC with more than four sides. A chamfered corner with two 135-degree obtuse angles can be referred to as a flat corner. Creating a chamfer can also involve rounding one or more IC corners, which may involve eliminating one or more vertices and forming a curve or arc. In some examples, chamfering IC corners can be accomplished using an etching process such as plasma cutting, which allows for the formation of edges and corners of arbitrary shapes.

[0072] Chamfering the corners of ICs to create a wider area at the intersection of runners offers several advantages. First, it increases the distance between the edges of adjacent ICs at the runner intersection, thereby reducing the likelihood of a tilted or rotated IC colliding with an adjacent IC. The runners can have a width of 100 μm, 10 μm, 5 μm, or any suitable width. Embodiments are particularly beneficial at these dimensions. Second, chamfering the corners of ICs reduces the stress and brittleness of the ICs at those corners, thereby reducing the likelihood of damage in a collision event. For example, in an IC-to-IC corner collision, the force experienced by each IC is concentrated at the corner point. By converting the corner into two or more vertices, or even by rounding the corner to create a chamfer, the force experienced over a larger area is dispersed, reducing the likelihood of damage. Third, chamfering the corners of the IC to create a wider area at the intersection of the scribe lines will result in larger open areas or openings at those intersections. This can improve the visibility of those intersections for vision-based alignment systems operating from the back of the scribe line, thereby assisting in needle-IC alignment.

[0073] Figure 9The examples illustrate various combinations of chamfered corners of ICs used to create a widened area at the intersection of two traces (and four ICs) on a die. Simplified diagrams 900A to 900D show examples of chamfered corners at the intersection of traces on a die. For example, simplified diagram 900A shows ICs 902A to 902D, where only IC 902D has a chamfered corner at trace intersection 904. Simplified diagram 900B shows two ICs, ICs 902C to 902D, with chamfered corners at trace intersection 904. Simplified diagram 900C shows ICs 902A, 902C, and 902D with chamfered corners at trace intersection 904. Simplified diagram 900D shows all ICs 902A to 902D with chamfered corners at trace intersection 904. Please note that in some cases where only the two IC corners at the intersection of a single engraving line form a chamfer, the two chamfered corners can be opposite each other on the diagonal.

[0074] The increase in distance between adjacent ICs depends on the chamfer applied to the corners. Referring to Figure 900D, assume a scribe line width of x, and the corners of ICs 902A to 902D are chamfered to a depth equal to the width x to create a flat angle with two equal obtuse angles of 135 degrees. Referring to IC 902A, this chamfer increases the edge-to-edge spacing between adjacent ICs 902B to 902D at all points on the chamfered edge, except at the exact endpoints of the edges. In one example, the edge-to-edge spacing can be defined using the midpoint of the chamfered edge. Using this definition, the midpoint of the chamfered edge of 902A provides an increase of x / 2 relative to the non-chamfered corner, i.e., the corner of 902A in Figure 900A. The increased edge-to-edge spacing between the midpoint of the chamfered edge of 902A and the midpoint of any adjacent ICs 902B to 902C is then at least equal to the scribe line width x. Edge-to-edge spacing can be defined in other ways, such as by the minimum distance between the edges of two adjacent ICs, the maximum distance between the edges of two adjacent ICs, the average distance between the edges of two ICs, or any other appropriate method.

[0075] As suggested in Figures 900A to 900D, in some examples, a rectangular IC may have one, two, three, or all four of its right-angled corners that have been chamfered or rounded. Figure 10 The examples illustrate various corner configurations for an IC. Figure 1000 shows IC 1002 with a single chamfered corner, IC 1004 with two chamfered corners, IC 1006 with three chamfered corners, and IC 1008 with four chamfered corners.

[0076] The specific IC corners that form a chamfer can be selected based on any suitable approach. In some cases, the IC corners to be chamfered can be chosen to provide a widened area with an orthographically dependent shape at a scribe line intersection. For example, if fewer than four IC corners exist at a particular scribe line intersection to form a chamfer, as shown in simplified figures 900A to 900C, the widened area resulting from that intersection has a shape when trenching is performed, which provides information about how the wafer is oriented. This orthographically dependent shape can be used as a means for vision-based alignment systems to determine the IC and / or wafer orientation.

[0077] Please note that, although Figure 9 and 10 The illustration shows IC corners that are chamfered in the same way (i.e., a right-angle corner is chamfered to create two vertices with equal included angles). In some cases, different corners existing on a single IC or at the intersection of a certain groove can be chamfered in different ways. For example, a corner can be chamfered as follows: Figure 9 and 10 The corner shown forms a chamfer, while another corner can form a chamfer to create three or more vertices, or to form an arc.

[0078] Chamfering one or more corners of an IC involves sacrificing some IC area that would otherwise be available for additional circuitry or support structures. Generally, the circuitry or structure closest to the IC's edge or corner will be most affected by the chamfering. In these cases, the relevant circuitry or structure can be designed to accommodate the potential chamfering. For example, some ICs include an IC sealing ring, which helps physically reinforce the IC and isolate the (electrical and / or physical) circuitry within it. In this situation, portions of the IC sealing ring that might be affected by the chamfering, such as the outer corners of the IC sealing ring, can be designed to accommodate the chamfered IC corners without damaging or otherwise impairing the functionality of the IC sealing ring. More specifically, the geometry of the chamfered IC can be considered a boundary within which the IC sealing ring is completely contained, ensuring that the IC sealing ring is not damaged when the IC corners are chamfered.

[0079] Figure 11 According to an embodiment, a flowchart of a method 1100 is illustrated for unifying and attaching RFID ICs to an RFID tag or an RFID tag precursor, while using chamfered corners to reduce IC-to-IC collisions. Method 1100 may begin at block 1102, where an unifying system receives a chip mounted on a dicing tape and including an uncut RFID IC.

[0080] At block 1104, the unification system can define an area to be etched on the wafer for IC unification. This area may include, but is not limited to, a first plurality of parallel scribe lines on the wafer between the ICs, a second plurality of parallel scribe lines on the wafer between the ICs and perpendicular to the first plurality of scribe lines, and a plurality of widened regions located at the intersections of the first and second plurality of scribe lines. Each widened region may be at least partially bounded by one or more IC corners at the respective intersections and may be configured such that the IC corner(s) are chamfered during a subsequent wafer dicing process to reduce the incidence of IC-to-IC corner contact and damage during a direct die attachment process. The incidence of IC-to-IC corner contact can be defined in any suitable manner, such as a measurement of IC-to-IC corner collisions per unit time, an amount or percentage of IC-to-IC collisions occurring during an ejection process, a percentage of IC-to-IC collisions occurring per wafer, or otherwise. Additionally, the incidence can also be correlated with the degree of IC damage caused by a collision. The implementation can significantly reduce the incidence of high damage levels (e.g., due to increased edge-to-edge spacing, force spreading from one point to an edge, or other factors).

[0081] In block 1106, the unification system can cut the wafer by trenching in the first and second plurality of scribe lines and the widened region to form scribe line trenches and pits or openings in the widened region. The openings in the widened region can be at least partially delimited by one or more chamfered IC corners. The unification process can be performed by mechanical sawing, laser cutting, plasma cutting, and other methods.

[0082] At block 1108, a direct die attach machine aligns a pin to a selected IC on a dicing wafer from a second surface of a dicing tape opposite a first surface to which the wafer is attached. A vision-based alignment system can be used to align the pin to the selected IC. An opening at the widened area created at block 1106 can be used to improve the accuracy of the vision-based alignment system. In some examples, orientation-dependent openings at the widened area formed by using three or fewer chamfered corners or different types of chamfers applied to two or more IC corners (e.g., flat corners, rounded corners, a combination of obtuse angles, or any other suitable arbitrary shape) can be used by the vision-based alignment system to determine the IC and / or wafer orientation and increase the accuracy of pin alignment.

[0083] At block 1110, the direct die attach machine can use ejector pins to eject selected ICs from a plane of a diced wafer. A widened area around the selected IC reduces the rate of IC-to-IC contact and damage during the ejection process. The selected IC can be ejected onto an adhesive on an RFID tag or RFID tag precursor, or onto an antenna terminal on an RFID tag or RFID tag precursor. The direct die attach machine can continue to eject multiple ICs from the dicing tape used. In some embodiments, as described above, the ICs can be ejected from the dicing tape one at a time. Thus, all ICs on the wafer can be repeatedly aligned and ejected using the alignment and ejection processes described in blocks 1108 and 1110. In other embodiments, the direct die attach machine can be configured to eject multiple ICs at once. A reduction in the rate of IC-to-IC corner contact and damage can be determined by comparing the probability of occurrence during multiple single ejections, a single ejection of multiple ICs, or multiple ejections of multiple ICs.

[0084] The number and order of steps in method 1100 are not intended to present a limitation in the embodiments. Using the principles described herein, method 1100 can be performed in a different order in the various blocks described above, and fewer or additional program blocks can be used.

[0085] According to some examples, a method for reducing integrated circuit (IC) damage during an IC ejection process may include receiving a wafer containing uncut ICs mounted on a dicing tape, and defining areas to be etched on the wafer. The wafer may include a first plurality of parallel scribes between the ICs, a second plurality of parallel scribes between the ICs perpendicular to the first plurality of scribes, and a plurality of widened regions located at intersections of the first and second plurality of scribes, each widened region being configured such that at least one IC corner located at each intersection is chamfered during a wafer dicing process to reduce the incidence of IC-to-IC corner contact and damage during an ejection process. The method may further include dicing the wafer by trenching the first and second plurality of scribes; and trenching the widened regions to form a plurality of chamfered IC corners, wherein each widened region is at least partially delimited by one or more chamfered IC corners. The method may also include ejecting a plurality of ICs from the dicing tape.

[0086] According to other examples, the plurality of chamfered IC corners may include one or more of a flat angle, a rounded corner, or a combination of two or more obtuse angles. At least one of the plurality of ICs may include an IC sealing ring designed to accommodate the chamfered corner of the IC. Ejecting the plurality of ICs from the dicing strip may include using a vision-based alignment system to align a pin with a selected IC among the plurality of ICs, wherein the vision-based alignment system is configured to align the pin using one or more of the plurality of trenched widened areas around the selected IC; and ejecting the selected IC onto an RFID tag or an RFID tag precursor. At least one of the widened areas around the selected IC may be trenched such that at least one, but not all, of the IC corners defining the widened area are chamfered to form an azimuthal trenched widened area, and the azimuthal trenched widened area is used by the vision-based alignment system to determine the orientation of the IC and / or the chip and to improve the accuracy of the alignment of the pin.

[0087] According to a further example, at least one of the widened regions is trenched such that different types of chamfering are applied to two or more IC corners defining the widened region to form an orthographically dependent trenched widened region. This orthographically dependent trenched widened region is used by the vision-based alignment system to determine the IC and / or wafer orientation and improve the accuracy of the alignment of the ejector pin. Ejecting the plurality of ICs from the dicing tape may include ejecting one IC at a time, wherein the incidence of IC corner contact and damage is determined by comparison with multiple ejections, or ejecting multiple ICs at once, wherein the incidence of IC corner contact and damage is determined by comparison with a single ejection of multiple ICs, or the incidence of IC corner contact and damage is determined by comparison with multiple ejections of multiple ICs.

[0088] According to some examples, an integrated circuit (IC) arrangement structure is configured to reduce IC damage during an IC ejection process, and may include a plurality of ICs mounted on a dicing tape; a first plurality of parallel trenches between the ICs; a second plurality of parallel trenches between the ICs, the second plurality being perpendicular to the first plurality; and a plurality of open widened regions located at the intersection of the first and second plurality of trenches, wherein each open widened region is at least partially delimited by one or more chamfered IC corners, and is configured to reduce the incidence of IC-to-IC corner contact and damage during the ejection process.

[0089] According to other examples, at least one of the open widening regions is at least partially demarcated by three or fewer IC corners, forming a unidirectionally dependent open widening region. In yet another example, at least one of the open widening regions is at least partially demarcated by two or more IC corners with different chamfer types, forming a unidirectionally dependent open widening region. The first and second plurality of parallel trenches and the plurality of open widening regions can be trenched using plasma cutting. For each of the plurality of ICs, a vision-based alignment system can be used to align a pin with the IC, and the vision-based alignment system is configured to align the pin using the open widening region around the IC. At least one of the plurality of ICs may include an IC sealing ring designed to accommodate the chamfered corners of the IC. The width of each trench in the first and second plurality of trenches may be less than 10 μm.

[0090] According to a further example, a wafer is configured to reduce damage during an integrated circuit (IC) ejection process, and may include a plurality of ICs; a first plurality of parallel scribe lines between the ICs; a second plurality of parallel scribe lines between the ICs, the second plurality being perpendicular to the first plurality; and a plurality of widened regions located at the intersections of the first and second plurality of scribe lines, configured to increase an edge-to-edge spacing between the ICs at the intersections by causing at least one IC corner at each intersection to be chamfered during a wafer dicing process, thereby reducing the incidence of IC-to-IC corner contact and resulting damage at the intersections during the IC ejection process.

[0091] According to some examples, the plurality of widened regions are orientationally dependent widened regions, which are at least partially defined by three or fewer IC corners to be chamfered at the intersection, or by two or more IC corners at the intersection causing different types of chamfering to be applied. Each of the plurality of ICs is ejected from the cut strip after the widened region is formed. The widened region can be formed by plasma cutting. The width of each of the first and second plurality of scribe lines may be less than 10 μm. The IC corners may be chamfered to form a flat angle, and the edge-to-edge spacing is measured between the midpoints of the chamfered corners of adjacent ICs and is at least twice the width of the scribe line.

[0092] As for the foregoing, the embodiments are aimed at facilitating RFID tag assembly using integrated circuits with chamfered corners. The embodiments further include a program and a method of operating the program for the manufacture of the RFID IC. A program is generally defined as a set of steps or operations that lead to a desired result, due to the nature of the elements in the steps and their sequence. A program is typically beneficially implemented as a sequence of steps or operations for a processor, but can be implemented in other processing elements such as FPGAs, DSPs, or other devices as described above.

[0093] Performing a procedure, instruction, or operation requires manipulating physical quantities. Typically, though not always, these quantities can be transferred, combined, compared, and otherwise manipulated or processed according to the stated steps or instructions, and they can also be stored in a computer-readable medium. These quantities, for example, include electrical, magnetic, and electromagnetic charges or particles, states of matter, and more generally, the state of any physical device or element. The information represented by the state of these quantities may be called bits, data bits, samples, values, symbols, characters, items, numbers, or the like. However, these and similar terms are associated individually or in groups with labels applied to the appropriate physical quantities and are merely convenient markings.

[0094] The embodiments further include storage media. These media, individually or in combination with other media, store instructions, data, keys, signatures, and other data of a program executed according to the embodiments. A storage medium according to an embodiment is a computer-readable medium, such as a memory, and can be read by a processor of the type described above. If it is a memory, it can be implemented using any of the methods described and any of the techniques described above.

[0095] Even if a program is said to be able to be stored on a computer-readable medium, it does not need to be a single memory, or even a single machine. Its various parts, modules, or features may reside in separate memory, or even in a separate machine. The separate machine may be directly connected, or connected through a network such as a local access network (LAN), or a global network such as the Internet.

[0096] Typically, for convenience, a program is intended to be implemented and described as software. This software can be a monolithic structure or it can be viewed as various interconnected software modules.

[0097] The foregoing detailed description has presented various embodiments of the described apparatus and / or processes using block diagrams and / or examples. Within this scope, as such block diagrams and / or examples contain one or more functionalities and / or states, each functionality and / or state within such block diagrams or examples can be individually and / or collectively implemented by various hardware, software, firmware, or virtually any combination thereof. Some states of the embodiments disclosed herein can be implemented, wholly or partially, using integrated circuits to equivalently implement one or more computer programs running on one or more computers (e.g., one or more programs running on one or more computer systems), one or more programs running on one or more processors (e.g., one or more programs running on one or more microprocessors), firmware, or virtually any combination thereof, and designing circuit systems and / or writing code for the software and / or firmware will, given this disclosure, be perfectly within the skill of those skilled in the art.

[0098] This disclosure is not intended to limit itself to the specific embodiments described herein, which are intended as examples of various embodiments. Many modifications and variations can be made without departing from its spirit and scope. In addition to those listed herein, functionally equivalent methods and apparatus within the scope of this disclosure will also be apparent to those skilled in the art from the foregoing description. Such modifications and variations are intended to fall within the scope of the appended claims. This disclosure is limited only by the terminology of the appended claims and the full scope of their equivalents. It should be understood that this disclosure is not limited to any particular method, configuration, tag, RFIC, reader, system, or the like, which are of course subject to change. It should also be understood that the terminology used herein is for illustrative purposes only and is not intended to be limiting.

[0099] Regarding the use of any plural and / or singular terms in this document, those skilled in the art can translate them from plural to singular and / or from singular to plural depending on the appropriateness of the context and / or application. For clarity, various singular / plural permutations may be explicitly presented herein.

[0100] Generally, the terminology used herein, and especially in the appended claims (e.g., the main body of the appended claims), is largely intended to be “open-ended” (e.g., the present participle of “comprising” should be interpreted as “including but not limited to”, the present participle of “having” should be interpreted as “at least having”, the present tense of “comprising” should be interpreted as “including but not limited to”, etc.). If a particular number in a claim statement is intended, this intention will be explicitly stated in that claim, and if no such statement is made, this intention does not exist. For example, to aid understanding, the appended claims may contain the use of introductory terms “at least one” and “one or more” to introduce the claim statement. However, the use of such words should not be construed as implying that the introduction of a claim statement by the indefinite article "a" or its variants limits any particular claim containing such an introduced claim statement to an embodiment containing only one such statement, even if the same claim includes the introductory words "a or more" or "at least one" and indefinite articles such as "a" or its variants (e.g., "a" and / or its variants should be interpreted as meaning "at least one" or "a or more"); the same applies to the use of definite articles used to introduce claim statements. Furthermore, even if a specific number is explicitly stated in an introductory claim statement, such a statement should still be interpreted as meaning at least the stated number (e.g., a simple statement of "two statements" without other modifiers implies at least two statements, or two or more statements).

[0101] Furthermore, in instances where a common phrase such as "at least one of A, B, and C" is used, this interpretation is generally intended to be understood by a person skilled in the art in terms of the concept of the common phrase (e.g., "a system having at least one of A, B, and C" includes, but is not limited to, systems having A alone, having B alone, having C alone, having A and B together, having A and C together, having B and C together, and / or having A, B, and C together). Any transition words and / or phrases presenting two or more alternative terms, whether in the specification, claims, or drawings, should be understood to encompass all possibilities: including one of the terms, any one of the terms, or both of the terms. For example, the term "A or B" would be understood to include the possibility of "A" or "B" or "A and B".

[0102] For any and all purposes, such as providing a written description, all scopes disclosed herein also encompass any and all possible subscopes and combinations thereof. Any listed scope can readily be considered sufficient to describe and realize the decomposition of the same scope into at least equal halves, thirds, quarters, fifths, tenths, etc. As a non-limiting example, the scopes discussed herein can readily be decomposed into the lower third, middle third, and upper third, etc. All expressions such as “up to,” “at least,” “greater than,” “less than,” and the like include the listed numbers and signify a scope that can subsequently be decomposed into subscopes as described above. Finally, a scope includes individual members. Thus, by example, a group having 1 to 3 units means a group having 1, 2, or 3 units. Similarly, a group having 1 to 5 units means a group having 1, 2, 3, 4, or 5 units, and so on.

Claims

1. A method for reducing IC damage during the ejection process of an integrated circuit (IC), the method comprising: Receive a wafer containing an uncut IC mounted on a dicing tape; The area to be etched is defined on the wafer, including: The first plurality of parallel scribe lines on the chip, located between the ICs. The second plurality of parallel scribe lines on the wafer, located between the ICs, are perpendicular to the first plurality of parallel scribe lines. Multiple widened regions are located at the intersection of the first plurality of scribe lines and the second plurality of scribe lines. Each widened region is configured such that at least one IC corner located at each intersection forms a chamfer during a wafer dicing process, so as to reduce the incidence of IC-to-IC corner contact and damage during an ejection process. The wafer is cut by performing the following actions: To excavate trenches for the first plurality of engraved grooves and the second plurality of engraved grooves; and The widened area is trenched to form a plurality of chamfered IC corners, wherein each widened area is at least partially demarcated by one or more of the chamfered IC corners; as well as Multiple ICs are ejected from the dicing strip.

2. The method of claim 1, wherein the plurality of chamfered IC corners comprise one or more of a combination of flat corners, rounded corners, or two or more obtuse angles.

3. The method of claim 1, wherein at least one of the plurality of ICs includes an IC sealing ring designed to accommodate the chamfered corner of the IC.

4. The method of claim 1, wherein ejecting the plurality of ICs from the dicing tape comprises: A vision-based alignment system is used to align the ejector pin with a selected IC from the plurality of ICs, wherein the vision-based alignment system is configured to align the ejector pin using one or more of a plurality of trenched widened areas surrounding the selected IC; and The selected IC is pushed onto the RFID tag or RFID tag precursor.

5. The method of claim 4, wherein At least one of the widened areas surrounding the selected IC is trenched, such that at least one, but not all, IC corners defining the widened area are chamfered to form an orientation-dependent trenched widened area. The orientation of the trenched and widened area is used by the vision-based alignment system to determine the orientation of the IC and / or chip and improve the accuracy of the alignment of the ejector pin.

6. The method of claim 4, wherein At least one of the widened areas is trenched, such that different types of chamfering are applied to two or more IC corners defining the widened area to form an azimuthally dependent trenched widened area, and The orientation of the trenched and widened area is used by the vision-based alignment system to determine the orientation of the IC and / or chip and improve the accuracy of the alignment of the ejector pin.

7. An integrated circuit (IC) arrangement structure, configured to reduce IC damage during the IC ejection process, the arrangement structure comprising: Multiple ICs assembled on a cutting tape; The first plurality of parallel trenches between the ICs; A second plurality of parallel trenches are located between the ICs, the second plurality of parallel trenches being perpendicular to the first plurality of parallel trenches; and Multiple open widening regions are located at the intersection of the first plurality of trenches and the second plurality of trenches, wherein each open widening region is at least partially demarcated by one or more chamfered IC corners and is configured to reduce the incidence of IC-to-IC corner contact and damage during the ejection process.

8. The IC arrangement structure as claimed in claim 7, wherein the first plurality of parallel trenches, the second plurality of parallel trenches, and the plurality of open widened regions are trenched using plasma cutting.

9. The IC arrangement as claimed in claim 7, wherein for each of the plurality of ICs, a vision-based alignment system is used to align a pin with the IC, and the vision-based alignment system is configured to align the pin using the open widened area around the IC.

10. The IC arrangement structure as claimed in claim 7, wherein the width of each of the first plurality of trenches and the second plurality of trenches is less than 10 μm.

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