Method for manufacturing semiconductor element

Abstract

The invention discloses a manufacturing method of a semiconductor element. A flat surface of the silicon pillar is provided. At least one first trench is formed in a substrate. A conductive material is deposited to partially fill the first trench. An insulating sheet is formed in the first trench and extends into the conductive material. An isolation material is deposited in the first trench to cover portions of the conductive material exposed around the insulating sheet. The deposition of the isolation material also includes enclosing at least one void in the isolation material.

Description

Technical Field

[0001] The present invention claims priority to U.S. patent application Ser. No. 18 / 635,407 (i.e., priority date is “April 15, 2024”), the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a method for manufacturing a semiconductor structure and a semiconductor structure formed by the method. In particular, the present disclosure relates to a method for preparing a planar surface for manufacturing a recessed access structure and the structure. Background Art

[0003] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically formed by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and assemblies. As the semiconductor industry has advanced to advanced technology process nodes in pursuit of greater device density, higher performance, and lower costs, the challenge of precisely controlling component configuration has emerged.

[0004] The discussion in the prior art section provides background information only. Statements in the discussion in the prior art section are not an admission that the contents disclosed in such section constitute the prior art of the present disclosure, and no part of the discussion in the prior art section shall be used as an admission that any part of the present disclosure, including the part in the discussion in the prior art section, constitutes the prior art of the present disclosure. Summary of the Invention

[0005] An object of the present invention is to provide a method for manufacturing a semiconductor device to solve at least one of the above problems.

[0006] One aspect of the present disclosure provides a method for fabricating a semiconductor structure. The method includes: forming at least one first trench in a substrate; depositing a conductive material to partially fill the first trench; forming an insulating sheet in the first trench and extending into the conductive material; and depositing an isolation material in the first trench to cover the portion of the conductive material exposed around the insulating sheet. Depositing the isolation material also includes enclosing at least one void in the isolation material.

[0007] Another aspect of the present disclosure provides a method for fabricating a semiconductor structure. The method includes: forming a silicon portion, multiple dielectric portions, and multiple oxide portions in a substrate; forming at least one first trench in the silicon portion of the substrate; forming a word line in the first trench; forming multiple first impurity regions and multiple second impurity regions in the substrate; forming a first dielectric layer over the substrate to cover the word line; and forming a second dielectric layer to cover the first dielectric layer. The first trench has a W-shaped profile. Each of the multiple second impurity regions is disposed between a pair of legs of the word line.

[0008] Another aspect of the present disclosure provides a semiconductor structure. The semiconductor structure includes: a substrate having a silicon portion, multiple dielectric portions, and multiple oxide portions; at least one first trench disposed in the silicon portion of the substrate; a word line disposed in the first trench; and multiple first impurity regions and multiple second impurity regions disposed in the substrate. The first trench has a W-shaped profile. Each of the multiple second impurity regions is disposed between a pair of legs of the word line.

[0009] The above has been a fairly broad overview of the technical features and advantages of the present disclosure so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those skilled in the art of the present disclosure that the concepts and specific embodiments disclosed below can be readily utilized to modify or design other structures or processes to achieve the same purposes as those of the present disclosure. It should also be understood by those skilled in the art of the present disclosure that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The disclosure of the present invention can be more fully understood by referring to the embodiments and claims. The present disclosure should also be understood in conjunction with the reference numerals of the accompanying drawings, which represent similar elements throughout the specification.

[0011] Figure 1 is a 3D perspective view illustrating an intermediate stage in the formation process of a semiconductor structure according to some embodiments of the present disclosure;

[0012] Figure 2 is a 3D perspective view illustrating an intermediate stage in the formation process of a semiconductor structure according to some embodiments of the present disclosure;

[0013] Figure 3 This is an enlarged view, for example Figure 2 a portion of an intermediate stage during formation of a semiconductor structure of some embodiments;

[0014] Figures 4 to 19 It is along Figure 2A cross-sectional view taken along the section line AA' in FIG. 1 illustrates an intermediate stage in the formation process of a semiconductor structure according to some embodiments of the present disclosure;

[0015] Figures 20 to 21 is a cross-sectional view illustrating an intermediate stage in the formation process of a semiconductor structure according to some embodiments of the present disclosure;

[0016] Figure 22 is a flow chart illustrating a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure;

[0017] Figure 23 is a flow chart illustrating a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0018] The reference numerals are as follows:

[0019] 10A: Semiconductor Structure

[0020] 10B: Semiconductor Structure

[0021] 12:Substrate

[0022] 12A: Surface

[0023] 13: Dielectric layer

[0024] 13A: Top surface

[0025] 13B: Surface

[0026] 13C: Top surface

[0027] 14: Insulation layer

[0028] 14A: Top surface

[0029] 16: Oxide layer

[0030] 16A: Top surface

[0031] 17: Dielectric layer

[0032] 17A: Top surface

[0033] 17B: Surface

[0034] 17C: Top surface

[0035] 53: first dielectric layer

[0036] 54: second dielectric layer

[0037] 61: Space

[0038] 71: Flattening

[0039] 112: Groove

[0040] 113: Groove

[0041] 114: Upper segment

[0042] 116: Lower fragment

[0043] 120: dielectric layer

[0044] 121: Columnar silicon part

[0045] 121A: Top surface

[0046] 121B: Top surface

[0047] 121C: Top surface

[0048] 121S: Sidewall

[0049] 121': Island silicon portion

[0050] 122: Remaining dielectric film

[0051] 123: Top corner

[0052] 124: Dielectric liner

[0053] 125: Rounded corners

[0054] 126: Plane part

[0055] 130: Diffusion barrier layer

[0056] 132: Remaining diffusion barrier layer

[0057] 134: Diffusion barrier liner

[0058] 140: Conductive material

[0059] 142: Remaining conductive material

[0060] 144: Character Line

[0061] 151: dielectric layer

[0062] 152: dielectric layer

[0063] 153: Insulation material

[0064] 155:Insulation sheet

[0065] 160: Isolation material

[0066] 161: Oxide part

[0067] 170: Gap

[0068] 171: Dielectric part

[0069] 172: Groove

[0070] 320: Groove

[0071] 330: first impurity region

[0072] 340: Second impurity region

[0073] 344: Contact

[0074] 350:Isolation film

[0075] 360: Diffusion barrier film

[0076] 374: Character Line

[0077] 374T: Top surface

[0078] 441: Open

[0079] 443: Open

[0080] 521: Line

[0081] 525: Dashed line

[0082] 1121: Depth

[0083] 1131: Depth

[0084] 1442: Top surface

[0085] 1443: Height

[0086] 1211:Silicon part

[0087] 3201: Depth

[0088] 3202: protrusion

[0089] 3443:Height

[0090] 3743:Height

[0091] 3742: base

[0092] 3744: feet

[0093] A-A': line

[0094] H: Predetermined thickness

[0095] R1: array area

[0096] R2: surrounding area

[0097] S1: Methods

[0098] S11: Operation

[0099] S12: Operation

[0100] S13: Operation

[0101] S14: Operation

[0102] S15: Operation

[0103] S2: Methods

[0104] S21: Operation

[0105] S22: Operation

[0106] S23: Operation

[0107] S24: Operation

[0108] S25: Operation

[0109] W1: width

[0110] W2: width DETAILED DESCRIPTION

[0111] Specific language will now be used to describe the embodiments or examples of the present disclosure shown in the accompanying drawings. It will be understood that this is not intended to limit the scope of the present disclosure. Any changes or modifications to the described embodiments, and any further applications of the principles described in this document, should be considered as would normally occur to a person skilled in the art to which the present disclosure belongs. Element symbols may be repeated throughout the embodiments, but this does not necessarily mean that one (or more) features of one embodiment are applicable to another embodiment, even if they share the same element symbol.

[0112] It should be understood that although the terms first, second, third, etc. may be used herein to describe various components, members, regions, layers, or portions, these components, members, regions, layers, or portions should not be limited by these terms. Rather, these terms are merely used to distinguish one component, member, region, layer, or portion from another component, member, region, layer, or portion. Thus, a first component, member, region, layer, or portion discussed below could be referred to as a second component, member, region, layer, or portion without departing from the teachings of the present disclosure.

[0113] The terms used herein are used only to describe specific exemplary embodiments and are not intended to limit the present inventive concept. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It should be further understood that the terms "comprises" and "comprising," when used in this specification, indicate the presence of stated features, integers, steps, operations, components, or members, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, members, or groups thereof.

[0114] As the semiconductor industry has developed to advanced technology process nodes in pursuit of greater device density, it is important to achieve high control accuracy for the configuration of components formed in the device. For example, the configuration of the silicon pillars of the substrate in the array area of ​​the memory element is affected by the operations performed in the subsequent process. When undesirable oxidation occurs on the silicon pillars, the configuration of the silicon pillars will change. The rounding of the edges of the silicon pillars or the formation of uneven surfaces will result in a reduction in the contact area between the silicon pillars and the contact pads, and electrical disconnection or high resistance will occur between the silicon pillars and the contact pads. The present disclosure relates to a method for manufacturing a semiconductor structure. In particular, the method of the present disclosure can provide a flat surface of the silicon pillars to avoid the problems of electrical disconnection and high resistance. Therefore, the performance and product yield of the components formed according to the method can be improved.

[0115] Figures 1 to 19 Schematic diagrams illustrating various manufacturing stages of one or more methods for manufacturing a semiconductor structure according to some embodiments of the present disclosure from different angles. Figures 1 to 19 The stages shown are also schematically shown in Figure 22 Method S1 or Figure 23 Method S2.

[0116] See also Figure 1 , one or more dielectric layers are formed on the substrate 12. In some embodiments, before forming the dielectric layer(s), the substrate 12 is provided, received, or formed.

[0117] In some embodiments, substrate 12 may have a multilayer structure, or may include a multilayer compound semiconductor structure. In some embodiments, substrate 12 includes semiconductor devices, electronic components, electronic assemblies, or a combination thereof. In some embodiments, substrate 12 includes transistors or functional units of transistors. In some embodiments, substrate 12 includes active devices, passive devices, and / or conductive components. Active components may include memory chips (e.g., dynamic random-access memory (DRAM) chips, static random-access memory (SRAM) chips, etc.), power management chips (e.g., power management integrated circuit (PMIC) chips), logic chips (e.g., system-on-a-chip (SoC), central processing unit (CPU), graphics processing unit (GPU), application processor (AP), microcontroller, etc.), radio frequency (RF) chips, sensor chips, micro-electro-mechanical-system (MEMS) chips, signal processing chips (e.g., digital signal processing (DSP) chips), front-end chips (e.g., analog front-end (AFE) chips), or other active components. Each active component may include multiple transistors. Transistors may include planar transistors, multi-gate transistors, gate-all-around field-effect transistors (GAAFETs), fin field-effect transistors (FinFETs), vertical transistors, nanosheet transistors, nanowire transistors, or combinations thereof. Passive components may include capacitors, resistors, inductors, fuses, or other passive components. Conductive components may include metal lines, metal islands, conductive vias, contacts, or other conductive elements.

[0118] The active components, passive components, and / or conductive elements described above can be formed in and / or on a semiconductor substrate. The semiconductor substrate can be a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or other similar materials. The semiconductor substrate can include an elemental semiconductor, including single-crystalline, polycrystalline, or amorphous silicon or germanium; a compound semiconductor material, including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor material, including at least one of silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, indium gallium phosphide, and indium gallium arsenide phosphide; or combinations thereof; any other suitable materials; or combinations thereof. In some embodiments, the alloy semiconductor substrate can be a silicon-germanium alloy having a gradient silicon-germanium (Si:Ge) feature structure, wherein the Si and Ge compositions change from one ratio at one location in the gradient silicon-germanium feature structure to another ratio at another location. In another embodiment, the silicon-germanium alloy is formed on a silicon substrate. In some embodiments, the silicon-germanium alloy can be mechanically strained by another material in contact with the silicon-germanium alloy.

[0119] To keep it simple, Figure 1 The illustrated substrate 12 may be only the topmost portion of the multilayer structure of substrate 12. Substrate 12 may include an array region R1 and a peripheral region R2 surrounding array region R1. In some embodiments, active components or transistors are primarily formed in array region R1, while peripheral region R2 is used for circuit wiring and may include passive components. In some embodiments, substrate 12 comprises silicon material.

[0120] Memory cells or devices (not shown) may be formed in array region R1 of substrate 12. For illustrative purposes, the figures show a portion of substrate 12 located above the memory cells or memory devices. Bit line (BL) metal and word line (WL) metal (not shown) are formed during subsequent processing. Figure 1 On and in the topmost portion of the substrate 12 shown.

[0121] The dielectric layer 151 and the dielectric layer 152 may be formed on the substrate 12. In some embodiments, the dielectric layer 151 and the dielectric layer 152 include different dielectric materials. In some embodiments, the dielectric material includes silicon oxide (SiO x ), silicon nitride (Si x N y), silicon oxynitride (SiON), or a combination thereof. In some embodiments, the dielectric material includes a high-k dielectric material. The high-k dielectric material may have a dielectric constant (k value) greater than 4. High dielectric constant dielectric materials may include zirconium dioxide (ZrO2), hafnium dioxide (HfO2), aluminum oxide (Al2O3), yttrium trioxide (Y2O3), lanthanum trioxide (La2O3); silicates of one or more of zirconium dioxide, hafnium dioxide, aluminum oxide, yttrium trioxide, and lanthanum trioxide; aluminates of one or more of zirconium dioxide, hafnium dioxide, yttrium trioxide, and lanthanum trioxide; tantalum pentoxide (Ta2O5), barium titanate (BaTiO3), titanium dioxide (TiO2), cerium dioxide (CeO2), lanthanum aluminum oxide (LaAlO3), lead titanate (PbTiO3), strontium titanate (SrTiO3), lead zirconate (PbZrO3), tungsten trioxide (WO3), bismuth silicon oxide (Bi4Si2O 12 ), barium strontium titanate (BST, Ba 1-x Sr x TiO3), lead magnesium niobate (PMN) (PbMg x Nb 1-x O3), lead zinc titanate (PZT, PbZr x Ti 1-x O3), lead zinc niobate (PZN, PbZn x Nb 1-x O3), lead tantalate scandate (PST, PbSc x Ta 1-x O3), hafnium zirconium oxide (Hf x Zr y O z ), alumina zirconium hafnium (Hf w Zr x Al y O z ), lithium oxide (Li2O), hafnium silicate (HfSiO4), strontium oxide (SrO), scandium trioxide (Sc2O3), molybdenum trioxide (MoO3), barium oxide (BaO), or a combination thereof. Other suitable materials are also within the contemplated scope of the present disclosure.

[0122] In some embodiments, dielectric layer 151 and dielectric layer 152 include different oxide materials selected from the group listed above. In some embodiments, dielectric layer 151 and dielectric layer 152 are formed using different deposition processes. In some embodiments, dielectric layer 151 is thinner than dielectric layer 152. Dielectric layers 151 and 152 can protect substrate 12 from subsequent patterning operations. Two dielectric layers 151 and 152 are shown for illustrative purposes. In alternative embodiments, only one dielectric layer is formed on substrate 12. In other alternative embodiments, more than two dielectric layers are formed on substrate 12.

[0123] See also Figure 2 、 Figure 3 and Figure 4 , Figure 2 It is a 3D stereogram. Figure 3 yes Figure 2 An enlarged view of a portion of array region R1 shown by the dashed line, and Figure 4 It is along Figure 2 The cross-sectional view taken along the AA' line in FIG. 1 illustrates one stage of one or more methods for manufacturing a semiconductor structure according to some embodiments of the present disclosure. The dielectric layer 151, the dielectric layer 152, and the substrate 12 may be patterned. In some embodiments, a plurality of columnar silicon portions 121 are formed in the array region R1. In some embodiments, a plurality of island-shaped silicon portions 121' are formed in the peripheral region R2. In some embodiments, each of the dielectric layer 151 and the dielectric layer 152 is patterned into a plurality of portions. In some embodiments, each columnar silicon portion 121 has a portion of the dielectric layer 151 and a portion of the dielectric layer 152 disposed thereon. In some embodiments, each island-shaped silicon portion 121' has a portion of the dielectric layer 151 and a portion of the dielectric layer 152 disposed thereon.

[0124] It should be noted that one silicon portion 1211 of the plurality of silicon portions 121 has a configuration different from that of the other silicon portions 121, such as Figure 2 and Figure 4 As shown. Silicon portion 1211 may extend along the periphery of array region R1. Silicon portion 1211 may be a dummy structure in a memory element formed in a subsequent process. In some embodiments, silicon portion 1211 is not considered to be part of the array of memory cells of the memory element. In some embodiments, silicon portion 1211 is provided to define the area of ​​the array of memory cells of the memory element.

[0125] The patterning operations performed on dielectric layer 151, dielectric layer 152, and substrate 12 may include one or more etching operations. In some embodiments, dielectric layer 151, dielectric layer 152, and substrate 12 are patterned sequentially using different etching operations. In some embodiments, one or more etching operations are performed that have high selectivity to the dielectric material of dielectric layer 151 and / or dielectric layer 152 and low selectivity to the silicon material of substrate 12. Depending on the dielectric material of dielectric layer 151 and dielectric layer 152, dielectric layer 151 and dielectric layer 152 may be patterned using one or more etching operations. Conventional patterning methods may be used and are not particularly limited herein. In some embodiments, an etching operation with low selectivity to the silicon material of substrate 12 is then performed. In some embodiments, dielectric layer 151, dielectric layer 152, and substrate 12 are patterned simultaneously using a single etching operation. In some embodiments, a non-selective etching operation is performed and dielectric layer 151, dielectric layer 152, and substrate 12 are patterned simultaneously using a single etching operation.

[0126] Figures 5 to 19 It is along Figure 2 The cross-sectional view along the line AA' in FIG. 1 illustrates the method S1 or one of the stages of the method S1 according to some embodiments of the present disclosure. For illustrative purposes, Figures 5 to 19 The cross-sectional view shown focuses on array region R1. However, such description is not intended to limit the present disclosure. Similar or identical operations may be performed simultaneously in peripheral region R2. In some embodiments, all operations or processes described below are performed simultaneously in array region R1 and peripheral region R2. In some embodiments, all operations or processes described below are performed on the entire substrate 12.

[0127] See also Figure 5 After forming the columnar silicon portion 121 and the island silicon portion 121', the dielectric layer 151 and the dielectric layer 152 are removed. Similar to the above process, one or more etching operations may be performed depending on the materials of the dielectric layer 151 and the dielectric layer 152. The one or more etching operations used to remove the dielectric layer 151 and the dielectric layer 152 should have low selectivity to the silicon material of the substrate 12. In some embodiments, at this stage, the top surface 121A of each columnar silicon portion 121 is a substantially flat surface, such as Figure 5 A plurality of spaces 61 are defined between the columnar silicon portions 121 in the array region R1.

[0128] See also Figure 6Oxide layer 16 is formed on substrate 12 and conforms to substrate 12. In some embodiments, the structure of oxide layer 16 conforms to the structure of silicon portions 121 and silicon portions 121' of substrate 12. In some embodiments, oxide layer 16 is formed by oxidation. In some embodiments, oxide layer 16 is formed by deposition. In some embodiments, oxide layer 16 conforms to columnar silicon portions 121 and does not fill spaces 61 between columnar silicon portions 121.

[0129] The silicon portion 121 and the silicon portion 121' may be oxidized during the formation of the oxide layer 16 so that the top surfaces of the silicon portion 121 and the silicon portion 121' become convex or rounded. Figure 6 As shown, after the oxide layer 16 is formed, the top surface 121B of each silicon portion 121 becomes a convex surface or a rounded surface. In some embodiments, the top corner 123 (such as Figure 5 (as shown) is oxidized during the formation of oxide layer 16. In some embodiments, the entirety of top surface 121B is rounded. In some embodiments, top surface 121B includes rounded corners 125 and planar portions 126 connecting rounded corners 125. It should be noted that for illustrative purposes, Figure 6 Only the silicon portion 121 located in the array region R1 is shown in FIG. It should be understood that the silicon portion 121′ located in the peripheral region R2 may have the same Figure 6 1B. In some embodiments, each silicon portion 121 has a sidewall 121S connected to and below the raised top surface 121B. In some embodiments, the sidewall 121S is substantially flat, and line 521 represents the horizontal plane of the connection point between the raised top surface 121B and the flat sidewall 121S of the silicon portion 121. In some embodiments, line 521 is located at the bottom of the raised top surface 121B of the silicon portion 121.

[0130] In some embodiments, oxide layer 16 conforms to raised top surface 121B of silicon portion 121. In some embodiments, oxide layer 16 includes a substantially flat surface below line 521. In some embodiments, the thickness of oxide layer 16 is substantially uniform across substrate 12. In some embodiments, oxide layer 16 covers the entire substrate 12.

[0131] See also Figure 7Dielectric layer 17 is formed over substrate 12 and silicon portion 121 and conforms to substrate 12 and silicon portion 121. In some embodiments, the thickness of dielectric layer 17 is substantially greater than the thickness of oxide layer 16. Dielectric layer 17 may include one or more dielectric materials selected from the dielectric materials described with reference to dielectric layers 151 and 152, and a repeated description is omitted herein. In some embodiments, dielectric layer 17 includes a different dielectric material than oxide layer 16. In some embodiments, dielectric layer 17 does not include oxide. In some embodiments, dielectric layer 17 includes silicon nitride.

[0132] In some embodiments, dielectric layer 17 is formed by blanket deposition. In some embodiments, the formation of dielectric layer 17 includes chemical vapor deposition (CVD), physical vapor deposition (PVD), or a combination thereof. In some embodiments, dielectric layer 17 fills at least space 61 between silicon portions 121 in array region R1. In some embodiments, dielectric layer 17 is disposed over oxide layer 16 and between portions of oxide layer 16 located on sidewalls 121S of silicon portions 121. In some embodiments, to fill space 61, the thickness of dielectric layer 17 is substantially greater than half the distance between silicon portions 121. In some embodiments, top surface 17A of dielectric layer 17 is not a flat surface. In some embodiments, due to the characteristics of deposition, top surface 17A of dielectric layer 17 includes a plurality of grooves 172 corresponding to the positions of space 61.

[0133] See also Figure 8 , a dielectric layer 13 is formed on the dielectric layer 17. In some embodiments, the dielectric layer 13 physically contacts the top surface 17A of the dielectric layer 17. In some embodiments, the dielectric layer 13 fills the groove 172 of the dielectric layer 17. The purpose of the dielectric layer 13 and the dielectric layer 17 is to electrically isolate between components. In some embodiments, the dielectric layer 13 and the dielectric layer 17 can be regarded as a dielectric structure. In some embodiments, the dielectric layer 13 and the dielectric layer 17 can be regarded as two sublayers of the dielectric layer. In some embodiments, the top surface 13A of the dielectric layer 13 is substantially flat. In some embodiments, the dielectric layer 13 is configured to provide a flat surface for providing better removal results in etching operations or grinding operations performed during subsequent processes. In some embodiments, the dielectric layer 13 includes a dielectric material, an anti-reflective coating material, an oxide-containing material, or other suitable materials. The dielectric layer 13 may include one or more dielectric materials selected from the dielectric materials described with reference to the dielectric layer 151 and the dielectric layer 152, and repeated descriptions are omitted here. In some embodiments, dielectric layer 13 includes a dielectric material different from that of dielectric layer 17 for etch selectivity.

[0134] See also Figure 9, removing the dielectric layer 13 above the dielectric layer 17. In some embodiments, a grinding operation is performed on the dielectric layer 13 and stops at the dielectric layer 17. In some embodiments, the grinding operation includes a chemical mechanical polishing (CMP) operation. In some embodiments, the slurry of the grinding operation has high selectivity to the dielectric material of the dielectric layer 13 and low selectivity to the dielectric material of the dielectric layer 17. In other embodiments, an etching operation is performed instead of a grinding operation, and the etching operation stops when the dielectric layer 17 is exposed. In some embodiments, the etchant of the etching operation has high selectivity to the dielectric material of the dielectric layer 13 and low selectivity to the dielectric material of the dielectric layer 17. In some embodiments, the removal of the dielectric layer 13 located above the dielectric layer 17 includes a grinding operation, an etching operation, or a combination thereof. In some embodiments, after the grinding (or etching) operation, the surface 13B of the dielectric layer 13 is defined. In some embodiments, a portion of the top surface 17A of the dielectric layer 17 is exposed through the dielectric layer 13. In some embodiments, surface 13B of dielectric layer 13 is substantially coplanar with the exposed portion of top surface 17A of dielectric layer 17 .

[0135] See also Figure 10 , removing the dielectric layer 17 located above the oxide layer 16 and the silicon portion 121. In some embodiments, a grinding operation is performed on the dielectric layer 17 and stops at the oxide layer 16. In some embodiments, the grinding operation includes a CMP operation. In some embodiments, the slurry of the grinding operation has high selectivity to the dielectric material of the dielectric layer 17 and low selectivity to the oxide material of the oxide layer 16. In other embodiments, an etching operation is performed instead of a grinding operation, and the etching operation stops when the oxide layer 16 is exposed. In some embodiments, the etchant of the etching operation has high selectivity to the dielectric material of the dielectric layer 17 and low selectivity to the oxide material of the oxide layer 16. In some embodiments, the removal of the dielectric layer 17 located above the oxide layer 16 includes a grinding operation, an etching operation, or a combination thereof.

[0136] In some embodiments, dielectric layer 13 includes an oxide material similar to or the same as oxide layer 16. In some embodiments, the slurry used in the polishing operation or the etchant used in the etching operation has low selectivity for the material of dielectric layer 13. Therefore, during and after removing oxide layer 16 and dielectric layer 17 over silicon portion 121, surface 13B of dielectric layer 13 in peripheral region R2 may remain.

[0137] In some embodiments, after the grinding (or etching) operation, a surface 17B of the dielectric layer 17 is defined. In some embodiments, a plurality of dielectric portions 171 of the dielectric layer 17 are defined between the silicon portions 121. In some embodiments, the top surfaces of the plurality of dielectric portions 171 together define the surface 17B of the dielectric layer 17. Figure 10 The plurality of dielectric portions 171 shown may appear to be connected to one another in a 3D perspective view or a top view (not shown). Portions of the oxide layer 16 located above the silicon portion 121 may be exposed through the dielectric layer 17. In some embodiments, the exposed portions of the oxide layer 16 protrude from the surface 17B of the dielectric layer 17, as shown in FIG. Figure 10 In other words, surface 17B is below the top of the exposed portion of oxide layer 16. In some embodiments, surface 17B of dielectric layer 17 is substantially coplanar with the exposed portion (not shown) of oxide layer 16. In some embodiments, surface 17B of dielectric layer 17 is above line 521.

[0138] See also Figure 11 , dielectric layer 13, oxide layer 16, dielectric layer 17 and silicon portion 121 are planarized 71. Planarization 71 is used to remove dielectric layer 13 and dielectric layer 17, oxide layer 16 and silicon portion 121 located above line 521. In some embodiments, planarization 71 includes an etching operation, such as ion beam etching, directional dry etching, reactive ion etching, solution wet etching or a combination thereof. In some embodiments, planarization 71 includes low selective etching. In some embodiments, low selective etching includes low etching selectivity between dielectric layer 13 and dielectric layer 17, oxide layer 16 and the material of substrate 12. In some embodiments, planarization includes a grinding operation (e.g., a CMP operation). In some embodiments, planarization includes a grinding operation and an etching operation. In some embodiments, the grinding operation and / or the etching operation include a solvent with high selectivity to silicon. In some embodiments, planarization 71 is a time mode operation. The duration of temporal planarization 71 is controlled such that temporal planarization 71 proceeds until dielectric layers 13 and 17, oxide layer 16, and silicon portion 121 above line 521 are removed. In some embodiments, planarization 71 stops at line 521. In some embodiments, planarization 71 stops below line 521 to ensure complete removal of raised top surface 121B.

[0139] See also Figure 12 , Figure 12 The result of planarization 71 is shown. In some embodiments, the height of dielectric portion 171 of dielectric layer 17 is reduced. In some embodiments, top surface 17C of dielectric portion 171 is at or below the height of line 521. Depending on the pattern of silicon portion 121, Figure 12 The plurality of dielectric portions 171 shown may appear to be connected to each other in a 3D perspective view or a top view (not shown). In some embodiments, the portion of the oxide layer 16 located above the line 521 is removed by planarization 71 to form a plurality of oxide portions 161 surrounding each silicon portion 121. Depending on the pattern of the silicon portion 121, Figure 12 The plurality of oxide portions 161 shown may appear to be connected to each other in a 3D perspective view or a top view (not shown). Figure 11 After planarization 71, a top surface 16A of the oxide layer 16 is defined. In some embodiments, the top surface 16A is defined by the top surfaces of the plurality of oxide portions 161. In some embodiments, Figure 11 After the planarization 71, the top surface 121C of the silicon portion 121 of the substrate 12 is defined. In some embodiments, Figure 11 After planarization 71, a top surface 13C of dielectric layer 13 is defined in peripheral region R2. In some embodiments, top surface 13C of dielectric layer 13, top surface 121C of silicon portion 121, top surface 16A of oxide portion 161, and top surface 17C of dielectric portion 171 are coplanar with one another. In some embodiments, top surface 13C of dielectric layer 13, top surface 121C of silicon portion 121, top surface 16A of oxide portion 161, and top surface 17C of dielectric portion 171 are substantially coplanar. Top surface 13C of dielectric layer 13, top surface 121C of silicon portion 121, top surface 16A of oxide portion 161, and top surface 17C of dielectric portion 171 collectively define surface 12A. In some embodiments, surface 12A is a planar surface.

[0140] Figures 13 to 19 It is along Figure 2 The cross-sectional view taken along the line AA′ in FIG. 1 illustrates an intermediate stage in the formation process of the semiconductor structure 10A according to some embodiments of the present disclosure.

[0141] See also Figure 13 , an insulating layer 14 may be formed on surface 12A above dielectric layer portion 171, oxide portion 161, silicon portion 121, and dielectric layer 13. Furthermore, at least one opening 441 may be formed to penetrate insulating layer 14, and at least one trench 112 may be formed in silicon portion 121. Insulating layer 14 comprises one or more dielectric materials. In some embodiments, insulating layer 14 is referred to as dielectric layer 14. In some embodiments, before forming opening 441 and trench 112, insulating layer 14 contacts dielectric portion 171, oxide portion 161, silicon portion 121, and dielectric layer 13. In some embodiments, insulating layer 14 is formed in array region R1 and peripheral region R2. Because surface 12A is a substantially flat surface, top surface 14A of insulating layer 14 formed on surface 12A is a substantially flat surface. In some embodiments, insulating layer 14 comprises a nitride, such as silicon nitride. In some embodiments, insulating layer 14 is formed using a CVD process, a PVD process, or any other suitable process. In some embodiments, the thickness of the insulating layer 14 is in the range of 5 to 30 nm.

[0142] In some embodiments, the opening 441 and the groove 112 are formed by a first patterning operation. The substrate 12 and the silicon portion 121 located in the array region R1 are partially removed by the first patterning operation. The first patterning operation may include a single step or multiple steps, and depending on the materials of the insulating layer 14 and the silicon portion 121, the insulating layer 14 and the silicon portion 121 may be patterned simultaneously by one etching step, or the insulating layer 14 and the silicon portion 121 may be patterned sequentially by different etching steps. In some embodiments, the opening 441 penetrates the insulating layer 14 and is surrounded by the insulating layer 14. In some embodiments, the opening 441 is defined by the insulating layer 14. In some embodiments, the groove 112 is defined by the silicon portion 121 of the substrate 12. In some embodiments, the groove 112 is formed in the silicon portion 121. In some embodiments, the bottom of the groove 112 may be rounded as needed to reduce the defect density and reduce the electric field concentration of the element during operation. In some embodiments, if the groove 112 is a U-shaped groove, the corner effect can be avoided. Figure 13 As shown, trench 112 may include an upper segment 114 having a uniform width near insulating layer 14, and a lower segment 116 having a gradually narrowing width away from insulating layer 14. In other words, the sidewalls of substrate 12 in upper segment 114 of trench 112 are substantially vertical, while the sidewalls of substrate 12 in lower segment 116 of trench 112 are inclined surfaces that transition to vertical. In some embodiments, upper segment 114 of trench 112 is wider than lower segment 116. In some embodiments, depths 1121 of trench 112, as measured from surface 12A, may be substantially equal.

[0143] See also Figure 14 , forming a dielectric film 120 lining the trench 112. In some embodiments, the dielectric film 120 contacts the silicon portion 121. The dielectric film 120 has a substantially uniform thickness and covers the exposed portion of the substrate 12, but does not fill the trench 112. In some embodiments, the dielectric film 120 and the insulating layer 14 may include the same material, but the present disclosure is not limited thereto. In some embodiments, a thermal oxidation process may be used to grow the dielectric film 120 on the exposed portion of the substrate 12. In some embodiments, the dielectric film 120 lines the sidewalls of the opening 441. In some embodiments, the dielectric film 120 includes an oxide, a nitride, an oxynitride, or a high dielectric constant material, and may be deposited using a CVD process, an ALD process, or a similar process. In some embodiments, an etching process may be performed to remove the portion of the dielectric film 120 deposited on the top surface 14A of the insulating layer 14, while retaining the portion of the dielectric film 120 deposited on the sidewalls of the opening 441 and the trench 112.

[0144] See also Figure 14 A diffusion barrier layer 130 may be deposited on the dielectric film 120 and the top surface 14A of the insulating layer 14, as needed. In some embodiments, the diffusion barrier layer 130 may have a substantially uniform thickness and may cover the dielectric layer 120. In some embodiments, the diffusion barrier layer 130 may be formed by a PVD process or an ALD process. In some embodiments, the diffusion barrier layer 130 may be a single-layer structure comprising a refractory metal (e.g., tantalum or titanium), a refractory metal nitride, or a refractory metal silicon nitride. In other embodiments, the diffusion barrier layer 130 may include a multi-layer structure, and the multi-layer structure may include one or more refractory metals, refractory metal nitrides, or refractory metal silicon nitrides.

[0145] See also Figure 14 , a conductive material 140 is deposited to partially fill the trench 112. The conductive material 140 is conformally deposited over the dielectric layer 120. Due to the directionality of the conductive material 140 deposition toward the bottom of the trench 112, the deposition rate of the conductive material 140 in the lower segment 116 of the trench 112 is greater than the deposition rate of the conductive material 140 in the upper segment 114 of the trench 112. As a result, the thickness of the conductive material 140 in the lower segment 116 of the trench 112 is significantly greater than the thickness of the conductive material 140 in the upper segment 114 of the trench 112. In some embodiments, the deposition of the conductive material 140 is stopped when the conductive material 140 deposited in the trench 112 reaches a predetermined thickness H. This can avoid detrimental short-channel effects and improve device reliability. The conductive material 140 includes polysilicon or a metal, such as tungsten, aluminum, copper, molybdenum, titanium, tantalum, ruthenium, or a combination thereof. The conductive material 140 may be formed using a CVD process, a PVD process, an ALD process, or other suitable processes.

[0146] See also Figure 14 An insulating material 153 is deposited over the conductive material 140 and fills the trench 112. The insulating material 153 has a thickness sufficient to fill the trench 112. The insulating material 153 is formed by a (plasma) CVD process and comprises a nitride. In some embodiments, the insulating material 153 may comprise silicon nitride. In some embodiments, the insulating material 153 preferably comprises a material having a high etch selectivity to the dielectric layer 120, the diffusion barrier layer 130, and the conductive material 140.

[0147] See also Figure 15A planarization process, such as a chemical mechanical polishing process and / or an etching process, may be sequentially performed to remove portions of the insulating material 153, the dielectric layer 120, the diffusion barrier layer 130, and the conductive material 140 located above the surface 12A. As a result, the remaining portions of the dielectric layer 120, the diffusion barrier layer 130, the conductive material 140, and the insulating material 153 that remain in place may be transformed into a remaining dielectric film 122, a remaining diffusion barrier layer 132, a remaining conductive material 142, and a plurality of insulating sheets 155, respectively.

[0148] See also Figure 16 , the remaining conductive material 142 is recessed to the position indicated by the dotted line 525, wherein the dotted line 525 indicates the designed top surface of the WL metal. Thus, a plurality of word lines 144 are formed. During the formation of the word lines 144, a single-step or multi-step etching process, such as an anisotropic etching process, is performed to remove a portion of the remaining conductive material 142 in the trench until the remaining conductive material 142 is flush with the dotted line 525 indicating the designed top surface of the WL metal. In this way, after the formation of the word lines 144, a portion of the remaining diffusion barrier layer 132 and a portion of the remaining dielectric film 122 are removed to form a dielectric liner 124 and a diffusion barrier liner 134 between the silicon portion 121 and the word lines. As shown in FIG. Figure 16 As shown, the word line 144 has a top surface 1442 , and the top surface 1442 is flush with the dashed line 525 .

[0149] See also Figure 16 , an isolation material 160 is deposited to at least partially fill the trench 112 and form one or more voids 170 around the insulating sheet 155. The isolation material 160 is conformally and uniformly deposited in the trench 112. Since the insulating sheet 155 narrows the width of the trench 112, voids 170 containing ambient gas (e.g., air) may be formed in the isolation material 160 to reduce the effective dielectric constant of the isolation material 160. Figure 16 As shown, a gap 170 is formed to surround the insulating sheet 155. The isolation material 160 can be deposited by a CVD process or an ALD process. In some embodiments, the deposition rate of the isolation material 160 can be adjusted to introduce the gap 170 into the isolation material 160. More specifically, when the isolation material 160 is deposited at a fast rate, the isolation material 160 may not completely fill the trench 112. In some embodiments, the isolation material 160 may include silicon oxide, silicon nitride, silicon oxynitride, hafnium dioxide, or zirconium dioxide.

[0150] See also Figure 17, a plurality of openings 443 can be formed to penetrate the insulating layer 14, a plurality of trenches 113 can be formed in the dielectric portion 171, and a plurality of contacts 344 can be formed in the plurality of trenches 113. A second patterning operation can be performed to form the openings 443 and the trenches 113. The second patterning operation is performed to partially remove the substrate 12 and the dielectric portion 171 in the array region R1. The second patterning operation can include a single step or multiple steps, and depending on the materials of the insulating layer 14, the dielectric layer 17, and the dielectric portion 171, the insulating layer 14, the dielectric layer 17, and the dielectric portion 171 can be patterned simultaneously through one etching step, or the insulating layer 14, the dielectric layer 17, and the dielectric portion 171 can be patterned sequentially through different etching steps. In some embodiments, each opening 443 penetrates the insulating layer 14 and is surrounded by the insulating layer 14. In some embodiments, the opening 443 is defined by the insulating layer 14. In some embodiments, the trench 113 is defined by the dielectric portion 171 of the substrate 12. In some embodiments, each trench 113 is formed in a dielectric portion 171 .

[0151] The depths of the grooves 113 may be substantially equal. In some embodiments, the depth 1131 of the grooves 113 measured from the surface 12A is different from the depth 1121 of the grooves 112 measured from the surface 12A (see FIG. Figure 13 In some embodiments, the depth 1121 of trench 112 is substantially less than the depth 1131 of trench 113. In some embodiments, the difference between depth 1121 and depth 1131 is due to different etch rates of different materials during an etching step in a patterning operation. In some embodiments, trench 112 and trench 113 are formed by different etching steps, and depth 1121 and depth 1131 are controlled to be different to facilitate the formation of WL metal in subsequent processes.

[0152] See also Figure 17Contacts 344 can be formed by depositing a conductive material (not shown) over substrate 12 and patterned insulating layer 14. The conductive material can fill opening 443 and trench 113. In some embodiments, the conductive material fills the entire trench 113. In some embodiments, the conductive material is formed by deposition. In some embodiments, the conductive material includes aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), titanium silicon nitride (TiSiN), other suitable materials, or combinations thereof. In some embodiments, the conductive material is tungsten, titanium nitride, or a combination thereof. In some embodiments, the upper portion of the conductive material is removed. In some embodiments, multiple contacts 344 are formed in trench 113. In some embodiments, contacts 344 are referred to as WL metal.

[0153] See also Figure 17 For electrical connection purposes, the designed top surface 525 should be lower than surface 12A (or the top surface of substrate 12). In other words, the distance from surface 12A to the designed top surface 525 should be greater than zero. However, the range of this distance can be adjusted depending on different applications and is not limited herein. Furthermore, it should be noted that the figures are for illustrative purposes, and the tops of different contacts 344 and / or word lines 144 can be at approximately the same height, but not necessarily at the same level. In some embodiments, because the depths 1121 and 1131 of trenches 112 and 113 are different, the height 1443 of word lines 144 from the designed top surface 525 and the height 3443 of contacts 344 from the designed top surface 525 are different. In some embodiments, the height 1443 of word lines 144 from the designed top surface 525 is substantially less than the height 3443 of contacts 344 from the designed top surface 525.

[0154] See also Figure 18 and Figure 19A first dielectric layer 53 and a second dielectric layer 54 are sequentially formed on the substrate 12. The first dielectric layer 53 and the second dielectric layer 54 may cover the contacts 344, the word lines 144, and the patterned insulating layer 14. In some embodiments, the first dielectric layer 53 and the second dielectric layer 54 include different dielectric materials. In some embodiments, the first dielectric layer 53 includes a nitride (e.g., silicon nitride), and the second dielectric layer 54 includes an oxide (e.g., silicon oxide). In some embodiments, the first dielectric layer 53 fills the trench 112 above the word line 144. In some embodiments, the first dielectric layer 53 fills the trench 113 above the contact 344. In some embodiments, the first dielectric layer 53 fills the opening 441 and the opening 443. In some embodiments, the first dielectric layer 53 covers the entire patterned insulating layer 14. In some embodiments, the second dielectric layer 54 covers the entire first dielectric layer 53. This forms the semiconductor structure 10A.

[0155] Figures 20 to 21 It is along Figure 2 The cross-sectional view taken along the line AA′ in FIG. 1 illustrates an intermediate stage in the formation process of the semiconductor structure 10A according to some embodiments of the present disclosure.

[0156] See also Figure 20 , providing an intermediate structure. Figure 20 The intermediate structure in Figure 12 The structure is similar to Figure 20 The intermediate structure in has a relatively sparse dielectric portion 171. In other words, Figure 20 The distance between the dielectric portion 171 and the adjacent dielectric portion is greater than Figure 12 The distance between the dielectric portion 171 and the adjacent dielectric portion.

[0157] See also Figure 21 The formation of the semiconductor structure 10B includes: forming at least one trench 320; forming a plurality of first impurity regions 330 and a plurality of second impurity regions 340 in the substrate 12; forming an isolation film 350 lining the trench 320; forming a diffusion barrier film 360 on the isolation film 350; forming a word line 374 on the diffusion barrier film 360 and filling the trench 320; forming a plurality of trenches 113; and forming a plurality of contacts 344 in the isolation film 350.

[0158] In some embodiments, trench 320 has a W-shaped profile. In some embodiments, trench 320 is formed by a patterning process and at least one reactive ion ion etching (RIE) process. In some embodiments, trench 320 has a depth 3201 as measured from surface 12A. In some embodiments, protrusion 3202 is formed in W-shaped trench 320. In some embodiments, protrusion 3202 is disposed at the center of trench 320.

[0159] In some embodiments, the substrate 12 and the first impurity region 330 have the same conductivity type. In some embodiments, the second impurity region 340 and the first impurity region 330 have a different conductivity type. In some embodiments, the second impurity region 340 is disposed between a pair of legs 3744 of the word line 374 .

[0160] In some embodiments, the isolation film 350, which has a substantially uniform thickness, covers the inner surface of the trench 320 but does not completely fill the trench 320. In other words, the isolation film 350 has a morphology that conforms to the trench 320. In some embodiments, the isolation film 350 is grown on the inner surface of the trench 320 using a thermal oxidation process. In other embodiments, the isolation film 350 can be formed using a CVD process or an atomic layer deposition (ALD) process.

[0161] In some embodiments, a diffusion barrier film 360 having a substantially uniform thickness covers the isolation film 350 but does not completely fill the trench 320. To ensure step coverage, the diffusion barrier film 360 can be formed using a PVD process or an ALD process. For example, the diffusion barrier film 360 deposited using an ALD process has a high degree of thickness uniformity. In some embodiments, the diffusion barrier film 360 is uniformly and conformally deposited on the isolation film 350. In some embodiments, the diffusion barrier film 360 can be a single-layer structure comprising a refractory metal (e.g., tantalum and titanium), a refractory metal nitride, or a refractory metal silicon nitride. In other embodiments, the diffusion barrier film 360 can include a multilayer structure, and the multilayer structure includes one or more refractory metals, refractory metal nitrides, or refractory metal silicon nitrides.

[0162] In some embodiments, a word line 374 may be formed in the trench 320. The word line 374 may have a W-shaped profile. The word line 374 has a top surface 374T that is coplanar with the designed top surface 525. The word line 374 has a height 3743. The material of the word line 374 includes polysilicon or a metal, such as tungsten, copper, aluminum, molybdenum, titanium, tantalum, ruthenium, or a combination thereof. The word line 374 may be formed using a CVD process, a PVD process, an ALD process, or other suitable process. The W-shaped word line 374 includes a leg 3744 and a base 3742. The leg 3744 has a width W1 that gradually decreases as the distance from the surface 12A of the substrate 12 increases. Because the width W1 of the legs 3744 of the word line 374 gradually decreases at positions where the distance from the surface 12A of the substrate 12 increases, the second impurity region 340 located between the legs 3744 of the word line 374 has a width W2 that gradually increases at positions where the distance from the base 3742 of the word line 374 increases.

[0163] The depths of trenches 113 can be substantially equal. In some embodiments, depth 1131 of trench 113, as measured from surface 12A, is different from depth 3201 of trench 320, as measured from surface 12A. In some embodiments, depth 3201 of trench 320 is substantially less than depth 1131 of trench 113. In some embodiments, the difference between depth 3201 and depth 1131 is due to different etch rates of the different materials during an etch step of a patterning operation. In some embodiments, trench 320 and trench 113 are formed by different etch steps, and depth 3201 is controlled to be different from depth 1131 to facilitate formation of WL metal during subsequent processing.

[0164] In some embodiments, contacts 344 can be formed by depositing a conductive material (not shown) over substrate 12 and patterned insulating layer 14. The conductive material can fill opening 443 and trench 113. In some embodiments, the conductive material fills the entire trench 113. In some embodiments, the conductive material is formed by deposition. In some embodiments, the conductive material includes aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), titanium silicon nitride (TiSiN), other suitable materials, or combinations thereof. In some embodiments, the conductive material is tungsten, titanium nitride, or a combination thereof. In some embodiments, the upper portion of the conductive material is removed. In some embodiments, multiple contacts 344 are formed in trench 113. In some embodiments, contacts 344 are referred to as WL metal. In some embodiments, contact 344 has a height 3443 that is greater than a height 3743 of word line 374 .

[0165] The bit line (BL) metal can be formed on Figure 19 The semiconductor structure 10A or Figure 21 10B. In some embodiments, after forming the bitline metal, contact pads are formed to electrically connect to the silicon portions 121 in array region R1. The present disclosure provides silicon portions 121 each having a flat top surface, thereby preventing electrical disconnection or high resistance between the silicon pillars and the contact pads caused by rounding of the silicon pillars. This improves the performance and product yield of devices formed using this method.

[0166] To summarize the above Figures 1 to 21 The operations shown provide method S1 and method S2 within the same concept of the present disclosure.

[0167] Figure 22 is a flow chart illustrating a method S1 for manufacturing a semiconductor structure according to some embodiments of the present disclosure. Method S1 includes multiple operations (S11, S12, S13, S14, and S15), and the description and drawings are not to be construed as limiting the order of the operations. In operation S11, a substrate is provided, wherein the substrate includes a plurality of pillars, and the top surface of each of the plurality of pillars is a substantially flat surface. In operation S12, a first oxide layer is formed on the substrate conforming to the plurality of pillars, wherein the formation of the first oxide layer includes oxidizing the top corners of the plurality of pillars, resulting in the top surface of each of the plurality of pillars becoming a raised surface. In operation S13, a first dielectric layer is formed between the plurality of pillars, wherein the first oxide layer located above the plurality of pillars is partially exposed through the first dielectric layer. In operation S14, the plurality of pillars are planarized to partially or completely remove the raised surfaces. In operation S15, a second dielectric layer is formed over the plurality of pillars, the first oxide layer, and the first dielectric layer, wherein the top surface of the second dielectric layer is a substantially flat surface. It should be noted that the operations of method S1 can be rearranged or otherwise modified within the scope of various aspects. Additional processes can be provided before, during, and after method S1, and only some other processes are briefly described here. Therefore, within the scope of various aspects described herein, other embodiments are possible.

[0168] Figure 23 is a flow chart illustrating a method S2 for manufacturing a semiconductor structure according to some embodiments of the present disclosure. Method S2 includes multiple operations (S21, S22, S23, S24, and S25), and the description and drawings are not to be construed as limiting the order of the operations. In operation S21, a substrate is provided, wherein the substrate includes a plurality of pillars, and the top surface of each of the plurality of pillars is a substantially flat surface. In operation S22, a first oxide layer is formed over the substrate conforming to the plurality of pillars, wherein each of the plurality of pillars is partially oxidized during the formation of the first oxide layer to form a rounded top surface for each of the plurality of pillars. In operation S23, a first dielectric layer is formed over the substrate and between the plurality of pillars. In operation S24, each of the plurality of pillars is partially removed until the rounded top surface becomes a flat top surface of the corresponding pillar. In operation S25, a second dielectric layer is formed over the plurality of pillars, wherein the top surface of the second dielectric layer is a substantially flat surface. It should be noted that the operations of method S2 may be rearranged or otherwise modified within the scope of various aspects. Additional processes may be provided before, during, and after method S2, and only some other processes are briefly described here. Therefore, other embodiments are possible within the scope of the various aspects described herein.

[0169] Method S1 and method S2 belong to the same concept of the present disclosure. In order to further illustrate the details of method S1 and method S2 and the concept of the present disclosure, method S1 and method S2 are fully described in conjunction with the embodiments of the present disclosure.

[0170] Therefore, the present disclosure provides a manufacturing method and semiconductor structure thereof. The manufacturing method disclosed herein can provide a flat surface of a silicon pillar while avoiding electrical disconnection and high resistance issues. This can improve the performance and product yield of the device formed using this method.

[0171] One aspect of the present disclosure provides a method for fabricating a semiconductor structure. The method includes: forming at least one first trench in a substrate; depositing a conductive material to partially fill the first trench; forming an insulating sheet in the first trench and extending into the conductive material; and depositing an isolation material in the first trench to cover the portion of the conductive material exposed around the insulating sheet. Depositing the isolation material also includes enclosing at least one void in the isolation material.

[0172] Another aspect of the present disclosure provides a method for manufacturing a semiconductor structure. The method includes: forming a silicon portion, multiple dielectric portions, and multiple oxide portions in a substrate; forming at least one first trench in the silicon portion of the substrate; forming a word line in the first trench; forming multiple first impurity regions and multiple second impurity regions in the substrate; forming a first dielectric layer over the substrate to cover the word line; and forming a second dielectric layer to cover the first dielectric layer. The first trench has a W-shaped profile. Each of the multiple second impurity regions is disposed between a pair of legs of the word line.

[0173] Another aspect of the present disclosure provides a semiconductor structure. This semiconductor structure includes: a substrate having a silicon portion, multiple dielectric portions, and multiple oxide portions; at least one first trench disposed in the silicon portion of the substrate; a word line disposed in the first trench; and multiple first impurity regions and multiple second impurity regions disposed in the substrate. The first trench has a W-shaped profile. Each of the multiple second impurity regions is disposed between a pair of legs of the word line.

[0174] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements can be made without departing from the spirit and scope of the present disclosure as defined in the claims. For example, many of the above processes can be implemented in different ways, and many of the above processes can be replaced by other processes or combinations thereof.

[0175] Furthermore, the scope of the present invention is not limited to the specific embodiments of the processes, machines, manufacture, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art will appreciate from the disclosure herein that existing or future developed processes, machines, manufacture, compositions of matter, means, methods, or steps that function the same as or achieve substantially the same results as the corresponding embodiments described herein may be used in accordance with the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps are intended to be encompassed by the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor element, comprising: forming at least one first trench in a substrate; depositing a conductive material to partially fill the first trench; forming an insulating sheet in the first trench, wherein the insulating sheet extends into the conductive material; and An isolation material is deposited in the first trench to cover the portion of the conductive material exposed around the insulating sheet, wherein depositing the isolation material further comprises closing at least one void in the isolation material.

2. The method for manufacturing a semiconductor device according to claim 1, further comprising: forming an insulating layer on the substrate; as well as At least one first opening is formed in the insulating layer, wherein the first trench is formed to penetrate the at least one first opening. 3 . The method for manufacturing a semiconductor device according to claim 2 , wherein the first depths of the first trenches are equal. 4 . The method for manufacturing a semiconductor device as claimed in claim 3 , wherein the first trench is disposed in a silicon portion of the substrate.

5. The method for manufacturing a semiconductor device as claimed in claim 4 , wherein before depositing the conductive material, the method further comprises: forming a dielectric film lining the first trench and the at least one first opening; as well as A diffusion barrier layer is formed to line the dielectric film and be located on the insulating layer, wherein the diffusion barrier layer is disposed between the dielectric film and the conductive material.

6. The method for manufacturing a semiconductor device according to claim 5, wherein forming the insulating sheet comprises: depositing an insulating material to cover the insulating layer, the opening and the first trench; as well as A removal process is performed to remove a portion of the insulating material located above the substrate surface.

7. The method for manufacturing a semiconductor device according to claim 6, further comprising: A word line is formed by recessing the remaining portion of the conductive material to a designed top surface.

8. The method for manufacturing a semiconductor device according to claim 7, further comprising: forming a plurality of second openings in the insulating layer; forming a plurality of second trenches in the substrate through the plurality of second openings; as well as A plurality of contacts are formed in the plurality of the second trenches. 9 . The method for manufacturing a semiconductor device according to claim 8 , wherein second depths of the second trenches are greater than first depths of the first trenches. 10 . The method for manufacturing a semiconductor device as claimed in claim 9 , wherein a height of the plurality of contacts is greater than a height of the word line.

11. The method for manufacturing a semiconductor device according to claim 10, further comprising: forming a first dielectric layer to cover the insulating layer, the at least one first opening, and the plurality of second openings; as well as A second dielectric layer is formed to cover the first dielectric layer.

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