Semiconductor device

Abstract

The invention relates to a semiconductor device. A semiconductor device includes: a bit line disposed to extend in a first direction; a first gate disposed to extend in a second direction intersecting the first direction; a second gate disposed to extend in parallel with the first gate; an active region having a first side in contact with the bit line; and a contact disposed in contact with the second side of the active region. The active region includes: a horizontal portion provided to extend in a first direction; a vertical portion disposed between the first gate and the second gate; and a first contact region provided in contact with the contact and the vertical portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2024-0050097, filed on April 15, 2024, the disclosure of which is incorporated herein by reference in its entirety as a part of the disclosure of this patent document. Technical Field

[0003] Embodiments of the present disclosure generally relate to a semiconductor device, and more particularly, to a semiconductor device including a memory cell. Background Art

[0004] As miniaturization and high integration of semiconductor devices become major issues, memory cells included in semiconductor devices may be formed to have a three-dimensional (3D) pattern. Miniaturized memory cells having a three-dimensional (3D) pattern may be equipped with a configuration that improves the operating characteristics of the memory cells. Summary of the Invention

[0005] Various embodiments of the present disclosure relate to semiconductor memory devices with higher integration.

[0006] Various embodiments of the present disclosure are directed to a semiconductor memory device in which contact resistance between an active region and an adjacent region is reduced.

[0007] According to an embodiment of the present disclosure, a semiconductor device may include: a bit line arranged to extend along a first direction; a first gate arranged to extend along a second direction intersecting the first direction; a second gate arranged to extend parallel to the first gate; an active region having a first side in contact with the bit line; and a contact arranged to contact the second side of the active region. The active region may include: a horizontal portion arranged to extend along the first direction; a vertical portion arranged between the first gate and the second gate; and a first contact region arranged to contact the contact and the vertical portion.

[0008] In some embodiments, a bit line may be disposed to contact the horizontal portion.

[0009] In some embodiments, the active region may further include a second contact region disposed between the bit line and the horizontal portion to contact the bit line and the horizontal portion.

[0010] In some embodiments, the active region may include indium gallium zinc oxide (IGZO).

[0011] In some embodiments, the width of the first contact region is equal to or greater than the width of the vertical portion.

[0012] In some embodiments, the width of the first contact region is equal to or smaller than the width of the contact member.

[0013] In some embodiments, the active region may further include a first extension region disposed to contact a bottom surface of the first contact region and a side surface of the vertical portion.

[0014] In some embodiments, the first contact region may be configured to contact a bottom surface and a side surface of the contact member.

[0015] In some embodiments, the first contact region may be disposed along sidewalls and a bottom surface of a contact trench disposed in the contact insulation layer.

[0016] In some embodiments, the contact trench may be disposed to overlap the vertical portion.

[0017] In some embodiments, the contact can be connected to the capacitor.

[0018] In some embodiments, the vertical portion may extend along a side surface of the first gate and may form a first angle with respect to the horizontal portion.

[0019] In some embodiments, the active region may further include a second extension region disposed on the horizontal portion.

[0020] In some embodiments, the first gate and the second gate may receive different control signals.

[0021] According to another embodiment of the present disclosure, a semiconductor device may include: a bit line arranged to extend along a first direction; a first gate arranged to extend along a second direction intersecting the first direction; a pair of second gates arranged on either side of the first gate to extend parallel to the first gate; an active region having a first side in contact with the bit line; and a contact arranged to contact the second side of the active region. The active region may include: a horizontal portion arranged to extend along the first direction and in contact with the bit line; a vertical portion arranged between the first and second gates to extend from the horizontal portion toward the contact; and a first contact region arranged between the contact and the vertical portion, wherein the horizontal portion is located below the second gate.

[0022] In some other embodiments, the active region may further include: a second contact region disposed between the bit line and the horizontal portion to contact the bit line and the horizontal portion.

[0023] In some other embodiments, the active region may include indium gallium zinc oxide (IGZO).

[0024] In some other embodiments, the active region may further include a first extension region disposed to contact a bottom surface of the first contact region and a side surface of the vertical portion.

[0025] In some other embodiments, the first extension region may be configured to contact a bottom surface and a side surface of the contact member.

[0026] In some other embodiments, the active region may further include a second extension region disposed above the horizontal portion.

[0027] According to another embodiment of the present disclosure, a semiconductor device may include: a bit line, which is configured to extend along a first direction; a first gate, which is configured to extend along a second direction intersecting the first direction, wherein a cross-section of the first gate has a trapezoidal shape; a pair of second gates, which are arranged on both sides of the first gate to extend parallel to the first gate; and an active area, which includes a horizontal portion and a vertical portion, the horizontal portion contacts the bit line, and the vertical portion is arranged between the first gate and the pair of second gates to extend along the vertical direction.

[0028] It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The foregoing and other features and advantageous aspects of the present disclosure will become apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0030] Figure 1 is a schematic perspective view illustrating an example of a semiconductor device according to an embodiment of the present disclosure.

[0031] Figure 2A is a cross-sectional view showing an example of a semiconductor device according to an embodiment of the present disclosure, in which the center of a first gate is taken along a cutting line parallel to the second direction.

[0032] Figure 2B is a cross-sectional view showing an example of a semiconductor device according to an embodiment of the present disclosure, in which the center of the second gate is taken along a cutting line parallel to the second direction.

[0033] Figure 2C is a cross-sectional view illustrating an example of a semiconductor device according to an embodiment of the present disclosure in which the center of a bit line is taken along a cutting line parallel to a first direction.

[0034] Figure 3A is a cross-sectional view illustrating an example of a semiconductor device according to another embodiment of the present disclosure, in which the center of a first gate is taken along a cutting line parallel to the second direction.

[0035] Figure 3B is a cross-sectional view illustrating an example of a semiconductor device according to another embodiment of the present disclosure, in which the center of a second gate is taken along a cutting line parallel to the second direction.

[0036] Figure 3C is a cross-sectional view illustrating an example of a semiconductor device according to another embodiment of the present disclosure in which the center of a bit line is taken along a cutting line parallel to a first direction.

[0037] Figure 4A is a cross-sectional view illustrating an example of a semiconductor device according to another embodiment of the present disclosure, in which the center of a first gate is taken along a cutting line parallel to the second direction.

[0038] Figure 4B is a cross-sectional view illustrating an example of a semiconductor device according to another embodiment of the present disclosure, in which the center of a second gate is taken along a cutting line parallel to the second direction.

[0039] Figure 4C is a cross-sectional view illustrating an example of a semiconductor device according to another embodiment of the present disclosure in which the center of a bit line is taken along a cutting line parallel to a first direction.

[0040] Figure 5A is a cross-sectional view illustrating an example of a semiconductor device according to still another embodiment of the present disclosure, in which the center of a first gate is taken along a cutting line parallel to the second direction.

[0041] Figure 5B is a cross-sectional view illustrating an example of a semiconductor device according to still another embodiment of the present disclosure, in which the center of a second gate is taken along a cutting line parallel to the second direction.

[0042] Figure 5C is a cross-sectional view illustrating an example of a semiconductor device according to still another embodiment of the present disclosure, in which the center of a bit line is taken along a cutting line parallel to a first direction. DETAILED DESCRIPTION

[0043] This patent document provides implementations and examples of semiconductor devices including memory cells that can be used in configurations to substantially solve one or more technical or engineering problems and alleviate limitations or shortcomings encountered in certain other semiconductor devices. Some embodiments of the present disclosure relate to semiconductor memory devices with higher integration. Some embodiments of the present disclosure relate to semiconductor memory devices in which the contact resistance between an active area and an adjacent area is reduced. Recognizing the above problems, the present disclosure can provide a semiconductor device with a three-dimensional (3D) channel to increase integration. The present disclosure can provide a semiconductor device that can reduce the contact resistance between an active area and a bit line and can reduce the contact resistance between an active area and a capacitor.

[0044] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. Although the present disclosure is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings. However, the present disclosure should not be construed as limited to the embodiments described herein.

[0045] Various embodiments will be described below with reference to the accompanying drawings. However, the present disclosure is not limited to specific embodiments, but includes various modifications, equivalents and / or alternatives of the embodiments. The embodiments of the present disclosure can provide various effects that can be directly or indirectly recognized through the content of the present disclosure.

[0046] In the following description, detailed description of related known configurations or functions incorporated herein will be omitted to avoid obscuring the subject matter.

[0047] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, the singular form as used herein is also intended to include the plural form. It should also be understood that the terms "comprise", "include", "contain" and / or "comprising" when used in this specification specify the presence of the constituent elements, steps, operations and / or components, but do not exclude the presence or addition of one or more other constituent elements, steps, operations and / or components. The term "and / or" can include a combination of multiple items or any one of the multiple items.

[0048] Hereinafter, a semiconductor device and a method for manufacturing the same according to embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0049] Figure 1 is a schematic perspective view showing an example of a semiconductor device 1 according to an embodiment of the present disclosure.

[0050] See also Figure 1 The semiconductor device 1 may include a substrate (LS) and a memory cell array (MCA) formed on the substrate (LS). The memory cell array (MCA) may include a plurality of memory cells (MC) repeatedly arranged on the substrate (LS).

[0051] In some embodiments, each memory cell may have a three-dimensional (3D) structure.

[0052] More specifically, each memory cell (MC) included in the memory cell array (MCA) may include a bit line (BL), a transistor (TR), a contact (CT), and a capacitor (CAP).

[0053] The bit lines (BL) may be disposed on the substrate (LS) and may extend in a first direction (D1) parallel to one surface of the substrate (LS). Adjacent bit lines (BL) may be isolated from each other by an insulating layer (not shown).

[0054] For example, the insulating layer may include silicon oxide, silicon nitride, or a combination thereof.

[0055] In some embodiments, the capacitors (CAP) may be spaced apart from the bit lines (BL) in a third direction (D3) and may be arranged in a matrix structure. Each capacitor (CAP) may be disposed on a contact (CT) located in a region where the gates (G1, G2) and the bit lines (BL) overlap.

[0056] In some other embodiments, each capacitor (CAP) may be arranged to be offset from the center of the contact (CT) located in a region where the gate (G1, G2) and the bit line (BL) overlap with each other.

[0057] More specifically, the capacitors (CAP) may be arranged in a zigzag or honeycomb shape with respect to the contacts (CT) arranged in a matrix structure.

[0058] The transistor (TR) may be arranged between the bit line (BL) and the capacitor (CAP) in the third direction (D3).

[0059] The transistor (TR) may include at least a portion of an active region (ACT) connected to a bit line (BL), and may include a first gate (G1) and a second gate (G2).

[0060] according to Figure 1 In an embodiment, a word line driving voltage may be provided to a second gate (G2) extending in a second direction (D2) perpendicular to the first direction (D1). In other words, the second gate (G2) may operate as a word line of the transistor (TR).

[0061] In these instances, a voltage different from the voltage of the second gate (G2) may be applied to the first gate (G1) extending opposite to the second gate (G2) to prevent interference between the second gates (G2) of adjacent transistors (TR). For example, a ground voltage may be applied to the first gate (G1), and the first gate (G1) may operate as a back gate.

[0062] The first direction ( D1 ) may be perpendicular to the second direction ( D2 ), and the third direction ( D3 ) may be perpendicular to each of the first direction ( D1 ) and the second direction ( D2 ).

[0063] Each memory cell (MC) may include a contact (CT) electrically connecting a capacitor (CAP) and a bit line (BL). The active region (ACT) may contact the contact (CT) via a first contact region (CR1) located on one side of a vertical portion of the active region (ACT). For example, the contact (CT) may include a conductive material.

[0064] The active region (ACT) may include a channel region and source / drain regions of the transistor (TR).

[0065] Depending on the voltage applied to the second gate (G2) of the transistor (TR), a channel region may be formed in the active region (ACT), and in these instances, electrons may move between the source / drain regions through the channel region.

[0066] The active region (ACT) may include a horizontal portion extending along the first direction ( D1 ) and a vertical portion extending along the third direction ( D3 ).

[0067] Each memory cell (MC) may include a transistor (TR).

[0068] Two adjacent vertical portions included in the active area (ACT) may be connected to one horizontal portion.The horizontal portion included in the active area (ACT) may be connected to the bit line (BL).

[0069] An insulating layer may be formed between the active region ACT and the gate ( G1 , G2 ), and the active region (ACT) may be electrically isolated from the gate ( G1 , G2 ) by the insulating layer.

[0070] The memory cell array (MCA) may include a DRAM cell array. In some other embodiments, the memory cell array (MCA) may include a phase change random access memory (PCRAM), a resistive random access memory (ReRAM), a magnetic random access memory (MRAM), etc.

[0071] Depending on the type of the memory cell array (MCA), the capacitor (CAP) may be replaced by another storage element.

[0072] The substrate (LS) may be a material suitable for semiconductor processing. The substrate (LS) may include at least one of a conductive material, an insulating material (also known as a dielectric material), and a semiconductor material (also known as a semiconducting material). In some embodiments, multiple material layers may be formed on the substrate (LS).

[0073] The substrate (LS) may include a semiconductor substrate. For example, the substrate (LS) may be formed of a semiconductor material including silicon. The substrate (LS) may include silicon, single-crystal silicon, amorphous silicon, silicon germanium, single-crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, combinations thereof, or multilayers thereof.

[0074] The substrate (LS) may also include other semiconductor materials such as germanium.The substrate (LS) may include a III / V semiconductor substrate, for example a compound semiconductor substrate such as GaAs.

[0075] The substrate (LS) may include a silicon-on-insulator (SOI) substrate.

[0076] In another embodiment, the substrate (LS) may include a peripheral circuit region (not shown) located at a lower portion thereof. The peripheral circuit region may include a plurality of control circuits for controlling the memory cell array (MCA). At least one control circuit in the peripheral circuit region may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit in the peripheral circuit region may include an address decoder circuit, a read circuit, a write circuit, etc.

[0077] At least one control circuit included in the peripheral circuit region may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, a fin channel transistor (FinFET), or the like.

[0078] At least one control circuit included in the peripheral circuit region may be electrically connected to the bit line (BL). The peripheral circuit region may include a sense amplifier (sense-amp), which may be electrically connected to the bit line (BL). Although not shown, a multilayer metal interconnect (MLM) may be provided between the substrate (LS) and the memory cell array (MCA). The peripheral circuit region and the bit line (BL) may be connected to each other via the multilayer metal interconnect (MLM).

[0079] See again Figure 1 The bit lines (BL) may be disposed in the substrate (LS). In some embodiments, an insulating layer may be disposed between the bit lines (BL) disposed in the substrate (LS) to electrically isolate adjacent bit lines (BL) from each other.

[0080] The bit lines (BL) may be oriented laterally (or horizontally) in a first direction ( D1 ).

[0081] The bit lines (BL) may be referred to as laterally oriented bit lines or laterally extending bit lines.

[0082] The bit lines (BL) may include a conductive material, a silicon-based material, a metal-based material, or a combination thereof, polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof.

[0083] The bit line (BL) may include polysilicon, titanium nitride, tungsten (W), or a combination thereof. For example, the bit line (BL) may include polysilicon or titanium nitride (TiN) doped with N-type impurities.

[0084] The bit line (BL) may include a stack structure (TiN / W) of titanium nitride (TiN) and tungsten (W). The bit line (BL) may further include an ohmic contact layer formed of, for example, metal silicide.

[0085] Memory cells (MC) arranged horizontally along a first direction (D1) may share a common bit line (BL). An insulating layer extending along the first direction (D1) may be provided between adjacent bit lines (BL). The insulating layer may include a plurality of layers and may function as a spacer to isolate adjacent bit lines (BL) from each other.

[0086] The transistors (TR) may be arranged in a matrix structure in a first direction (D1) and a second direction (D2).

[0087] Each transistor (TR) may be disposed between a bit line (BL) and a capacitor (CAP).

[0088] The transistor (TR) may include an active region (ACT), an insulating layer (not shown), and gates ( G1 , G2 ).

[0089] The gates (G1, G2) may extend along the second direction (D2), and the active region (ACT) may include a horizontal portion extending along the first direction (D1) and a vertical portion extending along the third direction (D3).

[0090] In some embodiments, the vertical portion may extend in a third direction ( D3 ) perpendicular to each of the first direction ( D1 ) and the second direction ( D2 ).

[0091] The active region (ACT) may include a first contact region (CR1) contacting one side of the vertical portion and located between the vertical portion and the capacitor (CAP).

[0092] An insulating layer may be provided to isolate adjacent active regions (ACT) and gates (G1, G2) from each other.

[0093] Each gate (G1, G2) may include a metal, a metal mixture, a metal alloy, titanium nitride, tungsten, polysilicon, or a combination thereof.

[0094] For example, the gates ( G1 , G2 ) may include a stack structure (TiN / W) in which titanium nitride and tungsten are sequentially stacked.

[0095] The gates (G1, G2) may extend in one direction, and the bit lines (BL) may extend in another direction perpendicular to the one direction. The active region (ACT) may include a semiconductor material or an oxide semiconductor material.

[0096] The bit line (BL) may be electrically isolated from the gate (G1, G2) by an insulating layer. In other words, the insulating layer may be provided between the bit line (BL) and the gate (G1, G2).

[0097] The active region (ACT) may include a plurality of impurity regions. The impurity regions may include source / drain regions of the transistor (TR).

[0098] The active region (ACT) may include doped polysilicon, undoped polysilicon, amorphous silicon, IGZO (amorphous indium gallium zinc oxide semiconductor), indium zinc oxide (IZO), indium tin oxide (ITO), indium oxide (InO 3 ), etc.

[0099] A horizontal portion included in the active region (ACT) may be electrically connected to the bit line (BL).

[0100] The capacitor (CAP) may be connected to the first contact region (CR1) included in the active region (ACT) through the contact (CT).

[0101] Furthermore, an insulating layer may be provided between the gates ( G1 , G2 ), and the gates ( G1 , G2 ) may be electrically isolated from each other by the insulating layer.

[0102] The insulating layer may include, for example, silicon oxide, silicon nitride, etc. The composition of the insulating layer may be different from one insulating layer to another depending on the location of the insulating layer.

[0103] The capacitor (CAP) may have a shape extending vertically from one surface of the substrate (LS) and may be arranged to contact the first contact region (CR1) included in the active region (ACT) through the contact (CT). The capacitor (CAP) may include, for example, a metal-insulator-metal (MIM) capacitor.

[0104] A capacitor (CAP) implemented as a MIM capacitor may include two electrodes and a dielectric layer disposed between the two electrodes. The dielectric layer may include silicon oxide, silicon nitride, a high-k material (eg, hafnium oxide or aluminum oxide), or a combination thereof.

[0105] The high-k material may have a higher dielectric constant than silicon oxide (SiO2). Silicon oxide (SiO2) may have a dielectric constant of approximately 3.9, and the dielectric layer may include a high-k material having a dielectric constant of 4 or greater. For example, the high-k material may have a dielectric constant of approximately 20 or greater.

[0106] The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). In another embodiment, the dielectric layer may include a composite layer including two or more layers formed of the above-mentioned high-k materials.

[0107] The dielectric layer may include a stacked structure of a high-k material and a high-bandgap material having a larger bandgap than the high-k material. For example, the dielectric layer may include silicon oxide (SiO2) as another high-bandgap material in addition to aluminum oxide (Al2O3). The dielectric layer containing the high-bandgap material can suppress leakage current.

[0108] The dielectric layer may include a laminate structure in which a high-k material and a high-bandgap material are alternately stacked. For example, the laminate structure may include ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3), ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2), HAHA (HfO2 / Al2O3 / HfO2 / Al2O3), or HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2).

[0109] The anode included in the capacitor (CAP) may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the anode included in the capacitor (CAP) may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, and tungsten nitride / tungsten (WN / W) stack.

[0110] In another embodiment, the electrode of the capacitor (CAP) may include a combination of a metal-based material and a silicon-based material. For example, the combination of the metal-based material and the silicon-based material may be a stacked structure of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN).

[0111] The capacitor (CAP) may have a three-dimensional (3D) structure, and the three-dimensional capacitor (CAP) may be repeatedly arranged in a matrix shape on one surface of the substrate (LS). The three-dimensional (3D) structure may be, for example, a cylindrical, columnar, or cylindrical-cylindrical shape. Here, the cylindrical-cylindrical shape may refer to a structure that combines a columnar and a cylindrical shape.

[0112] In another embodiment, the capacitor (CAP) may have a structure in which the capacitor (CAP) is arranged obliquely with respect to the contact (CT) located in a region where the bit line (BL) and the gate (G1, G2) are arranged to overlap each other, so that a maximum number of capacitors (CAP) can be arranged within the same area.

[0113] The memory cell (MC) may share a first gate (G1) and a second gate (G2). The first gate (G1) and the second gate (G2) may include the same conductive material.

[0114] Figure 2A To illustrate the cutting line ( Figure 1 AA') is a cross-sectional view of the center of the first gate G1. Figure 2B To illustrate the cutting line ( Figure 1 BB') is a cross-sectional view of the center of the second gate (G2).

[0115] Figure 2C To illustrate the cutting line ( Figure 1 FIG. 1 is a cross-sectional view of the center of the bit line (BL) taken along line CC').

[0116] See also Figure 2A 、 Figure 2B and Figure 2C , showing a substrate layer 210 , a silicide layer 220 formed on the substrate layer 210 , and a first nitride layer 230 formed on the silicide layer 220 .

[0117] The substrate layer 210 may include a silicon semiconductor material. For example, the substrate layer 210 may include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, etc.

[0118] The substrate layer 210 may include a plurality of control circuits configured to control the operation of the semiconductor device, and a region where the control circuits are provided may be referred to as a peripheral circuit region.

[0119] The silicide layer 220 formed on the substrate layer 210 may include a metal silicide material such as cobalt silicide (CoSi). The silicide layer 220 is provided in the semiconductor device so that the operating resistance of the semiconductor device can be reduced. In addition, the silicide layer 220 can serve as a protective layer for the substrate layer 210, thereby preventing damage to the substrate layer 210 during the semiconductor manufacturing process.

[0120] The first nitride layer 230 formed on the silicide layer 220 may be a layer containing silicon nitride. Since the first nitride layer 230 contains silicon nitride, damage to the substrate layer 210 can be avoided during a high-temperature semiconductor manufacturing process.

[0121] See also Figure 2A 、 Figure 2B and Figure 2C , the first oxide layer 240 may be disposed on the first nitride layer 230. The first oxide layer 240 may be a layer containing silicon oxide, etc., and may operate as an insulating layer together with the first nitride layer 230.

[0122] Since the first nitride layer 230 and the first oxide layer 240 are provided in the semiconductor device, the control circuit included in the substrate layer 210 may be electrically isolated from the bit line 250 .

[0123] The bit line 250 disposed on the first oxide layer 240 may include a plurality of layers extending along a first direction (D1). For example, the bit line 250 may include a first bit line layer 252 including titanium nitride (TiN), a second bit line layer 254 including tungsten (W), and a third bit line layer 256 including titanium nitride (TiN).

[0124] Since the materials of the multiple layers included in the bit line 250 are adjusted, the resistance of the semiconductor device may also be adjusted.

[0125] The first and third bit line layers 252 and 256 included in the bit line 250 may prevent the second bit line layer 254 from being oxidized by exposure to oxygen. When the second bit line layer 254 is exposed to oxygen, tungsten (W) may be oxidized, resulting in disconnection and defects.

[0126] Furthermore, titanium nitride (TiN) included in the first bitline layer 252 may have higher adhesion to silicon oxide than tungsten (W), and the first bitline layer 252 is disposed between the first oxide layer 240 and the second bitline layer 254 , thereby improving interface stability of the bitline 250 .

[0127] After depositing a plurality of layers, the bit line 250 may be formed through an etching process using a mask.

[0128] Adjacent bit lines 250 may be electrically isolated from each other by second and third bit line isolation layers 270 and 280. In some embodiments, second and third bit line isolation layers 270 may include silicon nitride and third and third bit line isolation layers 280 may include silicon oxide.

[0129] The bit line 250 and the first gate 290 may be isolated from each other by a first bit line isolation layer 260 .

[0130] The second and third bit line isolation layers 270 and 280 may serve as spacers that electrically isolate adjacent bit lines 250 from each other.

[0131] A first bit line isolation layer 260 may be disposed over each bit line 250 to electrically isolate the bit line 250 from the first gate 290. The first bit line isolation layer 260 may include silicon oxide containing carbon (SiCO).

[0132] See also Figure 2B and Figure 2C An active region 320 electrically connected to at least a portion of the bit line 250 may be disposed above the bit line 250 . The active region 320 may be electrically isolated from the second gate 340 by the second gate oxide layer 330 .

[0133] The first gate 290 and the second gate 340 may include metal, metal mixture, metal alloy, titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the first gate 290 and the second gate 340 may include titanium nitride.

[0134] See also Figure 2C , the first gate oxide 310 may be disposed not only on the first bit line isolation layer 260 but also on the sidewall of the first gate 290. Figures 2A to 2C Although not shown, at least a portion of the first gate oxide 310 may be disposed over the third bit line isolation layer 280 .

[0135] A first gate oxide 310 may be disposed between the first gate 290 and the active region 320. The first gate oxide 310 may include an insulating material such as silicon oxide.

[0136] A second nitride layer 300 may be disposed over the first gate 290 .

[0137] The third nitride layer 350 may be disposed between adjacent second gates 340. In addition, the third nitride layer 350 may be disposed between the first contact region 323 and the second gate 340.

[0138] The first contact region 323 may be formed by selectively etching at least a portion of the contact insulating layer 370 and depositing the same material as the active region 320. For example, the first contact region 323 may be a region including an oxide semiconductor material.

[0139] The second oxide layer 360 may be disposed on the third nitride layer 350 between the second gate electrodes 340. A vertical contact portion connected to the second gate electrodes 340 and the conductive line may be formed using a difference in etching rates between the second oxide layer 360 and the third nitride layer 350.

[0140] The active region 320 may include a horizontal portion 321 formed to contact the bit line 250 and a vertical portion formed to extend in a vertical direction ( D3 ) and disposed between the first gate 290 and the second gate 340 .

[0141] The active region 320 may include a first contact region 323 located at one side of the vertical portion 322 and in contact with the contact 410 .

[0142] The active region 320 may include, for example, an oxide semiconductor material, and the oxide semiconductor material may include indium gallium zinc oxide (IGZO).

[0143] In another embodiment, the active region 320 may include doped polysilicon, undoped polysilicon, amorphous silicon, indium zinc oxide (IZO), indium tin oxide (ITO), indium oxide (InO 3 ), or the like.

[0144] Since IGZO has a low leakage current characteristic and the active region 320 is formed of IGZO, a semiconductor device with low standby power can be realized.

[0145] In addition, since the active region 320 includes IGZO, the manufacturing process difficulty may be reduced, and the active region 320 having a three-dimensional (3D) structure including the horizontal portion 321 and the vertical portion 322 may be easily formed.

[0146] The first contact region 323 may include the same material as the active region 320 to reduce contact resistance between the oxide semiconductor material contacts 410 included in the active region 320 .

[0147] The width of the first contact region 323 in the first direction ( D1 ) may be greater than the width of the vertical portion. The width of the first contact region 323 may be the same as the width of the contact 410 .

[0148] Since the width of the first contact region 323 is greater than the width of the vertical portion 322 , the contact area between the contact 410 and the first contact region 323 can be ensured, thereby ensuring contact stability between the contact 410 and the first contact region 323 .

[0149] The contact 410 formed over the first contact region 323 may include a metal, a metal silicide, or a metal nitride. At least a portion of the capacitor (CAP) disposed over the contact 410 may be arranged to overlap with the contact 410.

[0150] The contact insulating layer 370 may be disposed between adjacent first contact regions 323. The contact insulating layer 370 may be disposed to surround the first contact regions 323. In other words, the contact insulating layer 370 may be disposed between adjacent first contact regions 323.

[0151] A layer provided with capacitors (CAP) may be referred to as a capacitor layer 400 .

[0152] The capacitor layer 400 may include at least a portion of the contact 410 , a capacitor (CAP) formed to overlap an upper portion of the contact 410 , and a capacitor insulating layer 420 disposed between the capacitor (CAP) and the contact 410 .

[0153] Each capacitor (CAP) may operate as a data storage unit for writing or reading data according to a control signal applied to the semiconductor device.

[0154] Each capacitor (CAP) may include a capacitor dielectric layer and a plurality of storage electrodes. Control signals supplied to the first gate 290 and the second gate 340 may determine whether a voltage is supplied to the capacitor (CAP) and may also determine the magnitude of the voltage supplied to the capacitor (CAP). The semiconductor device may read out stored data based on a signal corresponding to the voltage across the capacitor (CAP).

[0155] The capacitor (CAP) within the capacitor layer 400 may have a shape extending in a vertical direction (i.e., third direction D3) relative to the substrate layer 210. More specifically, the capacitor (CAP) may be formed in a cylindrical or columnar shape. Since the capacitor (CAP) has a cylindrical or columnar shape, the density of the capacitor (CAP) can be increased within the same area. As the density of the capacitor (CAP) increases, the data storage capacity of the semiconductor device can be increased.

[0156] Each capacitor (CAP) may correspond to one contact 410 , and one contact 410 may contact one capacitor (CAP).

[0157] See according to Figures 2A to 2C In the semiconductor device of the embodiment of the present invention, a ground voltage may be supplied to the first gate 290 at a data read / write time point, and a word line driving voltage may be supplied to the second gate 340 at a data read / write time point. When the ground voltage is supplied to the first gate 290, the first gate 290 may provide a reverse bias voltage to the semiconductor device.

[0158] The first gate 290 may be disposed between two adjacent second gates 340 (eg, between a pair of second gates 340 disposed parallel to the first gate 290). Since the ground voltage is supplied to the first gate 290, adjacent second gates 340 may be electrically isolated from each other.

[0159] Such electrical isolation between adjacent second gates 340 may mean that electrical interference between adjacent second gates 340 is blocked.

[0160] As semiconductor devices decrease in size, the distance between the second gates 340 becomes increasingly shorter. When the distance between the second gates 340 decreases, coupling may occur between adjacent second gates 340 due to the word line driving voltage supplied to each second gate 340. Due to the coupling, unexpected errors may occur during data read / write operations in the semiconductor device.

[0161] In some embodiments, the first gate 290 is disposed between the second gates 340, and a ground voltage is applied to the first gate 290, thereby avoiding coupling between the second gates 340, thereby improving the operating characteristics of the semiconductor device. In addition, since the ground voltage is applied to the first gate 290, coupling between adjacent active regions 320 can be avoided during operation of the semiconductor device.

[0162] Furthermore, the first gate 290, which is supplied with a ground voltage, can provide a reverse bias voltage to the semiconductor device, thereby effectively suppressing leakage current (e.g., gate-induced drain leakage (GIDL)) and improving the electrical characteristics of the semiconductor device. Furthermore, the first gate 290 can control the threshold voltage characteristics of the semiconductor device by providing a reverse bias voltage to the semiconductor device.

[0163] Figure 3A To illustrate a cutting line ( Figure 1 AA') is a cross-sectional view of the center of the first gate G1. Figure 3B To illustrate a cutting line ( Figure 1 BB') is a cross-sectional view of the center of the second gate (G2). Figure 3C To illustrate a cutting line ( Figure 1 FIG. 1 is a cross-sectional view of the center of the bit line (BL) taken along line CC').

[0164] according to Figures 3A to 3C In the embodiment, only the first contact regions 623 included in the active region 620, the contact insulating layer 670 for electrically isolating the first contact regions 623 from each other, and the contact member 710 are connected to the active region 620. Figures 2A to 2C Therefore, for the sake of brevity, the redundant description thereof will be omitted here, so that the following will focus on the Figures 2A to 2C The different features of the embodiments are described Figures 3A to 3C Example of .

[0165] See also Figure 3A 、 Figure 3B and Figure 3C, showing a substrate layer 510, a silicide layer 520 formed over the substrate layer 510, and a first nitride layer 530 formed over the silicide layer 520. In addition, a first oxide layer 540 may be disposed over the first nitride layer 530, and a bit line 550 may be disposed over the first oxide layer 540.

[0166] The bit line 550 may include a plurality of layers extending along a first direction (D1). For example, the bit line 550 may include a first bit line layer 552 including titanium nitride (TiN), a second bit line layer 554 including tungsten (W), and a third bit line layer 556 including titanium nitride (TiN).

[0167] The second bit line isolation layer 570 and the third bit line isolation layer 580 may be disposed between adjacent bit lines 550. In some embodiments, the second bit line isolation layer 570 may include silicon nitride, and the third bit line isolation layer 580 may include silicon oxide.

[0168] A first bit line isolation layer 560 may be disposed over each bit line 550 to electrically isolate the bit line 550 from the first gate 590. The first bit line isolation layer 560 may include silicon oxide containing carbon (SiCO).

[0169] See also Figure 3B and Figure 3C An active region 620 electrically connected to at least a portion of the bit line 550 may be disposed above the bit line 550 . A second gate oxide layer 630 may be disposed between the active region 620 and the second gate 640 .

[0170] The first gate 590 and the second gate 640 may include metal, a metal mixture, a metal alloy, titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the first gate 590 and the second gate 640 may include titanium nitride.

[0171] See also Figure 3C The first gate oxide 610 may be disposed not only on the first bit line isolation layer 560 , but also on the sidewall of the first gate 590 .

[0172] A first gate oxide 610 may be disposed between the first gate 590 and the active region 620. The first gate oxide 610 may include an insulating material such as silicon oxide.

[0173] The second nitride layer 600 may be disposed between the contact insulating layer 670 and the first gate 590 .

[0174] The third nitride layer 650 may be disposed between adjacent second gates 640. In addition, the third nitride layer 650 may be disposed between the contact insulating layer 670 and the second gate 640.

[0175] The second oxide layer 660 may be disposed on the third nitride layer 650 between the second gate electrodes 640. By utilizing the difference in etching rates between the second oxide layer 660 and the third nitride layer 650, a contact portion connected to the second gate electrode 640 and the conductive line may be formed in the second gate electrode 640.

[0176] The active region 620 may include a horizontal portion 621 formed to contact the bit line 550 and a vertical portion 622 formed to extend in a vertical direction (D3) and disposed between the first gate 590 and the second gate 640. The active region 620 may include, for example, an oxide semiconductor material.

[0177] The active region 620 may include a first contact region 623 contacting one end of the vertical portion 622 and connected to the contact 710 .

[0178] The first contact region 623 according to another embodiment of the present disclosure may be formed to surround sidewalls and a bottom surface of a contact trench formed in the contact insulating layer 670. The contact trench may overlap the vertical portion 622 of the active region 620.

[0179] In some embodiments, the contact trench may be formed in a trapezoidal shape, wherein the length of the upper side is greater than the length of the bottom side. In this case, the sidewall of the contact trench may have an inclined shape.

[0180] In addition, at least a portion of the contact 710 contacting the first contact region 623 may be recessed into the first contact region 623. Therefore, the first contact region 623 may contact the bottom surface and the side surface of the contact 710.

[0181] The first contact region 623 contacts the bottom and side surfaces of the contact 710 , and the contact 710 has a shape recessed into the first contact region 623 , so that contact stability between the first contact region 623 and the contact 710 can be ensured.

[0182] The contact 710 may include a metal, a metal silicide, or a metal nitride. At least a portion of the capacitor (CAP) disposed over the contact 710 may be arranged to overlap with the contact 710.

[0183] A contact insulation layer 670 may be disposed between adjacent first contact regions 623 .

[0184] A layer provided with capacitors (CAP) may be referred to as a capacitor layer 700 .

[0185] The capacitor layer 700 may include at least a portion of the contact 710 , and may include capacitors (CAP) and a capacitor insulating layer 720 disposed between the capacitors (CAP).

[0186] Each capacitor (CAP) may have a shape extending in a direction (ie, third direction D3) perpendicular to the substrate layer 510 within the capacitor layer 700. More specifically, the capacitor (CAP) may be formed in a cylindrical or columnar shape.

[0187] Figure 4A To illustrate a cutting line ( Figure 1 AA') is a cross-sectional view of the center of the first gate G1. Figure 4B To illustrate a cutting line ( Figure 1 BB') is a cross-sectional view of the center of the second gate (G2). Figure 4C To illustrate a cutting line ( Figure 1 FIG. 1 is a cross-sectional view of the center of the bit line (BL) taken along line CC').

[0188] according to Figures 4A to 4C In the embodiment, only the second contact region 924 included in the active region 920 is connected to Figures 2A to 2C Therefore, for the sake of brevity, the redundant description thereof will be omitted here, so that the following will focus on Figures 2A to 2C The different features of the embodiments are described Figures 4A to 4C Example of .

[0189] See also Figure 4A 、 Figure 4B and Figure 4C , showing a substrate layer 810, a silicide layer 820 formed on the substrate layer 810, and a first nitride layer 830 formed on the silicide layer 820. In addition, a first oxide layer 840 may be disposed on the first nitride layer 830, and a bit line 850 may be disposed on the first oxide layer 840.

[0190] The bit line 850 may include a plurality of layers extending along a first direction (D1). For example, the bit line 850 may include a first bit line layer 852 including titanium nitride (TiN), a second bit line layer 854 including tungsten (W), and a third bit line layer 856 including titanium nitride (TiN).

[0191] The second contact region 924 may be disposed over the bit line 850. The second contact region 924 may extend in a direction (D1) in which the bit line 850 extends.

[0192] The second contact region 924 may be included in the active region 920 and may include the same material as the active region 920 .

[0193] The second contact region 924 may extend along a horizontal portion 921 included in the active region 920 and may be electrically isolated from the first gate 890 by the first bit line isolation layer 860 and the first gate oxide 910 .

[0194] Since the second contact region 924 includes the same material as the active region 920, it is possible to reduce the contact resistance between the active region 920 and the bit line 850. In addition, since the second contact region 924 has been formed, the active region 920 can be expanded.

[0195] The second bit line isolation layer 870 and the third bit line isolation layer 880 may be disposed between adjacent bit lines 850. In some embodiments, the second bit line isolation layer 870 may include silicon nitride, and the third bit line isolation layer 880 may include silicon oxide.

[0196] The second bit line isolation layer 870 may be in contact with the second contact region 924. In addition, the second bit line isolation layer 870 may be in contact with the first bit line isolation layer 860.

[0197] The second bit line isolation layer 870 may have a shape in contact with the second contact region 924. In addition, the second bit line isolation layer 870 may be in contact with the first bit line isolation layer 860.

[0198] In other words, after forming the second contact region 924 over the bit line 850 and forming the first bit line isolation layer 860 over the second contact region 924 , the second bit line isolation layer 870 may be formed along side surfaces of the second contact region 924 and the bit line 850 .

[0199] The first bit line isolation layer 860 may be disposed between the first gate 890 and the second contact region 924. The first bit line isolation layer 860 may include silicon oxide containing carbon (SiCO).

[0200] The active region 920 formed over the bit line 850 may contact the bit line 850 through the second contact region 924 .

[0201] The second gate oxide 930 may be disposed between the active region 920 and the second gate 940 .

[0202] The first gate 890 and the second gate 940 may include metal, a metal mixture, a metal alloy, titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the first gate 890 and the second gate 940 may include titanium nitride.

[0203] See also Figure 4C The first gate oxide 910 may be disposed not only on the first bit line isolation layer 860 , but also on the sidewall of the first gate 890 .

[0204] A first gate oxide 910 may be disposed between the first gate 890 and the active region 920. The first gate oxide 910 may include an insulating material such as silicon oxide.

[0205] The second nitride layer 900 may be disposed between the contact insulating layer 970 and the first gate 890 .

[0206] The third nitride layer 950 may be disposed between adjacent second gates 940. In addition, the third nitride layer 950 may be disposed between the contact insulating layer 670 and the second gate 940.

[0207] The second oxide layer 960 may be disposed on the third nitride layer 950 between the second gate electrodes 940. By utilizing the difference in etching rates between the second oxide layer 960 and the third nitride layer 950, a contact portion connected to the second gate electrode 940 and the conductive line may be formed in the second gate electrode 940.

[0208] The active region 920 may include a horizontal portion 921 formed to contact the bit line 850 and a vertical portion 922 formed to extend in a vertical direction (D3) and disposed between the first gate 890 and the second gate 940. The active region 920 may include, for example, an oxide semiconductor material.

[0209] One end of the vertical portion 922 included in the active region 920 may include a first contact region 923 connected to the contact 1010 .

[0210] The contact 1010 may include a metal, a metal silicide, or a metal nitride. At least a portion of the capacitor (CAP) disposed over the contact 1010 may be arranged to overlap with the contact 1010.

[0211] A contact insulating layer 970 may be disposed between adjacent first contact regions 923 .

[0212] A layer provided with capacitors (CAP) may be referred to as a capacitor layer 1000 .

[0213] The capacitor layer 1000 may include at least a portion of the contact 1010 , and may include capacitors (CAP) and a capacitor insulating layer 1020 disposed between the capacitors (CAP).

[0214] Figure 5A 2 is a diagram showing a cutting line ( Figure 1 AA') is a cross-sectional view of the center of the first gate G1. Figure 5B To show the basis Figure 5A The embodiment of the invention is along the cutting line ( Figure 1BB') is a cross-sectional view of the center of the second gate (G2).

[0215] Figure 5C To show the basis Figure 5A and Figure 5B The embodiment of the invention is along the cutting line ( Figure 1 FIG. 1 is a cross-sectional view of the center of the bit line (BL) taken along line CC').

[0216] according to Figures 5A to 5C In the embodiment, only the shape of the active region 1220 and the first extension region 1225 and the second extension region 1226 included in the active region 1220 are different from Figures 2A to 2C Therefore, for the sake of brevity, the redundant description thereof will be omitted here, so that the following will focus on Figures 2A to 2C The different features of the embodiments are described Figures 5A to 5C Example of .

[0217] See also Figure 5A 、 Figure 5B and Figure 5C , showing a substrate layer 1110, a silicide layer 1120 formed over the substrate layer 1110, and a first nitride layer 1130 formed over the silicide layer 1120. In addition, a first oxide layer 1140 may be disposed over the first nitride layer 1130, and a bit line 1150 may be disposed over the first oxide layer 1140.

[0218] The bit line 1150 may include a plurality of layers extending in a first direction (D1). For example, the bit line 1150 may include a first bit line layer 1152 including titanium nitride (TiN), a second bit line layer 1154 including tungsten (W), and a third bit line layer 1156 including titanium nitride (TiN).

[0219] The active region 1220 may be disposed over the bit line 1150 .

[0220] A horizontal portion 1221 included in the active region 1220 may be connected to the bit line 1150 , and a first bit line isolation layer 1160 and a first gate oxide 1210 may be disposed between the active region 1220 and the first gate 890 .

[0221] The active region 1220 may include a horizontal portion 1221 formed to contact the bit line 1150 and a vertical portion 1222 formed to extend in a vertical direction (D3) and disposed between the first gate 1190 and the second gate 1240. The active region 1220 may include, for example, an oxide semiconductor material.

[0222] See also Figure 5C, the cross-section of the first gate 1190 according to an embodiment of the present disclosure may have a trapezoidal shape. More specifically, the first gate 1190 may have a rectangular shape in which the width of the upper portion is smaller than the width of the lower portion.

[0223] In some embodiments, when forming the first gate 1190 , a side surface of the first gate 1190 is etched to form an inclined surface, so that the first gate 1190 may have a trapezoidal cross-section.

[0224] The vertical portion 1222 included in the active region 1220 may be formed diagonally along the first gate oxide 1210 disposed on the side surface of the first gate 1190. The vertical portion 1222 may be formed to form a preset first angle with respect to the horizontal portion 1221. In some embodiments, the first angle may be greater than 90 degrees and less than 180 degrees.

[0225] The vertical portion 1222 may be obliquely formed to form a first angle with respect to the horizontal portion 1221 , such that the vertical portion 1222 may extend along a sidewall of the first gate 1190 .

[0226] The active region 1220 may include a first extension region 1225 disposed on a side surface of the vertical portion 1222 .

[0227] In addition, the active region 1220 may include a vertical portion 1222 and a first contact region 1223 disposed on the first extension region 1225 .

[0228] The first extension region 1225 and the first contact region 1223 may include an oxide semiconductor material such as amorphous indium gallium zinc oxide (IGZO).

[0229] Since the first extension region 1225 is disposed on the side surface of the vertical portion 1222 , the contact area between the vertical portion 1222 and the first contact region 1223 may be expanded.

[0230] Active region 1220 may include a second extension region 1226 disposed on horizontal portion 1221. Second extension region 1226 may include the same oxide semiconductor material as active region 1220. With the formation of second extension region 1226, active region 1220 may be expanded.

[0231] In some embodiments, first extension region 1225 and second extension region 1226 may be formed by a sputtering process.

[0232] More specifically, after depositing an oxide semiconductor layer as horizontal portion 1221 and vertical portion 1222 on first gate oxide 1210 , an oxide semiconductor material to be used as first extension region 1225 and second extension region 1226 may be selectively deposited through a sputtering process.

[0233] The second bit line isolation layer 1170 and the third bit line isolation layer 1180 may be disposed between adjacent bit lines 1150. In some embodiments, the second bit line isolation layer 1170 may include silicon nitride, and the third bit line isolation layer 1180 may include silicon oxide.

[0234] A first bit line isolation layer 1160 may be disposed between the first gate 1190 and the bit line 1150. The first bit line isolation layer 1160 may include silicon oxide containing carbon (SiCO).

[0235] The second gate oxide 1230 may be disposed between the active region 1220 and the second gate 1240 .

[0236] The first gate 1190 and the second gate 1240 may include metal, a metal mixture, a metal alloy, titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the first gate 1190 and the second gate 1240 may include titanium nitride.

[0237] See also Figure 5C The first gate oxide 1210 may be disposed not only on the first bit line isolation layer 1160 , but also on the sidewall of the first gate 1190 .

[0238] A first gate oxide 1210 may be disposed between the first gate 1190 and the active region 1220. The first gate oxide 1210 may include an insulating material such as silicon oxide.

[0239] The second nitride layer 1200 may be disposed between the first gate 1190 and the contact insulating layer 1270 .

[0240] The third nitride layer 1250 may be disposed between adjacent second gates 1240. In addition, the third nitride layer 1250 may be disposed between the first contact region 1223 and the second gate 1240.

[0241] The second oxide layer 1260 may be disposed on the third nitride layer 1250 between the second gate electrodes 1240. By utilizing the difference in etching rates between the second oxide layer 1260 and the third nitride layer 1250, a contact portion connected to the second gate electrode 1240 and the conductive line may be formed in the second gate electrode 1240.

[0242] The contact 1310 may include a metal, a metal silicide, or a metal nitride. At least a portion of the capacitor (CAP) disposed over the contact 1310 may be arranged to overlap with the contact 1310.

[0243] A contact insulation layer 1270 may be disposed between adjacent first contact regions 1223 .

[0244] A layer provided with capacitors (CAP) may be referred to as a capacitor layer 1300 .

[0245] The capacitor layer 1300 may include at least a portion of the contact 1310 , and may further include capacitors (CAP) and a capacitor insulating layer 1320 disposed between the capacitors (CAP).

[0246] As apparent from the above description, semiconductor devices according to some embodiments of the present disclosure include three-dimensional (3D) channels to improve integration.

[0247] In addition, the semiconductor device according to some embodiments of the present disclosure can reduce the contact resistance between the active region and the bit line, and can reduce the contact resistance between the active region and the capacitor.

[0248] The embodiments of the present disclosure can provide various effects that can be directly or indirectly recognized through the above-mentioned patent documents.

[0249] Those skilled in the art will appreciate that the present disclosure may be implemented in other specific ways than those described herein. In addition, claims not explicitly set forth in the appended claims may be set forth in combination as embodiments, or may be included as new claims through subsequent amendments after the application is submitted.

[0250] While a number of illustrative embodiments have been described, it should be understood that modifications and enhancements to the disclosed embodiments and other embodiments may be devised based upon what is described and / or illustrated in this patent document.

Claims

1. A semiconductor device comprising: A bit line is arranged to extend along a first direction; a first gate arranged to extend along a second direction intersecting with the first direction; a second grid electrode, arranged to extend parallel to the first grid electrode; an active region having a first side in contact with the bit line; as well as a contact arranged to contact the second side of the active region, Wherein, the active area includes: a horizontal portion arranged to extend along the first direction; a vertical portion disposed between the first gate and the second gate; and A first contact region is provided to contact the contact member and the vertical portion.

2. The semiconductor device according to claim 1, wherein The bit line is disposed to contact the horizontal portion.

3. The semiconductor device according to claim 1, wherein The active region further includes a second contact region disposed between the bit line and the horizontal portion to contact the bit line and the horizontal portion.

4. The semiconductor device according to claim 1, wherein The active region includes indium gallium zinc oxide (IGZO).

5. The semiconductor device according to claim 1, wherein The width of the first contact region is equal to or greater than the width of the vertical portion. The semiconductor device according to claim 1 , wherein: The width of the first contact region is equal to or smaller than the width of the contact element.

7. The semiconductor device according to claim 1, wherein The active region further includes a first extension region disposed to contact a bottom surface of the first contact region and a side surface of the vertical portion.

8. The semiconductor device according to claim 1, wherein The first contact region is disposed to contact a bottom surface and a side surface of the contact.

9. The semiconductor device according to claim 8, wherein The first contact region is provided along sidewalls and a bottom surface of a contact trench provided in the contact insulating layer.

10. The semiconductor device according to claim 9, wherein The contact trench is disposed to overlap with the vertical portion. The semiconductor device according to claim 1 , wherein the contact is connected to a capacitor.

12. The semiconductor device according to claim 1, wherein The vertical portion extends along a side surface of the first gate and forms a first angle with respect to the horizontal portion.

13. The semiconductor device according to claim 1, wherein The active region further includes a second extension region disposed above the horizontal portion.

14. The semiconductor device according to claim 1, wherein The first gate and the second gate receive different control signals.

15. A semiconductor device comprising: A bit line is arranged to extend along a first direction; a first gate arranged to extend along a second direction intersecting with the first direction; a pair of second grid electrodes disposed on both sides of the first grid electrode to extend parallel to the first grid electrode; an active region having a first side in contact with the bit line; as well as a contact arranged to contact the second side of the active region, Wherein, the active area includes: a horizontal portion arranged to extend along the first direction and contact the bit line; a vertical portion disposed between the first gate and the second gate to extend from the horizontal portion toward the contact; and a first contact region disposed between the contact member and the vertical portion, and The horizontal portion is located below the second gate.

16. The semiconductor device according to claim 15, wherein The active region further includes a second contact region disposed between the bit line and the horizontal portion to contact the bit line and the horizontal portion.

17. The semiconductor device according to claim 15, wherein The active region includes indium gallium zinc oxide (IGZO).

18. The semiconductor device according to claim 15, wherein The active region further includes a first extension region disposed to contact a bottom surface of the first contact region and a side surface of the vertical portion.

19. The semiconductor device according to claim 18, wherein The first extension region is disposed to contact a bottom surface and a side surface of the contact.

20. The semiconductor device according to claim 15, wherein The active region further includes a second extension region disposed above the horizontal portion.

21. A semiconductor device comprising: A bit line is arranged to extend along a first direction; a first gate disposed to extend along a second direction intersecting the first direction, wherein a cross section of the first gate has a trapezoidal shape; a pair of second gates disposed on both sides of the first gate to extend parallel to the first gate; and An active region includes a horizontal portion and a vertical portion, the horizontal portion contacting the bit line, and the vertical portion is provided between the first gate and the pair of second gates to extend in a vertical direction.

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