Formation method of semiconductor structure

Abstract

The invention discloses a method for forming a semiconductor structure. The method comprises the following steps: providing a substrate; the substrate is provided with a channel laminated material layer, and the channel laminated material layer comprises a sacrificial layer and a channel layer located on the sacrificial layer; etching a part of the channel laminated material layer until the substrate is exposed, and forming a fin structure on the substrate; the side wall of the fin structure is provided with a groove; forming a crystalline silicon layer on the fin structure, wherein the crystalline silicon layer is used for filling the groove in the fin structure; therefore, a sunken region is prevented from being formed on the side wall of the semiconductor structure; and then planarization processing is carried out on the crystalline silicon layer to obtain a fin structure with a flat side wall, thereby ensuring that the semiconductor structure has good electrical performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure. Background Art

[0002] Gate-all-around (GAA) transistors have a unique superlattice fin (FIN) structure. Because silicon-germanium alloy (SiGe) has faster oxidation and etching rates than silicon, and SiGe oxide is soluble in water, the sidewalls of the FINSiGe layer are recessed after FIN-ET. As a result, a-Si is filled during polysilicon deposition and is not removed during the subsequent GT (gate)-ET process, remaining in the channel. This leads to a very high risk of short circuits between GT-GT and SiP (silicon phosphide)-GT. Summary of the Invention

[0003] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which can avoid the formation of a recessed area on the side wall of the semiconductor structure and ensure that the semiconductor structure has good electrical properties.

[0004] In order to solve the above technical problems, the technical solutions of this application are as follows:

[0005] The present application provides a method for forming a semiconductor structure, the method comprising:

[0006] Providing a substrate; the substrate having a channel stack material layer, the channel stack material layer including a sacrificial layer and a channel layer located on the sacrificial layer;

[0007] Etching a portion of the channel stack material layer until the substrate is exposed, thereby forming a fin structure on the substrate; a groove is formed on a sidewall of the fin structure;

[0008] forming a crystalline silicon layer on the fin structure, wherein the crystalline silicon layer is used to fill the groove in the fin structure;

[0009] The crystalline silicon layer is planarized to obtain a fin structure with smooth sidewalls.

[0010] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0011] The present invention provides a method for forming a semiconductor structure, comprising providing a substrate; a channel stack material layer being provided on the substrate, the channel stack material layer comprising a sacrificial layer and a channel layer located on the sacrificial layer; etching a portion of the channel stack material layer until the substrate is exposed, thereby forming a fin structure on the substrate; a groove being provided on the sidewall of the fin structure; forming a crystalline silicon layer on the fin structure, the crystalline silicon layer being used to fill the groove in the fin structure, thereby avoiding the formation of a recessed area on the sidewall of the semiconductor structure; and then flattening the crystalline silicon layer to obtain a fin structure with smooth sidewalls, thereby ensuring that the semiconductor structure has good electrical properties. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0013] Figure 1 A schematic cross-sectional view of a semiconductor structure formed by a FIN in the prior art;

[0014] Figure 2 for Figure 1 Transmission electron microscope image of the corresponding semiconductor material;

[0015] Figure 3 A schematic cross-sectional view of a semiconductor structure forming process in the prior art;

[0016] Figure 4 Schematic diagram of the cross-sectional structure of the GAA formation process in the prior art;

[0017] Figure 5 A schematic flow chart of a method for forming a semiconductor structure provided by an embodiment of the present invention;

[0018] Figure 6-10 A schematic cross-sectional view of a semiconductor structure forming process according to an embodiment of the present invention;

[0019] 1-substrate, 2-channel stack material layer, 21-channel layer, 22-sacrificial layer, 3-silicon oxide layer, 4-first silicon nitride layer, 5-photoresist layer, 6-mask layer, 7-groove, 8-second silicon nitride layer, 9-oxide layer, 10-polysilicon layer, 11-crystalline silicon layer. DETAILED DESCRIPTION

[0020] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0021] "One embodiment" or "embodiment" as referred to herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present application. In the description of the present application, it is to be understood that spatially relative terms, such as "below", "below", "lower", "on", "upper", "front", "back", "above" and the like may be used herein for ease of description to describe the relationship between one element or feature and another element or feature as illustrated in the figures. This is for ease of description only and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as a limitation on the present application. Spatially relative terms are intended to cover different orientations of the device in use or operation other than the orientation depicted in the figures. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can be interpreted similarly.

[0022] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these components and configurations are merely examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0023] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of such features. Moreover, the terms "first," "second," etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein.

[0024] The problems existing in the existing Gate-All-Around (GAA) transistor will now be described in detail with reference to the accompanying drawings.

[0025] First, let’s introduce GAA:

[0026] GAA has a unique superlattice fin structure (FIN). In existing FINs, the oxidation and etching rates of silicon-germanium alloy (SiGe) are faster than those of silicon, and SiGe oxide is soluble in water. As a result, the sidewalls of the FIN SiGe layer are recessed after FIN-ET. As a result, a-Si is filled during polysilicon deposition and is not removed during the subsequent GT (gate)-ET process, thus remaining in the channel. This leads to a very high risk of short circuits between GT-GT and SiP (silicon phosphide)-GT.

[0027] like Figure 1 As shown, Figure 1 The semiconductor structure formed by FIN in the prior art is shown. The structure includes a substrate 1, three channel stack material layers 2 located on the substrate 1, and a silicon oxide layer 3, a first silicon nitride layer 4, and a photoresist layer 5 located on the three channel stack material layers 2 in sequence; each channel stack material layer 2 includes a sacrificial layer and a channel layer located on the sacrificial layer; a recessed area is formed on the sidewall of the SiGe layer of the semiconductor structure; Figure 2 As shown, Figure 2 for Figure 1 The corresponding transmission electron microscope image of the semiconductor material shows the thickness of each layer in the existing semiconductor structure (unit: nm). Through the transmission electron microscope image, it can be seen that a recessed area is formed on the sidewall of the SiGe layer.

[0028] like Figure 3 As shown, Figure 3 FIG. 1 is a schematic cross-sectional view of a semiconductor structure forming process in the prior art; FIG. Figure 3 As shown in Figure a, three channel stack material layers 2 are formed on a substrate 1; then a silicon oxide layer 3, a first silicon nitride layer 4, and a photoresist layer 5 are sequentially formed on the three channel stack material layers 2; wherein the silicon oxide layer 3, the first silicon nitride layer 4, and the photoresist layer 5 constitute a mask layer 6; then, plasma is used to etch the substrate 1 to form a Figure 3 In the fin structure shown in FIG. b, a groove is formed on the sidewall of the sacrificial layer 22 of the structure; ozone (OZ) and hydrofluoric acid (HF) are then used to further perform wet etching; Figure 3 As shown in Figure c, during the wet etching process, the existing technology cannot improve the defect of the groove on the side wall of the sacrificial layer 22 by reducing the hydrofluoric acid cleaning time and other operations.

[0029] like Figure 4 As shown, Figure 4Schematic diagram of the cross-sectional structure of the GAA formation process in the prior art; Figure 4 As shown in Figure a, three channel stack material layers 2 are formed on a substrate 1; then a silicon oxide layer 3, a first silicon nitride layer 4, and a photoresist layer 5 are sequentially formed on the three channel stack material layers 2; wherein the silicon oxide layer 3, the first silicon nitride layer 4, and the photoresist layer 5 constitute a mask layer 6; Figure 4 As shown in FIG. 2(b), the substrate 1 is etched by plasma to form a fin structure, and a groove 7 is formed on the side wall of the sacrificial layer 22 of the structure; Figure 4 As shown in Figure c, two second silicon nitride layers 8 are formed on the outer surface of the channel stack material layer 2 by two depositions, and the second silicon nitride layers 8 fill the grooves 7; Figure 4 As shown in Figure d, a shallow trench isolation (STI) process is used to deposit oxide in the trench of the fin structure to form an oxide layer 9; Figure 4 As shown in Figure e, the oxide layer 9 is thinned to reduce the thickness of the oxide layer 9; Figure 4 As shown in the middle figure f, polysilicon is deposited on the fin structure and the oxide layer 9 to form a polysilicon layer 10, thereby obtaining a GAA; it can be seen that there is still a groove 7 on the side wall of the sacrificial layer 22 of the GAA.

[0030] In order to solve the electrical performance problems of semiconductor structures such as short circuit caused by the recess of the sidewalls of the FIN sacrificial layer, the present invention provides a method for forming a semiconductor structure.

[0031] like Figure 5 As shown, an embodiment of the present invention provides a method for forming a semiconductor structure, such as Figure 6-10 As shown, Figure 6-10 A schematic cross-sectional view of a semiconductor structure forming process provided by an embodiment of the present invention includes:

[0032] S501: providing a substrate 1; the substrate 1 having a channel stack material layer 2 thereon, the channel stack material layer 2 including a sacrificial layer 22 and a channel layer 21 located on the sacrificial layer;

[0033] In an exemplary embodiment, the method further comprises:

[0034] forming a channel stack material layer 2 on the substrate 1;

[0035] A silicon oxide layer 3 , a first silicon nitride layer 4 and a photoresist layer 5 are sequentially formed on a portion of the channel stack material layer; the silicon oxide layer 3 , the first silicon nitride layer 4 and the photoresist layer 5 constitute the mask layer 6 .

[0036] In an embodiment of the present specification, the channel stack material layer 2 includes a channel layer 21 and a sacrificial layer 22. The material of the channel layer 21 can be an epitaxial material suitable for forming a channel region of, for example, an n-type FET, such as silicon; the material of the sacrificial layer 22 can be an epitaxial material suitable for forming a channel region of, for example, a p-type FET, such as silicon germanium (SixGe1-x, where x can be in the range of 0 to 1); the thickness of the channel layer 21 and the thickness of the sacrificial layer 22 can be the same or different; a plurality of channel stack material layers 2 can be formed in sequence on the substrate 1; illustratively, the number of the plurality of channel stack material layers 2 can be three; the channel stack material layer 2 can include an etched area and a non-etched area, wherein the non-etched area can include a plurality of equally spaced sub-areas, and a mask layer 6 can be formed on each sub-area respectively, thereby obtaining a plurality of mask layers 6; the plurality of mask layers 6 can be equally spaced on the non-etched area, and the material composition and thickness of each mask layer 6 are the same. Each mask layer 6 may include a silicon oxide layer 3, a first silicon nitride layer 4 and a photoresist layer 5; wherein the silicon oxide layer 3 and the first silicon nitride layer 4 are both rectangular, and the top of the photoresist layer 5 is arc-shaped; illustratively, the thickness of the silicon oxide layer 3 is less than the thickness of the first silicon nitride layer 4, and the thickness of the first silicon nitride layer 4 is greater than the thickness of the photoresist layer 5.

[0037] In the embodiments of this specification, photoresist, also known as photoresist, refers to a thin film of etching-resistant material whose solubility changes upon exposure to ultraviolet light, electron beams, ion beams, X-rays, or other radiation. It is currently widely used in the fabrication of fine-patterned circuits in the optoelectronic information industry. Photoresist is composed of a sensitizer (photoinitiator), a photosensitive resin (polymerizing agent), a solvent, and additives.

[0038] 1) Sensitizer (photoinitiator): It is a key component of photoresist and plays a decisive role in the sensitivity and resolution of photoresist.

[0039] 2) Photosensitive resin (polymerizer): used to polymerize different materials in the photoresist to form the skeleton of the photoresist, and determine the basic properties of the photoresist such as hardness, flexibility, and adhesion.

[0040] 3) Solvent: It is the largest component in photoresist. Its purpose is to keep the photoresist in liquid state, but the solvent itself has almost no effect on the chemical properties of the photoresist.

[0041] 4) Additives: Usually proprietary compounds, mainly used to change the specific chemical properties of photoresist.

[0042] In the embodiment of this specification, the channel stack material layer 2 may be formed on the substrate 1 first, and then a mask layer 6 may be formed on a portion of the channel stack material layer 2 to facilitate selective etching of the portion of the channel stack material layer 2 .

[0043] S502: etching a portion of the channel stack material layer until the substrate is exposed, thereby forming a fin structure on the substrate; a groove 7 is formed on a sidewall of the fin structure;

[0044] In the embodiments of the present specification, part of the channel stack material layer 2 can be etched until the substrate 1 is exposed. After the mask layer 6 is formed, part of the channel stack material layer 2 is the area corresponding to the non-mask layer 6; a fin structure is formed on the substrate; that is, the area outside the mask layer 6 on the channel stack material layer 2 is etched; during the etching process, grooves 7 are easily formed on the side walls of the fin structure; illustratively, the grooves 7 are mainly distributed on the side walls of the sacrificial layer 22 in the fin structure.

[0045] S503: forming a crystalline silicon layer 11 on the fin structure, wherein the crystalline silicon layer 11 is used to fill the groove 7 in the fin structure;

[0046] In the embodiment of this specification, a crystalline silicon layer 11 can be formed on the outer surface of the fin structure. The material of the crystalline silicon layer 11 can be single crystal silicon or polycrystalline silicon; the crystalline silicon layer 11 completely covers the outer surface of the fin structure, so that the groove 7 in the fin structure can be filled with single crystal silicon.

[0047] In an exemplary embodiment, forming a crystalline silicon layer 11 on the fin structure includes:

[0048] Depositing a first silicon layer on the outer surface of the fin structure using an epitaxial process;

[0049] depositing a second silicon layer on the first silicon layer using a furnace tube process;

[0050] The first silicon layer and the second silicon layer constitute the crystalline silicon layer 11 ; and the amount of silicon deposited in the groove 7 region of the sidewall of the fin structure is greater than the amount of silicon deposited in the non-groove 7 region of the sidewall.

[0051] In the embodiments of this specification, the epitaxy (EPI) process refers to growing a layer of single crystal material with the same lattice arrangement as the substrate on a single crystal substrate. The epitaxial layer can be a homoepitaxial layer (Si / Si) or a heteroepitaxial layer (SiGe / Si or SiC / Si, etc.). There are also many methods for achieving epitaxial growth, including molecular beam epitaxy (MBE), ultra-high vacuum chemical vapor deposition (UHV / CVD), atmospheric pressure and reduced pressure epitaxy (ATMRPEpi), etc. The epitaxy process can deposit a first silicon layer on the outer surface of the fin structure; then, a second silicon layer is deposited on the first silicon layer through a furnace tube process (FUR). The thickness of the first and second silicon layers can be controlled according to actual needs. The furnace tubes used in the IC (Integrated Circuit) industry are currently mainly vertical (horizontal types are rarely used), and are divided into atmospheric pressure furnace tubes and low-pressure furnace tubes according to the operating pressure. Atmospheric-pressure furnace tubes are primarily used for thermal oxidation processes, thermal annealing, BPSG (boron phospho-silicate glass) reflow, thermal baking, and alloying. Low-pressure furnace tubes are primarily used for LPCVD (Low Pressure CVD) processes, including the formation of polysilicon, silicon nitride, HTO, and TEOS; both HTO and TEOS are used to generate silicon dioxide. The first and second silicon layers formed constitute the crystalline silicon layer 11, and the amount of silicon deposited in the recessed 7 area of ​​the sacrificial layer sidewalls of the fin structure is greater than the amount of silicon deposited in the non-recessed 7 area of ​​the sacrificial layer sidewalls.

[0052] In the embodiments of this specification, an epitaxial process can be used to deposit a first silicon layer on the outer surface of the fin structure; the material of the first silicon layer can be single crystal silicon; and then a second silicon layer is deposited on the first silicon layer using a furnace tube process; the first silicon layer and the second silicon layer constitute the crystalline silicon layer 11, thereby improving the stability of the crystalline silicon layer 11 and making the surface of the crystalline silicon layer 11 smoother, and ensuring that the groove 7 area on the side wall of the sacrificial layer 22 is completely filled with single crystal silicon. While filling the groove 7 on the side wall of the sacrificial layer 22, it can also ensure that the filled sacrificial layer 22 is flush with the side wall of the channel layer 21, thereby achieving side wall flattening.

[0053] In an exemplary embodiment, the epitaxial process is performed at a temperature of 600-1000 degrees Celsius, a pressure of 5-20 Torr, and a gas flow rate of 10-40 slm.

[0054] In the embodiments of this specification, the temperature of the epitaxial process used for the first silicon layer can be 600-1000 degrees, the pressure is 5-20 torr, and the gas flow rate is 10-40 slm (standard litre per minute); slm refers to a flow rate of 1 L / min under standard conditions.

[0055] In an exemplary embodiment, when the depth of the sidewall recess 7 of the sacrificial layer of the fin structure is 10±2 angstroms, the ratio of the sidewall silicon deposition amount of the sacrificial layer to the sidewall silicon deposition amount of the channel layer in the first silicon layer is 2:1.

[0056] In an embodiment of the present specification, when the depth of the sidewall groove 7 of the sacrificial layer of the fin structure is 10±2 angstroms, the temperature of the epitaxial process can be controlled to be 600-1000 degrees, the pressure to be 5-20 Torr, and the gas flow rate to be 10-40slm; wherein the depth of the sidewall groove 7 of the sacrificial layer of the fin structure refers to the depth of the single-sided groove 7 in the cross-sectional view; illustratively, the depth of the sidewall groove 7 of the sacrificial layer of the fin structure can be 10 angstroms; at this time, the ratio of the sidewall silicon deposition amount of the sacrificial layer in the first silicon layer to the sidewall silicon deposition amount of the channel layer corresponds to 2:1; thereby, the groove 7 on the sidewall of the sacrificial layer can be completely filled.

[0057] In the embodiments of this specification, the filling depth of the groove 7 on the single side wall can be controlled by using parameters such as temperature, pressure, and gas flow of the epitaxial process; thereby achieving complete filling of the groove 7 and improving the filling effect of the groove 7.

[0058] In an embodiment of the present specification, the sidewall silicon deposition amount of the sacrificial layer in the first silicon layer is 20±5 angstroms, the sidewall silicon deposition amount of the channel layer is 10±5 angstroms, the silicon deposition amount on the mask layer 6 in the first silicon layer is less than a preset deposition amount threshold, and the mask layer is located in a non-etched area on the channel stack material layer.

[0059] In the embodiment of this specification, the amount of silicon deposited on the sidewall of the sacrificial layer 22 in the first silicon layer can be controlled to be 20±5 angstroms by the epitaxial process. The sidewall deposition amount refers to the deposition amount on a single sidewall. Since there is a groove 7 on the sidewall of the sacrificial layer 22 in the first silicon layer, and since there is no groove 7 on the sidewall of the channel layer 21 in the first silicon layer, the deposition amount on the sidewall of the sacrificial layer 22 can be controlled to be greater than the deposition amount on the sidewall of the channel layer 21. Exemplarily, the silicon deposition amount on the sidewall of the sacrificial layer 22 in the first silicon layer is 20±5 angstroms, and the silicon deposition amount on the sidewall of the channel layer 21 is 10±5 angstroms. Preferably, the silicon deposition amount on the sidewall of the sacrificial layer in the first silicon layer can be set to 20 angstroms, and the silicon deposition amount on the sidewall of the channel layer can be set to 10 angstroms. The silicon deposition amount on the mask layer 6 in the first silicon layer is less than a preset deposition amount threshold. The preset deposition amount threshold can be set according to actual conditions, for example, the preset deposition amount threshold can be set to be close to 0. Exemplarily, since the groove 7 is not on the mask layer 6, the silicon deposition amount on the mask layer 6 in the first silicon layer can be set to be close to 0. In an exemplary embodiment, the material of the first silicon layer may include at least one of single crystal silicon, silicon oxide doped with a trace amount of nitrogen, and silicon oxide doped with an excess amount of nitrogen.

[0060] In an embodiment of the present specification, when the depth of the sidewall groove 7 of the sacrificial layer of the fin structure is 10±2 angstroms, the ratio of the sidewall silicon deposition amount of the sacrificial layer in the first silicon layer to the sidewall silicon deposition amount of the channel layer can be controlled to be 2:1, thereby ensuring that the groove 7 in the sidewall of the sacrificial layer is completely filled.

[0061] In an exemplary embodiment, the temperature of the furnace process is lower than 750°, the thickness of the second silicon layer is within a preset thickness range, and the thickness of the second silicon layer is in direct proportional linear relationship with the time of the furnace process.

[0062] In the embodiments of this specification, the temperature of the furnace tube process can be set lower than 750°, and the temperature of the furnace tube process can also be set higher than a preset temperature threshold; illustratively, the preset temperature threshold can be less than 500°, so as to ensure that the thickness of the second silicon layer is within a preset thickness range, and the thickness of the second silicon layer is in a directly proportional linear relationship with the time of the furnace tube process; the longer the furnace tube process time, the thicker the second silicon layer; in an exemplary embodiment, when the furnace tube process time is 2h (hours), the thickness of the second silicon layer is 10 angstroms; when the thickness of the second silicon layer needs to be increased, the furnace tube process time can be extended.

[0063] In the embodiment of this specification, the thickness of the second silicon layer is in direct proportional linear relationship with the time of the furnace tube process. Therefore, the thickness of the second silicon layer can be controlled by setting the temperature of the furnace tube process, thereby achieving flexible control of the thickness of the second silicon layer.

[0064] In an exemplary embodiment, the material of the second silicon layer includes at least one of the following:

[0065] Single crystal silicon, silicon oxide doped with trace nitrogen, silicon oxide doped with excess nitrogen.

[0066] In the embodiments of this specification, the material of the second silicon layer formed by the furnace tube process may include at least one of single crystal silicon, silicon oxide doped with trace nitrogen, and silicon oxide doped with excess nitrogen. The silicon oxide doped with trace nitrogen or doped with excess nitrogen can be determined based on actual conditions; preferably, the material of the second silicon layer may be single crystal silicon material.

[0067] In the embodiments of this specification, the material of the second silicon layer can be set according to actual conditions. Single crystal silicon, silicon oxide doped with trace nitrogen, or silicon oxide doped with excess nitrogen can be used as the material of the second silicon layer; single crystal silicon, silicon oxide doped with trace nitrogen, and silicon oxide doped with excess nitrogen can also be combined to form the second silicon layer, thereby increasing the diversity of material selection for the second silicon layer.

[0068] S504: performing a planarization process on the crystalline silicon layer 11 to obtain a fin structure with smooth sidewalls.

[0069] In an exemplary embodiment, when the thickness of the second silicon layer is less than 10 angstroms, the planarizing process is performed on the crystalline silicon layer 11 to obtain a fin structure with a flat sidewall, including:

[0070] The crystalline silicon layer 11 is etched using a silicon trimming process to remove the single crystal silicon on the mask layer 6 , and the thickness of the crystalline silicon layer 11 on the sidewall of the fin structure is controlled to be less than 10 angstroms.

[0071] In the embodiment of this specification, when the thickness of the second silicon layer is less than 10 angstroms, a silicon trimming (Sitrim) process can be used to etch the crystalline silicon layer 11 to remove the single crystal silicon on the mask layer 6 and control the thickness of the crystalline silicon layer 11 on the sidewall of the fin structure to be less than 10 angstroms, thereby ensuring that the groove 7 is filled while preventing the crystalline silicon layer 11 from being too thick; the silicon trimming process may include but is not limited to a wet treatment process (WET), an ion surface treatment process (Redical surface treatment, RST), etc.

[0072] In the embodiment of the present specification, after the crystalline silicon layer 11 is formed, the crystalline silicon layer 11 can be etched using a silicon trimming process to remove the single crystal silicon on the mask layer 6, and the thickness of the crystalline silicon layer 11 on the side wall of the fin structure is controlled to be less than 10 angstroms, thereby ensuring that the groove 7 is filled while ensuring that the side wall of the fin structure is flat, thereby improving the electrical performance of the semiconductor structure.

[0073] In an exemplary embodiment, the etching process of the crystalline silicon layer 11 using a silicon trimming process includes:

[0074] The crystalline silicon layer 11 is etched by a wet treatment process. The chemical solution of the wet treatment process is the same as the chemical solution used in the formation of the channel stack material layer 2. The reaction temperature of the wet treatment process is 25-100°.

[0075] In the embodiments of this specification, the WET process may use the same chemical solution used to form the channel stack material layer 2 , and the chemical solution may include but is not limited to SE103 or E2504.

[0076] In the embodiment of this specification, the WET process can effectively remove the crystalline silicon layer 11 on the mask layer 6, avoid residual crystalline silicon material on the mask layer 6, and thin the crystalline silicon layer 11, while making the sidewalls of the fin structure more flat and smooth.

[0077] In an exemplary embodiment, the etching process of the crystalline silicon layer 11 using a silicon trimming process includes:

[0078] The crystalline silicon layer 11 is etched using an ion surface treatment process, with a reaction temperature of less than 100° and a reaction pressure of less than 1000 Torr.

[0079] In an exemplary embodiment, the etching gas used in the ion surface treatment process is at least one of NF3, CF4, CHF3, and H2.

[0080] In the embodiments of this specification, a silicon trimming process of ion surface treatment can be used to etch the crystalline silicon layer 11, and the reaction pressure, reaction temperature, etching gas, etc. can be set according to actual conditions; for example, the reaction temperature can be set to less than 100° and the reaction pressure can be less than 1000 Torr; the reaction temperature can also be set to 40-60° and the reaction pressure can be 100-800 Torr; the etching gas can be at least one of NF3, CF4, CHF3, and H2.

[0081] In the embodiments of this specification, a silicon trimming process using ion surface treatment can be used to etch the crystalline silicon layer 11, which can effectively remove the crystalline silicon layer 11 on the mask layer 6; avoid residual crystalline silicon material on the mask layer 6; and thin the crystalline silicon layer 11, while making the side walls of the fin structure more flat and smooth.

[0082] In some embodiments, the crystalline silicon layer 11 may be etched first by a wet treatment process, and then etched by an ion surface treatment process, so as to ensure the flatness of the sidewalls of the fin structure.

[0083] In an embodiment of the present specification, when the thickness of the second silicon layer is less than 10 angstroms, a silicon trimming process can be used to etch the crystalline silicon layer 11 to remove the single crystal silicon on the mask layer 6 and control the thickness of the crystalline silicon layer 11 on the side wall of the fin structure to be less than 10 angstroms; the silicon trimming process may include but is not limited to a wet treatment process and an ion surface treatment process.

[0084] In some embodiments, after etching the crystalline silicon layer 11 using a silicon trimming process to obtain a residual crystalline silicon layer 11, the method further includes:

[0085] forming a second silicon nitride layer 8 on the residual crystalline silicon layer 11;

[0086] Cutting the fin structure using a fin structure cutting process;

[0087] A shallow trench isolation process is used to deposit an oxide layer 9 on the cut fin structure, and then the oxide layer 9 is etched to control the thickness of the oxide layer 9 to a preset thickness;

[0088] A polysilicon layer 10 is formed on the oxide layer 9 .

[0089] In the embodiments of this specification, the shallow trench isolation (STI) process refers to the use of oxide to fill the trench and embed a thick oxide between the active areas of the device to form isolation between the devices. The STI isolation process can improve the parasitic field effect transistor and latch-up effect. Two second silicon nitride layers 8 can be formed on the residual crystalline silicon layer 11; Figure 10 As shown, Figure 10 Figure a in the middle is a cross-sectional view of a semiconductor structure obtained according to the silicon trimming process; Figure 10 Figure b is a cross-sectional view of a semiconductor structure formed after forming a second silicon nitride layer 8 on the residual crystalline silicon layer 11 and cutting the fin structure using a fin structure cutting process; Figure 10 Figure c is a cross-sectional view of the semiconductor structure obtained after the polysilicon layer 10 is formed.

[0090] In an exemplary embodiment, when the thickness of the second silicon layer is 20-60 angstroms, the planarization treatment of the crystalline silicon layer 11 to obtain a fin structure with smooth sidewalls includes:

[0091] The fin structure is cut by a fin structure cutting process, and the thickness of the crystalline silicon layer 11 is controlled by adjusting the reaction time to obtain a remaining silicon layer; the reaction liquid includes at least one of ozone, hydrofluoric acid, SC1, and SCN;

[0092] The remaining silicon layer is etched using a fluid chemical vapor deposition process to obtain a fin structure with smooth sidewalls; the thickness of the crystalline silicon layer 11 removed by etching is 10-50 angstroms.

[0093] In an embodiment of the present specification, when the thickness of the second silicon layer is 20-60 angstroms, the thickness of the crystalline silicon layer 11 can be adjusted in a subsequent processing flow by controlling the reaction time, reaction solution, etc.; exemplarily, during the fin structure cutting process, the remaining thickness of the crystalline silicon layer 11 can be controlled by the reaction time of the fin structure cutting process (ARV), and in a subsequent fluid chemical vapor deposition process, the etching depth of the remaining silicon layer can be adjusted by controlling the reaction temperature, thereby etching the remaining silicon layer to obtain a fin structure with smooth side walls; the thickness of the crystalline silicon layer 11 etched and removed is 10-50 angstroms; exemplarily, when the reaction temperature is reduced by 50°, the thickness of the crystalline silicon layer 11 etched and removed is 5 angstroms.

[0094] In the embodiments of this specification, when the thickness of the second silicon layer is 20-60 angstroms, there is no need to form two silicon nitride (SiN) layers on the fin structure, and the crystalline silicon layer 11 can be consumed by controlling process parameters in process flows such as the fin structure cutting process and the fluid chemical vapor deposition process, thereby simplifying the process steps in the semiconductor structure formation process and improving the production efficiency of the semiconductor structure.

[0095] In the embodiment of this specification, a suitable process can be selected to planarize the crystalline silicon layer 11 according to the thickness of the second silicon layer, thereby ensuring that the sidewalls of the fin structure have no grooves 7 and the sidewall surfaces are flat and smooth.

[0096] In an exemplary embodiment, when the temperature of the fluid chemical vapor deposition process is reduced from 800° C. to 750° C., the thickness of the crystalline silicon layer 11 that is etched and removed is 5 angstroms.

[0097] In the embodiments of this specification, the temperature of the fluid chemical vapor deposition process can be controlled to adjust the thinning thickness of the crystalline silicon layer 11 to meet the process requirements in different application scenarios, thereby achieving flexible adjustment of the thickness of the remaining crystalline silicon layer 11.

[0098] In an exemplary embodiment, after etching the remaining silicon layer using a fluid chemical vapor deposition process to obtain a fin structure with smooth sidewalls, the method further includes:

[0099] A shallow trench isolation process is used to deposit an oxide layer 9 on the cut fin structure, and then the oxide layer 9 is etched to control the thickness of the oxide layer 9 to a preset thickness;

[0100] A polysilicon layer 10 is formed on the oxide layer 9 .

[0101] In an exemplary embodiment, when the thickness of the second silicon layer is 20-60 angstroms, Figure 10 As shown, Figure 10 Figure a in the middle is a cross-sectional view of a fin structure with a smooth sidewall obtained by cutting the fin structure using a fin structure cutting process and etching the remaining silicon layer using a fluid chemical vapor deposition process. Figure 10 Figure b is a cross-sectional view of a fin structure after cutting and depositing an oxide layer 9 using a shallow trench isolation process; Figure 10 Figure c is a cross-sectional view of forming a polysilicon layer 10 on the oxide layer 9.

[0102] The semiconductor structure of this embodiment can be applied to electronic devices, which can be any electronic product or device with photoelectric sensing functions, such as mobile phones, tablet computers, laptops, navigators, cameras, video cameras, sweeping robots, virtual reality devices, augmented reality devices, etc., or any intermediate product that includes the aforementioned semiconductor structure.

[0103] An embodiment of the present specification provides a method for forming a semiconductor structure, comprising providing a substrate; a channel stack material layer is provided on the substrate, the channel stack material layer includes a sacrificial layer and a channel layer located on the sacrificial layer; a portion of the channel stack material layer is etched until the substrate is exposed, thereby forming a fin structure on the substrate; a groove is provided on the sidewall of the fin structure; a crystalline silicon layer is formed on the fin structure, the crystalline silicon layer is used to fill the groove in the fin structure, thereby avoiding the formation of a recessed area on the sidewall of the semiconductor structure; and the crystalline silicon layer is then flattened to obtain a fin structure with flat sidewalls, thereby ensuring that the semiconductor structure has good electrical properties.

[0104] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered merely as exemplary, and the true scope and spirit of the present application are indicated by the claims.

[0105] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: The method comprises: Providing a substrate; the substrate having a channel stack material layer, the channel stack material layer including a sacrificial layer and a channel layer located on the sacrificial layer; Etching a portion of the channel stack material layer until the substrate is exposed, thereby forming a fin structure on the substrate; a groove is formed on a sidewall of the fin structure; forming a crystalline silicon layer on the fin structure, wherein the crystalline silicon layer is used to fill the groove in the fin structure; The crystalline silicon layer is planarized to obtain a fin structure with smooth sidewalls.

2. The method according to claim 1, characterized in that The forming of a crystalline silicon layer on the fin structure includes: Depositing a first silicon layer on the outer surface of the fin structure using an epitaxial process; depositing a second silicon layer on the first silicon layer using a furnace tube process; The first silicon layer and the second silicon layer constitute the crystalline silicon layer; and the amount of silicon deposited in the recessed region of the sidewall of the fin structure is greater than the amount of silicon deposited in the non-recessed region of the sidewall.

3. The method according to claim 2, characterized in that The temperature of the epitaxial process is 600-1000 degrees, the pressure is 5-20 Torr, and the gas flow rate is 10-40 slm.

4. The method according to claim 2, characterized in that When the sidewall groove depth of the sacrificial layer of the fin structure is 10±2 angstroms, the ratio of the sidewall silicon deposition amount of the sacrificial layer to the sidewall silicon deposition amount of the channel layer in the first silicon layer is 2:

1.

5. The method according to claim 4, characterized in that The amount of silicon deposition on the sidewalls of the sacrificial layer in the first silicon layer is 20±5 angstroms, the amount of silicon deposition on the sidewalls of the channel layer is 10±5 angstroms, the amount of silicon deposition on the mask layer in the first silicon layer is less than a preset deposition amount threshold, and the mask layer is located in a non-etched area on the channel stack material layer.

6. The method according to claim 2, characterized in that The temperature of the furnace tube process is lower than 750°, the thickness of the second silicon layer is within a preset thickness range, and the thickness of the second silicon layer is in a proportional linear relationship with the time of the furnace tube process.

7. The method according to claim 6, characterized in that When the furnace process time is 2 hours, the thickness of the second silicon layer is 10 angstroms.

8. The method according to claim 2, characterized in that The material of the second silicon layer includes at least one of the following: Single crystal silicon, silicon oxide doped with trace nitrogen, silicon oxide doped with excess nitrogen.

9. The method according to claim 5, characterized in that When the thickness of the second silicon layer is less than 10 angstroms, the planarizing process is performed on the crystalline silicon layer to obtain a fin structure with a flat sidewall, comprising: The crystalline silicon layer is etched using a silicon trimming process to remove the single crystal silicon on the mask layer, and the thickness of the crystalline silicon layer on the sidewall of the fin structure is controlled to be less than 10 angstroms.

10. The method according to claim 9, characterized in that The etching process of the crystalline silicon layer using the silicon trimming process includes: The crystalline silicon layer is etched by a wet treatment process. The chemical solution of the wet treatment process is the same as the chemical solution used in the formation process of the channel stack material layer. The reaction temperature of the wet treatment process is 25-100°.

11. The method according to claim 9, characterized in that The etching process of the crystalline silicon layer using the silicon trimming process includes: The crystalline silicon layer is etched using an ion surface treatment process, with a reaction temperature of less than 100° and a reaction pressure of less than 1000 Torr.

12. The method according to claim 11, characterized in that The etching gas used in the ion surface treatment process is at least one of NF3, CF4, CHF3, and H2.

13. The method according to claim 2, characterized in that When the thickness of the second silicon layer is 20-60 angstroms, the planarizing process is performed on the crystalline silicon layer to obtain a fin structure with a flat sidewall, including: The fin structure is cut by a fin structure cutting process, and the thickness of the crystalline silicon layer is controlled by adjusting the reaction time to obtain a remaining silicon layer; the reaction liquid includes at least one of ozone, hydrofluoric acid, SC1, and SCN; The remaining silicon layer is etched using a fluid chemical vapor deposition process to obtain a fin structure with smooth sidewalls; the thickness of the crystalline silicon layer removed by etching is 10-50 angstroms.

14. The method according to claim 13, characterized in that When the temperature of the fluid chemical vapor deposition process is reduced from 800° C. to 750° C., the thickness of the crystalline silicon layer removed by etching is 5 angstroms.

15. The method according to claim 5, characterized in that After providing the substrate, the method further comprises: forming the channel stack material layer on the substrate; A silicon oxide layer, a first silicon nitride layer and a photoresist layer are sequentially formed on a partial area of ​​the channel stack material layer; the silicon oxide layer, the first silicon nitride layer and the photoresist layer constitute the mask layer.

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