Sensing, storing and computing integrated memory based on ion transmission as well as preparation method and application of sensing, storing and computing integrated memory

Abstract

The invention provides a sensing, storage and calculation integrated memory based on ion transmission and a preparation method and application thereof, and relates to the technical field of semiconductor devices. The sensing, storage and calculation integrated memory provided by the invention comprises a substrate, a bottom electrode, an ion transmission layer and a top electrode which are stacked, and the material of the ion transmission layer comprises perovskite quantum dots. According to the invention, through intrinsic characteristics of materials, functions of sensing external temperature information, memory storage and operation of the device are realized. The implementation method is simple, the implementation cost is low, the storage and detection performance of the device is improved, and the application scene of the halogen perovskite resistive random access memory is effectively expanded. And the working voltage of the device is low, so that energy conservation and consumption reduction are realized to a certain extent, stable operation of the device is realized, the service life of the device is prolonged, and the reliability of operating the whole system by the device is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and specifically relates to a sensing, storage and computing integrated memory based on ion transmission, and a preparation method and application thereof. Background Art

[0002] With the rapid development of artificial intelligence and the Internet of Things, the ever-increasing amount of data has made the constraints of memory on high-performance processors increasingly prominent. Traditional storage systems face more severe tests in information collection, computing and storage.

[0003] Currently, the traditional von Neumann computing architecture is composed of independent storage and computing units. The separation of information storage and computing units generates a large amount of power consumption. Frequent data exchanges and mismatched processing speeds result in additional power consumption and reduced data processing efficiency during data transmission. In the field of temperature sensing technology, the thermal resistance switching ratio of traditional thermistors (such as NTC / PTC) is usually less than 10, the temperature response sensitivity is low, and existing temperature sensors need to be set separately from the storage unit, resulting in increased system complexity and power consumption. Although resistive random access memory based on oxygen vacancy migration (such as HfO2-based RRAM) has storage function, it is not sensitive to temperature changes (ΔR / R <5% / °C) and cannot meet the needs of high-precision temperature detection. In addition, traditional temperature sensing memory requires continuous power supply to maintain working state, and the discrete design makes it difficult to achieve real-time perception and processing of information, which makes it face greater challenges in passive device application scenarios. Although recent studies have attempted to improve device performance through material modification (such as doping) or structural optimization (such as interface engineering), these methods can often only improve storage or sensing performance alone, and cannot simultaneously achieve the multifunctional integration of high-sensitivity temperature sensing, non-volatile storage, and in-memory computing.

[0004] Therefore, it is urgent to provide a solution to improve the above problems. Summary of the Invention

[0005] The purpose of the present invention is to provide a sensing, storage and computing integrated memory based on ion transmission, and its preparation method and application.

[0006] In the first aspect, the present invention provides a sensing-storage-computing integrated memory based on ion transport, comprising a stacked substrate 4, a bottom electrode 3, an ion transport layer 2 and a top electrode 1, and the material of the ion transport layer 2 comprises perovskite quantum dots.

[0007] Optionally, the materials of the bottom electrode and the top electrode independently include one of a metal material and a conductive oxide.

[0008] Optionally, the metal material includes one of Au, Ag, Cu, Al, Pt, Co, Ni, Ti, and W.

[0009] Optionally, the conductive oxide includes one of indium tin oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide or indium gallium zinc oxide.

[0010] Optionally, the perovskite quantum dot material structure is ABX3, wherein the A-site metal cation includes Cs + 、MA + , FA + One of the metal cations in the B position includes Pb 2+ 、Sn 2+ 、Mn 2+ 、Cu 2+ One of the X-position anions includes Br - 、Cl - , I - One of them.

[0011] In the second aspect, the present invention provides a method for preparing a sensing, storage and computing integrated memory based on ion transport, including forming a bottom electrode on a substrate to make a substrate and then pre-treating it; preparing a perovskite quantum dot solution and spin-coating it on the substrate to form an ion transport layer; and evaporating a top electrode on the ion transport layer.

[0012] Optionally, the pretreatment includes ultrasonic cleaning, soaking, drying and re-cleaning the substrate.

[0013] Optionally, the ultrasonic cleaning solvent includes ionized water, ethanol and acetone.

[0014] Optionally, the soaking solvent includes an isopropyl alcohol solution.

[0015] Optionally, the drying comprises drying under a nitrogen environment.

[0016] Optionally, the re-cleaning includes plasma cleaning.

[0017] Optionally, the spin coating speed is 2000 r / min-4000 r / min.

[0018] Optionally, the spin coating time is 20s-40s.

[0019] In a third aspect, the present invention also provides an application of a sensing, storage and computing integrated memory produced by any of the above optional production methods.

[0020] Optionally, the sensing, storage and computing integrated memory is used for temperature information perception.

[0021] Optionally, the sensing, storage and computing integrated memory is applied to non-volatile storage.

[0022] Optionally, the sensing, storage and computing integrated memory is used in logical operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a structural diagram of a sensor-storage-computing integrated memory; explanation of the accompanying symbols: 4, substrate; 3, bottom electrode; 2, ion transport layer; 1, top electrode.

[0024] Figure 2 The IV semi-logarithmic curves of the device before heating at 50°C, after heating and cooling to room temperature, and after large bias erasure;

[0025] Figure 3 The IV linearity curves of the device before heating at 50°C, after heating and cooling to room temperature, and after large bias erasure;

[0026] Figure 4 Schematic diagram of the low-resistance and high-resistance currents and the corresponding on-off ratios of the device before and after annealing at 50°C;

[0027] Figure 5 Schematic diagram of the data results of the device being written into the high-resistance state at 50°C and erased into the low-resistance state at 5V bias at room temperature and a read voltage of 0.05V;

[0028] Figure 6 The IV semi-logarithmic curve of the Au-CsPbBr3 QDs-ITO device during the transition from high resistance state to low resistance state;

[0029] Figure 7 The IV linear curve of the Au-CsPbBr3 QDs-ITO device during the transition from high resistance state to low resistance state;

[0030] Figure 8 Schematic diagram of the low-resistance and high-resistance currents and the corresponding on-off ratios of the device before and after annealing at different temperatures;

[0031] Figure 9 Output resistance histogram of the Au-CsPbBr3 QDs-ITO device as an OR logic gate.

[0032] The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be the common meanings understood by people with ordinary skills in the field to which the present invention belongs.

[0034] The present invention provides a sensing, storage and computing integrated memory based on ion transport, comprising a stacked substrate 4, a bottom electrode 3, an ion transport layer 2 and a top electrode 1, wherein the material of the ion transport layer 2 comprises perovskite quantum dots.

[0035] In some embodiments, the material of the substrate includes a highly doped silicon wafer, a glass wafer or a flexible polymer such as polyethylene terephthalate (PET), polydimethylsiloxane (PDMS), polyvinyl alcohol (PVA), polyvinylidene fluoride (PVDF), poly(3,4-ethylenedioxythiophene) (PEDOT), polyimide (PI), polystyrene sulfonate (PSS) and the like; the materials of the bottom electrode and the top electrode independently include a metal material, one of a conductive oxide, and one of a conductive oxide; wherein the metal material includes one of Au, Ag, Cu, Al, Pt, Co, Ni, Ti, and W, and the conductive oxide includes one of indium tin oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide, or indium gallium zinc oxide. In practice, the substrate provides mechanical support for the sensor-storage-computing integrated memory, ensuring the integrity of the device structure. Furthermore, flexible substrates can be adapted to applications such as wearable devices. Electrode materials play a crucial role in RRAM. Inert electrodes, such as Au and Pt, serve solely to transport electrons. Active electrodes, such as Ag and Cu, not only transport electrons but, under the influence of an electric field, may oxidize and enter the resistive layer, thereby affecting the resistive switching behavior. By selecting appropriate bottom and top electrode materials, the performance of RRAM can be effectively controlled and the device's resistive switching behavior optimized.

[0036] In some embodiments, the perovskite quantum dot material structure used in the ion transport layer is ABX3; wherein the A-site metal cation includes Cs + 、MA + , FA + One of the metal cations in the B position includes Pb 2+ 、Sn 2+ 、Mn 2+ 、Cu 2+ One of the X-position anions includes Br - 、Cl- , I - In fact, the ion transport layer refers to the functional layer in the integrated sensing, storage and computing storage device that can regulate ion migration and resistance changes. The ion transport layer prepared with perovskite quantum dots can realize the functions of integrating temperature sensing, storage and computing: perovskite quantum dots respond to temperature changes through ion migration, producing a giant thermal resistance effect; due to the sensitivity of perovskite materials to external temperature, after the prepared device is exposed to a relatively high temperature and restored to room temperature, the electrons in the trap are thermally excited and escape, and it is difficult for the electrons to cross the high and wide potential barrier. At this time, the device is in HRS. At the same time, under the action of a large voltage, the electrons at the negative electrode undergo FN tunneling and are injected into the trap, causing the device to convert from HRS to LRS, thereby realizing non-volatile resistance switching and neuromorphic computing functions through the unique electron-ion coupling characteristics of the perovskite material. Therefore, the on and off state of the ion transport layer is synergistically controlled by the external temperature and the load voltage, thereby realizing the functions of temperature information sensing, non-volatile storage and logical operation.

[0037] The present invention also provides a method for preparing a sensing, storage and computing integrated memory based on ion transport, comprising: forming a bottom electrode on a substrate to make a substrate and then pre-treating it; preparing a perovskite quantum dot solution and spin-coating it on the substrate to form an ion transport layer; and evaporating a top electrode on the ion transport layer.

[0038] In some embodiments, pretreatment includes ultrasonic cleaning, soaking, drying, and re-cleaning the substrate. The ultrasonic cleaning solvent includes deionized water, ethanol, and acetone; the soaking solvent includes an isopropyl alcohol solution; drying includes drying under a nitrogen atmosphere; and re-cleaning includes plasma cleaning. Ultrasonic cleaning is intended to remove organic contaminants and particles; post-cleaning isopropyl alcohol soaking displaces residual solvent and improves surface hydrophilicity; nitrogen drying prevents residual water marks; and plasma cleaning activates the surface and enhances the adhesion of the perovskite quantum dot film.

[0039] In some embodiments, the solvent used to prepare the perovskite quantum dot film includes one of n-hexane, toluene, and chlorobenzene. In practice, the solvent used must be able to disperse the quantum dots, prevent agglomeration, and ensure solution uniformity. Specifically, n-hexane is preferably the solvent.

[0040] In some embodiments, the perovskite quantum dot film is spin-coated at a speed of 2000-4000 rpm and / or for a time of 20-40 seconds. Selecting an appropriate spin-coating speed can control film thickness; the spin-coating time is necessary to ensure sufficient solvent evaporation. Specifically, the spin-coating speed is preferably maintained at 3000 rpm and the spin-coating time is preferably 30 seconds.

[0041] The present invention also provides an application of a sensing-storage-computing integrated memory manufactured by the manufacturing method of any of the above embodiments.

[0042] Specifically, the application of a sensing, storage and computing integrated memory based on ion transmission includes application in temperature information perception, application in non-volatile storage and application in logical operations.

[0043] Example 1:

[0044] This embodiment provides a method for preparing a sensing-storage-computing integrated memory using CsPbBr3 quantum dots as the ion transport layer material:

[0045] (1) Preparation of CsPbBr3 quantum dot solution: (a) Synthesis of crude CsPbBr3 quantum dot solution by hot injection method: 40 mg (0.125 mmol) Cs2CO3, 95 mg (0.25 mmol) (CH3COO)2Pb·3H2O, 2 mL oleic acid (OA), 2 mL oleylamine (OAm) and 10 mL octadecene (ODE) were added to a three-necked flask equipped with a magnetic stirrer. Under an inert gas argon atmosphere, the mixed solution was heated to 120°C, vacuum degassed and kept at 120°C for 40 min. After the insulation was completed, the three-necked flask was heated to 170°C. After the temperature stabilized, 0.2 mL of benzoyl bromide (C6H5COBr) solution was quickly injected and reacted for 5 seconds. The flask was immediately placed in ice water to quench the reaction, and finally a crude CsPbBr3 quantum dot solution was obtained. (b) Purification of CsPbBr3 quantum dots: First, 2 mL of the crude quantum dot solution was centrifuged (800 rpm, 1 min). After collecting the supernatant, ethyl acetate was added as an antisolvent in a 1:2 volume ratio, and liquid phase separation was achieved by high-speed centrifugation (6000 rpm, 10 min). This gradient centrifugation process can be repeated to fully remove excess ligand impurities. The precipitate is then redispersed with 2 mL of n-hexane to form a colloidal solution. After standing and stratification, the supernatant was taken and filtered using a 0.22 μm disposable needle filter to obtain the CsPbBr3 quantum dot solution to be spin-coated.

[0046] (2) A conductive ITO substrate was selected as the substrate and etched using dilute hydrochloric acid. The etched ITO substrate was then ultrasonically cleaned in deionized water, ethanol, acetone, and ethanol for 15 minutes, and then immersed in an isopropyl alcohol solution for later use. The cleaned conductive glass was dried in nitrogen and then plasma cleaned to obtain a clean and dry bottom electrode for later use.

[0047] (3) The CsPbBr3 quantum dot solution prepared in step (1) was spin-coated on the ITO substrate obtained in step (2), with the rotation speed maintained at 3000 r / min and the spin-coating time being 30 s. The spin-coated sample was placed on a heating table and annealed at 80°C for 10 min.

[0048] (4) 100 nm of Au was deposited as the top electrode on the quantum dot film layer using vacuum evaporation, thus completing the preparation of the Au-CsPbBr3 QDs-ITO device.

[0049] The above preparation method was repeated ten times to prepare ten Au-CsPbBr3 QDs-ITO device samples.

[0050] The Au-CsPbBr3 QDs-ITO device prepared in Example 1 was tested for resistive memory logic operation function, and the results in Table 1 were obtained:

[0051] Table 1: Au-CsPbBr3 QDs-ITO device logic operation truth table

[0052]

[0053] like Figure 1 As shown, the present invention provides a sensing, storage and computing integrated memory based on ion transport, wherein a bottom electrode 3 is provided on a substrate 4, an ion transport layer 2 is provided on the bottom electrode 3, and a top electrode 1 is provided on the ion transport layer 2.

[0054] The Au-CsPbBr3 QDs-ITO device prepared in Example 1 was tested for its current-voltage characteristics before heating at 50°C, after heating and cooling to room temperature, and after large bias erasure. The test data were processed to obtain an IV semi-logarithmic curve (e.g. Figure 2 As shown) and IV linear curve (as Figure 3 shown).

[0055] from Figure 2 and Figure 3 As can be seen from the thermal storage cycle IV semi-logarithmic curve and IV linear curve of the Au-CsPbBr3 QDs-ITO device at an annealing temperature of 50°C, it can be seen that after the unannealed device is heated to 50°C, annealed at this temperature and cooled to room temperature, the output current drops sharply to a low point, and the resistance switching ratio exceeds 10 5 , showing a giant negative thermal resistance effect. When the device is cooled to room temperature after annealing at 50°C, applying a 5V bias can cause it to change from HRS to LRS, confirming that the thermally induced resistive state information can be reversibly erased by voltage stimulation.

[0056] The resistance stability and on-off ratio of the ten Au-CsPbBr3 QDs-ITO device samples prepared in Example 1 were tested before and after thermal annealing of the resistive memory. Figure 4 The test results shown in Figure .

[0057] from Figure 4It can be seen that the HRS current of all samples is stable at 10 -10 A level, while the LRS current before annealing fluctuates due to process differences. It is particularly noteworthy that device sample 6 shows the best performance, with an on-off ratio of 7.8×10 5 .

[0058] The Au-CsPbBr3 QDs-ITO device prepared in Example 1 was tested for its resistance state retention characteristics based on thermal writing and electrical erasure. Figure 5 The result graph shown.

[0059] from Figure 5 It can be seen that after 1×10 4 s, the current floating of HRS and LRS of the device is small, showing excellent non-volatile storage performance (read at 0.05V).

[0060] The Au-CsPbBr3 QDs-ITO device prepared in Example 1 was tested for the current-voltage characteristics of the resistive memory high / low resistance state switching process, and the test data was processed to obtain an IV semi-logarithmic curve (such as Figure 6 As shown) and IV linear curve (as Figure 7 shown).

[0061] Figure 6 and Figure 7 The transition process of HRS to LRS after annealing is demonstrated, which corresponds to the erase operation of the memory device.

[0062] The resistance stability and on-off ratio of the Au-CsPbBr3 QDs-ITO device prepared in Example 1 were tested before and after annealing of the resistive random access memory at different temperatures. Figure 8 The test results shown in Figure .

[0063] from Figure 8 As can be seen in the figure, after the device was annealed at 40°C and cooled to room temperature, the output current decreased slightly compared to before annealing, but the magnitude was small. After annealing in the temperature range of 50°C-100°C, the unannealed devices all exhibited a significant giant negative thermal resistance switching effect. By comparing the electrical properties of samples annealed at 60°C, 80°C, and 100°C, it was found that their output current dropped by multiple orders of magnitude after annealing and remained at the lowest level. The difference in resistance before and after annealing reached more than 5 orders of magnitude.

[0064] Figure 9 Output resistance histogram of the Au-CsPbBr3 QDs-ITO device as an OR logic gate.

[0065] from Figure 9 As can be seen from Table 1, Figure 9 The corresponding histograms for the results shown in Table 1 are shown. The figure clearly shows the outputs of different logical OR operations: "00," "01," "10," and "11." The "00" state has the highest output resistance and the lowest current, while the "11" state has a lower output resistance and a higher current.

[0066] While the embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations of these embodiments are possible. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the claims. Furthermore, the invention described herein is susceptible to other embodiments and may be practiced or implemented in a variety of ways.

Claims

1. A sensor-storage-computing integrated memory based on ion transmission, characterized in that: The invention comprises a substrate, a bottom electrode, an ion transport layer and a top electrode which are stacked, and the material of the ion transport layer comprises perovskite quantum dots.

2. The sensing, storage and computing integrated memory according to claim 1, characterized in that: The materials of the bottom electrode and the top electrode independently include a metal material, one of a conductive oxide, and one of a conductive oxide; wherein the metal material includes one of Au, Ag, Cu, Al, Pt, Co, Ni, Ti, and W, and the conductive oxide includes one of indium tin oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide, or indium gallium zinc oxide.

3. The sensing, storage and computing integrated memory according to claim 1, characterized in that: The perovskite quantum dot material structure is ABX3; wherein the A-position metal cation includes Cs + 、MA + , FA + One of the metal cations in the B position includes Pb 2+ 、Sn 2+ 、Mn 2 + 、Cu 2+ One of the X-position anions includes Br - 、Cl - , I - One of them.

4. A method for preparing a sensing-storage-computing integrated memory based on ion transmission according to any one of claims 1 to 3, characterized in that: include: After forming a bottom electrode on a substrate to prepare a substrate, pre-processing the substrate; Preparing a perovskite quantum dot solution and spin coating it on the substrate to form an ion transport layer; A top electrode is evaporated on the ion transport layer.

5. The preparation method according to claim 4, characterized in that: The pretreatment includes ultrasonic cleaning, soaking, drying and re-cleaning of the substrate; the solvent for the ultrasonic cleaning includes ionized water, ethanol and acetone; the solvent for the soaking includes an isopropyl alcohol solution; the drying includes drying under a nitrogen environment; and the re-cleaning includes plasma cleaning.

6. The preparation method according to claim 4, characterized in that: The spin coating speed is 2000 r / min-4000 r / min; and / or the spin coating time is 20s-40s.

7. An application of the sensing, storage and computing integrated memory as described in any one of claims 1 to 3 in temperature information perception.

8. An application of the sensing, storage and computing integrated memory as claimed in any one of claims 1 to 3 in non-volatile storage.

9. An application of the sensing, storage and computing integrated memory as claimed in any one of claims 1 to 3 in logical operations.

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