Light detection device and electronic apparatus

Abstract

Provided is a light detection device capable of coping with micronization. This light detection device is provided with: a first semiconductor layer that includes one surface as an element formation surface and the other surface as a light incidence surface, and that includes a plurality of cell regions arranged in a matrix in a row direction and a column direction in a plan view; a trench separation wall that divides the cell regions, and a trench separation wall that separates the cell regions from each other; and an insulating region provided at an end portion of the trench separation wall close to the element forming surface, a size of the insulating region in a width direction being larger than a size of the trench separation wall in the width direction in a plan view, and the insulating region being made of an insulating material, a photoelectric conversion portion is configured in each of the cell regions, and each of the cell regions includes a first semiconductor region provided on a surface of the insulating region on an opposite side from a surface of the trench separation wall side.

Description

Technical Field

[0001] The present technology (technology according to the present disclosure) relates to a light detection device and an electronic device, and particularly to a light detection device and an electronic device that can cope with miniaturization. Background Art

[0002] In recent years, there has been a demand for further miniaturization of pixels. To achieve this, trench isolation can be used as a separation structure for partitioning semiconductor regions (for example, Patent Document 1). Citation list Patent Literature

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2022-55356 Summary of the Invention Technical issues

[0004] Further miniaturization of pixels is not always easily achievable.

[0005] The present technology aims to provide a light detection device and an electronic device that can cope with miniaturization. Technical solutions to technical problems

[0006] According to one aspect of the present technology, a light detection device includes: a first semiconductor layer, the first semiconductor layer includes a surface serving as an element forming surface and another surface serving as a light incident surface, and includes a plurality of unit areas arranged in a matrix in row and column directions in a plan view; a groove separation wall, the groove separation wall divides the unit areas; and an insulating area, the insulating area is arranged at the end of the groove separation wall close to the element forming surface, the size of the insulating area in the width direction in a plan view is larger than the size of the groove separation wall in the width direction, and the insulating area is made of an insulating material, wherein a photoelectric conversion portion is constructed in each of the unit areas, and each of the unit areas includes a first semiconductor region, the first semiconductor region is arranged on the surface of the insulating area on the side opposite to the surface of the groove separation wall side.

[0007] An electronic device according to one aspect of the present technology includes the above-mentioned light detection device and an optical system that forms an image of image light from a subject on the above-mentioned light detection device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 : is a chip layout diagram showing a configuration example of the light detection device according to the first embodiment of the present technology. Figure 2 : is a block diagram showing a configuration example of a light detection device according to a first embodiment of the present technology. Figure 3is an equivalent circuit diagram of a pixel in the light detection device according to the first embodiment of the present technology. Figure 4A is a longitudinal sectional view showing a sectional configuration of a pixel included in the light detection device according to the first embodiment of the present technology. Figure 4B It shows that along Figure 4A The cross-sectional view is formed by the section taken along the cutting line BB in FIG. Figure 4C It shows that along Figure 4A A transverse cross-sectional view of the section taken along the cutting line CC in FIG. Figure 4D It is an explanatory diagram showing the positional relationship of the electrode, the charge accumulation region, the contact region, the first semiconductor region, and the second semiconductor region on the first surface side of the first semiconductor layer according to the first embodiment. Figure 4E It is shown in an enlarged manner Figure 4D A partial enlarged view of a part of . Figure 4F is shown in an enlarged manner along Figure 4D A longitudinal sectional view of a portion is formed by a section taken along a plane of cutting line AA. Figure 4G It shows that along Figure 4D A longitudinal cross-sectional view is formed by a section taken along the cutting line DD in FIG. Figure 4H It is a plan view when the trunk portion according to the first embodiment is viewed in a plan view. Figure 5A 1 and 2 are cross-sectional views showing the steps of the method for manufacturing the light detecting device according to the first embodiment of the present technology. Figure 5B Then Figure 5A Process cross-section diagram. Figure 5C Then Figure 5B Process cross-section diagram. Figure 5D Then Figure 5C Process cross-section diagram. Figure 5E Then Figure 5D Process cross-section diagram. Figure 5F Then Figure 5E Process cross-section diagram. Figure 5G Then Figure 5F Process cross-section diagram. Figure 5H Then Figure 5G Process cross-section diagram. Figure 5I Then Figure 5H Process cross-section diagram. Figure 5J Then Figure 5I Process cross-section diagram. Figure 6 is a longitudinal sectional view showing a sectional configuration of an electrode and a charge accumulation region included in a light detecting device according to a comparative example. Figure 7A It is an explanatory diagram showing the positional relationship of the electrode on the first surface side of the first semiconductor layer, the charge storage region, the first semiconductor region, and the second semiconductor region included in the light detection device according to the first modification example of the first embodiment of the present technology. Figure 7B It shows that along Figure 7A A longitudinal cross-sectional view is formed by a section taken along the cutting line EE in FIG. Figure 8A 1 and 2 are cross-sectional views showing the steps of a method for manufacturing the light detecting device according to the first modification example of the first embodiment of the present technology. Figure 8B Then Figure 8A Process cross-section diagram. Figure 9A It shows Figure 8B This is a plan view of the planar shape of the opening of the resist pattern used in the illustrated steps. Figure 9B It is an explanatory diagram showing a state in which silicon is epitaxially grown only at the corners of the cell region in the photodetection device according to the first modification example of the first embodiment of the present technology. Figure 10 1 is an explanatory diagram showing, in plan view, a gate electrode and electrodes included in the photodetection device 1 according to the second modification example of the first embodiment. Figure 11 1 is an explanatory diagram showing, in plan view, a gate electrode and electrodes included in the photodetection device 1 according to the third modification example of the first embodiment. Figure 12 1 is an explanatory diagram showing, in plan view, a gate electrode and electrodes included in the photodetection device 1 according to the fourth modification example of the first embodiment. Figure 13 1 is an explanatory diagram showing electrodes included in the light detecting device 1 according to the fifth modification example of the first embodiment in a plan view. Figure 14A It is a longitudinal cross-sectional view showing a cross-sectional configuration of electrodes, a charge storage region, and an insulating region taken along a plane crossing a cutting line across a body portion in a light detecting device according to a second embodiment of the present technology. Figure 14B: is an explanatory diagram showing a positional relationship and a dimensional relationship between a charge storage region and electrodes in a plan view in a light detecting device according to a second embodiment of the present technology. Figure 15A 1 and 2 are cross-sectional views showing the steps of a method for manufacturing a light detecting device according to a second embodiment of the present technology. Figure 15B Then Figure 15A Process cross-section diagram. Figure 15C Then Figure 15B Process cross-section diagram. Figure 15D Then Figure 15C Process cross-section diagram. Figure 15E Then Figure 15D Process cross-section diagram. Figure 16 is an explanatory diagram showing a positional relationship, in a plan view, between a gate electrode and a charge accumulation region included in a photodetection device according to a comparative example. Figure 17 : is an explanatory diagram showing a positional relationship, in a plan view, between a gate electrode and a charge accumulation region included in a light detecting device according to a second embodiment of the present technology. Figure 18A It is an explanatory diagram showing the positional relationship, in a plan view, between a gate electrode and a charge accumulation region included in a photodetection device according to a first modification example of the second embodiment of the present technology. Figure 18B It is an explanatory diagram showing the positional relationship, in a plan view, between a gate electrode and a charge accumulation region included in a photodetection device according to a first modification example of the second embodiment of the present technology. Figure 19A 1 and 2 are cross-sectional views showing the steps of a method for manufacturing a light detecting device according to a second modification example of the second embodiment of the present technology. Figure 19B Then Figure 19A Process cross-section diagram. Figure 20A : is a longitudinal sectional view showing a sectional configuration of a phase difference detection section included in a light detection device according to a third embodiment of the present technology. Figure 20B It is an explanatory diagram showing a positional relationship between a first semiconductor region and a first trench separating wall on the first surface side of a phase difference detection section according to a third embodiment of the present technology. Figure 20C It shows that along Figure 20B A longitudinal cross-sectional view of the section taken along the cutting line GG in FIG. Figure 20DIt is an explanatory diagram showing a configuration of four phase difference detection sections arranged in two rows and two columns on the first surface side according to a third embodiment of the present technology. Figure 21 : is a plan view showing a resist pattern used when forming a groove by etching from the first surface S1 side by the method for manufacturing a light detecting device according to the third embodiment of the present technology. Figure 22 The shape and position in a plan view of an insulating region formed by the method for manufacturing a light detecting device according to the third embodiment of the present technology are shown. Figure 23 is a longitudinal cross-sectional view showing a first semiconductor region formed by epitaxial growth by the method for manufacturing a light detecting device according to the third embodiment of the present technology. Figure 24 is a longitudinal sectional view showing a sectional configuration of a pixel included in a light detection device according to a comparative example. Figure 25A It is an explanatory diagram showing a configuration of four phase difference detection sections arranged in two rows and two columns on the first surface side according to a first modification example of the third embodiment of the present technology. Figure 25B It shows that along Figure 25A A longitudinal cross-sectional view of the section taken along the cutting line GG in FIG. Figure 26 : is a plan view showing a resist pattern used when performing etching back to remove unnecessary portions of an insulating film to obtain an insulating region in the method for manufacturing a light detecting device according to the first modification of the third embodiment of the present technology. Figure 27 : is an explanatory diagram showing a planar configuration of a charge accumulation region on the first surface S1 side included in a photodetection device according to a second modification example of the third embodiment of the present technology. Figure 28 : is an explanatory diagram showing a planar configuration of a charge accumulation region on the first surface S1 side included in a photodetection device according to a third modification example of the third embodiment of the present technology. Figure 29 is a block diagram illustrating an example of the overall configuration of an electronic device. DETAILED DESCRIPTION

[0009] Hereinafter, preferred embodiments for implementing the present technology will be described with reference to the accompanying drawings. Note that the following embodiments illustrate examples of representative embodiments of the present technology, but the scope of the present technology should not be narrowly interpreted based on these examples.

[0010] In the following descriptions of the drawings, the same or similar elements are marked with the same or similar reference numerals. However, it should be noted that the drawings are only schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc. may differ from the actual relationship, proportion, etc. Therefore, the specific thickness and size should be determined with reference to the following description. In addition, it is undeniable that the drawings include elements whose dimensional relationships, proportions, etc. are different from one drawing to another. In addition, drawings suitable for illustrating the present technology are used, so there may be differences in composition between the drawings.

[0011] In addition, the following embodiments illustrate examples of devices and methods for embodying the technical ideas of the present technology, and the technical ideas of the present technology are not specific to the materials, shapes, structures, configurations, etc. of the constituent components described below. The technical ideas of the present technology can be modified in various ways within the technical scope defined by the claims. In addition, it should be understood that the definitions of directions such as up and down in the following description are only definitions provided for the sake of brevity and are not intended to limit the technical ideas of the present disclosure. For example, it is obvious that when an object is rotated 90 degrees and then observed, up and down will be transformed and interpreted as left and right; and when the object is rotated 180 degrees and then observed, up and down will be interpreted as upside down.

[0012] The description will be given in the following order. 1. First Implementation Plan 2. Second Implementation Plan 3. Third Implementation Plan 4. Fourth Implementation Plan Application examples of electronic equipment

[0013] [First embodiment] The first embodiment will explain an example in which the present technology is applied to a light detection device as a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor.

[0014] <<Overall Structure of Photodetection Device>> First, the overall structure of the light detection device 1 will be described. Figure 1 As shown in FIG. 1 , the light detecting device 1 according to the first embodiment of the present technology is mainly configured by a semiconductor chip 2 whose two-dimensional planar shape is a rectangle in a plan view. In other words, the light detecting device 1 is mounted on the semiconductor chip 2. Figure 29 As shown, the light detection device 1 captures image light (incident light 106 ) from a subject via an optical system (optical lens) 102 , converts the light quantity of the incident light 106 formed on an imaging surface into an electrical signal in units of pixels, and outputs the electrical signal as a pixel signal.

[0015] like Figure 1 As shown, the semiconductor chip 2 on which the light detecting device 1 is mounted includes, in a two-dimensional plane including the X direction and the Y direction intersecting each other, a rectangular pixel area 2A provided at the center; and a peripheral area 2B provided to surround the pixel area 2A on the outside of the pixel area 2A. For example, the pixel area 2A is a region receiving light from a Figure 29 The light receiving surface of the optical system 102 shown in FIG. In addition, in the pixel area 2A, a plurality of pixels 3 are arranged in a matrix in a two-dimensional plane including the X direction and the Y direction. In other words, the pixels 3 are repeatedly arranged in each of the X direction (e.g., row direction) and the Y direction (e.g., column direction) that intersect with each other in the two-dimensional plane. It should be noted that in this embodiment, as an example, the X direction and the Y direction intersect each other perpendicularly. In addition, the direction perpendicular to both the X direction and the Y direction is the Z direction (thickness direction, stacking direction). The direction perpendicular to the Z direction is the horizontal direction.

[0016] like Figure 1 As shown, a plurality of bonding pads 14 are arranged in the peripheral region 2B. For example, each of the plurality of bonding pads 14 is arranged along each of the four sides on the two-dimensional plane of the semiconductor chip 2. Each of the plurality of bonding pads 14 serves as an input / output terminal used when the semiconductor chip 2 is electrically connected to an external device.

[0017] <Logic Circuit> like Figure 2 As shown, semiconductor chip 2 includes logic circuit 13. Logic circuit 13 includes vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, output circuit 7, control circuit 8, and the like. For example, logic circuit 13 is configured as a field-effect transistor using a complementary MOS (CMOS) circuit, which includes an n-channel conductive metal oxide semiconductor field effect transistor (MOSFET) and a p-channel conductive MOSFET.

[0018] For example, the vertical drive circuit 4 includes a shift register. The vertical drive circuit 4 sequentially selects the desired pixel drive lines 10, supplies pulses for driving the pixels 3 to the selected pixel drive lines 10, and drives each pixel 3 in a row unit. In other words, the vertical drive circuit 4 sequentially and vertically scans the pixels 3 in the pixel area 2A in a row unit, and supplies pixel signals of the pixels 3 based on signal charges generated according to the amount of light received by the photoelectric conversion elements of each pixel 3 to the column signal processing circuit 5 via the vertical signal lines 11.

[0019] For example, the column signal processing circuit 5 is arranged in each column of pixels 3 and performs signal processing, such as noise removal, on the signals output from the pixels 3 corresponding to a row for each pixel column. For example, the column signal processing circuit 5 performs signal processing such as correlated double sampling (CDS) to remove fixed pattern noise inherent to the pixels and analog-to-digital conversion. A horizontal selection switch (not shown) is connected and arranged between the output section of the column signal processing circuit 5 and the horizontal signal line 12.

[0020] The horizontal drive circuit 6 is composed of a shift register, for example. The horizontal drive circuit 6 sequentially selects each column signal processing circuit 5 by sequentially outputting horizontal scanning pulses to the column signal processing circuits 5 and outputs pixel signals that have been signal-processed from each column signal processing circuit 5 to the horizontal signal line 12.

[0021] The output circuit 7 performs signal processing on the pixel signals sequentially supplied from the respective column signal processing circuits 5 via the horizontal signal line 12, and outputs the resulting pixel signals. Examples of signal processing that can be used include buffering, black level adjustment, column variation correction, various types of digital signal processing, and the like.

[0022] The control circuit 8 generates a clock signal or a control signal based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock signal, which serves as an operation reference for the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like. The control circuit 8 then outputs the generated clock signal or control signal to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like.

[0023] <pixels> Figure 3 is an equivalent circuit diagram illustrating an example configuration of a pixel 3. In the illustrated example, multiple pixels 3 share a single readout circuit 15. More specifically, four pixels 3 share a single readout circuit 15. Each pixel 3 includes a photoelectric conversion element PD, a transfer transistor TR, and a charge accumulation region FD (floating diffusion). The transfer transistor TR transfers signal charge obtained through photoelectric conversion by the photoelectric conversion element PD to the charge accumulation region FD. The readout circuit 15 is connected to the downstream portion of the charge accumulation region FD.

[0024] The photoelectric conversion element PD generates signal charge corresponding to the amount of received light. The photoelectric conversion element PD also temporarily accumulates (holds) the generated signal charge. The photoelectric conversion element PD is electrically connected to the source region of the transfer transistor TR on the cathode side and to a reference potential line (e.g., ground) on the anode side. For example, a photodiode is used as the photoelectric conversion element PD.

[0025] The drain region of the transfer transistor TR is electrically connected to the charge accumulation region FD. The gate electrode of the transfer transistor TR is electrically connected to the pixel drive line 10 (refer to Figure 2 ) in the transfer transistor driver line.

[0026] The charge accumulation region FD temporarily accumulates and holds the signal charge transferred from the photoelectric conversion element PD via the transfer transistor TR.

[0027] The readout circuit 15 reads the signal charge accumulated in the charge accumulation region FD and outputs a pixel signal based on the signal charge. For example, the readout circuit 15 includes, but is not limited to, an amplifier transistor AMP, a select transistor SEL, and a reset transistor RST as pixel transistors. For example, these transistors (AMP, SEL, RST) are constructed using MOSFETs, which include a gate insulating film made of a silicon oxide film (SiO2 film), a gate electrode, and a pair of main electrode regions serving as source and drain regions. Alternatively, these transistors may be metal insulator semiconductor FETs (MISFETs) in which the gate insulating film is formed of a silicon nitride film (Si3N4 film) or a stacked film of silicon nitride films, silicon oxide films, and the like.

[0028] The source region of the amplifier transistor AMP is electrically connected to the drain region of the selection transistor SEL, and the drain region of the amplifier transistor AMP is electrically connected to the power supply line Vdd and the drain region of the reset transistor. In addition, the gate electrode of the amplifier transistor AMP is electrically connected to the charge accumulation region FD and the source region of the reset transistor RST.

[0029] The source region of the selection transistor SEL is electrically connected to the vertical signal line 11 (VSL), and the drain region of the selection transistor SEL is electrically connected to the source region of the amplifier transistor AMP. In addition, the gate electrode of the selection transistor SEL is electrically connected to the pixel drive line 10 (refer to Figure 2 ) among the selection transistor drive lines.

[0030] The source region of the reset transistor RST is electrically connected to the charge accumulation region FD and the gate electrode of the amplifier transistor AMP, and the drain region of the reset transistor RST is electrically connected to the power supply line Vdd and the drain region of the amplifier transistor AMP. The gate electrode of the reset transistor RST is electrically connected to the pixel drive line 10 (refer to Figure 2 ) in the reset transistor drive line.

[0031] <<Specific Configuration of the Photodetection Device>> Next, use Figures 4A to 4H, the specific structure of the light detection device 1 will be described. It should be noted that the barrier metal layer and the gate insulating film of the transistor are omitted in some drawings.

[0032] <Laminated Structure of Photodetection Device> Figure 4A It shows that along Figure 4B and Figure 4C The cross-sectional view is formed by the section taken along the cutting line AA in FIG. Figure 4A As shown, for example, the light detecting device 1 (semiconductor chip 2) has a stacked structure in which a first semiconductor layer 20, a first wiring layer 30, a second semiconductor layer 40, a second wiring layer 50, and a third semiconductor layer (not shown) are stacked in this order. The first semiconductor layer 20 has a first surface S1 on one side and a second surface S2 on the other side. Furthermore, the light detecting device 1 (semiconductor chip 2) has a light incident surface-side stacked body 60 on the second surface S2 side.

[0033] <First Semiconductor Layer> The first semiconductor layer 20 is constructed of a semiconductor substrate. For example, the first semiconductor layer 20 is mainly constructed of a single crystal silicon (Si) substrate, but is not limited thereto. It should be noted that the first surface S1 can be referred to as an element forming surface or a main surface, and the second surface S2 can be referred to as a light incident surface or a back surface. The portion of the first semiconductor layer 20 corresponding to the pixel area 2A is provided with a plurality of unit areas 20a, which are arranged in a matrix along the row direction and the column direction in a plan view. The unit area 20a is provided for each pixel 3. For example, an island-shaped unit area 20a divided by a separation area 20b is provided for each pixel 3. It should be noted that the number of pixels 3 is not limited to Figure 4A The number in .

[0034] A semiconductor region 21 and a semiconductor region 22 are constructed in the cell region 20a. The semiconductor region 21 is a first conductivity type (e.g., p-type) or intrinsic semiconductor (i-type), and in this embodiment, the semiconductor region 21 is described as a first conductivity type (e.g., p-type) semiconductor. The semiconductor region 22 is a second conductivity type (e.g., n-type) semiconductor. Figure 3 The photoelectric conversion element PD shown is constructed in the cell region 20a, performs photoelectric conversion on incident light, and generates signal charges.

[0035] like Figure 4A As shown, a second conductive type (eg, n-type) semiconductor region 23 and a first conductive type (eg, p-type) semiconductor region 24 are constructed in the cell region 20a. The semiconductor region 23 corresponds to Figure 3The charge accumulation region FD shown. Hereinafter, the semiconductor region 23 will be referred to as the charge accumulation region FD. The charge accumulation region FD is a diffusion region having an impurity concentration higher than the impurity concentration of the photoelectric conversion portion 22. The semiconductor region 24 is a contact region connected to a wiring for fixing the semiconductor region 21 to a reference potential. Hereinafter, the semiconductor region 24 will be referred to as the contact region 24. The contact region 24 is a diffusion region having an impurity concentration higher than the impurity concentration of the semiconductor region 21. The charge accumulation region FD and the contact region 24 may be provided at a position close to the first surface S1 in the thickness direction, or may face the first surface S1. In addition, the unit region 20a includes Figure 4D The first semiconductor region 20a1 is shown. The first semiconductor region 20a1 will be described in detail separately.

[0036] like Figure 4A As shown, for example, the cell region 20a is provided with a transistor T1. The transistor T1 is provided at a position close to the first surface S1 of the first semiconductor layer 20. For example, the transistor T1 is Figure 3 The transfer transistor TR shown. Hereinafter, the transistor T1 will be referred to as the transfer transistor T1.

[0037] like Figure 4A As shown, the separation region 20b is provided with a separation structure for dividing the unit region 20a. The separation structure may be a known structure such as an impurity separation structure, a trench separation wall, etc. Figure 4A The following description assumes the trench separation wall 25 shown. The trench separation wall 25 is a trench structure in which a recess FTI is formed along the thickness direction in the separation region 20 b of the first semiconductor layer 20 and is filled with a separation material. For example, the trench separation wall 25 is a full trench isolation (FTI) structure in which the separation material is buried in the recess FTI extending along the thickness direction from the first surface S1 to the second surface S2.

[0038] The separation material may be a known material such as an insulating film or metal. In this embodiment, the trench separation wall 25 is configured to include an insulating film 25a and polysilicon 25b. The insulating film 25a establishes insulation between the polysilicon 25b and the semiconductor region 21. Figure 4B It shows that along Figure 4A The cross-sectional view is formed by the section taken along the cutting line BB in FIG. Figure 4BAs shown, the groove separation wall 25 includes a portion extending in the row direction and the thickness direction and a portion extending in the column direction and the thickness direction. In addition, the portion extending in the row direction and the thickness direction and the portion extending in the column direction and the thickness direction intersect with each other. The portion where the portion extending in the row direction and the thickness direction and the portion extending in the column direction and the thickness direction intersect with each other will be referred to as an intersection region. Figure 4B In the example shown, the trench separation walls 25 are arranged in a grid pattern along the row and column directions in a plan view. The dimension of the trench separation walls 25 in the width direction is W1.

[0039] like Figure 4D As shown, for example, each charge accumulation region FD is provided at a corner of the unit region 20a in a plan view, but the charge accumulation region FD is not limited thereto. More specifically, in a plan view, the charge accumulation region FD is provided at mutually facing corners of four unit regions 20a in two rows and two columns that share one readout circuit 15. In addition, for example, each contact region 24 is provided at a corner of each unit region 20a in a plan view, but the contact region 24 is not limited thereto. More specifically, the contact region 24 is provided at a corner of the unit region 20a that is different from the corner at which the charge accumulation region FD is provided. In a plan view, the contact region 24 is provided at mutually facing corners of four unit regions 20a in two rows and two columns.

[0040] <Insulation Area> like Figure 4A As shown, an insulating region 26 made of an insulating material is provided at the end of the trench separating wall 25 close to the first surface S1. One surface of the insulating region 26 (the surface close to the second surface S2) contacts the end of the trench separating wall 25 close to the first surface S1. Figure 4C It shows that along Figure 4A The cross-sectional view is formed by the section taken along the cutting line CC in FIG. Figure 4C As shown, the insulating regions 26 extend in the row and column directions in plan view to divide the cell regions 20a. In plan view, the insulating regions 26 are arranged along the trench separators 25 and overlap with them. More specifically, in plan view, the entire trench separators 25 overlap with the insulating regions 26. Furthermore, the insulating regions 26 are provided throughout all locations where the trench separators 25 are provided in plan view. The width dimension of the insulating regions 26 is W2, which is greater than the width dimension W1 of the trench separators 25 (W2 > W1). Examples of insulating materials constituting the insulating regions 26 include, but are not limited to, materials such as silicon oxide (SiO2).

[0041] Figure 4G It shows that along Figure 4DThe longitudinal cross-sectional view is formed by the cross-section taken along the cutting line DD in FIG. Figure 4D and Figure 4G As shown, a surface of the insulating region 26 close to the first surface S1 is provided with a narrow-width insulating region 27 extending in the row direction and the column direction to divide the cell region 20 a .

[0042] Figure 4F is shown in an enlarged manner along Figure 4D The longitudinal cross-sectional view of a portion of the cross-section taken along the plane of the cutting line AA is shown. Figure 4F As shown, the narrow insulating region 27 is removed, and an electrode 70 is provided at the location where the charge accumulation region FD is provided. Since the location where the contact region 24 is provided also includes a similar structure in the plan view, its illustration and description can be omitted. The following description uses the charge accumulation region FD as an example. The contact region 24 can be used in place of the charge accumulation region FD.

[0043] <First Semiconductor Region> like Figure 4F and Figure 4G As shown, the first semiconductor region 20a1 is provided between the insulating region 26 and the first surface S1 in the thickness direction, one surface of the first semiconductor region 20a1 is in contact with the surface of the insulating region 26 close to the first surface S1, and the other surface of the first semiconductor region 20a1 faces the first surface S1. More specifically, the first semiconductor region 20a1 is a portion of the cell region 20a provided on the surface of the insulating region 26 close to the first surface S1, and is a portion overlapping with the insulating region 26 in a plan view.

[0044] Figure 4D 1 is a diagram showing the cell region 20a in a plan view of the first semiconductor layer 20 as viewed from the first surface S1 side. Figure 4D As shown, a first semiconductor region 20a1 is provided for each cell region 20a. More specifically, when the first semiconductor region 20a1 is viewed from the first surface S1 in a plan view, the first semiconductor region 20a1 is provided throughout the entire edge of the cell region 20a. The first semiconductor regions 20a1 of adjacent cell regions 20a are provided so as to be spaced apart from each other and not in contact with each other. It should be noted that the portion of each cell region 20a located further inward than the insulating region 26 in a plan view will be referred to as a second semiconductor region 20a2, which is distinguished from the first semiconductor region 20a1.

[0045] like Figure 4DAs shown, the charge accumulation region FD is constructed in a region of the cell region 20a including at least a portion of the first semiconductor region 20a1. More specifically, the charge accumulation region FD is constructed in a region of the cell region 20a including both the first semiconductor region 20a1 and the second semiconductor region 20a2.

[0046] <Electrode> like Figure 4A As shown, the light detecting device 1 includes an electrode 70. Although the electrode 70 includes an electrode 70 electrically connected to the charge accumulation region FD and an electrode 70 electrically connected to the contact region 24, since the configurations of the two are similar to each other, the electrode 70 electrically connected to the charge accumulation region FD will be described as an example.

[0047] The electrode 70 is an electrode that connects the wiring connected to the readout circuit 15 and the charge storage region FD of each pixel 3, and one electrode 70 is provided for a plurality of (four in this embodiment) pixels 3 that share one readout circuit 15. Figure 4E As shown, the electrode 70 includes a trunk 71 and a head 72, one surface of the head 72 being connected to one end of the trunk 71. Figure 4F As shown, the other end of the trunk portion 71 is in contact with the surface of the insulating region 26 close to the first surface S1 (i.e., the surface on the side opposite to the groove separation wall 25 side), and the electrode 70 is in contact with the charge accumulation region FD via the side of the trunk portion 71 and one surface of the head portion 72 (the surface on the first semiconductor layer 20 side). More specifically, the side of the trunk portion 71 of the electrode 70 and one surface of the head portion 72 are in contact with the portion of the first semiconductor region 20a1 constructed with the charge accumulation region FD. It should be noted that this does not exclude the side of the trunk portion 71 of the electrode 70 and one surface of the head portion 72 from being in contact with the second semiconductor region 20a2 constructed with the charge accumulation region FD. The side of the trunk portion 71 is a surface connecting one end and the other end of the trunk portion 71. In addition, the other surface of the head portion 72 faces the first wiring layer 30, and the wiring 32 is connected to the other surface of the head portion 72. As Figure 4E and Figure 4F As shown, the head 72 extends in a plate-like shape in the horizontal direction, and the area of ​​one surface of the head 72 is larger than the area of ​​one end of the trunk 71. Figure 4F As shown in the longitudinal cross-sectional view, the head portion 72 may extend from the trunk portion 71 in the horizontal direction and may be in contact with the charge accumulation region FD. Figure 4D As shown, in a plan view, the electrodes 70 are provided at positions where the charge accumulation regions FD face each other. Figure 4E As shown, the body portion 71 separates (partitions) the unit region 20 a , more specifically, separates (partitions) the charge accumulation region FD.

[0048] One electrode 70 is in contact with a plurality of charge accumulation regions FD that share one readout circuit 15. More specifically, one electrode 70 is in contact with a plurality of (four in this embodiment) charge accumulation regions FD provided in mutually different cell regions 20a. Figure 4H As shown, the trunk portion 71 includes a first extending portion 71x extending in the row and thickness directions, and a second extending portion 71y extending in the column and thickness directions. In a plan view, the first extending portion 71x and the second extending portion 71y intersect each other at their center, more specifically, perpendicularly intersecting each other. The portion where they intersect will be referred to as an intersection portion 71c. The charge accumulation region FD contacts each of the four recessed corner portions of the trunk portion 71 formed by the first extending portion 71x and the second extending portion 71y.

[0049] Figure 4F It shows that along Figure 4D A longitudinal cross-sectional view of a portion of the cross section taken along the plane of the cutting line AA is shown. Figure 4F In the longitudinal cross-sectional view, when the distance between the two charge accumulation regions FD facing each other via the trunk portion 71 is defined as b, and the horizontal dimension of the insulating region 26 is defined as a, the relationship of distance b being less than dimension a (b < a) is satisfied. Furthermore, when the horizontal dimension of the head portion 72 is defined as c in the longitudinal cross-sectional view, the relationship of dimension c being equal to or greater than b (b ≤ c) is satisfied. When dimension c and distance b are equal to each other, this means that the head portion 72 does not have a portion extending from the trunk portion 71.

[0050] Even when the cross section of the intersection portion 71c is viewed along a plane that is different from the cutting line AA, the relationship between the distance b, the dimension a, and the dimension c is the same. Furthermore, even in a cross-sectional configuration in which the light detecting device 1 is longitudinally cut along a plane that does not cross the intersection portion 71c in a plan view but crosses the first extension portion 71x or the second extension portion 71y, the relationship between the distance b, the dimension a, and the dimension c is the same.

[0051] The material constituting the electrode 70 is a known conductive material. The material constituting the electrode 70 may be a known metal material such as aluminum (Al), copper (Cu), or tungsten (W). This embodiment will be described based on the assumption that the electrode 70 is constructed of polycrystalline silicon (poly-Si).

[0052] It should be noted that the electrode 70 electrically connected to the contact region 24 may be referred to as the contact electrode 70 to distinguish it from the electrode 70 electrically connected to the charge accumulation region FD. In this case, the body 71 and the head 72 of the contact electrode 70 will be referred to as the contact body 71 and the contact head 72.

[0053] <Pass transistor> like Figure 4A and Figure 4E As shown, a transfer transistor T1 is provided for each cell region 20a. The transfer transistor T1 is a transistor capable of transferring signal charge generated within the photoelectric converter 22 to the charge accumulation region FD. For example, when the transfer transistor T1 is turned on, conduction is established between the photoelectric converter 22 and the charge accumulation region FD, and the signal charge is transferred to the charge accumulation region FD. Subsequently, when the transfer transistor T1 is turned off, conduction between the photoelectric converter 22 and the charge accumulation region FD is disconnected.

[0054] The transfer transistor T1 includes a gate electrode G1. Figure 4A As shown, the gate electrode G1 includes: a columnar first portion G1a, which is embedded in the cell region 20a and extends in the thickness direction; and a second portion G1b, which is provided in the first wiring layer 30, connected to the end of the first portion G1a close to the first surface S1 and extends in a plate-like shape in the horizontal direction. Figure 4A In the drawings, the gate insulating film that establishes insulation between the first portion G1 a and the cell region 20 a is omitted from illustration.

[0055] <First Wiring Layer> like Figure 4A As shown, the first wiring layer 30 is a multilayer wiring layer having one surface in contact with the first semiconductor layer 20 and another surface in contact with the second wiring layer 50. For example, the first wiring layer 30 includes an insulating film 31 and wiring 32 disposed within the insulating film 31, but the first wiring layer 30 is not limited thereto. The wiring 32 includes longitudinal wiring extending primarily in the thickness direction and lateral wiring extending primarily in the horizontal direction. For example, the insulating film 31 has a structure in which multiple layers of known insulating films such as silicon oxide (SiO2) film, silicon nitride (Si3N4) film, and silicon oxynitride (SiON) film are stacked. For example, the wiring 32 is made of a known conductive material, a semiconductor material such as polycrystalline silicon, or a metal material such as copper (Cu), tungsten (W), or aluminum (Al).

[0056] <Second Semiconductor Layer> The second semiconductor layer 40 is constructed of a semiconductor substrate. For example, the second semiconductor layer 40 is constructed of a single crystal silicon substrate and has one surface in contact with the first wiring layer 30 and another surface in contact with the second wiring layer 50, but the second semiconductor layer 40 is not limited thereto. The second semiconductor layer 40 is provided with a plurality of transistors T2. For example, the transistor T2 includes a structure Figure 3 The transistors of the readout circuit 15 are shown.

[0057] <Second Wiring Layer> The second wiring layer 50 is a multilayer wiring layer having one surface in contact with the second semiconductor layer 40 and another surface in contact with a third semiconductor layer (not shown). For example, the second wiring layer 50 includes a multilayered insulating film 51 and wiring 52 provided in the insulating film 51, but the second wiring layer 50 is not limited thereto. The wiring 52 includes longitudinal wiring extending mainly in the thickness direction and transverse wiring extending mainly in the horizontal direction. Figure 4A As shown, the vertical wiring may include a through wiring that penetrates the second semiconductor layer. Wiring 52 includes vertical wiring that extends primarily in the thickness direction and lateral wiring that extends primarily in the horizontal direction. For example, insulating film 51 has a structure in which multiple layers of known insulating films such as silicon oxide (SiO2) film, silicon nitride (Si3N4) film, and silicon oxynitride (SiON) film are stacked. For example, wiring 52 may be made of a known conductive material, a semiconductor material such as polycrystalline silicon, or a metal material such as copper (Cu), tungsten (W), or aluminum (Al).

[0058] For example, the wiring 52 and the wiring 32 in the first wiring layer 30 construct electrical paths, such as an electrical path that establishes a connection between the head 72 of the electrode 70 connected to the charge accumulation region FD and the amplifier transistor AMP, and an electrical path that supplies a reference potential to the head 72 of the electrode 70 connected to the contact region 24.

[0059] <Third Semiconductor Layer> The third semiconductor layer (not shown) is constructed from a semiconductor substrate. For example, the third semiconductor layer is constructed from a single crystal silicon substrate and has one surface in contact with the second wiring layer 50, but the third semiconductor layer is not limited thereto. For example, the third semiconductor layer is provided with a structure Figure 2 The transistors of the logic circuit 13 are shown.

[0060] <Light-Incident-Side Laminate> For example, the light-incident-side stack 60 has a stacked structure comprising a planarization film 61, a color filter 62, a light-shielding wall 63, and a microlens (on-chip lens) 64, stacked in this order from the second surface S2 side. However, the light-incident-side stack 60 is not limited to this structure. The planarization film 61 is constructed from a known insulating material or a known resin material, and can be constructed from silicon oxide, for example, but the planarization film 61 is not limited to this structure. The color filter 62 performs color separation on the light incident on each cell region 20a. For example, the light-shielding wall 63 and the color filter 62 are constructed from a resin material. The light-shielding wall 63, which blocks stray light, is provided between the color filters 62. The microlens 64 is constructed from a resin material, for example.

[0061] <<Method for Manufacturing a Photodetection Device>> In the following, reference is made to Figures 5A to 5J , a method for manufacturing the light detecting device 1 will be described. Note that, in this embodiment, the method for forming the insulating region 26, the charge storage region FD, and the electrode 70 will be mainly described, and descriptions of other parts will be omitted.

[0062] First, if Figure 5A As shown, a trench separator 25 is formed from the first surface S1 side of the first semiconductor layer 20w to fill the recess FTI by a known method. A pinning region 28 of the first conductivity type (e.g., p-type) is provided on the periphery of the trench separator 25. Thereafter, an insulating film m1, an insulating film m2, and an insulating film m3 are sequentially formed on the first surface S1. For example, the insulating films m1 and m3 are silicon oxide films, and the insulating film m1 can be formed by thermal oxidation. For example, the insulating film m2 is a silicon nitride film.

[0063] Then, the insulating region 26 is formed using shallow trench isolation (STI) technology. Figure 5BAs shown, using known photolithography and etching techniques, recesses STI are first formed from the first surface S1 side so that they overlap with the trench separators 25 in plan view. The recesses STI are arranged in a grid pattern at locations where the recesses STI overlap with the trench separators 25 in plan view. At this point, the insulating films m1, m2, and m3 are first etched using a resist pattern as a mask. Then, these insulating films serve as hard masks to form the recesses STI. The recesses STI penetrate the insulating films m1, m2, and m3 and reach the interior of the first semiconductor layer 20w. Subsequently, when forming the recesses STI, the portion of the trench separators 25 near the first surface S1 is removed. In plan view, the width of the recesses STI is greater than the width of the recesses FTI (trench separators 25). The recesses STI are arranged throughout all locations where the trench separators 25 are located in plan view. Furthermore, the trench separators 25 are exposed from the bottom surface of the recesses STI.

[0064] Afterwards, if Figure 5C As shown in FIG. 1 , an insulating film m4 is formed to fill the interior of the recess STI. For example, the insulating film m4 is a silicon oxide film. Then, as shown in FIG. Figure 5D As shown, by performing etching back on the entire surface, the unnecessary portion of the insulating film m4 is removed. The insulating film m4 remaining on the bottom of the groove STI constitutes the insulating region 26. It should be noted that when etching back on the entire surface, the insulating film m3 is removed. The etching rate of the insulating film m2 is lower than the etching rate of the insulating film m4 and the insulating film m3, so even if the insulating film m2 is etched, it is only slightly etched. In addition, by etching back, the semiconductor constituting the first semiconductor layer 20w is exposed from the sidewall of the groove STI. The semiconductor surface exposed from the sidewall of the groove STI will be referred to as surface 20c.

[0065] Then, if Figure 5E As shown, the first semiconductor region 20a1 is obtained by epitaxially growing silicon on the surface 20c. For example, the first semiconductor region 20a1 obtained by epitaxial growth is an intrinsic semiconductor (i-type), but the first semiconductor region 20a1 is not limited to this and, depending on the design, can be a p-type or n-type semiconductor. Furthermore, depending on the design, the first semiconductor region 20a1 can be formed to have the same conductivity type as the second semiconductor region 20a2 or the semiconductor region 21, or can be formed to have a different conductivity type. For example, silicon is selectively epitaxially grown on the surface 20c made of semiconductor, while not growing on surfaces made of materials other than semiconductors (such as insulating films). Furthermore, epitaxial growth is performed by controlling the growth time to prevent the first semiconductor regions 20a1 grown on opposing surfaces 20c from connecting to each other.

[0066] Afterwards, if Figure 5F As shown, an insulating film m5 is formed to cover the first semiconductor regions 20a1 and fill the gaps between the first semiconductor regions 20a1. Then, by a known method such as a known chemical-mechanical polishing (CMP) method or etch-back, the excess portion of the insulating film m5 and the insulating films m1 and m2 are removed. In this way, as shown in FIG. Figure 5G As shown, the insulating film m5 remaining between the first semiconductor regions 20 a 1 configures the narrow width insulating region 27 , and the first semiconductor regions 20 a 1 and the first surface S 1 are exposed.

[0067] Then, if Figure 5H As shown, a resist pattern R1 is formed on the exposed surface. Resist pattern R1 has an opening at the location where the charge accumulation region FD is formed. Both the first semiconductor region 20a1 and the second semiconductor region 20a2 are exposed from this opening. Then, using resist pattern R1 as an ion implantation mask, known impurities are selectively implanted to form an n-type semiconductor, thereby forming the charge accumulation region FD. Thereafter, resist pattern R1 is removed. Although not shown, contact region 24 is similarly formed. However, the impurities to be implanted are known impurities to form a p-type semiconductor.

[0068] Then, if Figure 5I As shown, the narrow width insulating region 27 at the position where the electrode 70 is provided in the plan view is removed using known photolithography and etching techniques. Figure 5J As shown, a polysilicon film is formed using known film formation techniques to cover the first surface S1 and fill the gaps between the first semiconductor regions 20a1. Excess portions of the polysilicon film are then etched away using known photolithography and etching techniques, thereby forming the electrode 70. Subsequently, processing continues using known manufacturing methods, substantially completing the light detecting device 1. The light detecting device 1 is then obtained as a single piece, thereby obtaining the semiconductor chip 2.

[0069] <<Main Effects of the First Embodiment>> Although the main effects of the first embodiment will be described below, first Figure 6 A light detecting device according to a comparative example is shown. In this comparative example, a shallow trench 26A is provided at the end of the trench separation wall 25 close to the first surface S1, and an insulating film is embedded in the shallow trench 26A. Furthermore, the shallow trench 26A defines four charge accumulation regions FD. The electrode 70A is formed simply of a horizontally extending plate-like member and contacts the four charge accumulation regions FD via the surface on the first semiconductor layer 20 side.

[0070] The miniaturization of pixel 3 also requires reducing the size of the charge accumulation region FD and electrode 70A. However, reducing the size of the charge accumulation region FD and electrode 70A may reduce the contact area between the charge accumulation region FD and electrode 70A, thereby increasing the contact resistance. This may lead to deterioration of the electrical connection between the charge accumulation region FD and electrode 70A.

[0071] On the other hand, the photodetecting device 1 according to the first embodiment of the present technology includes an electrode 70 having a trunk portion 71 and a head portion 72. One surface of the head portion 72 is connected to one end of the trunk portion 71. A charge storage region FD is formed in a region of each cell region 20a that includes a portion of the first semiconductor region 20a1. The other end of the trunk portion 71 is in contact with one surface (the surface close to the first surface S1) of the insulating region 26. The electrode 70 is in contact with the charge storage region FD via a side surface of the trunk portion 71 and one surface of the head portion 72. In this manner, since the photodetecting device 1 according to the first embodiment of the present technology establishes contact with the charge storage region FD on the side surface of the trunk portion 71 in addition to one surface of the head portion 72, a reduction in the contact area between the charge storage region FD and the electrode 70 can be suppressed, and degradation of the electrical connection between the charge storage region FD and the electrode 70 can be suppressed. Therefore, even when the pixel 3 is miniaturized, degradation of the electrical connection between the charge storage region FD and the electrode 70 can be suppressed.

[0072] Furthermore, in the light detection device 1 according to the first embodiment of the present technology, each unit region 20a includes a first semiconductor region 20a1 provided on the surface of the insulating region 26 opposite to the surface on the trench separation wall 25 side. In this manner, the area occupied by the unit region 20a on the first surface S1 side can be increased to include the portion above the insulating region 26, and the charge accumulation region FD can be constructed over the entire increased area, thereby suppressing the reduction in the size of the charge accumulation region FD. Consequently, a reduction in the contact area between the charge accumulation region FD and the electrode 70 can be suppressed, and degradation of the electrical connection between the charge accumulation region FD and the electrode 70 can be suppressed. Therefore, even when miniaturization of the pixel 3 is achieved, degradation of the electrical connection between the charge accumulation region FD and the electrode 70 can be suppressed.

[0073] Furthermore, the area occupied by the cell region 20a on the first surface S1 side can be increased to the portion above the insulating region 26, thereby suppressing a decrease in the overlap margin between the electrode 70 and the charge storage region FD. Furthermore, the area occupied by the cell region 20a on the first surface S1 side can be increased to the portion above the insulating region 26, thereby increasing the degree of freedom in the arrangement of the gate electrode G1.

[0074] Furthermore, in the light detecting device 1 according to the first embodiment of the present technology, the side surface of the trunk portion 71 and one surface of the head portion 72 are in contact with the portion of the first semiconductor region 20a1 in which the charge accumulation region FD is formed. Since the electrode 70 is in contact with the charge accumulation region FD formed in the first semiconductor region 20a1, it is possible to suppress a reduction in the size of the electrode 70, more specifically, the size of the head portion 72 in a plan view, while suppressing a reduction in the contact area between the charge accumulation region FD and the electrode 70. In other words, while the size of the head portion 72 in a plan view remains the same, the contact area between the charge accumulation region FD and the electrode 70 can be increased.

[0075] Furthermore, in the photodetecting device 1 according to the first embodiment of the present technology, the contact region 24 also has the same effect as that of the above-described charge storage region FD.

[0076] It should be noted that, although in this embodiment, Figure 4E As shown, the head 72 contacts the charge accumulation region FD only in the first semiconductor region 20a1 among the first semiconductor region 20a1 and the second semiconductor region 20a2, but the head 72 may contact the charge accumulation region FD in both the first semiconductor region 20a1 and the second semiconductor region 20a2.

[0077] <<Modification of the First Embodiment>> Hereinafter, modifications of the first embodiment will be described.

[0078] <First Modification> Although in the light detecting device 1 according to the first embodiment, as Figure 4D As shown, the first semiconductor region 20a1 is provided over the entire edge portion of the cell region 20a on the first surface S1, but the present technology is not limited thereto. Figure 7A In the light detecting device 1 according to the first modified example of the first embodiment shown in FIG. 1 , the first semiconductor region 20a1 is provided only at the corners of each unit region 20a on the first surface S1. Figure 7B As shown, the first semiconductor region 20a1 is not provided at any portion other than the corner. Figure 7A The cross-sectional structure of the light detection device 1 taken longitudinally along the plane of the cutting line AA is the same as that of Figure 4F The cross-sectional structure is the same. Figure 7B Shown along Figure 7A The cross section of the light detection device 1 is formed by taking a longitudinal section of the plane of the cutting line EE. Figure 7B As shown, the first semiconductor region 20a1 is not provided in the region other than the corner portion of each cell region 20a. Figure 7AAs shown, the charge accumulation region FD is constructed in the semiconductor region including the entire region of the first semiconductor region 20a1 provided at one corner of each cell region 20a.

[0079] In the following, reference will be made to Figure 8A 、 Figure 8B 、 Figure 9A and Figure 9B The manufacturing method of the light detection device 1 is described. It should be noted that in this modification, only the parts that are different from the manufacturing method according to the first embodiment are described. The steps are performed in the same manner as the manufacturing method according to the first embodiment until Figure 5C The process shown in FIG. Figure 8A As shown in FIG. 1 , unnecessary portions of the insulating film m4 and the insulating film m3 are removed by CMP. Figure 8B As shown, a resist pattern R2 is formed on the exposed surface of the insulating film m2. Figure 8B and Figure 9A As shown, the resist pattern R2 includes an opening R2a at a position where the charge accumulation region FD or the contact region 24 is provided. In addition, etching back is performed on the insulating film m4 exposed from the opening R2a, and etching back is not performed on the portion of the insulating film m4 covered by the resist. It should be noted that the etching rate of the insulating film m2 is lower than the etching rates of the insulating film m4 and the insulating film m3, so even if the insulating film m2 is etched, it is only slightly etched. Then, as shown in FIG. Figure 8B As shown, the insulating film m4 remaining on the bottom of the recess STI constitutes the insulating region 26. Thereafter, the resist pattern R2 is removed.

[0080] Next, silicon Figure 8B Epitaxial growth is performed on the surface 20c shown in FIG. 1 , thereby obtaining the first semiconductor region 20a1. Figure 7B As shown, the portion of the insulating film m4 that is protected by the resist pattern R2 and not etched back covers the side of the cell region 20a. Figure 9B As shown, silicon epitaxially grows only at the corners, and silicon does not epitaxially grow at portions other than the corners.

[0081] Even with the light detecting device 1 according to the first modification of the first embodiment, effects similar to those of the light detecting device 1 according to the first embodiment described above can be obtained.

[0082] In the photodetection device 1 according to the first modified example of the first embodiment, at the corners of the cell region 20a where the charge storage region FD or the contact region 24 is provided, the area occupied by the cell region 20a on the first surface S1 side can be increased to the portion above the insulating region 26. The charge storage region FD can be constructed over this increased area, thereby suppressing a reduction in the size of the charge storage region FD. Consequently, a reduction in the contact area between the charge storage region FD and the electrode 70 can be suppressed, and degradation of the electrical connection between the charge storage region FD and the electrode 70 can be suppressed. Therefore, even when the pixel 3 is miniaturized, degradation of the electrical connection between the charge storage region FD and the electrode 70 can be suppressed.

[0083] <Second Modification> exist Figure 10 In the light detecting device 1 according to the second modified example of the first embodiment shown, the gate electrode G1 may have a rectangular shape, and its area in a plan view may be larger than that in the case of the first embodiment. In addition, in a plan view, the head portion 72 of the electrode 70 may have a rectangular shape instead of an octagonal shape. In addition, Figure 10 The pixel shown may be a phase difference detection unit for detecting a phase difference. Figure 10 Even with the photodetection device 1 according to the second modification of the first embodiment, effects similar to those of the photodetection device 1 according to the first embodiment described above can be obtained.

[0084] <Third Modification> Figure 11 The light detecting device 1 according to the third modified example of the first embodiment shown in FIG. 1 is a combination of the first modified example and the second modified example described above. More specifically, Figure 11 As shown, the first semiconductor region 20a1 is provided only at the corner of each cell region 20a, and the gate electrode G1 and the head 72 are the same as those in the second modification. Figure 11 Illustration of the charge accumulation region FD is omitted in . Even with the light detecting device 1 according to the third modification of the first embodiment, effects similar to those of the light detecting device 1 according to the first embodiment described above can be obtained.

[0085] <Fourth Modification> exist Figure 12 In the light detecting device 1 according to the fourth modification of the first embodiment shown, the head portion 72 of the electrode 70 has an elliptical shape in a plan view, and the first semiconductor region 20a1 is provided only at the corner portion of each unit region 20a. Figure 12Illustration of the charge accumulation region FD is omitted in . Even with the photodetection device 1 according to the fourth modification of the first embodiment, effects similar to those of the photodetection device 1 according to the first embodiment described above can be obtained.

[0086] <Fifth Modification> exist Figure 13 In the light detecting device 1 according to the fifth modification of the first embodiment shown in FIG. 1 , the head portion 72 of the electrode 70 has a circular shape in a plan view, and the first semiconductor region 20a1 is provided only at the corner portion of each unit region 20a. Figure 13 Illustration of the charge accumulation region FD is omitted in . Even with the light detecting device 1 according to the fifth modification of the first embodiment, effects similar to those of the light detecting device 1 according to the first embodiment described above can be obtained.

[0087] <Sixth Modification> While the light detecting device 1 (semiconductor chip 2) in the first embodiment and its variations includes three semiconductor layers: a first semiconductor layer 20, a second semiconductor layer 40, and a third semiconductor layer (not shown), the present technology is not limited thereto. The light detecting device 1 according to the sixth variation of the first embodiment may include only two layers: the first semiconductor layer 20 and the third semiconductor layer. In this case, elements constructed in the second semiconductor layer 40 may be constructed in the first semiconductor layer 20, etc. Even with the light detecting device 1 according to the sixth variation of the first embodiment, similar effects to those of the light detecting device 1 according to the first embodiment described above can be achieved.

[0088] [Second embodiment] The following will explain Figure 14A and Figure 14B The second embodiment of the present technology is shown. In the light detecting device 1 according to the second embodiment, the size of the area occupied by the charge accumulation region FD is different. The other configurations of the light detecting device 1 are basically similar to those of the light detecting device 1 according to the first embodiment described above. It should be noted that the components that have already been described will be denoted by the same reference numerals, and their description will be omitted. It should be noted that Figure 14A 71 is a longitudinal sectional view showing a cross-sectional configuration of the electrode 70, the charge accumulation region FD, and the insulating region 26 taken along a plane crossing a cutting line across the trunk portion 71. In this embodiment, Figure 14A is shown as an example along the cross Figure 14B The longitudinal cross-sectional view is formed by cutting a section of the electrode 70 along a plane of a cutting line of the first extension portion 71 x of the trunk portion 71 .

[0089] The charge accumulation region FD is constructed in the region of each unit region 20a made only of the first semiconductor region 20a1. More specifically, the charge accumulation region FD is constructed in the region made only of the first semiconductor region 20a1 among the first semiconductor region 20a1 and the second semiconductor region 20a2, and is not constructed in the second semiconductor region 20a2. In addition, in a plan view, the entire charge accumulation region FD overlaps with the insulating region 26, and the surface of the charge accumulation region FD on the second surface S2 side is in contact with the insulating region 26. In other words, the area occupied by the charge accumulation region FD in this embodiment is smaller than the area occupied by the charge accumulation region FD in the first embodiment. Therefore, the impurity concentration in the charge accumulation region FD according to this embodiment is set to be higher than the impurity concentration in the charge accumulation region FD according to the first embodiment. Even if the area occupied by the charge accumulation region FD is reduced, the deterioration of the charge accumulation performance can be suppressed by setting a high impurity concentration. In addition, even if the contact area between the charge accumulation region FD and the electrode 70 is reduced due to the reduction in the area occupied by the charge accumulation region FD, the increase in contact resistance can be suppressed by setting a high impurity concentration.

[0090] The charge accumulation region FD is constructed in a region made of only the first semiconductor region 20a1. Figure 14A In the longitudinal cross-sectional view of FIG, the relationship between dimension a, which is the horizontal dimension of the insulating region 26, distance b, which is the distance between the two charge storage regions FD facing each other via the trunk portion 71, and dimension d, which is the horizontal dimension of the charge storage regions FD, can be expressed as a ≥ 2d + b. In other words, the value obtained by adding the value of distance b to a value twice that of dimension d is equal to or less than dimension a. In other words, 2d + b is the width occupied in the horizontal direction by the two charge storage regions FD facing each other via the trunk portion 71.

[0091] In addition, if Figure 14A and Figure 14B As shown, in a plan view, the head portion 72 overlaps the entire charge accumulation region FD. In other words, the relationship between the aforementioned distance b and dimension d and the horizontal dimension c of the head portion 72 can be expressed as c ≥ 2d + b. In other words, dimension c is equal to or greater than the value obtained by adding twice the value of dimension d to the value of distance b. When limiting the value of dimension c, it is sufficient to determine distance b and dimension d so as to satisfy the aforementioned expression.

[0092] For example, the lower limit of dimension c may be the same width as the width of the groove separation wall 25, but the lower limit is not limited thereto. Also, for example, the lower limit of dimension d may be in the range of 1 / 4 to 1 / 5 of dimension c, but the lower limit is not limited thereto.

[0093] It should be noted that in the longitudinal cross-section along the plane, the relationship between dimension a, distance b, dimension c and dimension d is Figure 14A The same applies to different cross-sectional configurations.

[0094] <<Method for Manufacturing a Photodetection Device>> In the following, reference is made to Figures 15A to 15E , a method for manufacturing the light detection device 1 will be described. It should be noted that in this variation, only the differences from the manufacturing method according to the first embodiment described above will be described. Furthermore, the following description will also refer to the drawings used to illustrate the manufacturing method according to the first embodiment as needed.

[0095] The process is performed in the same manner as in the above-described manufacturing method according to the first embodiment until Figure 5E . Afterwards, as Figure 15A As shown, a resist pattern R5 having an opening R5a is formed on the exposed surface. Then, using the resist pattern R5 as a mask for ion implantation, known impurities are implanted from the first surface S1 side to obtain an n-type semiconductor. The resist forming the resist pattern R5 covers a portion of the first semiconductor region 20a1 obtained by epitaxial growth. In addition, another portion of the first semiconductor region 20a1 is exposed from the opening R5a. Compared with the case of the first embodiment, by ion implanting impurities through such an opening R5a, a charge accumulation region FD can be set in a narrower area. In addition, in order to form the charge accumulation region FD in a narrow area, it is necessary to perform ion implantation with a higher dose. In this embodiment, the entire opening R5a overlaps with the insulating region 26 in a plan view. In other words, impurities are implanted into a semiconductor region that overlaps with the surface of the insulating region 26 on the first surface S1 side in a plan view. Therefore, even if the impurity dose is increased to increase the impurity concentration in the charge accumulation region FD, the advancement of the impurities will be blocked by the insulating region 26, and it will be difficult for the impurities to reach deeper positions. Therefore, it is possible to maintain a high concentration of impurities in a region where the charge storage region FD is desired to be formed, and to form a fine charge storage region FD having a high impurity concentration.

[0096] Then, if Figure 15B As shown, an insulating film m5 is formed on the exposed surface to fill the charge accumulation region FD. Then, the excess portion of the insulating film m5 is removed by CMP, and then the insulating film m2 is removed, thereby obtaining Figure 15C Then, as Figure 15D As shown in FIG. 1 , the excess portion of the insulating film m5 and the insulating film m1 are removed by etching back. A portion of the insulating film m5 remains between the charge accumulation regions FD, and the remaining insulating film m5 and the insulating region 26 are collectively referred to as the insulating region 26. Next, as shown in FIG. Figure 15E As shown in FIG. 1 , the electrode 70 is formed so as to be in contact with each charge storage region FD. The subsequent processing is the same as that described in the first embodiment, and therefore the description thereof will be omitted.

[0097] <<Main Effects of the Second Embodiment>> Although the main effects of the second embodiment will be described below, first Figure 16 The light detection device according to the comparative example is shown. Figure 16 As shown in the plan view, if the distance between the charge accumulation region FD and the columnar first portion G1a included in the gate electrode G1 is too short, the electric field strength between the charge accumulation region FD and the first portion G1a may increase, and FD white spots may deteriorate. However, if the charge accumulation region FD and the electrode 70A are miniaturized to increase the distance between the charge accumulation region FD and the first portion G1a, the contact area between the charge accumulation region FD and the electrode 70A may decrease, which may lead to an increase in contact resistance. As a result, the electrical connection between the charge accumulation region FD and the electrode 70A may deteriorate.

[0098] On the other hand, the light detecting device 1 according to the second embodiment of the present technology can obtain effects similar to those of the light detecting device 1 according to the first embodiment described above.

[0099] Furthermore, in the light detecting device 1 according to the second embodiment of the present technology, the charge accumulation region FD is constructed in a region made only of the first semiconductor region 20a1 in the cell region 20a, and the entire charge accumulation region FD overlaps with the insulating region 26 in a plan view. In this way, it is possible to form the charge accumulation region FD which is fine and has a high impurity concentration. Therefore, in the light detecting device 1 according to the second embodiment of the present technology, as shown in FIG. Figure 17 As shown, the distance between the charge accumulation region FD and the first portion G1a can be widened compared to the comparative example. Consequently, an increase in the electric field strength between the charge accumulation region FD and the first portion G1a can be suppressed, and degradation of the FD white spot can be suppressed. Furthermore, the charge accumulation region FD can be formed with a high impurity concentration, thereby suppressing degradation of the charge accumulation performance even if the area occupied by the charge accumulation region FD is reduced. Furthermore, even if the contact area between the charge accumulation region FD and the electrode 70 is reduced, an increase in the contact resistance between the charge accumulation region FD and the electrode 70 can be suppressed.

[0100] In the photodetection device 1 according to the second embodiment of the present technology, in a longitudinal cross-sectional view, when the distance between two charge storage regions FD facing each other via the trunk portion 71 is defined as b, the horizontal dimension of the head portion 72 is defined as c, and the horizontal dimension of each charge storage region FD is defined as d, the relationship c ≥ 2d + b is satisfied. In other words, in a plan view, because the head portion 72 overlaps the entirety of each charge storage region FD, even if the area occupied by the charge storage region FD is reduced, the head portion 72 of the electrode 70 can effectively contact the charge storage region FD. It should be noted that if the contact area between the charge storage region FD and the electrode 70 is the same as that in the first embodiment, the higher impurity concentration in the charge storage region FD in this embodiment can reduce the contact resistance compared to the first embodiment. Furthermore, even if the contact area between the charge storage region FD and the electrode 70 is smaller than that in the first embodiment, the higher impurity concentration in the charge storage region FD in this embodiment can suppress an increase in contact resistance.

[0101] Furthermore, in the light detecting device 1 according to the second embodiment of the present technology, the width occupied in the horizontal direction by the two charge storage regions FD facing each other via the trunk portion 71 in the longitudinal cross-sectional view is equal to or smaller than the horizontal dimension of the insulating region 26 in the cross-sectional view. In this manner, even when one electrode 70 is provided for a plurality of charge storage regions FD, it is possible to form the charge storage regions FD that are fine and have a high impurity concentration.

[0102] <<Modification of the Second Embodiment>> Hereinafter, modifications of the second embodiment will be described.

[0103] <First Modification> Figure 18A The light detecting device 1 according to the first modified example of the second embodiment shown is a combination of the first modified example of the first embodiment and the second embodiment. Figure 18A As shown, the first semiconductor region 20a1 is provided only at the corner of each unit region 20a, and the charge accumulation region FD in the second embodiment is provided in such a first semiconductor region 20a1. In this modification, the relationship between the dimension a, the distance b, the dimension c, and the dimension d is also the same. In addition, the positional relationship and the size relationship between the electrode 70, the charge accumulation region FD, and the first semiconductor region 20a1 can be Figure 18B Even with the light detecting device 1 according to the first modified example of the second embodiment, effects similar to those of the light detecting device 1 according to the second embodiment described above can be obtained.

[0104] <Second Modification> The manufacturing method of the light detecting device 1 according to the second modification of the second embodiment is different from that in the second embodiment. Figure 19A and Figure 19B A method for manufacturing the light detection device 1 according to this variation will now be described. It should be noted that in this variation, only the differences from the manufacturing methods according to the first and second embodiments described above will be described. Furthermore, the following description will also refer to the figures used to illustrate the manufacturing method according to the first embodiment, as needed.

[0105] The process is performed in the same manner as in the above-described manufacturing method according to the first embodiment until Figure 5D . Afterwards, as Figure 19A As shown, silicon is epitaxially grown on surface 20c, thereby forming a portion of first semiconductor region 20a1. For example, the epitaxially grown first semiconductor region 20a1 is an intrinsic semiconductor (i-type), but first semiconductor region 20a1 is not limited to this and, depending on the design, may be a p-type or n-type semiconductor. Furthermore, depending on the design, first semiconductor region 20a1 may be formed to have the same conductivity type as second semiconductor region 20a2 or semiconductor region 21, or may be formed to have a different conductivity type.

[0106] Then, if Figure 19B As shown, silicon is further epitaxially grown to obtain the remaining portion of the first semiconductor region 20a1. At this time, the silicon is epitaxially grown while simultaneously implanting known impurities to obtain an n-type semiconductor. In this way, an n-type first semiconductor region 20a1 can be formed, and the resulting n-type region can be obtained as a charge accumulation region FD. Subsequent processing is identical to that in the manufacturing method of the second embodiment, and therefore its description will be omitted. Even with the light detecting device 1 according to the second modified example of the second embodiment, effects similar to those of the light detecting device 1 according to the second embodiment described above can be obtained.

[0107] Furthermore, with the light detecting device 1 according to the first modification of the second embodiment, it is not necessary to form the resist pattern R5 , and the number of photolithography steps can be reduced.

[0108] <Third Modification> In the light detecting device 1 according to the third modification of the second embodiment, the shape of the insulating region 26 is a flat plate in a longitudinal cross-sectional view, which is different from the Figure 4FThe shape of the insulating region 26 according to the first embodiment shown in FIG, etc. is the same. Even with the light detecting device 1 according to the third modification of the second embodiment, effects similar to those of the light detecting device 1 according to the second embodiment described above can be obtained.

[0109] [Third embodiment] The following, 20A to 20D The third embodiment of the present technology will be described below. The light detection device 1 according to the third embodiment includes a phase difference detection unit 80. The other configurations of the light detection device 1 are substantially similar to those of the light detection device 1 according to the first embodiment described above. It should be noted that the components that have already been described will be denoted by the same reference numerals, and their description will be omitted. It should be noted that Figure 20A It shows that along Figure 20B The longitudinal cross-sectional view is formed by the cross-section taken along the cutting line FF in FIG. Figure 20C It shows that along Figure 20B The longitudinal cross-sectional view is formed by the section taken along the cutting line GG in FIG. Figure 20B 1 is an explanatory diagram showing the positional relationship of each component on the first surface S1.

[0110] Note that in the drawings according to this embodiment, the first semiconductor region 20a1 and the second semiconductor region 20a2 are shown as distinct. Furthermore, in the drawings according to this embodiment, the conductivity types of semiconductors, such as first conductivity type (e.g., p-type), second conductivity type (e.g., n-type), and i-type, are not shown separately. In the drawings according to this embodiment, the focus is primarily on and depicts the first semiconductor layer 20, and illustration of other semiconductor layers, wiring layers, and the like may be omitted. In the drawings according to this embodiment, some portions of the light detection device 1 are depicted, while other portions are omitted. Furthermore, in the drawings according to this embodiment, electrodes and wiring, such as the electrode 70, disposed in contact with the first semiconductor region 20a1 are omitted to facilitate understanding of the shape of the first semiconductor region 20a1. Furthermore, while the trench separation wall 25 in this embodiment is constructed similarly to the first embodiment, including an insulating film 25a and polysilicon 25b, the insulating film 25a is omitted in the drawings according to this embodiment.

[0111] like Figure 20AAs shown, the phase difference detection section 80 includes multiple (two in this embodiment) adjacent unit regions 20a. Note that to distinguish the unit regions 20a on the right side of the drawing from the unit regions 20a on the left side, the unit regions on the right side of the drawing will be referred to as unit regions 20aR, while the unit regions on the left side of the drawing will be referred to as unit regions 20aL. When the distinction between the two unit regions is not made, the unit regions will simply be referred to as unit regions 20a. The light detection device 1 uses the phase difference detection section 80 to determine the direction from which light is incident. More specifically, the light detection device 1 compares the amount of signal charge accumulated in unit regions 20aR with the amount of signal charge accumulated in unit regions 20aL to determine the direction from which light is incident. For example, if the amount of signal charge accumulated in unit regions 20aR is greater than that accumulated in unit regions 20aL, it can be determined that light is incident on the light detection device 1 obliquely from the left side of the drawing.

[0112] In addition, the phase difference detection unit 80 includes a path PH through which the signal charge can move between the unit area 20aR and the unit area 20aL. Path PH can also be called an overflow path. When the signal charge contained in one of the unit areas 20aR and 20aL is saturated, the signal charge moves from this unit area to the other unit area via path PH, that is, overflows. The phase difference detection unit 80 can also be used as a pixel 3. When the phase difference detection unit 80 is also used as a pixel 3, the phase difference detection unit 80 outputs a summed signal as a pixel signal, which is the sum of the signal charge amount accumulated in the unit area 20aR and the signal charge amount accumulated in the unit area 20aL. Therefore, when the signal charge contained in one unit area reaches saturation first, by allowing the signal charge to overflow to the other unit area, it is possible to suppress a portion of the signal charge from being discarded. Therefore, it is possible to suppress the degradation of the linearity of the light amount and the summed signal.

[0113] The portion of the trench separation wall 25 located between the two unit regions 20a (unit region 20aR, unit region 20aL) in the phase difference detection unit 80 will be referred to as the first trench separation wall 25c to distinguish it from the other portions. In the absence of distinguishing the first trench separation wall 25c from the other trench separation walls 25, they are simply referred to as the trench separation wall 25. Figure 20A and Figure 20BAs shown, the first semiconductor region 20a1 is located at a position where the first semiconductor region 20a1 overlaps with the first trench separator 25c in a plan view, and a connection is established between the cell region 20aR and the cell region 20aL within the phase difference detection unit 80. More specifically, the first semiconductor region 20a1 included in the cell region 20aR and the first semiconductor region 20a1 included in the cell region 20aL are connected to each other at a position where they overlap with the first trench separator 25c in a plan view and are integrated into a single component. In addition, a path PH is constructed in the first semiconductor region 20a1 located at a position where the first semiconductor region 20a1 overlaps with the first trench separator 25c in a plan view. The conductivity type of the first semiconductor region 20a1 in which the path PH is constructed only needs to be configured to be a conductivity type compatible with the design.

[0114] like Figure 20C As shown, a portion of the end portion of the first trench separating wall 25c on the first surface S1 side is recessed in the thickness direction compared to other portions, and the insulating region 26 and the first semiconductor region 20a1 are provided only at the recessed portion 25d at the end portion of the first trench separating wall 25c.

[0115] Figure 20DFour phase difference detection units 80 are shown, arranged in two rows and two columns. In plan view, first semiconductor regions 20a1 with charge accumulation regions FD are provided at the mutually facing corners of the four phase difference detection units 80. Note that the electrode 70 is omitted from illustration in this embodiment. The first semiconductor region 20a1 with the charge accumulation region FD has a quadrangular ring shape in plan view and connects the mutually facing corners of the four unit regions 20a at the corners of the phase difference detection unit 80. Note that to distinguish between the first semiconductor region 20a1 with the path PH and the first semiconductor region 20a1 with the charge accumulation region FD, the first semiconductor region 20a1 with the path PH may be referred to as the first semiconductor region 20a1PH, while the first semiconductor region 20a1 with the charge accumulation region FD may be referred to as the first semiconductor region 20a1FD. In situations where the two first semiconductor regions are not distinguished from each other, the first semiconductor region is simply referred to as the first semiconductor region 20a1. Similar to the first semiconductor region 20a1PH, the first semiconductor region 20a1FD is also provided within the recessed portion 25d of the trench partition wall 25. Furthermore, the light detecting device 1 may include a contact region 24 having a configuration similar to that of the charge storage region FD, and in the above description, the charge storage region FD may be replaced with the contact region 24. When the electrode 70 is provided in the first semiconductor region 20a1FD, the body portion 71 of the electrode 70 may be formed into a columnar shape to fill the hollow portion of the annular first semiconductor region 20a1FD.

[0116] <<Method for Manufacturing a Photodetection Device>> In the following, reference will be made to Figures 21 to 23 The manufacturing method of the light detection device 1 is described. It should be noted that in this embodiment, only the parts that are different from the manufacturing method according to the first embodiment are described. In addition, the longitudinal cross-sectional view referred to in the following description shows the longitudinal cross-sectional view taken along the Figure 20B FF in the longitudinal cross-sectional view. In addition, in the following description, reference will also be made to the drawings for explaining the manufacturing method according to the first embodiment as needed.

[0117] The process is performed in the same manner as in the above-described manufacturing method according to the first embodiment until Figure 5A The process shown in FIG. Figure 21As shown, using known photolithography technology and etching technology, a groove STI is formed from the side of the first surface S1 so that the groove STI overlaps with the trench separation wall 25 in a plan view. At this time, a resist pattern R3 can be formed first, and the insulating films m1, m2 and m3 can be etched using the resist pattern R3 as a mask, and the groove STI can be formed using the insulating film as a hard mask. It should be noted that although in the first embodiment described above, the groove STI is formed in a grid shape in a plan view, in this embodiment, a resist pattern R3 having an opening R3a1 and an opening R3a2 is used to form the groove STI only in a rectangular area. The opening R3a1 of the resist pattern R3 is provided at a position where the first semiconductor region 20a1PH is formed in a plan view, and the opening R3a2 is provided at a position where the first semiconductor region 20a1FD is formed in a plan view.

[0118] Afterwards, if Figure 5C As shown, an insulating film m4 is formed to fill the interior of the recess STI, and as shown in FIG. Figure 5D As shown, etching is performed on the entire surface to remove unnecessary portions of the insulating film m4. The insulating film m4 remaining on the bottom of the recess STI forms the insulating region 26. Figure 22 The shape and position of the insulating region 26 in the plan view are shown. Then, silicon is made Figure 5D and Figure 22 Epitaxial growth is performed on the surface 20c shown, thereby obtaining Figure 23 The first semiconductor region 20a1 shown in FIG. It should be noted that the surface 20c is a semiconductor surface exposed from the sidewall of the recess STI. It should be noted that although in the first embodiment described above, epitaxial growth is controlled to prevent the first semiconductor regions 20a1 grown on the opposite surfaces 20c from being connected to each other, in this embodiment, as shown in FIG. Figure 23 As shown, the first semiconductor regions 20a1 grown on the opposing surfaces 20c are controlled so as to be connected to each other. In this way, the cell region 20aR and the cell region 20aL are electrically connected via the first semiconductor region 20a1PH, thereby obtaining a ring-shaped first semiconductor region 20a1FD.

[0119] For example, the epitaxially grown first semiconductor region 20a1 is an intrinsic semiconductor (i-type). However, the first semiconductor region 20a1 is not limited to this and, depending on the design, may be a p-type or n-type semiconductor. Furthermore, depending on the design, the first semiconductor region 20a1 may be formed to have the same conductivity type as the second semiconductor region 20a2 or the semiconductor region 21, or may be formed to have a different conductivity type. Subsequent processing is the same as that described in the first embodiment and the known method for manufacturing the phase difference detection unit 80, and therefore, description thereof will be omitted.

[0120] <<Main Effects of the Third Embodiment>> Although the main effects of the third embodiment will be described below, first, the miniaturization and Figure 24 By providing an impurity separation structure between the two unit regions 20a in the phase difference detection unit 80, a path PH serving as an overflow path can be provided on the first surface S1 side in the thickness direction. However, if further miniaturization of the pixel is desired and further miniaturization of the phase difference detection unit 80 is achieved, it may not be easy to provide an impurity separation structure between the two unit regions 20a. In this case, as shown in FIG. Figure 24 As shown in the comparative example in , it is necessary to separate the two unit areas 20a by the first groove separation wall 25c. In addition, the path PH as the overflow path can be set at a position close to the color filter 62 in the thickness direction. Therefore, it is necessary to form the height of the first groove separation wall 25c overlapping with the path PH in the plan view to a height different from the height of the other groove separation walls 25e, and it may not be easy to perform stable height control. In addition, the signal charge generated in one unit area among the unit area 20aR and the unit area 20aL may move to the other unit area, and the separation performance may deteriorate. In addition, in the case where the first groove separation wall 25c is formed of silicon oxide, the incident light L passes through the microlens 64 and the color filter 62 having a low refractive index, then passes through the path PH made of a semiconductor having a high refractive index, and then is incident on the first groove separation wall 25c having a low refractive index again. In this case, the incident light L propagates to the low refractive index region, the high refractive index region and the low refractive index region. In particular, when the light is incident on the first groove separation wall 25c having a low refractive index from the path PH in the high refractive index region, the light may be reflected or scattered.

[0121] On the other hand, in the light detecting device 1 according to the third embodiment of the present technology, the path PH is constructed in the first semiconductor region 20a1PH, which is provided on the surface of the insulating region 26 on the side opposite to the surface on the first groove separation wall 25c side. In this way, even when miniaturization of the pixel 3 is achieved, the path PH can be provided at a position close to the first surface S1 rather than at a position close to the second surface S2. Therefore, in the thickness direction, the position of the end of the first groove separation wall 25c on the color filter 62 side can be aligned with the position of the end of the other groove separation wall 25 on the color filter 62 side, and the deterioration of the separation performance can be suppressed. In addition, since the path PH having a high refractive index is not provided on the color filter 62 side, the increase in reflection and scattering of the incident light L can be suppressed. Since the position of the end of the first groove separation wall 25c on the color filter 62 side can be aligned with the position of the end of the other groove separation walls 25 on the color filter 62 side, when the first groove separation wall 25c and the other groove separation walls 25 are formed from the first surface S1 side, all groove separation walls having the same depth can be formed, and the increase in manufacturing load can be suppressed.

[0122] Furthermore, the photodetection device 1 according to the third embodiment of the present technology includes an insulating region 26 made of an insulating material, disposed between the end of the first trench separator 25c near the first surface S1 and the first semiconductor region 20a1PH. Since the insulating region 26 is interposed between the first trench separator 25c and the first semiconductor region 20a1PH, even when the trench separator 25 includes a portion made of a conductive material such as polysilicon, the conductive portion of the trench separator 25 can be electrically insulated from the path PH. Furthermore, the flow of signal charge in the path PH can be primarily concentrated in the horizontal direction. Furthermore, the provision of the insulating region 26 can, for example, clarify the difference in impurity concentration between the first semiconductor region 20a1 and other semiconductor regions such as the photoelectric conversion unit 22.

[0123] In the light detecting device 1 according to the third embodiment, similar to the light detecting device 1 according to the first embodiment and the light detecting device 1 according to the second embodiment described above, a charge accumulation region FD and a contact region 24 can also be constructed in a region including at least a portion of the first semiconductor region 20a1.

[0124] It should be noted that, as in the first embodiment Figure 4C As shown, the insulating region 26 may be arranged in a grid shape in a plan view.

[0125] <<Modification of the Third Embodiment>> Hereinafter, modifications of the third embodiment will be described.

[0126] <First Modification> exist Figure 25A and Figure 25B In the illustrated photodetecting device 1 according to the first modified example of the third embodiment, an insulating isolation region 29 made of an insulating material is provided between the sidewall 25f of the recessed portion 25d of the first trench separating wall 25c and the first semiconductor region 20a1PH. Furthermore, an insulating isolation region 29 made of an insulating material is also formed between the sidewall 25f of the recessed portion 25d of the trench separating wall 25 and the first semiconductor region 20a1FD. The material constituting the insulating isolation region 29 is a known insulating material. The insulating isolation region 29 can be constructed of the same material as that constituting the insulating region 26.

[0127] In the following, reference will be made to Figure 26 The manufacturing method of the light detection device 1 is described. It should be noted that in this modification, only the parts that are different from the manufacturing method according to the third embodiment described above are described. More specifically, the manufacturing method according to this modification is the same as the manufacturing method according to the third embodiment, until Figure 5C The insulating film m4 is formed to fill the interior of the recess STI. Thereafter, although not shown, the excess portion of the insulating film m4 and the insulating film m3 are removed by, for example, CMP. In this way, the insulating film m2 is exposed.

[0128] Then, if Figure 26 As shown, a resist pattern R4 having openings R4a1 and R4a2 is formed by a known photolithography technique. The opening R4a1 is provided at a position where the first semiconductor region 20a1PH is formed in a plan view, and the opening R4a2 is provided at a position where the first semiconductor region 20a1FD is formed in a plan view. Then, the portions exposed from the openings R4a1 and R4a2 are etched back to remove unnecessary portions of the insulating film m4, thereby obtaining the insulating region 26. Figure 26 In the example, the shapes of the openings R4a1 and R4a2 are aligned with Figure 21Compare the shapes of openings R3a1 and R3a2 in the resist pattern R3 shown. Note that, in plan view, the sizes of openings R3a1 and R3a2 are identical to the size of the recessed portion 25d of the trench separating wall 25. The dimension of opening R4a1 along the extension direction (Y direction) of the first trench separating wall 25c is smaller than that of opening R3a1. Therefore, both ends of the insulating film m4 embedded in the recessed portion 25d in the Y direction are covered by the resist and remain intact without being etched back. In this way, an insulating isolation region 29 can be provided between the first semiconductor region 20a1 and the sidewalls 25f of the recessed portion 25d of the first trench separating wall 25c. Furthermore, the dimension of opening R4a1 along the width direction (X direction) of the first trench separating wall 25c is larger than that of opening R3a1, and the insulating films m2 and m4 are exposed through opening R4a1. During the etch-back process, due to the difference in etching rates between the insulating film m2 and the insulating film m4 , even if the insulating film m2 is etched, it is only slightly etched.

[0129] Opening R4a2 is located at a position where the trench separation walls 25 intersect each other in a plan view. Therefore, the shape and size of opening R4a2 are determined in such a way that the insulating film m4 remains at the ends in both the X and Y directions. In addition, since silicon needs to be epitaxially grown on the semiconductor surface, opening R4a2 is widened so that the insulating film m4 does not remain on the surface 20c. More specifically, the dimensions of the corners of opening R4a2 in the X and Y directions are set to be larger than the dimensions of opening R3a2, while between the corners, at least in the area wider than the trench separation wall 25, the dimensions of opening R4a2 in the X and Y directions are set to be smaller than the dimensions of opening R3a2. Therefore, it is possible to provide an insulating separation region 29 between the first semiconductor region 20a1 and the sidewall 25f of the recessed portion 25d of the first trench separation wall 25c.

[0130] Even with the light detecting device 1 according to the first modified example of the third embodiment, effects similar to those of the light detecting device 1 according to the third embodiment described above can be achieved. Furthermore, in the light detecting device 1 according to the first modified example of the third embodiment, an insulating isolation region 29 made of an insulating material is provided between the sidewall 25f of the recessed portion 25d of the trench separating wall 25 and the first semiconductor region 20a1. Therefore, silicon can be epitaxially grown while the polycrystalline silicon material included in the trench separating wall 25 is covered by the insulating isolation region 29, and silicon can be grown only on the sidewall 25f and the surface 20c. In this manner, abnormal growth of silicon crystals on the sidewall 25f of the trench separating wall 25 can be suppressed.

[0131] <Second Modification> exist Figure 27 In the photodetection device 1 according to the second modified example of the third embodiment shown, the first semiconductor region 20a1FD having the charge accumulation region FD does not have a ring shape, and similarly to the case of the first embodiment, the first semiconductor region 20a1FD includes four portions provided for each unit region 20a. Note that the first semiconductor region 20a1FD may be provided with a contact region 24 instead of the charge accumulation region FD.

[0132] In order to divide the first semiconductor region 20a1FD into four parts, it is only necessary to Figure 21 The size of the opening R3a1 and the opening R3a2 of the resist pattern R3 shown in the figure in the X direction and the size in the Y direction of the opening R3a2 are set to be larger than the size of the opening R3a1 in the X direction (the width direction of the trench separation wall 25). In this way, the time required for the first semiconductor regions 20a1 grown on the opposing surfaces 20c to connect to each other can be made longer at the location where the first semiconductor region 20a1FD is provided than at the location where the first semiconductor region 20a1PH is provided. In this way, at the moment when a connected first semiconductor region 20a1PH is obtained, the first semiconductor region 20a1FD is still in a state of not being connected, and a Figure 27 The first semiconductor region 20a1FD is shown.

[0133] Even with the light detecting device 1 according to the second modified example of the third embodiment, effects similar to those of the light detecting device 1 according to the third embodiment described above can be obtained. In addition, in the light detecting device 1 according to the second modified example of the third embodiment, the electrode 70 having a shape similar to that in the first embodiment can be provided.

[0134] <Third Modification> exist Figure 28 In the illustrated photodetection device 1 according to the third modification of the third embodiment, the first semiconductor regions 20a1FD configuring the charge storage region FD may be connected in a ring shape and may include a cross-shaped gap at the center.

[0135] Even with the light detecting device 1 according to the third modification of the third embodiment, effects similar to those of the light detecting device 1 according to the third embodiment described above can be obtained. In addition, in the light detecting device 1 according to the third modification of the third embodiment, the electrode 70 having a shape similar to that in the first embodiment can be provided.

[0136] <Fourth Modification> Although the trench separation wall 25 is configured to include the insulating film 25a and the polysilicon 25b in the third embodiment, the present technology is not limited thereto. For example, the trench separation wall 25 included in the light detecting device 1 according to the fourth modification of the third embodiment may be configured only from a known insulating film such as silicon oxide.

[0137] Even with the light detection device 1 according to the fourth variation of the third embodiment, effects similar to those of the light detection device 1 according to the third embodiment described above can be achieved. In this variation, the trench separation wall 25 is constructed solely of silicon oxide having a refractive index lower than that of the path PH, the end of the trench separation wall 25 faces the second surface S2, and no path PH having a high refractive index is provided on the color filter 62 side. Therefore, when considering light sequentially passing through the microlens 64, the color filter 62, and the trench separation wall 25, the light passes through the microlens 64 and the color filter 62, which have a refractive index lower than that of the path PH, and then directly enters the trench separation wall 25 without being disturbed by regions having a high refractive index. In this way, light enters from a low refractive index region to a low refractive index region, thereby suppressing reflection and scattering of light when it enters the trench separation wall 25.

[0138] [Fourth embodiment] <1. Application Examples in Electronic Devices> Then, Figure 29 The electronic device 100 according to the fourth embodiment of the present technology is described below. The electronic device 100 includes a solid-state imaging device 101, an optical lens 102, a shutter device 103, a drive circuit 104, and a signal processing circuit 105. For example, the electronic device 100 may be an electronic device such as a camera, but is not limited thereto. The electronic device 100 includes the aforementioned light detection device 1 as the solid-state imaging device 101.

[0139] The optical lens (optical system) 102 forms an image of the image light (incident light 106) from the subject on the imaging surface of the solid-state imaging device 101. As a result, signal charge accumulates within the solid-state imaging device 101 for a certain period of time. The shutter device 103 controls the periods of light exposure and light shielding of the solid-state imaging device 101. The drive circuit 104 supplies drive signals that control the transmission operation of the solid-state imaging device 101 and the shutter operation of the shutter device 103. Signal transmission in the solid-state imaging device 101 is performed using the drive signals (timing signals) supplied by the drive circuit 104. The signal processing circuit 105 performs various signal processing on the signals (pixel signals) output from the solid-state imaging device 101. The video signals that have undergone signal processing are stored in a storage medium such as a memory or output to a monitor.

[0140] With this configuration, the electronic device 100 includes the first semiconductor region 20a1 provided on the surface of the insulating region 26 opposite to the trench separation wall 25 side in the solid-state imaging device 101, thereby improving the image quality of the video signal.

[0141] It should be noted that the electronic device 100 is not limited to a camera and may be other electronic devices. For example, the electronic device 100 may be an imaging device such as a camera module for a mobile device such as a mobile phone.

[0142] In addition, the electronic device 100 may include a light detection device 1 according to any one of the first to third embodiments and their variations, and a light detection device 1 according to a combination of at least two of the first to third embodiments and their variations as a solid-state imaging device 101.

[0143] [Other implementation plans] As described above, although the present technology has been described with reference to the first to fourth embodiments, the description and drawings forming part of this disclosure should not be construed as limiting this technology. It is obvious to those skilled in the art that various alternative embodiments, examples, and application technologies can be obtained based on this disclosure.

[0144] For example, the technical concepts described in the first through fourth embodiments can be combined. For example, while the light detecting device 1 according to the sixth variation of the first embodiment described above includes only two semiconductor layers, this technical concept can be applied to the light detecting devices 1 described in the second and third embodiments. Furthermore, while the light detecting device 1 according to the third embodiment described above includes a phase difference detection unit 80, this technical concept can be applied to the light detecting devices 1 described in the first and second embodiments, and various combinations based on the respective technical concepts are possible.

[0145] This technology is generally applicable to light detection devices, including distance-measuring sensors, also known as time-of-flight (ToF) sensors, as well as solid-state imaging devices such as those described above, which serve as image sensors. A distance-measuring sensor emits illumination light toward an object, detects reflected light from the object's surface, and calculates the distance to the object based on the time of flight from the emission of the illumination light to the receipt of the reflected light. The distance-measuring sensor can employ the structure of the pixel 3 described above.

[0146] In addition, for example, the materials listed above as the configuration constituent elements may include additives and impurities.

[0147] In this manner, it is needless to say that the present technology includes various embodiments and the like that are not described herein. Therefore, the technical scope of the present technology is limited only by the inventive specific matters described in the claims according to the above description.

[0148] Furthermore, the effects described in this specification are merely exemplary and are not intended to be limiting, and other effects may also be provided.

[0149] The present technology can be configured as follows. (1) A light detection device comprising: a first semiconductor layer including one surface serving as an element formation surface and the other surface serving as a light incident surface, and including a plurality of unit regions arranged in a matrix in row and column directions in a plan view; a trench separation wall that divides the unit area; and an insulating region, the insulating region being provided at an end portion of the trench separation wall close to the element forming surface, the dimension of the insulating region in the width direction being larger than the dimension of the trench separation wall in the width direction in a plan view, and the insulating region being made of an insulating material, A photoelectric conversion unit is constructed in each of the unit regions, and Each of the cell regions includes a first semiconductor region provided on a surface of the insulating region on a side opposite to a surface on a side of the trench separation wall. (2) The light detection device according to (1), further comprising: an electrode comprising a trunk and a head, wherein a surface of the head is connected to an end of the trunk, A charge accumulation region is constructed in a region of each of the unit regions including at least a portion of the first semiconductor region. The other end of the trunk portion contacts the surface of the insulating region close to the element forming surface, and The electrode contacts the charge accumulation region via the side surface of the trunk and the one surface of the head. (3) The light detection device according to (2), wherein the side surface of the trunk portion and the one surface of the head portion are in contact with the first semiconductor region in which the charge storage region is configured. (4) The photodetection device according to (2) or (3), wherein the electrode is in contact with each of the plurality of charge accumulation regions provided in different unit regions. (5) The light detecting device according to (4), wherein, in a longitudinal cross-sectional view, when a distance between two of the charge accumulation regions facing each other via the trunk portion is defined as b and a size of the insulating region in the horizontal direction is defined as a, a relationship of b < a is satisfied. (6) The light detection device according to (5), wherein, in the longitudinal cross-sectional view, when a dimension of the head in a horizontal direction is defined as c, a relationship of b ≤ c is satisfied. (7) The light detection device according to any one of (4) to (6), wherein, in the four unit regions of two rows and two columns, the charge accumulation regions are provided at mutually facing corners of the unit regions in a plan view, The trunk portion includes a first extending portion and a second extending portion, the first extending portion extending in a row direction and a thickness direction, the second extending portion extending in a column direction and a thickness direction and intersecting the first extending portion in a plan view, and The charge accumulation region is in contact with the trunk portion at a concave corner portion constructed by the first extending portion and the second extending portion. (8) The light detection device according to any one of (2) to (7), further comprising: a contact electrode comprising a contact body and a contact head, wherein one surface of the contact head is connected to one end of the contact body, wherein a contact region fixed to a reference potential via the contact electrode is constructed in a region including at least a portion of the first semiconductor region in each of the cell regions; The other end of the contact body portion contacts the surface of the insulating region close to the element forming surface, and The contact electrode contacts the contact area via a side surface of the contact body and the one surface of the contact head. (9) The light detecting device according to any one of (2) to (8), wherein the insulating region is provided over all positions where the trench separation walls are provided in a plan view. (10) The light detection device according to any one of (2) to (9), wherein the first semiconductor region is provided over the entire edge portion of each of the unit regions on the element formation surface. (11) The light detection device according to any one of (2) to (9), wherein the first semiconductor region is provided only at a corner portion of each of the unit regions on the element formation surface. (12) The photodetection device according to any one of (2) to (11), wherein each of the charge accumulation regions is configured by a region of each of the unit regions including only the first semiconductor region, and the entire charge accumulation region overlaps with the insulating region in a plan view. (13) The light detection device according to (12), wherein, in a longitudinal cross-sectional view, when the distance between the two charge accumulation regions facing each other via the trunk is defined as b, the size of the head in the horizontal direction is defined as c, and the size of each charge accumulation region in the horizontal direction is defined as d, the relationship c ≥ 2d + b is satisfied. (14) The light detecting device according to (12) or (13), wherein, in a longitudinal cross-sectional view, a width occupied in the horizontal direction by the two charge accumulation regions facing each other via the trunk portion is equal to or smaller than a size in the horizontal direction of the insulating region in the cross-sectional view. (15) The light detection device according to (1), further comprising: a phase difference detection section including two adjacent unit regions and a path through which signal charges can move between the two adjacent unit regions; Wherein, when a portion of the trench separation wall located between the two unit regions in the phase difference detection portion is defined as a first trench separation wall, the first semiconductor region is provided at a position where the first semiconductor region overlaps with the first trench separation wall in a plan view, and connects the two unit regions in the phase difference detection portion, and The path is formed in the first semiconductor region. (16) The light detection device according to (15), wherein the end portion of the first trench separation wall on the element forming surface side has a portion that is recessed in the thickness direction compared to other portions, and The insulating region and the first semiconductor region are provided only at the recessed portion of the end portion. (17) The light detecting device according to (16), wherein an insulating isolation region made of an insulating material is provided between a side wall of the recessed portion of the first trench separation wall and the first semiconductor region. (18) The light detection device according to any one of (2) to (8) and (12) to (17), The end portion of the trench separation wall located on the element forming surface side has a portion that is recessed in the thickness direction compared to other portions. The insulating region and the first semiconductor region are provided only at the recessed portion of the end portion, and The charge storage region or the contact region fixed to a reference potential is formed in the first semiconductor region. (19) The light detecting device according to (18), wherein an insulating isolation region made of an insulating material is provided between a side wall of the recessed portion of the trench separation wall and the first semiconductor region. (20) An electronic device comprising: a light detection device; and an optical system that forms an image of image light from a subject on the light detection device, Wherein, the light detection device includes: a first semiconductor layer including one surface serving as an element formation surface and the other surface serving as a light incident surface, and including a plurality of unit regions arranged in a matrix in row and column directions in a plan view; a trench separation wall that divides the unit area; and an insulating region, the insulating region being provided at an end portion of the trench separation wall close to the element forming surface, the dimension of the insulating region in the width direction being larger than the dimension of the trench separation wall in the width direction in a plan view, and the insulating region being made of an insulating material, A photoelectric conversion unit is constructed in each of the unit regions, and Each of the cell regions includes a first semiconductor region provided on a surface of the insulating region on a side opposite to a surface on a side of the trench separation wall.

[0150] The scope of the present technology is not limited to the exemplary embodiments shown and described, but includes all embodiments that provide effects equivalent to those sought by the present technology. In addition, the scope of the present technology is not limited to the combination of inventive features defined in the claims, but can be defined by any desired combination of specific features among all disclosed features. Reference Signs List

[0151] 1. Light detection device 20 first semiconductor layer 20a, 20aL, 20aR unit areas 20a1, 20a1FD, 20a1PH first semiconductor region 20b separation area 24 contact area (semiconductor area) 25 groove separation wall 25c first groove separation wall 25d recessed part 25f sidewall 26 insulation areas 29 Insulation separation area 70 electrodes 70 contact electrodes 71 trunk 71 Contact with the trunk 71x first extension 71y second extension 72 head 72 Contact with head 80 phase difference detection unit 100 electronic devices 102 Optical System a size b distance c-size d size FD charge accumulation area pH path W1, W2 size

Claims

1. A light detection device, comprising: a first semiconductor layer including one surface serving as an element formation surface and the other surface serving as a light incident surface, and including a plurality of unit regions arranged in a matrix in row and column directions in a plan view; A groove separation wall, wherein the groove separation wall divides the unit area; and an insulating region, the insulating region being provided at an end portion of the trench separation wall close to the element forming surface, the dimension of the insulating region in the width direction being larger than the dimension of the trench separation wall in the width direction in a plan view, and the insulating region being made of an insulating material, A photoelectric conversion unit is constructed in each of the unit regions, and Each of the cell regions includes a first semiconductor region provided on a surface of the insulating region on a side opposite to a surface on a side of the trench separation wall.

2. The light detection device according to claim 1, further comprising: an electrode comprising a trunk and a head, wherein a surface of the head is connected to an end of the trunk, A charge accumulation region is constructed in a region of each of the unit regions including at least a portion of the first semiconductor region. The other end of the trunk portion contacts the surface of the insulating region close to the element forming surface, and The electrode contacts the charge accumulation region via the side surface of the trunk and the one surface of the head.

3. The light detection device according to claim 2, wherein The side surface of the trunk portion and the one surface of the head portion are in contact with the first semiconductor region in which the charge storage region is configured.

4. The light detection device according to claim 2, wherein The electrode is in contact with each of the plurality of charge accumulation regions provided in different cell regions.

5. The light detection device according to claim 4, wherein In the longitudinal cross-sectional view, when the distance between the two charge accumulation regions facing each other via the trunk portion is defined as b and the size of the insulating region in the horizontal direction is defined as a, a relationship of b<a is satisfied. The light detection device according to claim 5 , wherein: In the longitudinal cross-sectional view, when the dimension of the head in the horizontal direction is defined as c, a relationship of b≦c is satisfied.

7. The light detection device according to claim 4, in, In the four unit regions of two rows and two columns, the charge accumulation regions are provided at mutually facing corners of the unit regions in a plan view, The trunk portion includes a first extending portion and a second extending portion, the first extending portion extending in a row direction and a thickness direction, the second extending portion extending in a column direction and a thickness direction and intersecting the first extending portion in a plan view, and The charge accumulation region is in contact with the trunk portion at a concave corner portion constructed by the first extending portion and the second extending portion.

8. The light detection device according to claim 2, further comprising: a contact electrode comprising a contact body and a contact head, wherein one surface of the contact head is connected to one end of the contact body, wherein a contact region fixed to a reference potential via the contact electrode is constructed in a region including at least a portion of the first semiconductor region in each of the cell regions; The other end of the contact body portion contacts the surface of the insulating region close to the element forming surface, and The contact electrode contacts the contact area via a side surface of the contact body and the one surface of the contact head.

9. The light detection device according to claim 2, wherein The insulating region is provided over all positions where the trench separation walls are provided in a plan view.

10. The light detection device according to claim 2, wherein The first semiconductor region is provided on the element forming surface over the entire edge portion of each of the cell regions.

11. The light detection device according to claim 2, wherein The first semiconductor region is provided only at the corner portion of each of the cell regions on the element forming surface.

12. The light detection device according to claim 2, wherein Each of the charge accumulation regions is configured by a region of each of the unit regions including only the first semiconductor region, and the entire charge accumulation region overlaps with the insulating region in a plan view.

13. The light detection device according to claim 12, wherein In the longitudinal cross-sectional view, when the distance between the two charge accumulation areas facing each other via the trunk is defined as b, the size of the head in the horizontal direction is defined as c, and the size of each charge accumulation area in the horizontal direction is defined as d, the relationship c ≥ 2d + b is satisfied.

14. The light detection device according to claim 12, wherein In a longitudinal cross-sectional view, the width occupied in the horizontal direction by the two charge accumulation regions facing each other via the trunk portion is equal to or smaller than the size of the insulating region in the horizontal direction in the cross-sectional view.

15. The light detection device according to claim 1, further comprising: a phase difference detection section including two adjacent unit regions and a path through which signal charges can move between the two adjacent unit regions; Wherein, when a portion of the trench separation wall located between the two unit regions in the phase difference detection portion is defined as a first trench separation wall, the first semiconductor region is provided at a position where the first semiconductor region overlaps with the first trench separation wall in a plan view, and connects the two unit regions in the phase difference detection portion, and The path is formed in the first semiconductor region.

16. The light detection device according to claim 15, in, The end portion of the first trench separation wall on the element forming surface side has a portion that is recessed in the thickness direction compared to other portions, and The insulating region and the first semiconductor region are provided only at the recessed portion of the end portion.

17. The light detection device according to claim 16, wherein An insulating isolation region made of an insulating material is provided between a side wall of the recessed portion of the first trench separator and the first semiconductor region.

18. The light detection device according to claim 2, in, The end portion of the trench separation wall on the element forming surface side has a portion that is recessed in the thickness direction compared to other portions. The insulating region and the first semiconductor region are provided only at the recessed portion of the end portion, and The charge storage region or the contact region fixed to a reference potential is formed in the first semiconductor region.

19. The light detection device according to claim 18, wherein An insulating isolation region made of an insulating material is provided between a side wall of the recessed portion of the trench separation wall and the first semiconductor region.

20. An electronic device comprising: light detection device; and an optical system that forms an image of image light from a subject on the light detection device, Wherein, the light detection device includes: a first semiconductor layer including one surface serving as an element formation surface and the other surface serving as a light incident surface, and including a plurality of unit regions arranged in a matrix in row and column directions in a plan view; a trench separation wall that divides the unit area; and an insulating region, the insulating region being provided at an end portion of the trench separation wall close to the element forming surface, the dimension of the insulating region in the width direction being larger than the dimension of the trench separation wall in the width direction in a plan view, and the insulating region being made of an insulating material, A photoelectric conversion unit is constructed in each of the unit regions, and Each of the cell regions includes a first semiconductor region provided on a surface of the insulating region on a side opposite to a surface on a side of the trench separation wall.

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