Bus-type PLC (Programmable Logic Controller) double-CPU (Central Processing Unit) hot standby redundant system

Abstract

The invention discloses a bus type PLC (Programmable Logic Controller) double-CPU (Central Processing Unit) hot standby redundant system, and belongs to the technical field of industrial automation. The system comprises a first CPU module, a second CPU module, a plurality of IO modules, an LVDS bus communication unit, a synchronous communication unit, a role determination unit, a bus scanning unit, a data synchronization unit, a state monitoring unit and a switching control unit. According to the distributed redundancy system, high-speed redundancy switching can be achieved, and the distributed redundancy system is high in fault isolation performance and good in expansibility.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of industrial automation, and particularly relates to a bus type PLC dual-CPU hot backup redundancy system. BACKGROUND

[0002] Programmable logic controller (PLC) systems in the field of industrial automation often use dual-CPU redundancy architecture to improve reliability, that is, one main CPU module performs control, and another hot backup CPU module synchronizes data in real time and takes over when the main module fails. In the prior art, there is a design of installing dual-CPU modules in close proximity, aiming to maximize internal communication speed by shortening the physical distance to achieve fast synchronization of states.

[0003] However, this close-neighbor design concentrates redundant resources in one domain, and the robustness of the system topology has inherent limitations. When the master control end fails seriously, local electromagnetic interference or power disturbance may occur, and since the two CPUs are too close in physical location, this failure is easily spread to the hot backup module, resulting in the risk of simultaneous downtime of the dual system, and effective fault isolation is not achieved. In addition, the scalability of this architecture is poor, and when new IO devices are added, their signals need to be transmitted long distances to the central processor, increasing delay and attenuation, making it difficult to adapt to distributed and modular industrial field layouts.

[0004] Therefore, how to construct a distributed redundancy system that can realize high-speed redundancy switching, has high fault isolation and good scalability, has become a technical problem to be solved. SUMMARY

[0005] The embodiment of the present application provides a bus type PLC dual-CPU hot backup redundancy system, which solves the technical problem of how to construct a distributed redundancy system that can realize high-speed redundancy switching, has high fault isolation and good scalability.

[0006] In a first aspect, the embodiments of the present application provide a bus type PLC dual-CPU hot backup redundancy system, which comprises: a first CPU module and a second CPU module, which are used as a master role and a hot backup role; a plurality of IO modules, which are used to collect external sensor signals and device parameter data and output control instruction data; an LVDS bus communication unit, which is used to connect the first CPU module, the second CPU module and the plurality of IO modules at the head end and the tail end to form a ring network topology, so as to realize bidirectional data transmission; a synchronous communication unit, which is used to establish a synchronous communication connection between the first CPU module and the second CPU module, so as to transmit heartbeat signals and bus scanning result data; a role determination unit, which is used to determine a master role CPU module and a hot backup role CPU module in the first CPU module and the second CPU module based on a preset rule negotiation; a bus scanning unit, which is used to scan the LVDS bus by the master role CPU module to obtain address information and state data of the plurality of IO modules, and generate bus scanning result; a data synchronization unit, which is used to synchronize the bus scanning result to the hot backup role CPU module by the master role CPU module, so that the hot backup role CPU module obtains IO module information data; a state monitoring unit, which is used to monitor working state data of the master role CPU module through heartbeat signal data transmitted by the synchronous communication unit; and a switching control unit, which is used to trigger the hot backup role CPU module to switch from a standby state to a master working state and take over LVDS bus communication and control instruction output data when a fault of the master role CPU module is detected.

[0007] In an implementation manner of the present application, the role determination unit comprises: obtaining version number data of the first CPU module and version number data, address code data or serial number data of the second CPU module; determining the master role and the hot backup role based on the version number data to generate role allocation data; or determining the master role and the hot backup role based on the address code data to generate role allocation data; or determining the master role and the hot backup role based on the serial number data to generate role allocation data; outputting the role allocation data to a preset system configuration unit; based on the role allocation data, enabling the LVDS bus communication function of the master role CPU module and disabling the LVDS bus communication function of the hot backup role CPU module.

[0008] In an implementation manner of the present application, the bus scanning unit comprises: sending scanning instruction data to the LVDS bus by the master role CPU module; receiving response data returned by the plurality of IO modules, wherein the response data comprises address code data and current state data of each IO module; generating bus scanning result based on the response data, wherein the bus scanning result comprises an address list and state report data of all IO modules; and storing the bus scanning result to a memory unit of the master role CPU module.

[0009] In one implementation of the present application, the data synchronization unit specifically includes: obtaining the bus scan result data stored in the master role CPU module; the bus scan result data includes the address information and status data of multiple IO modules; transmitting the bus scan result data to the hot standby role CPU module through the synchronization communication unit; after the hot standby role CPU module receives and stores the bus scan result data, generating synchronization completion confirmation data; based on the synchronization completion confirmation data, updating the IO module information data stored in the hot standby role CPU module, so that the hot standby role CPU module has all the IO module information required to take over control.

[0010] In one implementation of the present application, the status monitoring unit specifically includes: the main control role CPU module generates heartbeat signal data according to a preset period; the heartbeat signal data is sent to the hot standby role CPU module through the synchronous communication unit; after the hot standby role CPU module receives the heartbeat signal data, the interval time data between adjacent heartbeat signals is monitored; if the interval time data exceeds the preset time threshold, the hot standby role CPU module generates survival query instruction data and sends it to the main control role CPU module; based on whether the response data returned by the main control role CPU module is received, the fault status data of the main control role CPU module is judged.

[0011] In one implementation of the present application, the switching control unit specifically includes: receiving fault status data from the status monitoring unit, the fault status data indicating that the main control role CPU module has failed; based on the fault status data, disabling the LVDS bus communication function of the original main control role CPU module; enabling the LVDS bus communication function of the hot standby role CPU module, so that the hot standby role CPU module takes over the communication management rights of the LVDS bus; generating control instruction data based on the stored IO module information data through the hot standby role CPU module and outputting it to multiple IO modules; sending fault alarm information data to the host computer through the hot standby role CPU module.

[0012] In one implementation of the present application, the synchronous communication unit is used to establish a synchronous communication connection between the first CPU module and the second CPU module, specifically including: connecting the first CPU module and the second CPU module through a physical synchronous port; transmitting a synchronous data packet based on the synchronous port; the synchronous data packet includes heartbeat signal data and bus scan result data; performing data verification during data transmission to generate verification result data; and adjusting the transmission rate data based on the verification result data.

[0013] In an implementation manner of the present application, the LVDS bus communication unit specifically comprises: the first CPU module is installed at a head end position of the LVDS bus, and the second CPU module is installed at an end position; a plurality of IO modules are connected through LVDS differential signal lines to form a closed-loop network structure; a bus communication timing data is managed by the master role CPU module; in a data transmission process, a two-way data flow of the LVDS bus is processed by the first CPU module or the second CPU module to generate communication control data; and bandwidth usage data of the LVDS bus is optimized based on the communication control data.

[0014] In an implementation manner of the present application, the plurality of IO modules specifically comprise: sensor signal data is received through input ports of the plurality of IO modules; the sensor signal data at least comprises temperature data, pressure data and liquid level data; device parameter report data is determined based on the sensor signal data; control instruction data is sent to external devices through output ports of the plurality of IO modules; the control instruction data at least comprises motor start-stop instructions and valve control instructions; and output state data is updated based on instruction data from the master role CPU module to control the external devices.

[0015] In an implementation manner of the present application, the switching control unit is further used for taking over the control work by the original master role CPU module after the hot standby role CPU module fails, and specifically comprises: when detecting the failure state data of the hot standby role CPU module, the LVDS bus communication function of the hot standby role CPU module is disabled; the LVDS bus communication function of the original master role CPU module is re-enabled, so that the original master role CPU module is switched to a master working state; control instruction data is output to the plurality of IO modules based on the stored IO module information data by the original master role CPU module; and switching completion notification data is sent to the upper computer to update system running state information.

[0016] The bus type PLC dual-CPU hot standby redundancy system provided by the embodiments of the present application has at least the following technical effects: By arranging the first CPU module and the second CPU module at the head end and the end of the LVDS ring network bus respectively, the signal transmission path and the fault isolation capability are effectively optimized. The layout structure not only shortens the communication distance between each IO module and any CPU module, but also can quickly take over the bus control right by the CPU at the other end when a CPU module fails, greatly reducing the communication delay and reconstruction time caused by switching, and significantly reducing the time cost and performance fluctuation in the system switching process.

[0017] By adopting LVDS communication technology, common mode noise can be effectively suppressed in high-speed data transmission process, signal integrity is improved, especially in complex electromagnetic environment in industrial field, the stability and accuracy of communication between the main control CPU module, hot standby CPU module and multiple IO modules are effectively ensured, and the risk of communication failure caused by signal attenuation or interference is reduced.

[0018] The dual CPU module works in a hot standby redundancy mode, and in combination with real-time heartbeat monitoring and fast switching mechanism, the control right can be quickly and smoothly transferred to the hot standby CPU when the main control CPU fails, the interruption time is greatly shortened, the entire control is prevented from being paralyzed due to single point failure, and the uninterrupted operation of the key industrial process is ensured.

[0019] Through the independent synchronous communication unit, the main control CPU can synchronize the bus scanning result, device state and running data to the hot standby CPU in time, so that the hot standby CPU always maintains the same state information as the main control CPU. Not only the re-scanning and configuration time in the switching process is reduced, but also the control logic error or output abnormality caused by asynchronous information is avoided.

[0020] Modular design allows users to flexibly configure the number and type of IO modules according to actual needs, and the ring network bus structure also facilitates the access and expansion of subsequent devices. At the same time, with the functions of fault reporting and state notification, alarm information can be sent to the upper computer in time to help operation and maintenance personnel quickly locate and handle faults, and reduce maintenance complexity and time cost. BRIEF DESCRIPTION OF DRAWINGS

[0021] The drawings described herein are used to provide further understanding of the present application, and form a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application, and do not constitute an improper limitation on the present application. In the drawings: Figure 1 A schematic diagram of a bus type PLC dual CPU hot standby redundancy system is provided. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme of the present application will be described clearly and completely in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0023] The embodiment of the present application provides a bus type PLC dual CPU hot standby redundancy system, which solves the technical problem of how to construct a distributed redundancy system which can realize high-speed redundancy switching, has high fault isolation and good expansibility.

[0024] The technical solutions provided by the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0025] Figure 1 A bus type PLC dual-CPU hot backup redundancy system schematic diagram is provided by the embodiments of the present application. As shown in the figure, the bus type PLC dual-CPU hot backup redundancy system provided by the embodiments of the present application specifically includes: Figure 1 a first CPU module and a second CPU module, used as a master role and a hot backup role; a plurality of IO modules, used for collecting external sensor signals and device parameter data, and outputting control instruction data; an LVDS bus communication unit, used for connecting the first CPU module, the second CPU module and the plurality of IO modules to form a ring network topology structure at the head end and the tail end, so as to realize bidirectional data transmission; a synchronous communication unit, used for establishing a synchronous communication connection between the first CPU module and the second CPU module, so as to transmit heartbeat signals and bus scanning result data; a role determination unit, used for determining a master role CPU module and a hot backup role CPU module in the first CPU module and the second CPU module based on a preset rule negotiation; a bus scanning unit, used for scanning the LVDS bus by the master role CPU module to obtain address information and state data of the plurality of IO modules, and generating a bus scanning result; a data synchronization unit, used for synchronizing the bus scanning result to the hot backup role CPU module by the master role CPU module, so that the hot backup role CPU module obtains IO module information data; a state monitoring unit, used for monitoring working state data of the master role CPU module through heartbeat signal data transmitted by the synchronous communication unit; a switching control unit, used for triggering the hot backup role CPU module to switch from a standby state to a master working state and to take over LVDS bus communication and control instruction output data when a fault of the master role CPU module is detected.

[0026] ​The role determination unit includes: obtaining version number data of the first CPU module and version number data, address code data or serial number data of the second CPU module; determining the master role and the hot standby role based on the version number data to generate role allocation data; or determining the master role and the hot standby role based on the address code data to generate role allocation data; or determining the master role and the hot standby role based on the serial number data to generate role allocation data; outputting the role allocation data to a preset system configuration unit; based on the role allocation data, enabling the LVDS bus communication function of the master role CPU module and disabling the LVDS bus communication function of the hot standby role CPU module.

[0027] First, the version number data of the first CPU module and the version number data, address code data or serial number data of the second CPU module are acquired.

[0028] Version data refers to the firmware or hardware version of the CPU module and is used to distinguish module update status. Address code data uniquely identifies the module in the hardware configuration, such as through jumpers or software settings. Serial number data is a unique number assigned during production that identifies the module. This data is typically stored in nonvolatile memory, such as EEPROM or Flash, and is read when the system is powered on.

[0029] In a specific example, during system startup, the first CPU module (CPU-A) reads version number V2.1 from its EEPROM, while the second CPU module (CPU-B) reads version number V2.0. At the same time, the address code of CPU-A is 0x01, and the address code of CPU-B is 0x02, with serial numbers SN12345 and SN12346, respectively. This data is loaded into memory for use by the role determination unit.

[0030] Further, the master role and hot standby role are determined based on the version number data to generate role allocation data; or the master role and hot standby role are determined based on the address code data to generate role allocation data; or the master role and hot standby role are determined based on the serial number data to generate role allocation data.

[0031] The default rule can be: the module with the higher version number is the master, the module with the lower address code is the master, or the module with the higher serial number is the master. The rule selection is achieved through the system configuration parameters.

[0032] In a specific example, the system is configured to determine roles based on version numbers. CPU-A's version number, V2.1, is higher than CPU-B's, V2.0. Therefore, CPU-A is assigned the master role, and CPU-B the hot standby role. Role assignment data is generated as a data structure containing the role type (master or hot standby) and module identifiers (e.g., address codes) and stored in a temporary buffer.

[0033] Further, output the role assignment data to a preset system configuration unit.

[0034] The system configuration unit is a shared memory area or a configuration register, which is used to store system state information for access by other units. After the role assignment data is written, each part of the system can read it to understand the current role assignment.

[0035] In a specific example, the role determination unit writes role assignment data (such as {master: CPU-A, hot standby: CPU-B}) to a specific address 0x1000 of a dual-port RAM, which is marked as a system configuration area and can be accessed by CPU-A and CPU-B.

[0036] Further, based on the role assignment data, enable the LVDS bus communication function of the master role CPU module and disable the LVDS bus communication function of the hot standby role CPU module.

[0037] Enable and disable are achieved by controlling the enable signal of the LVDS bus driver: the driver of the master role is enabled, and can send and receive data; the driver of the hot standby role is disabled, and can only receive data but cannot send, to avoid bus conflict.

[0038] In a specific example, CPU-A acts as a master role, and the enable pin of its LVDS bus controller is set to high level to activate the bus driver; CPU-B acts as a hot standby role, and the enable pin is set to low level, so that the bus driver enters a high impedance state and can only listen to bus data.

[0039] The bus scanning unit includes: sending scanning instruction data to the LVDS bus by the master role CPU module; receiving response data returned by multiple IO modules, the response data including address code data and current state data of each IO module; generating bus scanning results based on the response data, the bus scanning results including address list and state report data of all IO modules; storing the bus scanning results in the memory unit of the master role CPU module.

[0040] First, send scanning instruction data to the LVDS bus by the master role CPU module.

[0041] The scanning instruction data is a broadcast frame containing a specific command code (such as 0x55 indicating a scanning request), which is sent to all devices on the bus to request response.

[0042] In a specific example, the master role CPU module (CPU-A) sends a broadcast frame through the LVDS bus, with a command code of 0x55 and a specified address range of 0x00 to 0xFF to cover all possible IO modules.

[0043] Further, the response data returned by the plurality of IO modules is received, and the response data includes address code data and current state data of each IO module.

[0044] Upon receiving the scanning instruction, each IO module returns a response packet in the allocated time slot, which contains its unique address code and state data (such as input value, error flag).

[0045] In a specific example, IO module 1 (address 0x10) returns a response packet including address 0x10 and state word 0x00 (normal), and IO module 2 (address 0x11) returns address 0x11 and state word 0x01 (overheating warning). CPU-A receives these responses and parses them.

[0046] Further, the bus scan result is generated based on the response data, and the bus scan result includes an address list of all IO modules and state report data.

[0047] The master CPU module collects all responses, creates a data structure (such as a linked list or array), lists the addresses and states of all responding IO modules, and marks non-responding modules as offline or faulty.

[0048] In a specific example, CPU-A integrates the response data to generate a bus scan result: a table containing entries address 0x10 (normal state), address 0x11 (warning state), and address 0x12 (no response, marked as faulty). The result also includes a timestamp and bus load information.

[0049] Further, the bus scan result is stored in the memory unit of the master CPU module.

[0050] The memory unit can be internal RAM or Flash, used for temporary storage or persistence, for subsequent access and synchronization.

[0051] In a specific example, CPU-A stores the bus scan result at address 0x2000 in its internal SRAM and simultaneously writes it to a Flash sector for backup, ensuring that it can be restored after a system restart.

[0052] The data synchronization unit specifically includes: obtaining bus scan result data stored in the master CPU module; the bus scan result data includes address information and state data of a plurality of IO modules; transmitting the bus scan result data to the hot standby CPU module through the synchronization communication unit; after the hot standby CPU module receives and stores the bus scan result data, generating synchronization completion confirmation data; based on the synchronization completion confirmation data, updating the IO module information data stored in the hot standby CPU module, so that the hot standby CPU module has all the IO module information required for takeover control.

[0053] Firstly, the bus scan result data stored in the master CPU module is acquired; the bus scan result data contains address information and state data of multiple IO modules.

[0054] The master CPU module reads the bus scan result data from the memory and prepares for transmission.

[0055] In a specific example, CPU-A reads the bus scan result data from the memory address 0x2000, which includes the IO module address list, state byte and checksum.

[0056] Further, the bus scan result data is transmitted to the backup CPU module through the synchronous communication unit.

[0057] The synchronous communication unit is a dedicated communication link (such as SPI or UART) for high-speed data transmission between CPUs.

[0058] In a specific example, the synchronous communication unit is configured as an SPI bus, CPU-A as the SPI master device, and CPU-B as the slave device. CPU-A sends the bus scan result data in packets, each packet containing a header and tail flag and CRC check.

[0059] Further, after the backup CPU module receives and stores the bus scan result data, it generates synchronization completion confirmation data.

[0060] After receiving the data, the backup CPU module stores it in its memory and sends an acknowledgement signal (such as an ACK byte) to indicate successful reception.

[0061] In a specific example, CPU-B receives the data and stores it in its RAM address 0x3000, then sends an acknowledgement byte 0xAA to CPU-A through SPI.

[0062] Further, based on the synchronization completion confirmation data, the IO module information data stored in the backup CPU module is updated to enable the backup CPU module to have all the IO module information required to take over control.

[0063] The backup CPU module updates its internal IO database based on the synchronization data to ensure consistency with the master CPU and prepare for possible switching.

[0064] In a specific example, CPU-B parses the stored bus scan result, updates its IO configuration table, marks online modules and faulty modules, and calculates control parameters, thereby preparing to take over the control task.

[0065] The state monitoring unit specifically comprises: heartbeat signal data generated by the master CPU module at a preset period; the heartbeat signal data is sent to the hot standby CPU module through the synchronous communication unit; after the hot standby CPU module receives the heartbeat signal data, interval time data between adjacent heartbeat signals is monitored; if the interval time data exceeds a preset time threshold, survival inquiry instruction data is generated by the hot standby CPU module and sent to the master CPU module; based on whether response data returned by the master CPU module is received, fault state data of the master CPU module is judged.

[0066] Firstly, heartbeat signal data is generated by the master CPU module at a preset period.

[0067] The heartbeat signal data is a simple message (such as a pulse or a specific byte) sent periodically to indicate that the master CPU module is running normally.

[0068] In a specific example, CPU-A generates a heartbeat signal every 100 milliseconds, with data being byte 0x55, and sends it through the synchronous communication unit.

[0069] Further, the heartbeat signal data is sent to the hot standby CPU module through the synchronous communication unit.

[0070] The heartbeat signal is transmitted through the synchronous communication link to ensure real-time performance.

[0071] In a specific example, CPU-A sends a heartbeat signal data packet to CPU-B through the SPI bus, and the data packet includes a sequence number and a timestamp.

[0072] Further, after the hot standby CPU module receives the heartbeat signal data, interval time data between adjacent heartbeat signals is monitored.

[0073] The hot standby CPU module uses an internal timer to measure the heartbeat interval and compare it with the preset period.

[0074] In a specific example, CPU-B resets the watchdog timer every time it receives a heartbeat signal. The timer is set to 150 milliseconds, and if it times out, an exception handling process is triggered.

[0075] Further, if the interval time data exceeds a preset time threshold, survival inquiry instruction data is generated by the hot standby CPU module and sent to the master CPU module.

[0076] The preset time threshold is slightly greater than the heartbeat period (such as 150 milliseconds for a 100-millisecond period), and after the timeout, the hot standby role sends an inquiry instruction to confirm the master state.

[0077] In one specific instance, if CPU-B does not receive the heartbeat within 150 milliseconds, it sends a query instruction 0xCC to CPU-A through the synchronization communication unit and starts a response timeout timer.

[0078] Further, based on whether the response data returned by the master CPU module is received, the fault state data of the master CPU module is determined.

[0079] If the master CPU module responds to the query, the state is normal; otherwise, it is determined to be faulty, and the fault state data is generated.

[0080] In one specific instance, after CPU-B sends the query, it waits for 50 milliseconds, and if it does not receive a response from CPU-A, it sets a fault flag (e.g., Master_Fault = 1) and notifies the switching control unit.

[0081] The switching control unit specifically includes: receiving fault state data from the state monitoring unit, the fault state data indicating that the master CPU module has failed; based on the fault state data, disabling the LVDS bus communication function of the original master CPU module; enabling the LVDS bus communication function of the hot standby CPU module, so that the hot standby CPU module takes over the communication management right of the LVDS bus; generating control instruction data based on the stored IO module information data through the hot standby CPU module and outputting it to the plurality of IO modules; sending fault alarm information data to the upper computer through the hot standby CPU module.

[0082] First, receive fault state data from the state monitoring unit, the fault state data indicating that the master CPU module has failed.

[0083] The fault state data is a signal or message transmitted through an interrupt or a shared variable.

[0084] In one specific instance, the state monitoring unit sets a global variable Master_Fault to true, and the switching control unit detects the change of the variable through polling or interrupt.

[0085] Further, based on the fault state data, the LVDS bus communication function of the original master CPU module is disabled.

[0086] The bus driver of the original master CPU module is disabled through a hardware control signal to prevent it from interfering with the bus.

[0087] In one specific instance, the switching control unit outputs a signal to the LVDS enable pin of CPU-A, setting it to low to disable the bus driver.

[0088] Further, the LVDS bus communication function of the hot standby role CPU module is enabled, so that the hot standby role CPU module takes over the communication management right of the LVDS bus.

[0089] The bus driver of the hot standby role CPU module is enabled to start sending control frames.

[0090] In a specific example, the LVDS enable pin of CPU-B is set to high level to activate the bus driver, and CPU-B sends a bus reset frame to declare itself as the master role.

[0091] Further, the hot standby role CPU module generates control instruction data based on the stored IO module information data and outputs it to the plurality of IO modules.

[0092] The hot standby role CPU module uses synchronized IO module information (such as address and state) to generate control commands to maintain system operation.

[0093] In a specific example, CPU-B reads the IO module state from memory, calculates the motor speed command according to the control algorithm, and sends it to IO module 1 (address 0x10) for execution through the LVDS bus.

[0094] Further, the hot standby role CPU module sends fault alarm information data to the upper computer.

[0095] The upper computer is a monitoring computer or HMI, and the alarm information is sent through a communication interface (such as Ethernet).

[0096] In a specific example, CPU-B sends a string message to the upper computer through UART: "Master CPU failure, hot standby CPU has taken over, time 2023-10-01 12:00:00".

[0097] The synchronization communication unit is used to establish a synchronous communication connection between the first CPU module and the second CPU module, specifically including: connecting the first CPU module and the second CPU module through a physical synchronization port; transmitting synchronization data packets based on the synchronization port; the synchronization data packet includes heartbeat signal data and bus scanning result data; data verification is performed during data transmission to generate verification result data; the transmission rate data is adjusted based on the verification result data.

[0098] First, connect the first CPU module and the second CPU module through a physical synchronization port.

[0099] The physical synchronization port refers to a dedicated high-speed communication interface, such as an Ethernet port using an RJ45 connector or a customized multi-pin connector, used to establish a point-to-point physical link between two CPU modules.

[0100] In one embodiment, the first CPU module (CPU-A) and the second CPU module (CPU-B) are both equipped with Gigabit Ethernet synchronization ports and are directly connected using shielded twisted pair wires, and the ports are working in full duplex mode to provide a high-bandwidth and low-latency communication channel.

[0101] Further, the synchronization data packets are transmitted based on the synchronization ports; the synchronization data packets include heartbeat signal data and bus scan result data.

[0102] The synchronization data packets are data units framed according to a specific communication protocol, including a frame header, payload data (such as heartbeat signal or bus scan result) and frame tail check part.

[0103] In one embodiment, the CPU-A generates heartbeat signal data (such as a data block containing a timestamp and a status word) every 100 milliseconds, encapsulates the data into a packet according to the UDP protocol, and sends the packet to the CPU-B through the synchronization port; when the bus scan is completed, the scan result is divided into multiple data packets, which are sent to the CPU-B through a TCP-like reliable transmission method.

[0104] Further, data verification is performed during data transmission to generate verification result data.

[0105] The data verification uses cyclic redundancy check (CRC) or parity check and other methods to calculate the verification code for the transmitted data, and the receiver recalculates the verification code based on the received data and compares it with the received verification code to generate the verification result data (such as a "verification success" or "verification failure" flag).

[0106] In one embodiment, the CPU-A calculates the CRC32 verification code for each synchronization data packet before sending it and appends it to the end of the packet; the CPU-B recalculates the CRC32 after receiving it, and if it is consistent with the verification code at the end of the packet, the verification result data is set to "success", otherwise to "failure".

[0107] Further, the transmission rate data is adjusted based on the verification result data.

[0108] If multiple consecutive data packets fail the verification, it is determined that the link quality is poor, and the transmission rate is automatically reduced to improve reliability; if the link quality is stable, the transmission rate is gradually increased to improve efficiency.

[0109] In one embodiment, the synchronization communication unit monitors the verification results of the last 10 data packets, and if the failure rate exceeds 20%, the transmission rate is reduced from 1000 Mbps to 100 Mbps; if 100 consecutive packets pass the verification, the rate is gradually increased back to 1000 Mbps.

[0110] The LVDS bus communication unit specifically comprises: a first CPU module installed at a head end of the LVDS bus, and a second CPU module installed at an end position; a plurality of IO modules connected by LVDS differential signal lines to form a closed loop network structure; a bus communication timing data managed by a master CPU module; during data transmission, a two-way data stream of the LVDS bus processed by the first CPU module or the second CPU module to generate communication control data; and bandwidth usage data of the LVDS bus optimized based on the communication control data.

[0111] First, a first CPU module is installed at a head end of the LVDS bus, and a second CPU module is installed at an end position.

[0112] The head end and the end position refer to the start point and the end point of the physical link of the LVDS bus, and the two CPU modules are respectively located at both ends of the bus, and a plurality of IO modules are connected in series in the middle to form a ring topology.

[0113] In a specific example, the LVDS bus adopts a twisted pair cable, the bus head end is connected to the LVDS transmitting port of CPU-A, the end is connected to the LVDS receiving port of CPU-B, and 16 IO modules are connected in series in the middle to form a physical ring network.

[0114] Further, a plurality of IO modules are connected by LVDS differential signal lines to form a closed loop network structure.

[0115] The LVDS differential signal line refers to a communication line pair adopting low-voltage differential signal technology, has high noise suppression capability, each IO module has input and output ports, and is connected in series in turn, and finally the head and the tail are closed to form a ring network.

[0116] In a specific example, CAT6 twisted pair cables are used to connect the modules, the LVDS_OUT port of each IO module is connected to the LVDS_IN port of the next module, the OUT port of the last IO module is connected to the IN port of CPU-B, and a closed loop is formed.

[0117] Further, a bus communication timing data is managed by a master CPU module.

[0118] The bus communication timing data refers to time scheduling parameters in communication, such as frame start time, time slot allocation, baud rate, etc., which are uniformly planned and synchronized by the master CPU module.

[0119] In a specific example, CPU-A is configured as a master role, and LVDS bus communication parameters are configured: the baud rate is 100 Mbps, 1 ms is a communication period, and fixed time slots are allocated in the period for broadcast instructions, data collection and synchronization signals.

[0120] Further, during data transmission, the bidirectional data flow of the LVDS bus is processed by the first CPU module or the second CPU module to generate communication control data.

[0121] The bidirectional data flow includes downlink control instructions and uplink collected data. After receiving the data, the master or hot standby CPU module parses and generates communication control data, such as retransmission instructions, flow control commands, or error responses.

[0122] In a specific example, CPU-A sends control instructions to IO module 1 and receives collected data returned by IO module 16; CPU-A generates communication control data according to data integrity, such as requesting IO module 2 to retransmit lost data frames.

[0123] Further, based on the communication control data, the bandwidth usage data of the LVDS bus is optimized.

[0124] The bandwidth usage data refers to the allocation and utilization rate information of the bus bandwidth. The communication control data is used to dynamically adjust the bandwidth allocation, such as preferentially allocating high-priority data, compressing idle time slots, or adjusting the communication rate.

[0125] In a specific example, CPU-A monitors the bus load. If the bandwidth utilization rate exceeds 80%, it cancels the transmission of low-priority state queries through communication control data instructions to ensure that high-priority control instructions have sufficient bandwidth.

[0126] The plurality of IO modules specifically includes: receiving sensor signal data through the input ports of the plurality of IO modules; the sensor signal data at least includes temperature data, pressure data and liquid level data; determining device parameter report data based on the sensor signal data; sending control instruction data to external devices through the output ports of the plurality of IO modules; the control instruction data at least includes motor start-stop instructions and valve control instructions; updating output state data based on instruction data from the master role CPU module to control external devices.

[0127] First, receive sensor signal data through the input ports of each IO module; the sensor signal data at least includes temperature data, pressure data and liquid level data.

[0128] The input port is an analog or digital signal acquisition channel that connects the sensor and receives its output electrical signal, and after AD conversion or digital filtering, the sensor signal data is obtained.

[0129] In a specific example, the analog input port AI1 of IO module 1 is connected to a temperature sensor to receive a 4-20mA current signal, and after AD conversion, temperature data (unit: ℃) is obtained; the digital input port DI1 is connected to a pressure switch to receive a switch signal to obtain pressure state data.

[0130] Further, the device parameter report data is determined based on the sensor signal data.

[0131] The device parameter report data is structured data processed from the original sensor signal, containing parameter value, unit, timestamp and status flag.

[0132] In a specific example, the microcontroller of IO module 1 reads temperature data, compares it with upper and lower limits, generates device parameter report data: {temperature: 25.5℃, status: normal, time: 2023-10-01 12:00:00}, and sends it through the LVDS bus.

[0133] Further, control instruction data is sent to external devices through the output ports of each IO module; the control instruction data at least includes motor start-stop instructions and valve control instructions.

[0134] The output port is a digital or analog output channel, which drives external actuators such as relays or servo drivers after receiving control instruction data.

[0135] In a specific example, the digital output port DO1 of IO module 2 receives the motor start-stop instruction (such as "start") from CPU-A, drives the relay to close, and thus starts the external motor; the analog output port AO1 receives the valve opening degree instruction (such as 50%), and outputs a 4-20mA signal to control the regulating valve.

[0136] Further, the output state data is updated based on the instruction data from the master CPU module to control external devices.

[0137] The output state data refers to the current state of the IO module output channel, such as the on-off state or output value, and the master CPU module sends instruction data to update the state and thus control external devices.

[0138] In a specific example, CPU-A sends instruction data to IO module 2: {output port: DO1, instruction: high level}, IO module 2 updates the output state data and sets DO1 to high level, thereby turning on the connected inductor coil.

[0139] The switching control unit is also used for taking over the control work by the original master CPU module after the hot standby CPU module fails, and specifically includes: when detecting the failure state data of the hot standby CPU module, disabling the LVDS bus communication function of the hot standby CPU module; re-enabling the LVDS bus communication function of the original master CPU module, so that the original master CPU module switches to a master working state; outputting control instruction data to the plurality of IO modules by the original master CPU module based on the stored IO module information data; and sending switching completion notification data to the upper computer to update system running state information.

[0140] First, when detecting the failure state data of the hot standby CPU module, the LVDS bus communication function of the hot standby CPU module is disabled.

[0141] The failure state data is a Boolean flag or a state word indicating that the hot standby CPU module has failed, such as watchdog timeout or self-check error.

[0142] In a specific example, CPU-A monitors the heartbeat of CPU-B through the synchronization communication unit, and if 3 consecutive heartbeat packets are lost, the failure state data is set to "true", and the LVDS bus driver enable pin of CPU-B is disabled through a hardware signal.

[0143] Further, the LVDS bus communication function of the original master CPU module is re-enabled, so that the original master CPU module switches to a master working state.

[0144] Re-enabling is to activate the bus driver of the original master CPU module through a control signal, so that it regains the control right of the bus.

[0145] In a specific example, the LVDS enable pin of CPU-A is re-set to high level, and the driver is activated; CPU-A sends a bus reset frame, declares itself as a master role, and reconfigures the bus communication parameters.

[0146] Further, the original master CPU module outputs control instruction data to the plurality of IO modules based on the stored IO module information data.

[0147] The IO module information data includes module address, type and latest state, and the original master CPU module reads the data from the local memory and generates corresponding control instructions.

[0148] In a specific example, CPU-A reads IO module information data from memory address 0x2000, learns that IO module 1 address 0x10 needs to control the motor to start, and then generates control instruction data to send to IO module 1 through the LVDS bus.

[0149] Further, the switching completion notification data is sent to the host computer to update the system running state information.

[0150] The switching completion notification data is a state message sent to the host computer through a communication interface (such as Ethernet or serial port) to notify that the system control right has been switched.

[0151] In a specific example, CPU-A sends a UDP message to the host computer through the Ethernet interface: "hot standby CPU failure, master CPU has recovered control, time 2023-10-01 12:05:00", and the host computer software updates the interface to display the system state.

[0152] The above is the method embodiment of the present application. Based on the same inventive concept, the present application also provides a bus type PLC dual CPU hot standby redundancy method based on LVDS communication, which specifically includes: Step 1, deploy devices, including a host computer, a first CPU module (CPU module 1), a second CPU module (CPU module 2), and multiple IO modules, and connect them through an LVDS bus to form a ring network topology.

[0153] Step 1.1, deploy the host computer, CPU module 1, CPU module 2, and multiple IO modules.

[0154] The host computer refers to a monitoring computer or a human-machine interface (HMI) for system configuration and state display; CPU module 1 and CPU module 2 are master units with processing and control functions; IO module is an input-output module for collecting sensor data and controlling actuators. When deployed, CPU module 1 and CPU module 2 are installed in the control cabinet, and IO modules are installed in the device field through cable connection.

[0155] In a specific example, the host computer is an industrial PC, CPU module 1 and CPU module 2 use ARM architecture processors, and IO module includes digital input module and analog output module, which are connected to temperature sensor and motor driver respectively.

[0156] Step 1.2, connect CPU module 1, CPU module 2, and multiple IO modules through an LVDS bus to form a ring network topology.

[0157] The LVDS bus uses differential signal lines to connect all devices, with the first end starting from CPU module 1 and the last end ending at CPU module 2, and then returning to CPU module 1 to form a closed loop, ensuring bidirectional communication redundancy.

[0158] In a specific example, the LVDS bus is connected from the TX+ and TX- pins of the CPU module 1 to the RX+ and RX- pins of the first IO module, and then connected to all the IO modules in sequence, and finally connected from the TX+ and TX- pins of the last IO module to the RX+ and RX- pins of the CPU module 2, and the TX+ and TX- pins of the CPU module 2 are connected back to the RX+ and RX- pins of the CPU module 1, forming a physical ring network.

[0159] Step 2, configure CPU module 1 and CPU module 2 as master and hot standby roles by the host computer, or determine the roles by module self-negotiation.

[0160] Step 2.1, configure the roles of CPU module 1 and CPU module 2 by the host computer.

[0161] The host computer runs the configuration software, and the user can choose to manually specify the master and standby roles or enable the self-negotiation mode. The configuration data is downloaded to the non-volatile memory of the CPU module through the serial port or Ethernet.

[0162] In a specific example, the user selects "manual configuration" in the host computer software, sets CPU module 1 as the master role and CPU module 2 as the hot standby role, and clicks "apply". The configuration data is written to the Flash memory of CPU module 1 and CPU module 2 through the RS485 interface.

[0163] Step 2.2, or determine the roles by self-negotiation of CPU module 1 and CPU module 2.

[0164] Self-negotiation is based on preset rules (such as version number, serial number or address code). After the CPU module is powered on, the information is exchanged and the data is compared to determine the master and standby roles.

[0165] In a specific example, after CPU module 1 and CPU module 2 are powered on, the version number data is exchanged through the synchronous communication unit. The version of CPU module 1 is V3.0 and the version of CPU module 2 is V2.0. According to the rule (the higher version is the master), CPU module 1 self-negotiates as the master role and CPU module 2 as the hot standby role.

[0166] Step 3, if CPU module 1 is the master role, then CPU module 1 is the master control CPU module and CPU module 2 is the hot standby control CPU module.

[0167] Step 3.1, CPU module 1 as the master control CPU module, enable the LVDS bus connection function.

[0168] The master control CPU module activates its LVDS bus driver and starts sending and receiving data, managing the bus communication timing.

[0169] In one specific case, CPU module 1 sets the enable signal of its LVDS controller to high level, starts bus driver, and sends a sync frame to the bus to coordinate the communication of IO modules.

[0170] Step 3.2, CPU module 2 as the hot standby control CPU module, disables the LVDS bus connection function.

[0171] The hot standby control CPU module keeps its LVDS bus driver disabled, only listens to the bus data, and does not actively send data to avoid conflicts.

[0172] In one specific case, CPU module 2 sets the enable signal of its LVDS controller to low level, the bus driver enters high impedance state, but the receiver is still working to monitor the bus state and data synchronization.

[0173] Step 4, CPU module 1 as EtherCAT master manages EtherCAT network devices, scans LVDS bus to obtain IO module information, and synchronizes the scan results to CPU module 2.

[0174] Step 4.1, CPU module 1 as EtherCAT master manages EtherCAT network devices.

[0175] EtherCAT master function is realized through software protocol stack, CPU module 1 sends EtherCAT frame to IO module, reads input data and writes output data.

[0176] In one specific case, CPU module 1 runs EtherCAT master protocol stack, periodically sends process data frame (PDO) to IO module, reads temperature sensor value and updates motor control instruction.

[0177] Step 4.2, CPU module 1 scans LVDS bus to obtain address information and state data of multiple IO modules.

[0178] The scanning process includes sending broadcast query command, collecting IO module response, and parsing response data to generate bus topology graph.

[0179] In one specific case, CPU module 1 sends scan command (0x55) to LVDS bus, IO module 1 (address 0x01) replies normal state, IO module 2 (address 0x02) replies warning state, and CPU module 1 integrates these data to generate scan result list.

[0180] Step 4.3, CPU module 1 synchronizes bus scan results to CPU module 2.

[0181] Synchronization is done through dedicated communication link (e.g. SPI or UART) to ensure data consistency and real-time performance.

[0182] In one specific example, CPU module 1 sends scan result data packet to CPU module 2 through SPI bus, the data packet includes IO module address, status and checksum; CPU module 2 receives and stores to its memory, and replies an acknowledgement signal.

[0183] Step 5, CPU module 1 performs control work, CPU module 2 is in standby state, receives synchronization data but does not send data externally.

[0184] Step 5.1, CPU module 1 executes control logic based on IO module data, generates control instructions.

[0185] Control logic includes PID algorithm or state machine, calculates output instructions according to input data.

[0186] In one specific example, CPU module 1 reads temperature sensor value (25°C), calculates heater output percentage (50%) through PID control algorithm, and sends to IO module for execution through LVDS bus.

[0187] Step 5.2, CPU module 2 is in standby state, receives and stores synchronization data, but does not activate bus output.

[0188] CPU module 2 updates its internal state regularly, ensures consistency with CPU module 1, and prepares for switching.

[0189] In one specific example, CPU module 2 receives synchronization data every second, updates its IO module information table, but keeps LVDS bus driver disabled, does not interfere with bus communication.

[0190] Step 6, if CPU module 1 failure is detected, switching is triggered: CPU module 2 switches to main control CPU module, CPU module 1 switches to hot standby control CPU module.

[0191] Step 6.1, monitor the working state of CPU module 1, for example through heartbeat signal or watchdog timer.

[0192] Heartbeat signal is a pulse message sent periodically, if timeout, it is determined as failure.

[0193] In one specific example, CPU module 1 sends heartbeat signal (0xAA) to CPU module 2 every 100 milliseconds; if CPU module 2 does not receive heartbeat within 150 milliseconds, it is determined that CPU module 1 has failed.

[0194] Step 6.2, disable the LVDS bus connection function of CPU module 1.

[0195] The bus drivers of CPU module 1 are disabled by hardware signals to prevent interference with the bus.

[0196] In one specific example, the switch control unit outputs a signal to the enable pin of CPU module 1, setting it to low, disabling the LVDS bus driver.

[0197] Step 6.3, enable the LVDS bus connection function of CPU module 2, making it take over control as an EtherCAT master.

[0198] CPU module 2 activates its bus drivers and begins sending control frames and management communications.

[0199] In one specific example, CPU module 2 sets its LVDS enable signal to high, sends an EtherCAT startup frame to the IO module, declares itself as the master, and continues to execute control logic based on synchronization data.

[0200] Step 6.4, CPU module 1 switches to hot standby state, receiving synchronization data from CPU module 2.

[0201] After fault recovery or switching, CPU module 1 disables bus output and only listens to data.

[0202] In one specific example, after switching, CPU module 1 enters hot standby mode, receives synchronization data sent by CPU module 2 through SPI, updates its internal state, but does not participate in bus control.

[0203] Step 7, if CPU module 2 is detected to be faulty, CPU module 1 takes over control work again.

[0204] Step 7.1, monitor the working state of CPU module 2, for example through heartbeat signals or state queries.

[0205] CPU module 2 also sends heartbeat signals when it is in hot standby mode, and if it times out, it is determined to be faulty.

[0206] In one specific example, CPU module 2 sends a heartbeat signal to CPU module 1 every 100 milliseconds; if CPU module 1 does not receive a heartbeat within 150 milliseconds, it is determined that CPU module 2 is faulty.

[0207] Step 7.2, re-enable the LVDS bus connection function of CPU module 1, making it continue to serve as the master control CPU module.

[0208] If CPU module 2 fails, CPU module 1 resumes the master role and reactivates the bus output.

[0209] In a specific example, CPU module 1 automatically sets its LVDS enable signal to high after detecting the failure of CPU module 2, re-sends EtherCAT frames, and takes over control.

[0210] Step 7.3: Send a fault notification to the upper computer and update the system status.

[0211] Send an alarm message to the upper computer through the communication interface for user intervention or log recording.

[0212] In a specific example, CPU module 1 sends a message to the upper computer through Ethernet: "Hot standby CPU module fails, main control CPU module resumes control, time 2023-10-01 12:00:00".

[0213] In a specific example, after the system is powered on, the upper computer configures CPU module 1 as the main control role and CPU module 2 as the hot standby role. CPU module 1 scans the LVDS bus and finds IO module 1 (address 0x01, temperature sensor) and IO module 2 (address 0x02, motor driver) in normal state. CPU module 1 synchronizes the scan results to CPU module 2 and starts executing the temperature control logic: reads the temperature value, calculates the heater output, and controls the motor speed through IO module 2. CPU module 2 is in standby state, receives synchronization data but does not output. Assuming CPU module 1 stops working due to hardware failure, CPU module 2 detects heartbeat timeout, triggers switching: disables CPU module 1's bus function, enables CPU module 2's bus function, CPU module 2 takes over control based on synchronized IO information, continues to maintain production line operation, and sends an alarm to the upper computer. When CPU module 2 fails, CPU module 1 takes over.

Claims

1. A bus type PLC dual CPU hot backup redundancy system, characterized in that, The system comprises: a first CPU module and a second CPU module, which are used as a master role and a hot standby role; a plurality of IO modules, which are used to collect external sensor signals and device parameter data and output control instruction data; an LVDS bus communication unit, which is used to connect the first CPU module, the second CPU module and the plurality of IO modules at the head end and the tail end to form a ring network topology, so as to realize bidirectional data transmission; a synchronous communication unit, which is used to establish a synchronous communication connection between the first CPU module and the second CPU module, so as to transmit a heartbeat signal and bus scanning result data; a role determination unit, which is used to determine a master role CPU module and a hot standby role CPU module in the first CPU module and the second CPU module based on a preset rule; a bus scanning unit, which is used to scan the LVDS bus by the master role CPU module to obtain address information and state data of the plurality of IO modules, and generate bus scanning result; a data synchronization unit, which is used to synchronize the bus scanning result to the hot standby role CPU module by the master role CPU module, so that the hot standby role CPU module obtains IO module information data; a state monitoring unit, which is used to monitor working state data of the master role CPU module through the heartbeat signal data transmitted by the synchronous communication unit; a switching control unit, which is used to trigger the hot standby role CPU module to switch from a standby state to a master working state and take over LVDS bus communication and control instruction output data when detecting that the master role CPU module fails.

2. The bus type PLC dual-CPU hot-standby redundancy system according to claim 1, characterized in that, The role determination unit comprises: obtaining version number data of the first CPU module and version number data, address code data or serial number data of the second CPU module; determining a master role and a hot standby role based on the version number data to generate role allocation data; or determining a master role and a hot standby role based on the address code data to generate role allocation data; or determining a master role and a hot standby role based on the serial number data to generate role allocation data; outputting the role allocation data to a preset system configuration unit; based on the role allocation data, enabling an LVDS bus communication function of the master role CPU module and disabling an LVDS bus communication function of the hot standby role CPU module.

3. The bus type PLC dual-CPU hot-standby redundancy system according to claim 1, wherein, The bus scanning unit comprises: sending scanning instruction data to the LVDS bus by the master role CPU module; receiving response data returned by the plurality of IO modules, the response data comprising address code data and current state data of each IO module; generating bus scanning result based on the response data, the bus scanning result comprising an address list and state report data of all IO modules; storing the bus scanning result to a memory unit of the master role CPU module.

4. The bus-based PLC dual-CPU hot-standby redundancy system according to claim 1, wherein, The data synchronization unit specifically comprises: obtaining bus scanning result data stored in the master role CPU module, the bus scanning result data containing address information and state data of the plurality of IO modules; transmitting the bus scanning result data to the hot standby role CPU module through the synchronous communication unit; After the hot standby role CPU module receives and stores the bus scanning result data, synchronization completion confirmation data is generated; Based on the synchronization completion confirmation data, the IO module information data stored in the hot standby role CPU module is updated, so that the hot standby role CPU module has all the IO module information required for takeover control.

5. The bus-based PLC dual-CPU hot-standby redundancy system according to claim 1, wherein, The state monitoring unit specifically includes: The master control role CPU module generates heartbeat signal data at a predetermined period; The heartbeat signal data is sent to the hot standby role CPU module through the synchronization communication unit; After the hot standby role CPU module receives the heartbeat signal data, the interval time data between adjacent heartbeat signals is monitored; If the interval time data exceeds a predetermined time threshold, the hot standby role CPU module generates survival inquiry instruction data and sends it to the master control role CPU module; Based on whether the response data returned by the master control role CPU module is received, the fault state data of the master control role CPU module is determined.

6. The bus-based PLC dual-CPU hot-standby redundancy system according to claim 1, wherein, The switching control unit specifically includes: Receive the fault state data from the state monitoring unit, which indicates that the master control role CPU module has failed; Based on the fault state data, the LVDS bus communication function of the original master control role CPU module is disabled; The LVDS bus communication function of the hot standby role CPU module is enabled, so that the hot standby role CPU module takes over the communication management right of the LVDS bus; The hot standby role CPU module generates control instruction data based on the stored IO module information data and outputs it to multiple IO modules; The hot standby role CPU module sends fault alarm information data to the upper computer.

7. The bus-based PLC dual-CPU hot-standby redundancy system according to claim 1, wherein, The synchronization communication unit is used to establish a synchronous communication connection between the first CPU module and the second CPU module, specifically including: Connect the first CPU module and the second CPU module through a physical synchronization port; Transmit synchronization data packets based on the synchronization port; the synchronization data packets include heartbeat signal data and bus scanning result data; Data verification is performed during data transmission to generate verification result data; Based on the verification result data, the transmission rate data is adjusted.

8. The bus-based PLC dual-CPU hot-standby redundancy system according to claim 1, wherein, The LVDS bus communication unit specifically includes: The first CPU module is installed at the first end of the LVDS bus, and the second CPU module is installed at the end; Multiple IO modules are connected through LVDS differential signal lines to form a closed-loop network structure; The master control role CPU module manages the bus communication timing data; During data transmission, the first CPU module or the second CPU module processes the bidirectional data flow of the LVDS bus to generate communication control data; Based on the communication control data, the bandwidth usage data of the LVDS bus is optimized.

9. The bus-based PLC dual-CPU hot-standby redundancy system according to claim 1, wherein, The multiple IO modules specifically include: Sensor signal data is received through the input port of the multiple IO modules; the sensor signal data at least includes temperature data, pressure data and liquid level data; Based on the sensor signal data, device parameter report data is determined; The control instruction data is sent to the external device through the output port of the plurality of IO modules, and the control instruction data at least includes motor start-stop instruction and valve control instruction; The output state data is updated based on the instruction data from the master role CPU module to control the external device.

10. The bus-based PLC dual-CPU hot-standby redundancy system according to claim 1, wherein, The switching control unit is also used for taking over the control work by the original master role CPU module after the hot standby role CPU module fails, and specifically includes: When the failure state data of the hot standby role CPU module is detected, the LVDS bus communication function of the hot standby role CPU module is disabled; The LVDS bus communication function of the original master role CPU module is re-enabled, so that the original master role CPU module switches to the master working state; The control instruction data is output to the plurality of IO modules by the original master role CPU module based on the stored IO module information data; Switching completion notification data is sent to the upper computer to update the system running state information.

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