Controller and memory system

Abstract

The invention discloses a controller and a memory system. In some embodiments of the disclosed technology, by designating a portion of memory regions in memory devices included in a memory system used by a plurality of host devices as a shared memory region, and managing access and operation of the plurality of host devices to the shared memory region, use efficiency of the memory regions can be improved, and the memory device can be used by the plurality of host devices. Errors caused by access of a plurality of host devices to a shared memory region are prevented.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent document claims priority to and the benefit of U.S. Provisional Application No. 63 / 636,474, filed on April 19, 2024, and Korean Patent Application No. 10-2024-0075056, filed on June 10, 2024. The entire contents of the above patent applications are incorporated by reference as part of the disclosure of this patent document. Technical Field

[0003] Various embodiments of the disclosed technology generally relate to a controller and memory system. Background Art

[0004] A computing system can use a processor and memory to perform data processing. For example, a processor can use memory located within the computing system to perform data processing.

[0005] In some cases, the processor can perform data processing using memory located outside the computing system. The processor can enhance the performance of data processing by utilizing both memory located inside the computing system and memory located outside the computing system.

[0006] Memory located outside a computing system can be used by multiple computing systems. In this case, the memory must be used efficiently. Summary of the Invention

[0007] In some embodiments, the disclosed techniques can be implemented to prevent memory errors and improve efficiency in memory usage when multiple host devices use memory that is external to the host device.

[0008] In an embodiment, a memory system may include: one or more memory devices, each memory device including a first memory area and a second memory area, wherein the number of host devices that can access the first memory area is equal to or greater than the number of host devices that can access the second memory area; and a controller configured to, upon receiving a first command for a first address included in the first memory area, control an operation according to the first command based on an indirect mapping table, the indirect mapping table including: sharing status information indicating a sharing status of the first address, the sharing status of the first address being used to indicate whether the first address is a memory area shared by multiple host devices or a memory area dedicated to a specific host device; accessible status information indicating whether the first address is accessible to a specific host device; and overwrite status information indicating a usage status of at least two data areas corresponding to the first address, the usage status being used to indicate whether data in the at least two data areas is overwrite data.

[0009] In an embodiment, a memory system can include one or more memory devices each including a first memory area and a second memory area, and a controller configured to, upon receiving a first command for a first address included in the first memory area, control an operation according to the first command based on an indirect mapping table including information of at least two data areas in the first memory area corresponding to the first address, and upon receiving a second command for a second address included in the second memory area, control an operation according to the second command on one data area in the second memory area corresponding to the second address.

[0010] In an embodiment, a controller can include an internal memory device configured to store an indirect mapping table including shared state information, accessible state information, and overwrite state information of at least a portion of a memory area included in an external memory device, and a control circuit configured to, upon receiving a command from an external device, check the shared state information, the accessible state information, and the overwrite state information in the indirect mapping table corresponding to an address according to the command, and perform an operation according to the command on the external memory device.

[0011] In an embodiment, a memory system can include at least one memory including a first memory area and a second memory area, wherein a number of host devices that can access the first memory area is equal to or greater than a number of host devices that can access the second memory area, and a controller configured to, upon receiving a first command for a first address included in the first memory area, control an operation according to the first command based on an indirect mapping table including shared state information indicating a shared state of the first address, accessible state information indicating whether a device can access the first address, and overwrite state information indicating a use state of at least two data areas corresponding to the first address.

[0012] In an embodiment, a memory system can include at least one memory including a first memory area and a second memory area, and a controller configured to, upon receiving a first command for a first address included in the first memory area, control an operation according to the first command based on an indirect mapping table including information of at least two data areas corresponding to the first address, and upon receiving a second command for a second address included in the second memory area, control an operation according to the second command on one data area corresponding to the second address.

[0013] In an embodiment, a controller can include an internal memory configured to store an indirect mapping table including sharing state information, accessible state information, and overwriting state information of at least a portion of a memory region included in an external memory, and a control circuit configured to, upon receiving a command from the outside, check the sharing state information, the accessible state information, and the overwriting state information corresponding to an address according to the command in the indirect mapping table, and perform an operation according to the command on the external memory.

[0014] In some embodiments of the disclosure, each of the plurality of host devices can independently allocate at least a portion of a memory region included in a memory located outside the plurality of host devices, or at least two host devices can share at least a portion of a memory region included in a memory located outside the plurality of host devices, thereby improving the use efficiency of the memory. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a diagram illustrating an example configuration of a memory system based on embodiments of the disclosed technology.

[0016] Figure 2 is a diagram illustrating an example of a memory system providing a shared memory region based on embodiments of the disclosed technology.

[0017] Figure 3 is a diagram illustrating an example of an indirect mapping table of a memory system managing access to a shared memory region based on embodiments of the disclosed technology.

[0018] Figures 4 to 6 is a diagram illustrating an example method of a memory system processing a read command based on embodiments of the disclosed technology.

[0019] Figures 7 to 9 is a diagram illustrating an example method of a memory system processing a write command based on embodiments of the disclosed technology.

[0020] Figure 10 is a diagram illustrating an example of a memory system managing access to a non-shared memory region based on embodiments of the disclosed technology. DETAILED DESCRIPTION

[0021] Figure 1 is a diagram illustrating an example configuration of a memory system 100 based on embodiments of the disclosed technology.

[0022] REFERENCE Figure 1 The memory system 100 based on embodiments of the disclosed technology can include at least one memory 120. Figure 1The case in which the memory system 100 includes four memories 121, 122, 123, and 124 is shown as an example, but the disclosed technology is not limited thereto.

[0023] The at least one memory 120 can be, for example, a volatile memory such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM, but the disclosed technology is not limited thereto.

[0024] In some embodiments, the at least one memory 120 can be a non-volatile memory such as NAND flash memory, 3D NAND flash memory, and NOR flash memory. In addition, in some embodiments, a portion of the memories 120 included in the memory system 100 can be a volatile memory, and another portion can be a non-volatile memory.

[0025] The memory 120 can be one of various types of memories such as resistive RAM, phase change memory, magnetoresistive memory, ferroelectric memory, and spin transfer torque random access memory. In some embodiments, the memory 120 can be a processing-in-memory including a computing function or a data processing function.

[0026] The memory system 100 can include a controller 110 that manages the memory 120.

[0027] The controller 110 can manage the operation of the memory 120 when communicating with the outside. The controller 110 can control a read operation and a write operation to the memory 120 when managing the operation of the memory 120.

[0028] Optionally, a separate memory controller that manages the read operation and the write operation to the memory 120 can be provided in the memory system 100 in addition to the controller 110. For example, a memory controller corresponding to each of the plurality of memories 121, 122, 123, and 124 can be provided in the memory system 100. The memory controller can control the read operation and the write operation to the memory 120. In this case, the controller 110 can manage the state or operation of the memory 120 when communicating with the memory controller.

[0029] The memory system 100 can operate when communicating with a computing system or a host device 200 located outside. In some embodiments, the host device 200 and the memory system 100 can be collectively referred to as a computing system.

[0030] For example, the host device 200 can be a computer, an ultra mobile PC (UMPC), a workstation, a personal digital assistant (PDA), a tablet, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device configured for a data center, one of various electronic devices configured for a home network, one of various electronic devices configured for a telematics network, an RFID (radio frequency identification) device, a mobile device capable of traveling under human control or autonomous driving (e.g., a vehicle, a robot, or a drone), or the like. Alternatively, the host device 200 can be a virtual / augmented reality device providing a 2D or 3D virtual reality image or an augmented reality image. Furthermore, the host device 200 can be any one of various electronic devices each of which needs a memory system 100 capable of storing data.

[0031] A plurality of host devices 200 can use the memory system 100. For example, a first host device 210 and a second host device 220 can use the memory system 100.

[0032] Each of the plurality of host devices 200 can include a processor and a local memory. The local memory can be the same type of memory as the memory 120 included in the memory system 100, or can be a different type of memory.

[0033] The first host device 210 can include a first processor 211 and a first local memory 212. The second host device 220 can include a second processor 221 and a second local memory 222.

[0034] The first processor 211 can perform data processing using the first local memory 212. In addition, the first processor 211 can perform data processing using at least a portion of the memory 120 included in the memory system 100.

[0035] The second processor 221 can perform data processing using the second local memory 222. In addition, the second processor 221 can perform data processing using at least a portion of the memory 120 included in the memory system 100.

[0036] Each of the plurality of host devices 200 can perform data processing using a local memory included in the host device 200 and the memory system 100 located outside. Since an application to be driven in the host device 200 uses the local memory inside the host device 200 and the memory system 100 outside the host device 200 for operation, the operation performance of the application can be improved.

[0037] The host device 200 can perform communication with the memory system 100 through a preset interface.

[0038] For example, the host device 200 can communicate with the memory system 100 through a Compute Express Link (CXL) interface. The host device 200 can be set as a CXL root port, and the memory system 100 can be set as a CXL endpoint.

[0039] Since the host device 200 communicates with the memory system 100 through the CXL interface, in a structure in which a large-capacity memory system 100 is communicated with, an environment in which latency is reduced and high bandwidth is accessible can be provided. Since the communication speed between the host device 200 and the memory system 100 is improved, the host device 200 can effectively perform data processing using the internal local memory and the external memory system 100.

[0040] Alternatively, in some embodiments, the host device 200 can communicate with the memory system 100 through an interface other than the CXL interface. For example, the host device 200 and the memory system 100 can communicate through at least one of various interface protocols such as a USB (Universal Serial Bus) protocol, an MMC (Multi Media Card) protocol, a PCI (Peripheral Component Interconnect) protocol, a PCI-E (Peripheral Component Interconnect Express) protocol, an ATA (Advanced Technology Attachment) protocol, a Serial ATA protocol, a Parallel ATA protocol, a SCSI (Small Computer System Interface) protocol, an ESDI (Enhanced Small Disk Interface) protocol, and an IDE (Integrated Drive Electronics) protocol, but is not limited thereto.

[0041] Since the host device 200 performs data processing using the internal local memory and performs data processing using the memory system 100 located outside when necessary, the data processing performance can be improved.

[0042] Since the plurality of host devices 200 share and use the memory system 100, the memory 120 included in the memory system 100 can be effectively used. In some embodiments, by managing a part of the memory 120 included in the memory system 100 as an area that can be shared and used by at least two host devices 200, the performance of a workload to be performed by the plurality of host devices 200 can be improved.

[0043] The memory 120 of the memory system 100 can be used as pooled memory or shared fabric-attached memory. Host management device memory (HDM) exposed from the memory system 100 that supports multiple host devices 200 can be referred to as fabric-attached memory. Fabric-attached memory exposed from a logical device can be referred to as logical device fabric-attached memory (LD-FAM). Fabric-attached memory exposed to a larger scheme using port-based routing (PBR) links can be referred to as global fabric-attached memory (G-FAM).

[0044] Fabric-attached memory that is used by each host management device memory region dedicated to a single host interface can be referred to as “pooled memory” or “pooled fabric-attached memory”. Fabric-attached memory that is set up so that multiple host interfaces can access a single host management device memory region at the same time can be referred to as “shared fabric-attached memory”. Different shared fabric-attached memory regions can be set up to support different host interface setups.

[0045] Logical device fabric-attached memory can include various modifications. Multi-logical device (MLD) can expose multiple logical devices over a single shared link. Multi-header single logical device (MH-SLD) can expose multiple logical devices, each with a dedicated link. Multi-header multi-logical device (MH-MLD) can include multiple links, each of which supports multi-logical device or single logical device operation (which can be selectively set up). At least one link can support multi-logical device operation.

[0046] Global fabric-attached memory devices can be designed to support at least one link of multiple host / peer interfaces. The host interface of an incoming CXL.mem or UIO request can be determined by the source PBR ID (SPID) field included in the port-based routing (PBR) message.

[0047] Multi-header single logical device and multi-header multi-logical device can be distinguished from arbitrary multi-port configurations that support multiple CPU topologies in a single OS domain.

[0048] The consistency model of each shared host management device memory DB region can be specified by the FM as either multi-host hardware consistency or software managed consistency.

[0049] Multi-host hardware coherency can require multi-logic device hardware that tracks host coherency state defined for each cache line to varying degrees, depending on the tracking mechanism of the particular implementation of the multi-logic device, which can generally be categorized as a snoop filter or a global directory. Each host device 200 can perform any atomic operation supported by the instruction set architecture (ISA) by taking exclusive access to a cache line and performing an atomic operation in the cache. Data can be globally observed using cache coherency, and can follow the general hardware cache eviction process. A MemWr command for a memory region can set the SnpType field to No-Op to prevent deadlock. The host device 200 can need to take ownership using the M2S request channel before running the MemWr result in two stages to complete the write. This can be a requirement for the hardware coherency model in shared fabric attached memory and direct P2P CXL.mem.

[0050] Shared fabric attached memory can expose the memory 120 to the host devices 200 as a single host managed device memory. Software coherency model can be supported between the host devices 200.

[0051] Software managed coherency can not require multi-logic device tracking of host coherency state. Software on each host device 200 can use software specific mechanisms to coordinate software ownership of each cache line. Software can choose to rely on multi-host hardware coherency in different host managed device memory regions to coordinate software ownership of cache lines in host managed device memory regions of software managed coherency. Other mechanisms for software to coordinate cache line ownership can be included within the scope of the present specification.

[0052] Figure 2 FIG. 1 is a diagram illustrating an example of a memory system 100 providing a shared memory region based on embodiments of the disclosed technology.

[0053] Referring to Figure 2 The first host device 210 and the second host device 220 can perform data processing using the memory system 100. Figure 2 The case of two host devices 200 using the memory system 100 is illustrated as an example, but the number of host devices 200 using the memory system 100 can be three or more.

[0054] The first processor 211 of the first host device 210 can perform data processing using the first local memory 212 and at least a part of the memory 120 included in the memory system 100. The second processor 221 of the second host device 220 can perform data processing using the second local memory 222 and at least a part of the memory 120 included in the memory system 100.

[0055] The controller 110 of the memory system 100 can provide the memory regions to the first host device 210 and the second host device 220 in managing the memory regions included in the memory 120.

[0056] The controller 110 can manage the memory regions included in the plurality of memories 120 individually and collectively. Figure 2 An example of managing the memory regions included in the four memories 121, 122, 123, and 124 shown in FIG. 1 is illustrated, but the disclosed technology is not limited thereto. Figure 1

[0057] The controller 110 can allocate at least a part of the memory regions included in the memory 120 to one host device 200.

[0058] For example, when receiving a memory region allocation request from the host device 200, the controller 110 can allocate a part of the memory region to the host device 200. The allocated memory region can be used by the host device 200 that sent the allocation request. Access to the corresponding memory region by another host device 200 can be prohibited.

[0059] The controller 110 can manage at least a part of the memory regions included in the memory 120 so that at least a part of the memory regions is shared and used by at least two host devices 200.

[0060] For example, the controller 110 can manage a part of the memory region according to a request from the host device 200 so that the part of the memory region is accessible by at least two host devices 200. For example, the controller 110 can receive a memory region allocation request from the first host device 210. The controller 110 can receive a memory region sharing request from the first host device 210.

[0061] The controller 110 can manage the memory region allocated to the first host device 210 as a memory region accessible by another host device 200.

[0062] ​The controller 110 can manage the respective memory region by setting the respective memory region to a state in which another host device 200 can perform a read operation on the respective memory region. Alternatively, the controller 110 can manage the respective memory region by setting the respective memory region to a state in which another host device 200 can perform a read operation and a write operation on the respective memory region.

[0063] The controller 110 can manage the host devices 200 that can access the respective memory region based on information received from the first host device 210 that requests to share the respective memory region.

[0064] For example, the first host device 210 can transmit a request to share a memory region to the memory system 100. The first host device 210 can transmit a request to allow the second host device 220 to access the respective memory region to the memory system 100.

[0065] According to the request of the first host device 210, the controller 110 can set and manage the respective memory region to a state in which the second host device 220 can access the respective memory region. The access authority (e.g., a read authority or a read authority and a write authority) of the second host device 220 to the respective memory region can also be managed based on the request received from the first host device 210.

[0066] For another example, the controller 110 can manage a part of a memory region included in the memory 120 by setting the part of the memory region as a shared memory region. The controller 110 can manage the memory region by setting a part of the memory region as a shared memory region and the remaining part as a non-shared memory region.

[0067] The controller 110 can manage the memory region by dividing the memory region included in the memory 120 into a first memory region 120a and a second memory region 120b.

[0068] The first memory region 120a can be a shared memory region that is accessible to at least two host devices 200. The second memory region 120b can be a non-shared memory region that is accessible to only one host device 200. The number of host devices 200 that can access the first memory region 120a can be equal to or greater than the number of host devices 200 that can access the second memory region 120b.

[0069] The size of the first memory region 120a can be smaller than the size of the second memory region 120b, but the disclosed technology is not limited thereto. The memory region and size corresponding to the first memory region 120a can be fixedly managed, or can be differently managed according to a usage state.

[0070] The controller 110 can control access to the first memory area 120a according to a request of the at least two host devices 200.

[0071] The controller 110 can allocate at least a part of the second memory area 120b according to a request of each of the at least two host devices 200. The controller 110 can manage only the corresponding host device 200 so that only the corresponding host device 200 accesses the allocated memory area.

[0072] The controller 110 can set and manage a separate table to control access of the host devices 200 to the first memory area 120a and process a command from the host devices 200.

[0073] When the host devices 200 generate an allocation request or an access request for the first memory area 120a, the controller 110 can use the set table to manage access and operation of the host devices 200 to the first memory area 120a.

[0074] The form of the table through which the controller 110 manages access to the first memory area 120a can be different.

[0075] Figure 3 FIG. 1 is a diagram illustrating an example of an indirect mapping table through which a memory system 100 manages access to a shared memory area based on an embodiment of the disclosed technology.

[0076] Referring to Figure 3 , the controller 110 of the memory system 100 can use an indirect mapping table to manage access and operation of the host devices 200 to the first memory area 120a of the memory 120. For example, the controller 110 can perform management of the first memory area 120a using the indirect mapping table, or can perform management of the first memory area 120a and the second memory area 120b using the indirect mapping table.

[0077] The controller 110 can set an indirect mapping table including an address included in the first memory area 120a and information of a host device 200 that can access the corresponding address.

[0078] For example, as illustrated in <Example 1>, the indirect mapping table can include an address information field 310 and an accessible state information field 320.

[0079] The address information field 310 can include information of an address included in the first memory area 120a.

[0080] The accessible state information field 320 can include information of a device that can access the corresponding address.

[0081] For example, if the accessible state information includes a first accessible state value, it can indicate that the corresponding host device 200 can access the corresponding address. If the accessible state information includes a second accessible state value, it can indicate that the corresponding host device 200 cannot access the corresponding address. For example, the first accessible state value can be set to "0" and the second accessible state value can be set to "1", but the disclosed technology is not limited thereto.

[0082] For example, the accessible state information included in the accessible state information field 320 can consist of a 4-bit accessible state value. The 4-bit accessible state value can indicate whether up to four host devices 200 are accessible.

[0083] For example, the least significant bit of the accessible state value included in the accessible state information field 320 can indicate the accessible state of the first host device 210. The third bit of the 4-bit accessible state value can indicate the accessible state of the second host device 220.

[0084] In some embodiments, on the contrary, the most significant bit of the accessible state value can indicate the accessible state of the first host device 210 and the second bit can indicate the accessible state of the second host device 220.

[0085] When an access request for a specific address is received from the first host device 210 or the second host device 220, the controller 110 can control whether the corresponding host device 200 can access the specific address based on the accessible state information included in the accessible state information field 320.

[0086] There can be a data region 330 corresponding to the address of the address information field 310 included in the indirect mapping table. The data region 330 can correspond to a portion of the memory region physically included in the first memory region 120a.

[0087] When the address information field 310 corresponding to the address, the accessible state information field 320, and the data region 330 included in the indirect mapping table are managed as one information, the controller 110 can control the access and operation of the host device 200 to the first memory region 120a as a shared memory region.

[0088] In some embodiments, the indirect mapping table can further include information setting or indicating the sharing state of the corresponding memory region.

[0089] For example, as shown in <Example 2>, the indirect mapping table can include the address information field 310, the sharing state information field 340, and the accessible state information field 320. The controller 110 can manage the data region 330 corresponding to the address of the address information field 310 as one information.

[0090] The address information field 310 can include information of an address included in the first memory area 120a.

[0091] The sharing state information field 340 can include information of a sharing state of a corresponding address. In some embodiments, the term "sharing state" of a specific address can indicate whether the specific address is a memory area shared by a plurality of host devices or a memory area dedicated to a specific host device.

[0092] For example, if the sharing state information included in the sharing state information field 340 is a first sharing state value, the corresponding address can be an address of a shared area. If the sharing state information is a second sharing state value, the corresponding address can be an address of a non-shared area. The non-shared area can be an area allocated to and used by the specific host device 200.

[0093] The first sharing state value can be set to "1" and the second sharing state value can be set to "0", but the disclosed technology is not limited thereto.

[0094] The accessible state information field 320 can include accessible state information indicating an accessible host device 200.

[0095] When a request for an address included in the first memory area 120a is received from the host device 200, the controller 110 can process the request from the host device 200 based on the sharing state information and the accessible state information corresponding to the address included in the indirect mapping table.

[0096] In some embodiments, the controller 110 can manage a plurality of data areas 330 corresponding to the first memory area 120a using the indirect mapping table. Since the shared memory area is an area accessible by a plurality of host devices 200, the controller 110 can improve the efficiency of the plurality of host devices 200 using the memory 120 in setting and managing at least two data areas 330 corresponding to the address.

[0097] For example, as shown in <Example 3>, the indirect mapping table can include the address information field 310, the sharing state information field 340, the accessible state information field 320, and the override state information field 350.

[0098] In <Example 3>, the address information field 310, the sharing state information field 340, and the accessible state information field 320 can be used similarly to the methods described in <Example 1> and <Example 2>.

[0099] The overwrite state information field 350 can include overwrite state information of the data area 330 corresponding to the address of the address information field 310. The overwrite state information can indicate an overwrite state of data in the data area 330 corresponding to the address.

[0100] For example, there can be at least two data areas 330 corresponding to an address included in the first memory area 120a. A first data area 331 and a second data area 332 can correspond to the address.

[0101] The first data area 331 can represent an area in which old data is written, and the second data area 332 can represent an area in which new data is written. A time point at which data is written to the first data area 331 can be earlier than a time point at which data is written to the second data area 332.

[0102] In some embodiments, a helper data area 370 can be used in an operation of writing data to the first data area 331 and the second data area 332. The size of the helper data area 370 can be smaller than the size of the first data area 331. The size of the helper data area 370 can be smaller than the size of the second data area 332.

[0103] In the first memory area 120a, there can be the first data area 331, the second data area 332, and the helper data area 370 corresponding to the address of the address information field 310.

[0104] The usage state of the first data area 331 and the second data area 332 can be indicated based on the overwrite state information of the overwrite state information field 350.

[0105] For example, if the overwrite state information is a first overwrite state value, it can be indicated that no overwrite has been made in the data area 330 corresponding to the address.

[0106] It can be indicated that the second data area 332 corresponding to the address is not used and only the first data area 331 is used. Alternatively, it can be indicated that neither the first data area 331 nor the second data area 332 corresponding to the address is used.

[0107] If the overwrite state information is a second overwrite state value, it can be indicated that overwrite has been made in the data area 330 corresponding to the address. It can be indicated that the first data area 331 and the second data area 332 corresponding to the address are used.

[0108] The first overwrite state value can be set to "0" and the second overwrite state value can be set to "1", but the disclosed technology is not limited thereto.

[0109] According to the overwrite status information of the overwrite status information field 350, additional information may be required to process the request from the host device 200. The host device 200 may send request status information to the memory system 100 to access the first data area 331 or the second data area 332 according to the overwrite status request.

[0110] The controller 110 may receive the request status information from the host device 200. The request status information may be received together with the command, or may be received separately from the command.

[0111] The controller 110 may configure the request status information as the request status information field 360 of the indirect mapping table, thereby processing the request from the host device 200. The controller 110 may control access to the data area 330 according to the request status information while managing the request status information received from the host device 200 as a partial field or a separate field of the indirect mapping table.

[0112] For example, if the request status information is a first request status value, the controller 110 may control access and operation to the first data area 331. If the request status information is a second request status value, the controller 110 may control access and operation to the second data area 332.

[0113] The first request status value may be set to “0” and the second request status value may be set to “1”, but the disclosed technology is not limited thereto.

[0114] By controlling access by multiple host devices 200 to the first memory area 120a, which is a shared memory area of ​​the memory 120, based on the indirect mapping table, the memory system 100 can improve the use efficiency of the memory area and prevent errors from occurring due to the use of the shared memory area.

[0115] Figures 4 to 6 is a diagram illustrating an example method in which the memory system 100 processes a read command based on an embodiment of the disclosed technology.

[0116] Reference Figure 4 , as an example, a case where the first host device 210 and the second host device 220 perform data processing using the memory system 100 is shown.

[0117] Each of the first host device 210 and the second host device 220 may perform data processing using a local memory and, if necessary, may perform data processing using a portion of a memory area of ​​the memory system 100 .

[0118] Each of the first host device 210 and the second host device 220 can be allocated and independently use at least a portion of the second memory region 120b among the memory regions of the memory 120 included in the memory system 100. In addition, each of the first host device 210 and the second host device 220 can perform data processing when accessing the first memory region 120a of the memory 120.

[0119] At least a portion of the first memory region 120a can be accessed by the first host device 210 and the second host device 220 according to a time period, or can be accessed only by one of the first host device 210 and the second host device 220.

[0120] When a command for an address included in the first memory region 120a is received from the first host device 210 or the second host device 220, the controller 110 of the memory system 100 can control access of the corresponding address by the host device 200 and command processing of the host device 200 based on the indirect mapping table.

[0121] For example, the controller 110 can include a control circuit 111 and an auxiliary memory 112.

[0122] The control circuit 111 can manage or control allocation, access, and use status of the memory region and operations on the corresponding memory region according to a request of the host device 200.

[0123] The auxiliary memory 112 can be located inside the controller 110. In some embodiments, the auxiliary memory 112 can be located outside the controller 110.

[0124] The auxiliary memory 112 can operate under the control of the control circuit 111 and can store the indirect mapping table. In this specification, the auxiliary memory 112 can be referred to as an internal memory, and the memory 120 included in the memory system 100 can be referred to as an external memory.

[0125] When a command from the host device 200 is received, the control circuit 111 of the controller 110 can check information corresponding to an address according to the command in the indirect mapping table stored in the auxiliary memory 112, and can perform processing of the corresponding command.

[0126] For example, with reference to Figure 4 , the control circuit 111 can check an address according to a read command received from the host device 200. The control circuit 111 can check the shared status information field 340 and the accessible status information field 320 corresponding to the address in the indirect mapping table stored in the auxiliary memory 112.

[0127] If the sharing state information of the sharing state information field 340 corresponding to the address is the first sharing state value, the control circuit 111 can determine that the corresponding address indicates a memory region accessible by the plurality of host devices 200.

[0128] If the accessible state information of the accessible state information field 320 corresponding to the address is the second accessible state value, the control circuit 111 can determine that the host device 200 which transmitted the read command is not accessible to the corresponding address.

[0129] Since the host device 200 is not accessible to the corresponding address, the control circuit 111 can transmit an error value to the host device 200 which transmitted the read command. The error value can be a value indicating that the host device 200 does not have a read authority for the corresponding address, and the type of the error value can not be limited to a specific type. Alternatively, the control circuit 111 can provide the host device 200 with a value converted based on data written to the memory region corresponding to the address.

[0130] For example, the control circuit 111 can transmit a result value of performing a preset operation on data read from the memory region corresponding to the address to the host device 200.

[0131] The control circuit 111 can transmit a result value of performing a bit operation on data read from the memory region corresponding to the address using a preset value and a preset operator to the host device 200. The control circuit 111 can transmit a result value of performing an AND operation on all read data and "0" to the host device 200. The memory system 100 can process a read command transmitted by the host device 200 which is not accessible to the shared memory region without an error.

[0132] When the host device 200 is accessible, the memory system 100 can perform access to the corresponding address and processing of a command based on the indirect mapping table.

[0133] For example, referring to Figure 5 When a read command is received from the host device 200, the controller 110 can check whether the host device 200 is accessible based on the indirect mapping table. Hereinafter, a case where the controller 110 performs processing of a read command is described as an example, but can include a case processed by the above-described control circuit 111.

[0134] If the sharing state information of the sharing state information field 340 in the indirect mapping table is the first sharing state value and the accessible state information of the accessible state information field 320 is the first accessible state value, the controller 110 can determine that the corresponding host device 200 is accessible to the corresponding address.

[0135] The controller 110 can check the overwrite state information of the overwrite state information field 350 corresponding to the address.

[0136] If the overwrite state information of the overwrite state information field 350 is the first overwrite state value, the controller 110 can determine that the data region 330 corresponding to the address is not in the overwrite state.

[0137] The controller 110 can perform a read operation on the first data region 331 among the first data region 331 and the second data region 332 corresponding to the address. As described above as an example, the read operation can be controlled by the controller 110, or the read operation can be controlled by a memory controller that controls the operation of the memory 120 according to the instruction of the controller 110.

[0138] The controller 110 can transmit the data read from the first data region 331 to the host device 200 that transmitted the read command.

[0139] If the data region 330 corresponding to the address is in the overwrite state according to the overwrite state information of the overwrite state information field 350, the controller 110 can process the read command by checking the request state information transmitted by the host device 200.

[0140] For example, referring to Figure 6 When the read command is received from the host device 200, the controller 110 can check the shared state information field 340, the accessible state information field 320, and the overwrite state information field 350 in the indirect mapping table.

[0141] If the overwrite state information of the overwrite state information field 350 is the second overwrite state value, the controller 110 can determine that the data region 330 corresponding to the corresponding address is in the overwrite state.

[0142] If the overwrite state information is the second overwrite state value, the controller 110 can select the data region 330 to be read according to the read command based on the request state information transmitted by the host device 200.

[0143] For example, as in <Case 1>, if the overwrite state information is the second overwrite state value, the controller 110 can check the request state information of the host device 200.

[0144] If the request state information is the first request state value, the controller 110 can read the data written to the first data region 331 of the data region 330 corresponding to the address. The controller 110 can transmit the data read from the first data region 331 to the host device 200.

[0145] For another example, as in <Case 2>, if the request state information is the second request state value, the controller 110 can read data of a second data region 332 in which data is written corresponding to the address. The controller 110 can transmit the data read from the second data region 332 to the host device 200.

[0146] The controller 110 can manage at least two data regions 330 corresponding to addresses of memory regions included in the first memory region 120a using the overwrite state information field 350 of the indirect mapping table.

[0147] The controller 110 can control a read operation of data written in at least two data regions 330 based on the overwrite state information and the request state information received from the host device 200. By classifying data written in each address of the first memory region 120a accessible to a plurality of host devices 200 into old data and new data, it is possible to efficiently manage the memory region accessible to the plurality of host devices 200.

[0148] The controller 110 can manage the overwrite state by setting the overwrite state information of the overwrite state information field 350 during a write operation to an address included in the first memory region 120a.

[0149] Figures 7 to 9 FIG. 1 is a diagram illustrating a memory system 100 according to an embodiment of the disclosed technology.

[0150] Referring to Figure 7 , the memory system 100 can receive a write command from the host device 200.

[0151] The controller 110 of the memory system 100 can check an address according to the write command. When the address is included in the first memory region 120a of the memory 120, the controller 110 can check the indirect mapping table.

[0152] The controller 110 can check the shared state information field 340, the accessible state information field 320, and the overwrite state information field 350 corresponding to the address in the indirect mapping table.

[0153] If the accessible state information of the accessible state information field 320 is the second accessible state value, the controller 110 can determine that the corresponding host device 200 is not accessible, and can transmit an error value to the host device 200.

[0154] If the accessible state information of the accessible state information field 320 is the first accessible state value, the controller 110 can determine that the corresponding host device 200 is accessible. The controller 110 can check the overwrite state information of the overwrite state information field 350.

[0155] If the write command is a first write command for the data region 330 corresponding to the address according to the write command, the overwrite state information field 350 can be in an unset state. It can be a state in which the overwrite state information of the overwrite state information field 350 is set to a first overwrite state value.

[0156] If it is a first write for the corresponding address, the controller 110 can control a write operation for the first data region 331 among the first data region 331 and the second data region 332 corresponding to the address. Data of the write command from the host device 200 can be written to the first data region 331 corresponding to the address.

[0157] When data is written to the first data region 331, the controller 110 can set the overwrite state information of the overwrite state information field 350 corresponding to the address to a first overwrite state value.

[0158] Alternatively, the controller 110 can select a data region 330 to be written data according to the attribute of the write command received from the host device 200.

[0159] For example, when the write command is a normal write command, the controller 110 can write data to the first data region 331 corresponding to the address according to the write command. When the write command is an overwrite command, the controller 110 can write data to the second data region 332 corresponding to the address according to the write command.

[0160] The host device 200 can differently transmit a normal write command and an overwrite command through a write command.

[0161] Alternatively, the host device 200 can differently transmit a normal write command and an overwrite command using request state information. For example, if the request state information is a first request state value, a write to the first data region 331 can be requested, and if the request state information is a second request state value, a write to the second data region 332 can be requested.

[0162] When a write command is received after a first write to the data region 330 corresponding to the address or an overwrite command is received from the host device 200, the controller 110 can control a write operation for the second data region 332 corresponding to the address.

[0163] For example, referring to Figure 8 , the controller 110 can receive a write command for an address to write data to the first data region 331.

[0164] The controller 110 can check the overwrite state information of the overwrite state information field 350 and select a data region 330 to write data.

[0165] When the overwrite state information of the overwrite state information field 350 is set to the first overwrite state value, the controller 110 can determine that data is written to the first data area 331.

[0166] The controller 110 can write data corresponding to the address to the second data area 332 according to the write command received from the host device 200. After the data is written to the second data area 332, the controller 110 can set the overwrite state information of the overwrite state information field 350 corresponding to the address to the second overwrite state value.

[0167] When the overwrite state information of the overwrite state information field 350 is set to the second overwrite state value, the data area 330 corresponding to the address can be managed to be in the overwrite state.

[0168] When a read command for the corresponding address is received, the controller 110 can check the request state information according to the read command and process the read command. When a write command for the corresponding address is received, the controller 110 can retain only the data written to the second data area 332 among the data written to the first data area 331 and the second data area 332, and can perform a write operation according to the newly received write command.

[0169] For example, with reference to Figure 9 When a write command is received from the host device 200, the controller 110 can check the overwrite state information field 350 corresponding to the address according to the write command in the indirect mapping table.

[0170] If the overwrite state information of the overwrite state information field 350 is the second overwrite state value, the controller 110 can determine the state in which data is written to the first data area 331 and the second data area 332 corresponding to the address.

[0171] The controller 110 can write data corresponding to the address to the auxiliary data area 370 according to the write command (①).

[0172] When data is written to the auxiliary data area 370, the controller 110 can copy the data written to the second data area 332 to the first data area 331 (②). The controller 110 can copy the data written to the auxiliary data area 370 to the second data area 332 (③).

[0173] By using the overwrite state information included in the overwrite state information field 350 of the indirect mapping table and the first data region 331 and the second data region 332, the controller 110 can manage two data recently written in a memory region corresponding to an address shared with the plurality of host devices 200. In some embodiments, at least three data regions 330 can correspond to an address included in the first memory region 120a, in which case the overwrite state information of the overwrite state information field 350 is composed of at least 2 bits, and a write operation to at least three data regions 330 can be controlled.

[0174] In this way, the controller 110 can control access and operation of the first memory region 120a of the memory 120 by the plurality of host devices 200 using the indirect mapping table.

[0175] Since the controller 110 manages the second memory region 120b by allocating the second memory region 120b to one of the plurality of host devices 200, the controller 110 can manage access and operation of an address based on an address received from the host device 200 without using the indirect mapping table.

[0176] Alternatively, since the first memory region 120a and the second memory region 120b can be differently set and managed according to a use state, access to the second memory region 120b can also be controlled using the indirect mapping table.

[0177] Figure 10 is a diagram illustrating an example of a memory system 100 managing access to a non-shared memory region based on an embodiment of the disclosed technology.

[0178] Referring to Figure 10 When a command is received from the host device 200, the controller 110 of the memory system 100 can check the indirect mapping table.

[0179] In the indirect mapping table, the controller 110 can check the sharing state information field 340 corresponding to an address according to the command. If the sharing state information of the sharing state information field 340 is a second sharing state value, the controller 110 can determine a state that the corresponding address is not shared. The corresponding address can be included in the second memory region 120b.

[0180] The controller 110 can process the command of the host device 200 by accessing the corresponding address in the second memory region 120b.

[0181] Alternatively, in the case of using the indirect mapping table, the controller 110 can process the command by checking the accessible state information field 320.

[0182] The second memory area 120b can not be shared by the plurality of host devices 200, but can be used by being allocated to a specific host device 200. The accessible state information of the accessible state information field 320 can be set so that only the host device 200 to which the corresponding address is allocated among the plurality of host devices 200 can access the corresponding address.

[0183] For example, when the accessible state information is set to a 4-bit accessible state value and the corresponding address is allocated to the first host device 210, only the most significant bit or the least significant bit of the 4-bit accessible state value can be set to the first accessible state value, and the remaining bits can be set to the second accessible state value.

[0184] The override state information field 350 can not be set, or can be managed by being set to a default value.

[0185] The controller 110 can manage the first memory area 120a and the second memory area 120b using the indirect mapping table, and can differently set and manage the first memory area 120a and the second memory area 120b in the memory 120.

[0186] In this way, since the controller 110 of the memory system 100 manages access and operation of the first memory area 120a by the plurality of host devices 200 based on the indirect mapping table, it is possible to improve the use efficiency of the memory area of the memory system 100 used by the plurality of host devices 200, and to prevent operation errors due to the use of a shared memory area.

[0187] Only some embodiments and examples have been described. The disclosed embodiments and other embodiments can be enhanced and varied based on what is described and illustrated in this patent document.

Claims

1. A memory system comprising: one or more memory devices each including a first memory area and a second memory area, wherein a number of host devices that can access the first memory area is equal to or greater than a number of host devices that can access the second memory area; and a controller that, upon receiving a first command for a first address included in the first memory area, controls an operation according to the first command based on an indirect mapping table including: shared status information indicating a shared status of the first address to indicate whether the first address is a memory area shared by a plurality of host devices or a memory area dedicated to a specific host device; accessible status information indicating whether a specific host device can access the first address; and overwritten status information indicating a usage status of at least two data areas corresponding to the first address to indicate whether data in the at least two data areas is overwritten data.

2. The memory system of claim 1, wherein, Upon receiving a read command as the first command, the controller checks the overwritten status information of the first address and, upon determining that the overwritten status information corresponds to a first overwritten status value, performs a read operation on a first data area of the at least two data areas corresponding to the first address.

3. The memory system of claim 2, wherein, The controller: upon determining that the overwritten status information corresponds to a second overwritten status value, checks request status information according to the first command; upon determining that the request status information corresponds to a first request status value, performs a read operation on the first data area; and upon determining that the request status information corresponds to a second request status value, performs a read operation on a second data area of the at least two data areas corresponding to the first address.

4. The memory system of claim 3, wherein, A time point at which data is written to the first data area is earlier than a time point at which data is written to the second data area.

5. The memory system of claim 1, wherein, Upon receiving a write command as the first command, in a case where the write command is a first write command for the first address, the controller performs a write operation on a first data area of the at least two data areas corresponding to the first address and sets the overwritten status information of the first address to a first overwritten status value.

6. The memory system of claim 5, wherein, In a case where the write command is a write command subsequent to the first write command for the first address, the controller: performs a write operation on a second data area corresponding to the first address and sets the overwritten status information of the first address to a second overwritten status value.

7. The memory system of claim 6, wherein, A size of a supplementary data area corresponding to the first address is smaller than at least one of a size of the first data area or a size of the second data area.

8. The memory system of claim 7, wherein, The controller: performs a write operation on the supplementary data area according to the first command; copies data from the second data area to the first data area; and copies data from the supplementary data area to the second data area.

9. The memory system according to claim 1, wherein, Upon receiving a read command as the first command, the controller checks accessible state information of the first address, and in a case where the first address is accessible to a host device that transmits the first command, the controller performs a read operation on a data region corresponding to the first address, and in a case where the first address is not accessible to the host device that transmits the first command, the controller provides the host device with a result value of performing a bit operation on data stored in a data region corresponding to the first address using a preset value and a preset operator. 10.The memory system of claim 1, wherein, Upon receiving a write command as the first command, the controller checks accessible state information of the first address, and in a case where the first address is accessible to a host device that transmits the first command, the controller performs a write operation on a data region corresponding to the first address, and in a case where the first address is not accessible to the host device that transmits the first command, the controller returns an error value to the host device.

11. The memory system of claim 1, wherein, In a case where shared state information for the first address is a first shared state value, and the first address is accessible to a host device that transmits the first command according to the accessible state information for the first address, the controller performs an operation according to the first command.

12. The memory system of claim 1, wherein, Upon receiving a second command for a second address included in the second memory region, the controller controls an operation according to the second command, and allocates a data region among at least two data regions corresponding to the second address to a host device that transmits the second command.

13. The memory system of claim 12, wherein, The shared state information for the first address included in the first memory region is set to a first shared state value, and the shared state information for the second address included in the second memory region is set to a second shared state value.

14. The memory system of claim 13, wherein, The accessible state information of the second address is set to be inaccessible to a host device other than the host device that transmits the second command. 15.A memory system comprising: one or more memory devices, each memory device including a first memory region and a second memory region; and a controller: upon receiving a first command for a first address included in the first memory region, controlling an operation according to the first command based on an indirect mapping table including information of at least two data regions in the first memory region corresponding to the first address; and upon receiving a second command for a second address included in the second memory region, controlling an operation according to the second command on one data region in the second memory region corresponding to the second address.

16. The memory system of claim 15, wherein, The indirect mapping table includes: shared state information indicating a shared state of the first address to indicate whether the first address is a memory region shared by a plurality of host devices or a memory region dedicated to a specific host device; accessible state information indicating whether a specific host device can access the first address; and Overwrite state information indicating a use state of at least two data areas corresponding to the first address to indicate whether data in the at least two data areas is overwrite data.

17. The memory system of claim 15, wherein, A number of host devices that can access the first memory area is equal to or greater than a number of host devices that can access the second memory area.

18. A controller comprising: an internal memory device storing an indirect mapping table including sharing state information, accessible state information, and overwrite state information of at least a portion of memory areas included in an external memory device; and a control circuit: upon receiving a command from an external device, checking the sharing state information, the accessible state information, and the overwrite state information in the indirect mapping table corresponding to an address according to the command; and performing an operation according to the command on the external memory device.

19. The controller of claim 18, wherein, in a case where the overwrite state information corresponds to a first overwrite state value, the control circuit performs the operation according to the command on a first data area corresponding to the address.

20. The controller of claim 19, wherein, the controller: in a case where the overwrite state information corresponds to a second overwrite state value, checking request state information according to the command; in a case where the request state information corresponds to a first request state value, performing the operation according to the command on the first data area; and in a case where the request state information corresponds to a second request state value, performing the operation according to the command on a second data area corresponding to the address.

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