Data storage device and method for handling lifecycle read disturbances

Abstract

A block of memory in a data storage device may experience read disturbances based on the number of times the block of memory is read and a program-erase count of the block. Non-data word line maintenance triggered by a program-erase count may address the read disturb in some cases, but cannot address the read disturb in other cases, such as when host reads are very dense and not frequently written to the memory. In one embodiment, maintenance is performed on non-data word lines in a block of memory in response to a total life cycle of data reads from the block being above a threshold. In another embodiment, a block is allocated for use based on a life cycle read count of the block rather than only based on the program-erase count of the block. Other embodiments are disclosed.

Description

BACKGROUND

[0001] Typical read disturb (RD) phenomena in a block of memory can be corrected after the block is erased and programmed. For a new generation of three-dimensional memory, the total number of reads that a block can sustain throughout its lifetime can be limited. This is referred to as cumulative read disturb or lifetime read disturb. The lifetime read disturb constraint is due to the threshold voltage (Vt) of any non-data word line (NDWL) moving out of a specified threshold voltage (Vt) window. NDWL disturb can also occur due to the total number of reads rather than the total number of program / erase cycles in previous generations of memory. Once the disturb on the select gate on the drain side (SGD) exceeds a certain limit, it can lead to loss of user’s data and the block can become unusable. BRIEF DESCRIPTION OF DRAWINGS

[0002] Figure 1A is a block diagram of a data storage device of one embodiment.

[0003] Figure 1B is a block diagram of a storage module illustrating one embodiment.

[0004] Figure 1C is a block diagram of a hierarchical storage system illustrating one embodiment.

[0005] Figure 2A is a block diagram of a data storage device illustrating one embodiment. Figure 1A is a block diagram of components of a controller of a data storage device.

[0006] Figure 2B is a block diagram of a data storage device illustrating one embodiment. Figure 1A is a block diagram of components of a data storage device.

[0007] Figure 3 is a block diagram of a host and a data storage device of one embodiment.

[0008] Figure 4 is a flow diagram of a method of a non-data word line (NDWL) maintenance procedure to address lifetime read disturb of one embodiment.

[0009] Figure 5 is a total byte read threshold calculation table of one embodiment.

[0010] Figure 6 is a flow diagram of a wear leveling procedure of one embodiment.

[0011] Figure 7 is a flow diagram of an alternative wear leveling procedure of one embodiment.

[0012] Figure 8FIG. 10 is a flowchart of an alternative wear leveling procedure of an embodiment.

[0013] Figure 9 FIG. 11 is a flowchart of a block program-erase count maintenance method of an embodiment.

[0014] FIG. 10 is a flowchart of a prior art method for non-data word line (NDWL) maintenance. DETAILED DESCRIPTION

[0015] The following embodiments relate generally to data storage devices and methods for handling life cycle read disturbance. In one embodiment, a data storage device is provided that includes a memory and one or more processors. The one or more processors, individually or in combination, are configured to: read a block in the memory; determine whether a total amount of life cycle reads from the block is above a first threshold; and in response to determining that the total amount of life cycle reads from the block is above the first threshold, perform maintenance on non-data word lines in the block.

[0016] In another embodiment, a method performed in a data storage device that includes a memory having a plurality of blocks is provided. The method includes: selecting a block having a lowest program-erase count from the plurality of blocks for possible allocation; determining whether a life cycle read count of the block is greater than a threshold; in response to determining that the life cycle read count of the block is not greater than the threshold, allocating the block; and in response to determining that the life cycle read count of the block is greater than the threshold, selecting another block from the plurality of blocks for possible allocation.

[0017] In yet another embodiment, a data storage device is provided that includes: a memory; and means for handling life cycle read disturbance of a block of the memory based on a number of times the block of the memory is read, rather than only based on a number of times the block of the memory is programmed and erased.

[0018] Other embodiments are possible, and each of the embodiments can be used alone or in combination. Accordingly, various embodiments will now be described with reference to the drawings.

[0019] Embodiments

[0020] The following embodiments relate to a data storage device (DSD). As used herein, “data storage device” refers to a non-volatile device that stores data. Examples of CSDs include, but are not limited to, a hard disk drive (HDD), a solid state drive (SSD), a tape drive, a hybrid drive, etc. Details of an example DSD are provided below.

[0021] Figures 1A to 1C Examples of data storage devices suitable for implementing aspects of these embodiments are shown in the figures. It should be noted that these are merely examples and other implementations can be used. Figure 1A is a block diagram illustrating a data storage device 100 according to one embodiment. Referring to Figure 1A The data storage device 100 in this example includes a controller 102 coupled with non-volatile memory, which can be made up of one or more non-volatile memory dies 104. As used herein, the term die refers to a collection of non-volatile memory cells formed on a single semiconductor substrate and associated circuitry for managing the physical operations of those non-volatile memory cells. The controller 102 interfaces with a host system and transmits command sequences for read, program, and erase operations to the non-volatile memory dies 104. Additionally, as used herein, the phrase “in communication with” or “coupled with” can mean direct communication / coupling or indirect communication / coupling through one or more components, which can or can not be shown or described herein. The communication / coupling can be wired or wireless.

[0022] The controller 102, which can be a non-volatile memory controller (e.g., a flash, resistive random access memory (ReRAM), phase change memory (PCM), or magnetoresistive random access memory (MRAM) controller), can include one or more components configured individually or in combination to perform certain functions, including but not limited to those described herein and shown in the flowcharts. For example, as shown in Figure 2A The controller 102 can include one or more processors 138 configured individually or in combination to perform functions, such as but not limited to those described herein and shown in the flowcharts, by executing computer-readable program code stored internally in the controller 102 and / or in one or more non-transitory memories 139 external to the controller 102 (e.g., in random access memory (RAM) 116 or read-only memory (ROM) 118), as shown in

[0023] In one example embodiment, the non-volatile memory controller 102 is a device that manages data stored on non-volatile memory and communicates with a host, such as a computer or electronic device, having any suitable operating system. In addition to the specific functions described herein, the non-volatile memory controller 102 can have various functions. For example, the non-volatile memory controller can format the non-volatile memory to ensure that the memory is operating correctly, flag bad non-volatile memory cells, and allocate spare cells to replace future failed cells. Some portion of the spare cells can be used to hold firmware (and / or other metadata used for housekeeping and tracking) to operate the non-volatile memory controller and implement other features. In operation, when the host needs to read data from or write data to the non-volatile memory, it can communicate with the non-volatile memory controller. If the host provides a logical address at which to read / write data, the non-volatile memory controller can convert the logical address received from the host to a physical address in the non-volatile memory. The non-volatile memory controller can also perform various memory management functions, such as, but not limited to, wear leveling (allocating writes to avoid wearing out blocks of particular memory that would otherwise be repeatedly written to) and garbage collection (after a block is full, only valid data pages are moved to a new block so the entire block can be erased and reused).

[0024] The non-volatile memory die 104 can include any suitable non-volatile storage medium, including resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), phase change memory (PCM), NAND flash memory cells, and / or NOR flash memory cells. The memory cells can be in the form of solid state (e.g., flash) memory cells and can be single programmable, multi-programmable, or multi-time programmable. The memory cells can also be single level cells (SLC), multi-level cells (MLC) (e.g., dual level cells, triple level cells (TLC), quad level cells (QLC)), or use other memory cell level technology now known or later developed. Additionally, the memory cells can be fabricated in two-dimensional or three-dimensional fashion.

[0025] The interface between the controller 102 and the non-volatile memory die 104 can be any suitable flash interface, such as Toggle Mode 200, 400, or 800. In one embodiment, the data storage device 100 can be a card-based system, such as a secure digital (SD) card or a micro secure digital (microSD) card. In alternative embodiments, the data storage device 100 can be part of an embedded data storage device.

[0026] While in Figure 1AIn the illustrated example, the data storage device 100 (sometimes referred to herein as a storage module) includes a single channel between the controller 102 and the non-volatile memory die 104, although the subject matter described herein is not limited to having a single memory channel. For example, in some storage system architectures (such as the architecture shown in Figure 1B and Figure 1C there can be 2, 4, 8, or more memory channels between the controller and the memory device depending on the capabilities of the controller. In any of the embodiments described herein, there can be more than one single channel between the controller and the memory die, even if a single channel is shown in the figures.

[0027] Figure 1B A storage module 200 is illustrated that includes multiple non-volatile data storage devices 100. As such, the storage module 200 can include a storage controller 202 that interfaces with a host and data storage devices 204 that include multiple data storage devices 100. The interface between the storage controller 202 and the data storage devices 100 can be a bus interface such as a Serial Advanced Technology Attachment (SATA), Peripheral Component Interconnect Express (PCIe) interface, Double Data Rate (DDR) interface, or Serial Attached Small Computer Interface (SAS / SCSI). In one embodiment, the storage module 200 can be a solid state drive (SSD) or a Non-Volatile Dual In-Line Memory Module (NVDIMM) such as found in a server PC or a portable computing device such as a laptop computer and a tablet.

[0028] Figure 1C is a block diagram illustrating a hierarchical storage system. The hierarchical storage system 250 includes multiple storage controllers 202, each of which controls a respective data storage device 204. A host system 252 can access the memory within the storage system 250 via a bus interface. In one embodiment, the bus interface can be a Non-Volatile Memory Express (NVMe) or an Ethernet Fibre Channel (FCoE) interface. In one embodiment, Figure 1C The illustrated system can be a rack-mountable mass storage system that is accessible by multiple host computers, such as can be found in a data center or other location where mass storage is needed.

[0029] Referring again to Figure 2AThe controller 102 in this example also includes a front-end module 108 that interfaces with a host, a back-end module 110 that interfaces with one or more non-volatile memory dies 104, and various other components or modules such as, but not limited to, a buffer manager / bus controller module that manages buffers in a RAM 116 and controls internal bus arbitration of the controller 102. As described above, the modules can include one or more processors or components. A ROM 118 can store system boot code. While Figure 2A The RAM 116 and ROM 118 are shown positioned separately from the controller 102, but in other embodiments, one or both of the RAM 116 and ROM 118 can be located within the controller 102. In still other embodiments, portions of the RAM 116 and ROM 118 can be located within and outside of the controller 102.

[0030] The front-end module 108 includes a host interface 120 and a physical layer interface (PHY) 122 that provide an electrical interface to a host or next level storage controller. The type of host interface 120 can be selected depending on the type of memory used. Examples of host interfaces 120 include, but are not limited to, SATA, SATA Express, Serial Attached Small Computer System Interface (SAS), Fibre Channel, Universal Serial Bus (USB), PCIe, and NVMe. The host interface 120 generally facilitates the transfer of data, control signals, and timing signals.

[0031] The back-end module 110 includes an error correction code (ECC) engine 124 that encodes data bytes received from a host and decodes and error corrects data bytes read from the non-volatile memory. A command sequencer 126 generates command sequences, such as program command sequences and erase command sequences, for transmission to the non-volatile memory dies 104. A RAID (Redundant Array of Independent Drives) module 128 manages the generation of RAID parity and the recovery of failed data. The RAID parity can be used as an additional level of integrity protection for data written into the memory devices 104. In some cases, the RAID module 128 can be part of the ECC engine 124. A memory interface 130 provides command sequences to the non-volatile memory dies 104 and receives status information from the non-volatile memory dies 104. In one embodiment, the memory interface 130 can be a double data rate (DDR) interface, such as a Toggle Mode 200, 400, or 800 interface. The controller 102 in this example also includes a media management layer 137 and a flash control layer 132 that controls the overall operation of the back-end module 110.

[0032] The data storage device 100 also includes other discrete components 140, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that can interface with the controller 102. In alternative embodiments, one or more of the physical layer interface 122, the RAID module 128, the media management layer 138, and the buffer management / bus controller are optional components that are unnecessary in the controller 102.

[0033] Figure 2B is a block diagram illustrating components of the non-volatile memory die 104 in more detail. The non-volatile memory die 104 includes a peripheral circuit 141 and a non-volatile memory array 142. The non-volatile memory array 142 includes non-volatile memory cells for storing data. The non-volatile memory cells can be any suitable non-volatile memory cells, including ReRAM, MRAM, PCM, NAND flash memory cells, and / or NOR flash memory cells in two-dimensional and / or three-dimensional configurations. The non-volatile memory die 104 also includes a data cache 156 that caches data, and address decoders 148, 150. In this example, the peripheral circuit 141 includes a state machine 152 that provides status information to the controller 102. The peripheral circuit 141 can also include one or more components that are individually or in combination configured to perform certain functions, including but not limited to the functions described herein and illustrated in the flowcharts. For example, as illustrated in Figure 2B As another example, the one or more components can include circuitry, such as but not limited to logic gates, switches, application specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0034] In addition to or instead of one or more processors 138 (or more generally, components) in the controller 102 and one or more processors 168 (or more generally, components) in the memory die 104, the data storage device 100 can include another set of one or more processors (or more generally, components). Generally, regardless of where the one or more processors (or more generally, components) in the data storage device 100 are located, and regardless of how many there are, the one or more processors can be individually or in combination configured to perform various functions, including but not limited to the functions described herein and shown in the flowcharts. For example, the one or more processors (or components) can be located in the controller 102, the memory device 104, and / or other locations in the data storage device 100. Additionally, different processors (or components) or combinations of processors (or components) can be used to perform different functions. Moreover, the means for performing a function can be implemented with a controller that includes one or more components (e.g., processors or other components described above).

[0035] Again, returning to Figure 2A , the flash control layer 132 (which will be referred to herein as the flash translation layer (FTL)) handles flash errors and interfaces with the host. Specifically, the FTL (which can be an algorithm in firmware) is responsible for the internals of memory management and translating writes from the host to writes to the memory 104. The FTL can be needed because the memory 104 can have limited durability, can only be written to a number of pages, and / or can not be written to (unless it is erased as a block). The FTL understands these potential limitations of the memory 104, which can not be visible to the host. Thus, the FTL attempts to translate writes from the host to writes in the memory 104.

[0036] The FTL can include a logical to physical address (L2P) mapping (sometimes referred to herein as a table or data structure) and an allocated cache memory. As such, the FTL translates logical block addresses (“LBAs”) from the host to physical addresses in the memory 104. The FTL can include other features, such as but not limited to power fail recovery (so that the data structures of the FTL can be recovered in the event of a sudden loss of power) and wear leveling (so that wear is evenly distributed across memory blocks to prevent certain blocks from wearing out too much, which would lead to a greater chance of failure).

[0037] Again, returning to the figures, Figure 3is a block diagram of a host 300 and data storage device 100 of an embodiment. The host 300 can take any suitable form, including but not limited to a computer, a mobile phone, a tablet, a wearable device, a digital video recorder, a surveillance system, etc. In this embodiment, the host 300 (here, a computing device) includes one or more processors 330 and one or more memories 340. In an embodiment, computer-readable program code stored in the one or more memories 340 configures the one or more processors 330 to perform the actions described herein as being performed by the host 300. Thus, the actions performed by the host 300 are sometimes referred to herein as being performed by an application (computer-readable program code) running on the host 300. For example, the host 300 can be configured to send data (e.g., initially stored in the host's memory 340) to the data storage device 100 for storage in the data storage device's memory 104.

[0038] As described above, a typical read disturb (RD) phenomenon in a block of memory can be corrected after the block is erased and programmed. For a new generation of three-dimensional memory, the total number of reads that a block can sustain throughout its lifetime can be limited. This is referred to as cumulative read disturb or lifetime read disturb. The lifetime read disturb constraint is due to the threshold voltage (Vt) of any non-data word line (NDWL) (e.g., a word line that does not store data) shifting out of a specified threshold voltage (Vt) window. NDWL disturb can also occur due to the total number of reads rather than the total number of program / erase cycles in a previous generation of memory. Once the select gate on the drain side (SGD) is disturbed beyond a certain limit, it can result in loss of user’s data and the block can become unusable.

[0039] The lifecycle / cumulative read disturb problem can be partially addressed using NDWL maintenance, which can be triggered after a certain number of program-erase cycles (PECs). FIG. 10 is a flowchart 1000 of a prior art method for non-data word line (NDWL) maintenance. As shown in FIG. 10, in this method, the controller of the data storage device checks the PEC of a metablock prior to an erase operation (1005). The controller then erases the metablock (1010) and determines whether the metablock PEC is equal to the maintenance PEC threshold (1015). If not, no detection / correction is needed, and the controller continues its normal operation (1020). However, if so, the controller executes the select gate (SG) dummy word line maintenance flow. In this flow, the controller determines whether the PEC of the upper tail is detected (1025). If so, the controller attempts to detect and correct the upper tail (104), and then determines whether the PEC of the lower tail is detected (1045). If the PEC of the lower tail is not detected, the controller 102 continues its normal operation (1050). However, if the PEC of the lower tail is detected, the controller executes the lower tail detection / correction procedure (1030), and then executes the over program (OP) indication procedure (1035), which is executed regardless of whether the lower tail detection fails or passes (for the extreme case of an abnormal shutdown). The controller then continues normal operation (1050).

[0040] If the NDWL / SGD Vt shifts due to lifecycle read disturb, the above-described flow can be used to detect and correct this situation. However, if the host reads are very dense and infrequently write to the memory, the NDWL flow can not be triggered frequently enough to address the lifecycle read disturb problem.

[0041] The following embodiments provide several solutions that can address the lifecycle read disturb problem. Some of these embodiments can be implemented at the firmware level, while others can be implemented at a higher level (e.g., at the architecture level).

[0042] In one embodiment, the controller 102 in the data storage device is configured to detect a life cycle read disturb issue in the read path. As noted above, if the total reads that occur on a block exceed a certain number (e.g., “x” million reads), this can disturb the non-data word lines, causing data loss and grown bad blocks (GBBs). If the data storage device 100 does not have a counter for each block to track this, the total data reads (e.g., terabytes read (TBR)) from the memory 104 can be recorded and read from a log in the data storage device 100. Thus, a certain TBR threshold can be used as a trigger mechanism for NDWL maintenance. In the proposed flow, the controller 102 can check the blocks against the TBR threshold to trigger the NDWL maintenance flow. Thus, the NDWL flow is triggered even in the case of read-intensive workloads with little PEC increment, which is different from the current NDWL flow.

[0043] Adding a bit error rate (BER)-based NDWL trigger on top of the TBR-based trigger in the read path can further help detect this life cycle read disturb issue, and more detailed checks can be added to the BER-based NDWL trigger. The life cycle read disturb can only occur on the edge blocks, and a typical symptom of this issue is that the erase shoulder on the last few word lines of these blocks is higher than normal. Thus, in one example, an additional erase shoulder check sequence can be added in order to precisely enter the NDWL maintenance only when the BER on those highly sensitive word lines of these blocks is high. These detailed checks can help to more precisely enter the NDWL maintenance, as frequent entry into the NDWL maintenance can impact system performance / delay.

[0044] Again referring back to the figures, Figure 4 is a flowchart 400 of a method for one embodiment of the NDWL maintenance flow to address life cycle read disturb. As shown in Figure 4 For a block in the memory 104 (401), the controller 102 reads the block (405) and determines whether the bit error rate (BER) is greater than a first threshold (act 410), as shown in Figure 5 A TBR threshold calculation table for one example implementation is shown. As shown in the table, in this example, a block is read about one million times, and the threshold is set to half of the value of the total TBR (if this value is exceeded, the NDWL maintenance flow is triggered).

[0045] If the TBR is not above the second threshold, the controller 102 continues normal operation (420). However, if the BER is above the first threshold or if the TBR is above the second threshold, the controller 102 performs the NDWL maintenance procedure (425). In this procedure, the controller 102 determines whether the detection attempt passes (426). In one example, for NDWL detection, the controller 102 sets the NAND parameters for upper tail detection. The controller 102 issues a read operation on the NDWL and, if the upper tail detection bits fail, the controller 102 relinks the new physical block and continues normal operation. If all of the flask interface modules (FIMs) are checked and no upper tail detection bits fail, the controller 102 moves to lower tail detection. In lower tail detection, the controller 102 sets the PEC and NAND parameters for lower tail detection. The controller 102 issues a read operation on the NDWL. If the lower tail detection bits fail, the controller 102 marks the location of the FIM / die / plane / block for lower tail correction.

[0046] Referring again to Figure 4 If the detection attempt passes, the controller 102 continues normal operation (420). However, if the detection attempt does not pass, the controller 102 determines whether the correction attempt passes (427). In one example embodiment, for NDWL correction, the controller 102 sets the NAND parameters for the marked block for lower tail programming. The controller 102 issues a program operation on the NDWL and checks the program status. If the program status fails, the controller 102 resets the NAND parameters and marks the block as a GBB. If the program status passes, the controller 102 checks whether the block is over programmed. If the block is not over programmed, the controller 102 resets the NAND parameters and continues normal operation. Thus, referring again to Figure 4 If the correction attempt passes, the controller 102 continues normal operation (420). However, if the correction attempt does not pass, the controller 102 marks the block as a growing bad block (GBB) (445).

[0047] If the controller 102 erases the block (430), the controller 102 determines whether the block program-erase count (PEC) is equal to the maintenance PEC (435). If the block program-erase count (PEC) is equal to the maintenance PEC, the controller 102 performs the NDWL maintenance procedure (425), as described above. However, if the block program-erase count (PEC) is not equal to the maintenance PEC, the controller 102 determines whether there is an erase failure (440). If there is an erase failure, the controller 102 marks the block as a growing bad block (GBB) (445). Otherwise, the controller 102 continues normal operation (420).

[0048] Thus, in this example embodiment, the block is erased and the PEC is checked. If the PEC is equal to the maintenance PEC threshold, then NDWL detection is started. If there is an erase failure, then the block is marked as GBB; otherwise, normal operation is performed. The block is read and the BER is checked against a predetermined threshold. If the BER is greater than the threshold, then NDWL detection is performed. If the BER is less than the threshold and the TBR is greater than a predetermined threshold, then NDWL processing is performed. If the TBR is less than the threshold, then normal operation continues for the block. If the detection phase fails, then the block is corrected, followed by normal operation. If the correction fails, then the block is marked as GBB.

[0049] Turning now to another embodiment, wear leveling is now typically based entirely on PEC counts. However, since a block can become a bad block purely based on total read counts over its lifetime, some wear leveling can also be based on reads. This embodiment can be subdivided into two parts: (1) read counts based on cold data block allocation, and (2) use of read counts in the overall wear leveling mechanism. Regarding read counts based on cold data block allocation, this can be done by monitoring the read counts on each block. For blocks showing high read counts, the controller 102 can avoid allocating these blocks in the next program-erase cycle. This can prevent runaway blocks based on read counts.

[0050] Since the lifetime read disturb problem due to NDWL Vt shift only occurs on edge blocks, the read counts of those blocks can be monitored only, and then cold data (based on read perspective) can be placed in these blocks only. This mechanism can further reduce system / firmware / RAM overhead to keep read counts of each block or metablock. Figures 6 to 8 This embodiment is illustrated, which uses a wear leveling procedure to address the lifetime read disturb problem.

[0051] Figure 6 is a flowchart 600 of a typical wear leveling procedure. As shown in Figure 6 When the controller 102 determines that a block is needed (600), the controller 102 selects a block with the lowest PEC (620). The controller 102 then erases the block (630) and writes and reads the block (640). If the data in the block is invalid, then the data needs to be relocated (650), after which the block is released (660).

[0052] Figure 7 is a flowchart 700 of an alternative wear leveling procedure of an embodiment. As shown in Figure 7As shown in FIG, when the controller 102 determines that a block is needed (700), the controller 102 selects the block with the lowest PEC (720). The controller 102 then erases the block (730) and writes and reads the block (670). If the data in the block is invalid, the data needs to be relocated (750) and then the block is released (760). However, after the controller 102 selects the block, the controller 102 performs additional processing to use the read count before allocating the block. More specifically, the controller 102 checks the lifetime read (LTRD) count of the block (720) and determines whether the LTRD is greater than a certain threshold (730). If so, the method loops back to 620. If not, the method proceeds to 630.

[0053] Figure 8 FIG. 8 is a flow chart 800 of another alternative wear leveling process according to an embodiment. Figure 8 As shown in , when the controller 102 determines that a block is needed (800), the controller 102 selects the block with the lowest PEC (820). The controller 102 then erases the block (830) and then writes and reads the block (840). If the data in the block is invalid, the data needs to be relocated (850) and then the block is released (860). However, after the controller 102 selects the block, the controller 102 further optimizes the additional processing so that the read counter is only used for edge blocks. More specifically, the controller 103 determines whether the block is an edge block (810). If the block is not an edge block, the method proceeds to 830. However, if the block is an edge block, the controller 102 checks the lifetime read disturbance (LTRD) count of the block (820) and determines whether the LTRD is greater than a certain threshold (730). If so, the method loops back to 620. If not, the method proceeds to 630.

[0054] In short, Figure 6 As shown, typical wear leveling uses only PEC when selecting blocks, while Figure 7 In the embodiment shown in , the controller 102 uses the LTRD count and the PEC when selecting a block. In addition, Figure 8 The implementation shown in has a marginal block check on top of the LTRD count to address this issue while minimizing the counters kept by the system / firmware.

[0055] The second subsection (using read counts in the overall wear leveling mechanism) will now be discussed. In many data workloads on data storage devices such as SSDs (both client and enterprise), some portions of the data are read frequently, while other portions are stored on those data blocks with minimal reads. In order to ensure that at a system level, no memory block exceeds the lifetime read count, certain changes can be made to the wear leveling algorithm. Currently, the wear leveling algorithm is based solely on the PEC and does not consider any reads at all. In this embodiment, if the number of reads on the block exceeds a certain threshold, the controller 102 can increase the block PEC. After exceeding the threshold, the controller 102 can increase the PEC of the block. The existing wear leveling algorithm can then ensure that no block in the system exceeds the lifetime block read count before the end of the life of the block PEC.

[0056] An example of this implementation is provided below, using the following assumptions:

[0057] - Maximum PEC allowed per block = 2000

[0058] -The maximum number of reads allowed for a block in its entire life cycle = 1000M

[0059] - To maintain the lifetime read count, the maximum read allowed for each erase cycle of the block = 1000M / 2K = 0.5M

[0060] Therefore, in this example, for every 0.5M block reads, the controller 102 will increment the block PEC by one.

[0061] If the block read count exceeds 0.5M before marking the block as free, the controller 102 may increase the block erase count by one. If the block read count exceeds 1M reads, the controller 102 may increase the PEC by two.

[0062] The current wear leveling algorithm selects the block with the lowest PEC. Therefore, this block should not be selected. Even if it is selected and the workload is read-intensive (0.5M read count per block), this block will only be cycled (erased) 1000 times, thus keeping the lifetime read count of the block at 1000M.

[0063] Figure 9 FIG. 9 is a flow chart of a block PEC maintenance method according to an embodiment. Figure 9As shown in the middle, after the controller 102 determines that a new block is needed (910), the controller 102 checks the lowest PEC block (920). The controller 102 then erases (940), programs (950), and reads (960) the block. The controller 102 then increments the PEC of the block by X (960), which is added to the total PEC impact (980). Additionally, after the block is erased, the controller 102 increments the block PEC by 1 (970), and this is added to the total PEC impact (980). After being added to the total PEC impact, the controller 102 increments the PEC of this block, and the method loops back to 920.

[0064] It should be noted that the block-based counter used in this implementation can increase the ASIC RAM budget. In cases where there is a RAM budget issue, the read-based counter can only be applied to the edge blocks, which are susceptible to the life cycle read disturb issue. Thus, the PEC of only these blocks can be incremented if the read count exceeds a threshold. It should also be noted that this implementation also accounts for reads for wear leveling purposes, whereas existing wear leveling algorithms only use PEC. Here, reads can be used to address the life cycle read disturb issue, but there can be other scenarios where a read-based wear leveling concept can be used in data storage devices such as SSDs.

[0065] These implementations have several advantages. For example, these implementations can improve the quality / reliability of a data storage device by preventing data loss, preventing growing bad blocks, and ultimately preventing the data storage device from becoming read-only. These implementations can also allow blocks to remain in good condition for longer in read-intensive workloads. Given that today’s popular applications such as artificial intelligence, machine learning, and deep learning are write-once and read-many, these implementations can improve the lifetime of data storage devices for these workloads and applications.

[0066] Finally, as noted above, any suitable type of memory can be used. Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices, nonvolatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read-only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), and other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, a flash memory device can be configured in a NAND or a NOR configuration.

[0067] The memory devices can be formed of passive elements and / or active elements in any combination. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements such as resistive random access memory (ReRAM), phase change material, etc., and optionally include steering elements such as diodes, etc. Further by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing charge storage regions such as floating gates, conductive nanoparticles, or charge storage dielectric material.

[0068] The plurality of memory elements can be configured such that they are connected in series or such that each element can be individually accessed. By way of non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND memory array can be configured such that the array is composed of a plurality of strings of memory, where a string is composed of a plurality of memory elements that share a single bit line and are accessed as a group. Alternatively, the memory elements can be configured such that each element can be individually accessed, such as a NOR memory array. NAND and NOR memory configurations are examples, and the memory elements can be configured in other ways.

[0069] Semiconductor memory elements located within and / or above a substrate can be arranged in two or three dimensions, such as a two-dimensional memory structure or a three-dimensional memory structure.

[0070] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane (e.g., in an x-z directional plane) that extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate can be a wafer upon or in which layers of memory elements are formed, or it can be a carrier substrate that is attached to the memory elements after they are formed. By way of non-limiting example, the substrate can comprise a semiconductor such as silicon.

[0071] The memory elements can be arranged in a single memory device level in an ordered array, such as in a plurality of rows and / or columns. However, the memory elements can be arranged in irregular or non-orthogonal configurations. The memory elements can each have two or more electrodes or contact lines, such as bit lines and word lines.

[0072] A three-dimensional memory array is arranged such that memory elements occupy multiple planes or multiple memory device levels, forming a structure in three dimensions (i.e., in an x-direction, a y-direction, and a z-direction, where the y-direction is substantially perpendicular to a major surface of the substrate, and the x-direction and z-direction are substantially parallel to the major surface of the substrate).

[0073] As non-limiting examples, three-dimensional memory structures can be arranged vertically as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to a major surface of a substrate, i.e., in the y-direction), with multiple memory elements in each column in each level. The columns can be arranged in a two-dimensional configuration, e.g., in the x-z plane, resulting in a three-dimensional arrangement of memory elements with elements on multiple vertically stacked memory levels. Other configurations of three-dimensional memory elements can also constitute a three-dimensional memory array.

[0074] As a non-limiting example, in a three-dimensional NAND memory array, memory elements can be coupled together to form NAND strings within a single horizontal (e.g., x-z) memory device level. Alternatively, memory elements can be coupled together to form vertical NAND strings that traverse multiple horizontal memory device levels. Other three-dimensional configurations are contemplated, with some NAND strings containing memory elements in a single memory level and other strings containing memory elements across multiple memory levels. Three-dimensional memory arrays can also be designed in NOR configurations as well as ReRAM configurations.

[0075] Generally, in a monolithic three-dimensional memory array, one or more memory device levels are formed over a single substrate. Optionally, a monolithic three-dimensional memory array can also have one or more memory tiers at least partially within a single substrate. As a non-limiting example, the substrate can comprise a semiconductor, such as silicon. In a monolithic three-dimensional array, the tiers that make up each memory device level of the array are generally formed on the tiers of the underlying memory device levels of the array. However, the tiers of adjacent memory device levels of a monolithic three-dimensional memory array can be shared or have intervening tiers between the memory device levels.

[0076] Two-dimensional arrays can then be formed individually and then packaged together to form a non-monolithic memory device having multiple memory tiers. For example, a non-monolithic stacked memory can be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of one another. The substrates can be thinned or removed from the memory device levels prior to stacking, but because the memory device levels are initially formed over separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. Further, multiple two-dimensional memory arrays or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0077] Memory elements are typically operated and communicated with using associated circuitry. As non-limiting examples, a memory device can have circuitry for controlling and driving the memory elements to implement functions such as programming and reading. This associated circuitry can be on the same substrate as the memory elements and / or on a separate substrate. For example, a controller for memory read-write operations can be positioned on a separate controller chip and / or on the same substrate as the memory elements.

[0078] Those skilled in the art will recognize that the present application is not limited to the two-dimensional and three-dimensional structures described, but encompasses all related memory structures within the spirit and scope of the present application as described herein and as understood by those skilled in the art.

[0079] It is contemplated that the foregoing detailed description is to be understood as an illustration of selected forms that the application can employ, and not as a definition of the application. It is only the following claims, including all equivalents, that are intended to define the scope of the application. Finally, it should be noted that any of the aspects of any of the embodiments described herein can be used alone or in combination with one another.

Claims

1. A data storage device, the data storage device comprising: a memory; and one or more processors, individually or in combination, configured to: read a block in the memory; determine whether a total amount of lifetimes of data reads from the block is above a first threshold; and in response to determining that the total amount of lifetimes of data reads from the block is above the first threshold, perform maintenance on non-data word lines in the block.

2. The data storage device of claim 1, wherein, the one or more processors, individually or in combination, further configured to: determine whether a bit error rate of the block is above a second threshold; and in response to determining that the bit error rate of the block is above the second threshold, perform maintenance on non-data word lines in the block.

3. The data storage device of claim 1, wherein, the one or more processors, individually or in combination, further configured to: in response to determining that the total amount of lifetimes of data reads from the block is not above the first threshold, perform an additional operation without performing maintenance on the non-data word lines in the block.

4. The data storage device of claim 1, wherein, the one or more processors, individually or in combination, further configured to: attempt to erase the block; determine whether a program-erase count of the block is equal to a maintenance program-erase count; and in response to determining that the program-erase count of the block is equal to the maintenance program-erase count, perform maintenance on the non-data word lines in the block.

5. The data storage device of claim 4, wherein, the one or more processors, individually or in combination, further configured to: in response to determining that the program-erase count of the block is not equal to the maintenance program-erase count: determine whether the attempt to erase the block is successful; and in response to determining that the attempt to erase the block is not successful, mark the block as a grow bad block.

6. The data storage device of claim 5, wherein, the one or more processors, individually or in combination, further configured to: in response to determining that the attempt to erase the block is successful, perform an additional operation without performing maintenance on the non-data word lines in the block.

7. The data storage device of claim 1, wherein, the one or more processors, individually or in combination, further configured to perform maintenance on the non-data word lines in the block by performing a detection operation and performing a correction operation in response to the detection operation failing.

8. The data storage device of claim 7, wherein, the one or more processors, individually or in combination, further configured to perform the detection operation by: performing a read operation on the block; determining whether an upper tail error exists; in response to determining that the upper tail error does not exist, determining whether a lower tail error exists; and in response to determining that the lower tail error exists, performing a correction operation.

9. The data storage device of claim 8, wherein, the one or more processors, individually or in combination, further configured to: perform the correction operation by performing a lower tail program operation; and in response to the lower tail program operation being unsuccessful, mark the block as a grow bad block.

10. The data storage device of claim 9, wherein, the one or more processors, individually or in combination, further configured to: in response to the lower tail program operation being successful, perform an additional operation without performing maintenance on the non-data word lines in the block.

11. The data storage device of claim 1, wherein, the memory comprises a three-dimensional memory.

12. A method performed in a data storage device, the data storage device comprising a memory, the memory comprising a plurality of blocks, the method comprising: selecting a block from the plurality of blocks having a lowest program-erase count for possible allocation; determining whether a lifetime read count of the block is greater than a threshold; in response to determining that the lifetime read count of the block is not greater than the threshold, allocating the block; and in response to determining that the lifetime read count of the block is greater than the threshold, selecting another block from the plurality of blocks for possible allocation.

13. The method of claim 12, wherein, allocating the block includes: erasing the block; writing and reading the block; relocating data in the block in response to the data being invalid; and releasing the block.

14. The method of claim 12, wherein, The block includes an edge block.

15. The method of claim 12, further comprising increasing a program-erase count of the block by one in response to erasing the block.

16. The method of claim 12, further comprising increasing a program-erase count of the block in response to reading the block more than a certain number of times.

17. The method of claim 12, further comprising using a read counter to determine the lifetime read count of the block.

18. The method of claim 12, further comprising using the lifetime read count of the block to trigger a wear leveling operation.

19. The method of claim 12, wherein, The memory includes a three-dimensional memory.

20. A data storage device, the data storage device comprising: a memory; and means for handling lifetime read disturbance of a block of the memory based on a number of times the block of the memory is read, and not only based on a number of times the block of the memory is programmed and erased.

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