A multi-level branch predictor supporting branch target buffer compression and a prediction method

Abstract

The application discloses a multi-stage branch predictor supporting branch target buffer compression and a prediction method. The predictor comprises a three-stage structure. The first-stage branch predictor is a single-cycle predictor, which is used for giving a prediction result in one cycle. The second-stage branch predictor is a double-cycle predictor, which is used for giving a prediction result in the second cycle. The third-stage branch predictor is a triple-cycle predictor, which is used for giving a prediction result in the third cycle. A per-cycle PC multiplexer simultaneously sends the selected PC into the three-stage branch predictor, and the three-stage branch predictor respectively gives corresponding prediction results. The low delay of the low-stage predictor guarantees the continuous flow of instructions in the pipeline. The high accuracy of the high-stage predictor reduces the pipeline refresh times caused by branch prediction failure. The combination of the short prediction cycle of the low-stage branch predictor and the high prediction accuracy of the high-stage branch predictor optimizes and compresses the branch target buffer structure of the branch predictor, and reduces the area of the branch target buffer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer system structure, and particularly relates to a multi-level branch predictor supporting branch target buffer compression and a prediction method. BACKGROUND

[0002] Instruction throughput is a core performance indicator of a processor, and superscalar is an instruction-level parallel method for improving instruction throughput. A superscalar processor usually has a deep pipelining feature to improve the running frequency of the processor. An instruction queue divides the pipeline into a front end and a back end. The front end of the pipeline is responsible for providing sufficient instruction supply to prevent instruction starvation. Among them, a branch predictor is responsible for predicting a correct instruction flow.

[0003] The current branch predictor mainly predicts the jump direction and the jump destination address separately, and combines them as the final prediction result. The prediction of the jump direction usually adopts a form of a saturation counter to record the jump form, record the branch jump history and PC extraction features to index the saturation counter, and obtain the jump direction. The prediction of the jump destination address is to store the historical jump destination address of the corresponding instruction in a table, and use PC indexing and comparison of the tag field to obtain the jump destination address result. In order to improve the accuracy of branch prediction, a large number of storage components are used.

[0004] The deep pipelining demand feature of a modern processor, especially a superscalar out-of-order processor, is derived from the restriction of integrated circuit technology on hardware logic complexity per unit time, the high clock frequency demand of the processor, the more complex microarchitecture hardware logic of the processor, and the functional demand of the architecture itself. Moreover, these aspects are mutually restrictive. In order to improve the performance of the processor, the function of the architecture needs to be continuously expanded, which leads to the more complex microarchitecture hardware logic. Restricted by integrated circuit technology, in order to maintain high running frequency, the hardware logic needs to be deep pipelined. The pipeline delay and more complex instruction dependency relationship brought by deep pipelining force the architecture function to be increased again.

[0005] Processor pipelining is a double-edged sword. From the perspective of processor performance, deep pipelining makes the hardware logic between registers less, and achieves higher frequency. The number of pipeline stages of modern processors is deep mainly driven by high operating frequency. However, deep pipelining will lead to an increase in the recovery cost of speculative execution, and deep pipelining will introduce more bubbles when the speculative execution fails, thereby leading to performance degradation. Branch predictor is a typical speculative execution component, which predicts the program control flow in the instruction fetch stage and guides the instruction fetch unit to obtain instructions. When the branch prediction fails, all instructions after the predicted branch instruction will be flushed unconditionally, and the value will be restarted at the correct branch target, thereby introducing a large number of bubbles. With the introduction of advanced predictor structure and multi-level branch predictor, the branch prediction accuracy is very high, but branch prediction needs more storage component area to handle increasingly complex prediction tasks. SUMMARY

[0006] The purpose of the present application is to provide a multi-level branch predictor supporting branch target buffer compression and a prediction method, which can improve the overall branch predictor accuracy while reducing the area of the branch target buffer.

[0007] The technical solution of the present application is:

[0008] A multi-level branch predictor supporting branch target buffer compression, comprising: a three-level branch predictor, from low level to high level, respectively: a first-level branch predictor, a 16-way full-associative branch target buffer, storing jump information and PC value of jump destination address, used to provide jump direction prediction and jump destination address prediction for PC in one cycle; a second-level branch predictor, having a one-cycle delay, used to give a prediction result in the second cycle; the second-level branch predictor comprising: a jump direction predictor, a 1024-row structure, each row containing a 2-bit saturating counter; a branch jump destination address predictor, comprising a branch target buffer offset table and a hit table; a third-level branch predictor, having a two-cycle delay, used to give a prediction result in the third cycle, the third-level branch predictor comprising: a 5-way confidence-based direction predictor and a 5-way confidence-based branch jump destination address predictor, the confidence-based direction predictor comprising a 5-way direction prediction table, each row in each way direction prediction table containing a 2-bit saturating counter, a Tag item and a 1-bit valid bit; a multiplexer, used to receive prediction values of the three-level branch predictor and select a prediction value as the next input of the three-level branch predictor; an instruction cache queue, used to store the final prediction result predicted by the three-level branch predictor and provide the next pipeline stage; a global branch history register, used to save the prediction history of the global branch instruction from the start of execution to the end of the final prediction of the three-level branch predictor; a plurality of branch history registers of different folding lengths, the branch history registers forming a folded history register after being hashed and folded, used to save the prediction history of the globally hashed and folded branch instruction.

[0009] Further, in the second-level branch predictor, the jump direction predictor performs a hash operation on the Index field of the PC and the global branch history, indexes the jump direction prediction table according to the result, and the jump direction prediction table comprises a two-bit saturating counter, used to give a prediction result of the jump direction of the branch prediction instruction, wherein the global branch history is not directly operated, but is hashed and folded to a fixed number of bits, and then is hashed with the PC, and the folded history is updated each time the branch prediction result updates the global branch history.

[0010] Further, in the branch jump destination address predictor of the second-level branch predictor, the branch target buffer offset table is an 8-way set-associative structure, each way having 1024 rows, and the offset bit widths of different ways are respectively: 4 bits, 4 bits, 8 bits, 8 bits, 16 bits, 16 bits, 32 bits and 32 bits; the hit table is a 512-row structure, each row containing a 3-bit hit way number and a 1-bit valid bit.

[0011] Further, the second level branch predictor predicts the jump destination address by querying the branch target buffer offset table and the hit table, the Tag field of the PC of the branch instruction and the corresponding folded history register are subjected to Tag hashing operation, and the Index field and the corresponding folded history register are subjected to Index hashing operation, the Tag hashing result is used to index the hit table to determine in which way the offset of the jump destination address is; the Index hashing result is used to index the branch target buffer table to determine in which row the offset of the jump destination address is, and finally the offset of the jump destination address is determined, wherein the two hashing operations are both hashing operations of different folded histories of the global history branch predictor, that is, the corresponding folded history register, and the folding method is the same as that of the jump direction prediction, if the results of the indexes of the two table items are one invalid state, it is judged that the branch target buffer is missed; when the branch target buffer table is updated, the update is performed according to the offset bit width, and the low offset bit width can be stored in the offset way of the next higher level at most, for example: the 4-bit offset can be stored in the 4-bit width way and the 8-bit width way, the update method uses the improved Tree-LRU algorithm, and the branch target buffer is updated while the Tag index table is updated.

[0012] Further, each way direction prediction table of the third level branch predictor is 1024 rows, 512 rows, 256 rows, 128 rows and 64 rows respectively; the Index field of the PC and the hashing result of the corresponding folded history are used for indexing, the global history length of each way is 0 bit, 13 bit, 37 bit, 91 bit and 145 bit respectively, and the compressed folded history length is 0 bit, 9 bit, 8 bit, 7 bit and 6 bit respectively, and the stored Tag length in different ways is 0 bit, 7 bit, 9 bit, 10 bit and 11 bit respectively.

[0013] Further, the multi-way results of the confidence-based direction predictor are selected as follows:

[0014] If none of the second to fifth prediction tables matches the prediction result, the prediction result of the first prediction table is directly used.

[0015] If one of the second to fifth prediction tables gives a prediction result, the prediction result of the table is directly used.

[0016] If more than two of the second to fifth prediction tables give prediction results, the same prediction result is given.

[0017] If more than two of the second to fifth prediction tables give prediction results, the prediction result of the table with the longest folded history is used as the final prediction result.

[0018] Further, the branch jump destination address predictor in the third level branch predictor based on confidence includes a 5-way support table entry compressed branch target buffer offset table and a 4-way confidence based hit table, each way of the support table entry compressed branch target buffer offset table is a 8-way set associative structure, the structure of each way of the support table entry compressed branch target buffer offset table is the same as the structure of the branch jump destination address predictor in the second level branch predictor, the number of rows is 1024, 512, 256, 128 and 64 respectively; in the 4-way confidence based hit table, 3 bits of confidence and 2 bits of valid bit replace the original 1 bit of valid bit, the number of rows of each way of the hit table is 256, 128, 64 and 32 respectively, and each way of the hit table corresponds to each way of the support table entry compressed branch target buffer offset table from the 2nd way to the 5th way one by one, the folding history length used for indexing each way of the support table entry compressed branch target buffer offset table is different, the Index field is directly used for indexing in the first way, and the Tag field is used for comparison to determine the branch prediction jump destination address, and 3 bits of confidence table item are added in each hit table in the second prediction table to the fifth prediction table to assist in determining the result.

[0019] Further, the multi-way result selection of the branch jump destination address predictor based on confidence is as follows:

[0020] If no prediction result is matched in the second prediction table to the fifth prediction table, the prediction result of the first way is directly selected.

[0021] If a prediction result is matched in the second prediction table to the fifth prediction table, if the confidence in the folding history hit table with the first history length is greater than the result of the confidence in the folding history hit table with the second history length minus 1, and the valid bit is greater than 1, the prediction result corresponding to the folding history hit table with the first history length is selected as the final prediction result, otherwise the prediction result corresponding to the folding history hit table with the second history length is selected.

[0022] Further, the update method of the branch jump destination address predictor based on confidence is as follows:

[0023] If the branch prediction result is correct:

[0024] If the longest folding history result is the final prediction result, and the second longest folding history and its prediction result are inconsistent, the confidence of the longest folding history result is increased by 1, and if the confidence exceeds threshold 4, the valid bit is increased by 1.

[0025] If the longest folding history result is the final prediction result, and the second longest folding history and its prediction result are consistent, the confidence of the second longest folding history result is increased by 1, and if the confidence exceeds threshold 4, the valid bit is increased by 1.

[0026] If the second longest folding history result is the final prediction result and the longest folding history result is not consistent with its prediction result, the longest folding history result confidence is reduced by 1, and the valid bit is reduced by 1 if the confidence is below the threshold. The second longest folding history confidence is increased by 1, and the valid bit is increased by 1 if the confidence is above the threshold.

[0027] If the second longest folding history result is the final prediction result and the longest folding history result is consistent with its prediction result, the longest folding history result valid bit is reduced by 1. The second longest folding history confidence is increased by 1, and the valid bit is increased by 1 if the confidence is above the threshold.

[0028] If the branch prediction result is incorrect:

[0029] If the longest folding history result is the final prediction result, the second longest folding history result is not consistent with its result and the second longest folding history result is correct, the longest history result confidence is reduced by 1, and the valid bit is reduced by 1 if the confidence is below the threshold. The second longest folding history confidence is increased by 1, and the valid bit is increased by 1 if the confidence is above the threshold.

[0030] If the longest folding history result is the final prediction result, the second longest folding history result is not consistent with its result and the second longest folding history result is incorrect, the longest history result confidence is reduced by 1, and the valid bit is reduced by 1 if the confidence is below the threshold. An attempt is made to allocate a table entry in a longer folding history table entry, and if the table entry cannot be allocated, the new result is updated to the current table entry, the confidence is set to 3, and the valid bit is 1.

[0031] If the longest folding history result is the final prediction result, the second longest folding history result is consistent with its result, the longest history result confidence is reduced by 1, and the valid bit is reduced by 1 if the confidence is below the threshold. The second longest folding history valid bit is zeroed, and an attempt is made to allocate a table entry in a longer folding history table entry.

[0032] If the second longest folding history result is the final prediction result, the longest folding history result is not consistent with its result and the longest folding history result is correct, the second longest folding history result confidence is reduced by 1, and the valid bit is reduced by 1 if the confidence is below the threshold. The longest folding history confidence is increased by 1, and the valid bit is increased by 1 if the confidence is above the threshold.

[0033] If the second longest folding history result is the final prediction result, the longest folding history result is not consistent with its result and the longest folding history result is incorrect, the second longest folding history result confidence is reduced by 1, and the valid bit is reduced by 1 if the confidence is below the threshold. An attempt is made to allocate a table entry in a longer history than the longest history.

[0034] If the second longest folding history result is the final prediction result, the longest folding history result is consistent with its result, the second longest folding history result confidence is reduced by 1, and the valid bit is reduced by 1 if the confidence is below the threshold. The longest folding history result is directly set to invalid, and an attempt is made to allocate a table entry in a longer history than the longest history.

[0035] Every 128K instructions, the valid bit is refreshed once.

[0036] A multi-stage branch prediction method supporting branch target buffer compression, uses the above-mentioned predictor to predict, comprising the following steps:

[0037] The PC multi-selector selects the PC every cycle, and the selected PC is sent into the three-stage branch predictor at the same time, the three-stage branch predictor gives the corresponding prediction results respectively, when the prediction results of the high-level branch predictor and the low-level branch predictor are inconsistent, the final prediction result is the result of the high-level branch predictor, and the previously predicted result is refreshed.

[0038] Compared with the prior art, the beneficial effects of the present application are:

[0039] 1、The three-stage branch predictor structure is adopted in the present application, the prediction period of the first-stage branch predictor is short, the branch prediction result can be given within one cycle, the direction and target address can be provided at the same time, two key prediction problems are solved at one time, the dependence on the subsequent prediction stage is reduced, and the fastest path of prediction is ensured; the second-stage branch predictor and the third-stage branch predictor give the prediction results within two cycles and three cycles respectively, the prediction result of the first-stage branch predictor can be corrected in time, and more reliable prediction can be provided; the jump direction predictor of the second-stage branch predictor is of a 1024-row structure, each row contains a 2-bit saturation counter, the capacity is larger than that of the first-stage branch predictor, more branch instructions can be covered, prediction failure caused by insufficient capacity can be avoided, and the branch target buffer table of the second-stage branch predictor is stored in the form of offset amount to store the jump destination address; the offset amount can be compressed into 4bit, 8bit, 16bit and 32bit, the branch target buffer structure of the branch predictor is optimized and compressed, compared with the prior art of storing all destination addresses, the area of the branch target buffer is greatly reduced; the third-stage branch predictor comprises a 5-way confidence-based direction predictor and a 5-way confidence-based branch jump destination address predictor, a larger effective capacity is provided, more different branch instruction histories can be stored, more complex branch patterns can be captured in combination with different prediction algorithms or history index modes, higher prediction accuracy can be realized, and the third-stage branch predictor is based on the confidence mechanism, so that each way predictor in the third-stage branch predictor can evaluate the reliability of the prediction, and the pollution of the low-quality prediction to the pipeline is significantly reduced; the output results of the three-stage predictors are integrated by the multi-selector, the optimal prediction result is dynamically selected, the overall prediction accuracy is maximized, and the accuracy of the overall branch predictor is improved under the condition that the front-end instructions are continuously flowing through the three-stage branch prediction structure.

[0040] 2. This invention redesigns the branch target cache organization structure of the branch predictor. For example, in the third-level branch predictor, a hit table is designed, and the original Tag field is converted into a PC hash calculation. During prediction, the index field and Tag field are hashed simultaneously to index the offset table and the hit table respectively. The hit table stores the path number in the offset table. This design transforms the traditional serial behavior of indexing and tag comparison into a parallel behavior of indexing and tag indexing, which can effectively reduce branch prediction latency and improve pipeline performance. Attached Figure Description

[0041] Figure 1 This is a design architecture diagram of a multi-level branch predictor that supports branch target cache compression according to the present invention.

[0042] Figure 2 This is a schematic diagram of the Tree-Plru algorithm.

[0043] Figure 3 This is a schematic diagram of the second-level branch predictor structure.

[0044] Figure 4 A schematic diagram illustrating the improvement of the Tree-Plru algorithm.

[0045] Figure 5 This is a third-level confidence-based jump direction predictor.

[0046] Figure 6 This is a third-level confidence-based jump destination address predictor that supports branch target cache compression. Detailed Implementation

[0047] The following is combined with Figures 1 to 6 The specific embodiments of the present invention will be described in detail below. In the description of the present invention, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0048] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0049] Example

[0050] As shown in Figure 1 A multi-level branch predictor supporting branch target buffer compression, comprising: a three-level branch predictor, a multiplexer, an instruction cache queue, a global branch history register and a plurality of branch history registers with different folding lengths, the three-level branch predictor comprises, from low level to high level, a first-level branch predictor, a second-level branch predictor and a third-level branch predictor, the first-level branch predictor is a 16-way fully associative branch target buffer, storing jump information and PC value of jump destination address, used to provide jump direction prediction and jump destination address prediction for PC in one cycle; the second-level branch predictor has a one-cycle delay, used to give a prediction result in the second cycle; the second-level branch predictor comprises: a jump direction predictor and a branch jump destination address predictor, the jump direction predictor is a 1024-row structure, each row containing a 2-bit saturating counter; the branch jump destination address predictor comprises a branch target buffer offset table and a hit table; the third-level branch predictor has a two-cycle delay, used to give a prediction result in the third cycle, the third-level branch predictor comprises: a 5-way confidence-based direction predictor and a 5-way confidence-based branch jump destination address predictor, the confidence-based direction predictor comprises 5-way direction prediction tables, each row in each direction prediction table containing a 2-bit saturating counter, a Tag item and a 1-bit valid bit; the multiplexer is used to receive the prediction values of the three-level branch predictor and select one prediction value as the next input of the three-level branch predictor; as shown in Figure 1 The PC multiplexer MUX selects the PC and sends it to the three-level branch predictor, the three-level branch predictor gives the corresponding prediction result respectively, when the prediction result of the high-level branch predictor is inconsistent with that of the low-level branch predictor, the final prediction result is the result of the high-level branch predictor, and the previous predicted result is refreshed; the instruction cache queue is used to store the final prediction result predicted by the three-level branch predictor and provide it to the next pipeline stage; the global branch history register is used to save the prediction history of the global branch instruction from the start of execution to the end of the final prediction; the plurality of branch history registers with different folding lengths form the folded history register after being hashed and folded, and are used to save the prediction history of the global branch instruction after being hashed and folded.

[0051] As shown in Figure 3As shown, in the second level branch predictor, the jump direction predictor hashes the Index field of the PC and the global branch history, indexes the jump direction prediction table according to the result, and the jump direction prediction table includes two-bit saturating counters for giving the prediction result of the jump direction of the branch prediction instruction. Since the global branch history is long, and more history information is used when performing the hash operation, the history is folded to a fixed number of bits for facilitating the hash operation with the corresponding field. The global branch history is not directly operated, but is folded to a fixed number of bits, and then is hashed with the PC. The folded history is updated each time the branch prediction result is updated.

[0052] The branch jump destination address predictor of the second level branch predictor includes an 8-way set associative branch target buffer offset table, 1024 rows in each way, and the bit widths of the offsets corresponding to different ways are respectively 4 bits, 4 bits, 8 bits, 8 bits, 16 bits, 16 bits, 32 bits and 32 bits. The hit table has a 512-row structure, and each row includes a 3-bit hit way number and a 1-bit valid bit.

[0053] The second level branch predictor predicts the jump destination address by querying the branch target buffer offset table and the hit table. The Tag field of the PC of the branch instruction and the corresponding folded history register are subjected to Tag hash operation, and the Index field and the corresponding folded history register are subjected to Index hash operation. The Tag hash result is used to index the hit table to determine in which way the offset of the jump destination address is; the Index hash result is used to index the branch target buffer table to determine in which row the offset of the jump destination address is, and finally the offset of the jump destination address is determined. Both times of hash operation are performed on different folded histories of the global history branch predictor, that is, the corresponding folded history registers, and the folding method is the same as that of the jump direction prediction. If the result of indexing the two table entries is invalid, it is determined that the branch target buffer is missing. When the branch target buffer table is updated, the update is performed according to the offset bit width. The low offset bit width can be stored in the offset way of the next higher level at most. For example, a 4-bit offset can be stored in a 4-bit wide way and an 8-bit wide way. The update method uses an improved Tree-LRU algorithm. The branch target buffer is updated, and the Tag index table is also updated. The Tree-LRU algorithm and the improved Tree-LRU algorithm are respectively as follows. Figure 2 and Figure 4As shown, the improved Tree-Plru algorithm selects a node according to the required offset length. If the node record number is 0, the left leaf node is selected, otherwise the right leaf node is selected. When the hit table entry needs to update the Plru register in reverse, the parent node of the current node is negated from the lowest level to the top. The improved Tree-Plru algorithm used in the compressed branch target cache has the same register bit width length as the original algorithm. The improved Tree-Plru algorithm can place the branch target offset in the entry corresponding to its length as much as possible, reducing area waste. This makes the chip area smaller and the energy efficiency higher under the same prediction accuracy, which is more suitable for the current offset table structure, while avoiding the case of 4-bit offset occupying 32-bit table entries, improving the area utilization.

[0054] As shown in Figure 5 The third-level branch predictor has 1024 rows, 512 rows, 256 rows, 128 rows, and 64 rows in each direction prediction table, respectively. The index field of PC and the hash result of the corresponding folding history are used for indexing. The global history length of each path is 0 bits, 13 bits, 37 bits, 91 bits, and 145 bits, respectively. The compressed folding history length is 0 bits, 9 bits, 8 bits, 7 bits, and 6 bits, respectively. The Tag length stored in different paths is 0 bits, 7 bits, 9 bits, 10 bits, and 11 bits, respectively.

[0055] The multi-path result selection of the confidence-based direction predictor is as follows:

[0056] If none of the second to fifth prediction tables match the prediction result, the prediction result of the first prediction table is directly used.

[0057] If one of the second to fifth prediction tables gives a prediction result, the prediction result of that table is directly used.

[0058] If more than two of the second to fifth prediction tables give the same prediction result, the prediction result is given.

[0059] If more than two of the second to fifth prediction tables give different prediction results, the prediction result of the table with the longest folding history is used as the final prediction result.

[0060] As shown in Figure 6As shown, the confidence-based branch jump destination address predictor in the third-level branch predictor includes a 5-way support table entry compressed branch target buffer offset table and a 4-way confidence-based hit table, each of the 5-way support table entry compressed branch target buffer offset tables is an 8-way set associative structure, each of the 5-way support table entry compressed branch target buffer offset tables has the same structure as the branch jump destination address predictor in the second-level branch predictor, and the number of rows is 1024, 512, 256, 128 and 64 respectively; in the 4-way confidence-based hit table, 3-bit confidence and 2-bit valid bits are used to replace the original 1-bit valid bit, the number of rows of each hit table is 256, 128, 64 and 32 respectively, and each hit table corresponds to one of the second to fifth support table entry compressed branch target buffer offset tables, respectively, each support table entry compressed branch target buffer offset table uses a different folding history length for indexing, the first table uses the Index field for indexing and the Tag field for comparison to determine the branch prediction jump destination address, and each hit table in the second to fifth prediction tables is provided with a 3-bit confidence table item to assist in determining the result.

[0061] The multi-way result selection of the confidence-based branch jump destination address predictor is as follows:

[0062] If no prediction result is matched in the second to fifth prediction tables, the prediction result of the first table is directly used.

[0063] If a prediction result is matched in the second to fifth prediction tables, if the confidence of the longest folding history hit table is greater than or equal to the confidence of the second longest folding history hit table minus 1 and the valid bit is greater than 1, the prediction result corresponding to the longest folding history is selected as the final prediction result, otherwise the prediction result corresponding to the second longest folding history hit table is selected.

[0064] The confidence-based jump destination address predictor updating method is as follows:

[0065] If the branch prediction result is correct:

[0066] If the longest folding history result is the final prediction result and the second longest folding history result is inconsistent with the prediction result, the confidence of the longest folding history result is increased by 1, and if the confidence exceeds threshold 4, the valid bit is increased by 1.

[0067] If the longest folding history result is the final prediction result and the second longest folding history result is consistent with the prediction result, the confidence of the second longest folding history result is increased by 1, and if the confidence exceeds threshold 4, the valid bit is increased by 1.

[0068] If the second longest folding history result is the final prediction result, and the longest folding history result is inconsistent with its prediction result, the longest folding history result confidence is reduced by 1, and the valid bit is reduced by 1 if the confidence is lower than the threshold; the second longest folding history confidence is increased by 1, and the valid bit is increased by 1 if the confidence is higher than the threshold.

[0069] If the second longest folding history result is the final prediction result, and the longest folding history result is consistent with its prediction result, the longest folding history result confidence is reduced by 1, and the valid bit is reduced by 1; the second longest folding history confidence is increased by 1, and the valid bit is increased by 1 if the confidence is higher than the threshold.

[0070] If the branch prediction result is incorrect:

[0071] If the longest folding history result is the final prediction result, the second longest folding history result is inconsistent with its result and the second longest folding history result is correct, the longest history result confidence is reduced by 1, and the valid bit is reduced by 1 if the confidence is lower than the threshold; the second longest folding history confidence is increased by 1, and the valid bit is increased by 1 if the confidence is higher than the threshold.

[0072] If the longest folding history result is the final prediction result, the second longest folding history result is inconsistent with its result and the second longest folding history result is incorrect, the longest history result confidence is reduced by 1, and the valid bit is reduced by 1 if the confidence is lower than the threshold, and try to allocate table items in longer folding history table items, if unable to allocate table items, update the new result to the current table item, set the confidence to 3, and the valid bit to 1.

[0073] If the longest folding history result is the final prediction result, the second longest folding history result is consistent with its result, the longest history result confidence is reduced by 1, and the valid bit is reduced by 1 if the confidence is lower than the threshold, the second longest folding history valid bit is zero, and try to allocate table items in longer folding history table items.

[0074] If the second longest folding history result is the final prediction result, the longest folding history result is inconsistent with its result and the longest folding history result is correct, the second longest folding history result confidence is reduced by 1, and the valid bit is reduced by 1 if the confidence is lower than the threshold; the longest folding history confidence is increased by 1, and the valid bit is increased by 1 if the confidence is higher than the threshold.

[0075] If the second longest folding history result is the final prediction result, the longest folding history result is inconsistent with its result and the longest folding history result is incorrect, the second longest folding history result confidence is reduced by 1, and the valid bit is reduced by 1 if the confidence is lower than the threshold, and try to allocate table items in longer history than the longest history.

[0076] If the second longest folding history result is the final prediction result, the longest folding history result is consistent with its result, the second longest folding history result confidence is reduced by 1, and the valid bit is reduced by 1 if the confidence is lower than the threshold, and the longest folding history result is directly set to invalid, and try to allocate table items in longer history than the longest history.

[0077] Every 128K instructions, the valid bit is refreshed once.

[0078] The initial value of the new table entry valid bit is 2'b01, and the confidence is 3'b011.

[0079] Under the same setting, the area is reduced by about 53.1% by using the offset table instead of the original jump destination address storage table, and the area is reduced by about 60% by using the hit table instead of the original Tag storage mode.

[0080] A multi-level branch prediction method supporting branch target cache compression, which utilizes the above-mentioned predictor for prediction, comprises the following steps:

[0081] The PC multi-selector selects the PC every cycle, which is sent into the three-level branch predictor at the same time, and the three-level branch predictor gives the corresponding prediction results respectively; when the high-level branch predictor prediction result is inconsistent with the low-level branch predictor prediction result, the final prediction result is the high-level branch predictor result, and the previously predicted result is refreshed.

[0082] The above only discloses several preferred specific embodiments of the present application, but the embodiments of the present application are not limited thereto, and any changes that can be thought of by those skilled in the art shall fall within the protection scope of the present application.

Claims

1. A multi-level branch predictor supporting branch target buffer compression, characterized in that, The application relates to a branch prediction device, comprising: a three-level branch predictor, sequentially comprising a first-level branch predictor, a second-level branch predictor and a third-level branch predictor, the first-level branch predictor being a 16-way full-associative branch target buffer, storing jump information and PC values of jump destination addresses, used for providing jump direction prediction and jump destination address prediction for a PC in one cycle; the second-level branch predictor having a one-cycle delay, used for giving a prediction result in a second cycle; the second-level branch predictor comprising a jump direction predictor, being a 1024-line structure, each line containing a 2-bit saturating counter; a branch jump destination address predictor, comprising a branch target buffer offset table and a hit table; the third-level branch predictor having a two-cycle delay, used for giving a prediction result in a third cycle, the third-level branch predictor comprising a 5-way confidence-based direction predictor and a 5-way confidence-based branch jump destination address predictor, the confidence-based direction predictor comprising 5-way direction prediction tables, each line of each direction prediction table containing a 2-bit saturating counter, a Tag item and a 1-bit valid bit; a multiplexer, used for receiving prediction values of the three-level branch predictor and selecting a prediction value as the next input of the three-level branch predictor; an instruction cache queue, used for storing a final prediction result predicted by the three-level branch predictor; a global branch history register, used for saving a prediction history of a global branch instruction from execution to end of the three-level branch predictor; a plurality of branch history registers with different folding lengths, used for saving a prediction history of a globally hashed branch instruction.

2. The multi-level branch predictor supporting branch target buffer compression of claim 1, wherein, In the second-level branch predictor, a jump direction predictor performs hash operation on an Index field of a PC and a global branch history, indexes a jump direction prediction table according to a result, and the jump direction prediction table comprises two-bit saturating counters, used for giving a prediction result of a branch prediction instruction jump direction.

3. The multi-level branch predictor supporting branch target buffer compression of claim 1, wherein, In the branch jump destination address predictor of the second-level branch predictor, a branch target buffer offset table is an 8-way set-associative structure, each way being 1024 lines, and different ways correspond to offset bit widths of 4bit, 4bit, 8bit, 8bit, 16bit, 16bit, 32bit and 32bit respectively; a hit table is a 512-line structure, each line containing a 3-bit hit way number and a 1-bit valid bit.

4. The multi-level branch predictor supporting branch target buffer compression as recited in claim 3, wherein, The second branch predictor predicts the jump destination address by querying a branch target buffer offset table and a hit table, performing Tag hashing on a Tag field of a PC of a branch instruction and a corresponding folded history register thereof, and performing Index hashing on an Index field and a corresponding folded history register thereof, the Tag hashing result being used to index the hit table to determine in which path the offset of the jump destination address is; the Index hashing result being used to index the branch target buffer table to determine in which row the offset of the jump destination address is, and finally determining the offset of the jump destination address, wherein both times of hashing operation are with different folded histories of the global history branch predictor, and the folding method is the same as that of the jump direction prediction; if the results of indexing of two table entries are in an invalid state, it is determined that the branch target buffer is missing; when updating the branch target buffer table, the updating is performed according to the offset bit width, and the low offset bit width can be stored in the offset path of the next level at most, the updating method uses an improved Tree-LRU algorithm, and the updating of the branch target buffer is performed simultaneously with the updating of the Tag index table.

5. The multi-level branch predictor supporting branch target buffer compression of claim 1, wherein, Each direction prediction table of the third branch predictor has 1024 rows, 512 rows, 256 rows, 128 rows and 64 rows respectively; the Index field of the PC and the hashing result of the corresponding folded history are used for indexing, and the global history length of each path is 0 bit, 13 bit, 37 bit, 91 bit and 145 bit respectively, and the compressed folded history length is 0 bit, 9 bit, 8 bit, 7 bit and 6 bit respectively, and the Tag length stored in different paths is 0 bit, 7 bit, 9 bit, 10 bit and 11 bit respectively.

6. The multi-level branch predictor supporting branch target buffer compression of claim 5, wherein, The multi-path result selection of the confidence-based direction predictor is as follows: If none of the second to fifth prediction tables matches a prediction result, the prediction result of the first prediction table is directly used; If one of the second to fifth prediction tables gives a prediction result, the prediction result of the table is directly used; If more than two of the second to fifth prediction tables give prediction results, the same prediction result is given; If more than two of the second to fifth prediction tables give different prediction results, the prediction result of the table with the longest folded history is used as the final prediction result.

7. The multi-level branch predictor supporting branch target buffer compression of claim 1, wherein, The confidence-based branch jump destination address predictor in the third branch predictor comprises: 5 branch target buffer offset tables supporting table entry compression, each of which has the same structure as the branch jump destination address predictor in the second level branch predictor, and each of which has 1024, 512, 256, 128 and 64 rows, wherein each of the branch target buffer offset tables supporting table entry compression is a 8-way set associative structure, and each of the branch target buffer offset tables supporting table entry compression uses different folding history length for indexing, the first of which uses the Index field for indexing and the Tag field for comparison to determine the branch prediction jump destination address, and each of the second to fifth of which adds a 3-bit confidence table item to assist in determining the result. 4 confidence-based hit tables, each of which has 256, 128, 64 and 32 rows, and each of which corresponds to the second to fifth branch target buffer offset tables supporting table entry compression one by one.

8. The multi-level branch predictor supporting branch target buffer compression of claim 7, wherein, The multi-way result selection of the confidence-based branch jump destination address predictor is as follows: If none of the second to fifth prediction tables matches the prediction result, the prediction result of the first prediction table is directly used; If the second to fifth prediction tables match the prediction result, if the confidence of the folding history hit table with the first history length is greater than the confidence of the folding history hit table with the second history length minus 1, and the valid bit is greater than 1, the prediction result corresponding to the folding history hit table with the first history length is selected as the final prediction result, otherwise the prediction result corresponding to the folding history hit table with the second history length is selected.

9. A multi-level branch prediction method supporting branch target buffer compression, characterized in that, The use of the predictor of any one of claims 1-8 for prediction includes the following steps: The PC selected by the PC multi-way selector is sent to the three-level branch predictor, and the three-level branch predictor gives the corresponding prediction result, and when the prediction result of the high-level branch predictor is inconsistent with that of the low-level branch predictor, the final prediction result is the result of the high-level branch predictor, and the previously predicted result is refreshed.

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