A task scheduling device, system, method, medium, program product and mainboard

Abstract

The application discloses a task scheduling device, system, method, medium, program product and mainboard in the technical field of computers.In the application, the task scheduling device realized by hardware helps the host to perform management operations related to task scheduling, and the scheduling efficiency is relatively high.As the assistant of the host, the task scheduling device does not need to determine the task execution sequence, manage the task priority, allocate the required resources of the task and the like, so that the host resources such as the memory, the computing power and the bandwidth of the host processor are saved, the host processor has more resources to execute tasks, and the efficiency of the host processor in executing tasks can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a task scheduling device, system, method, medium, program product and mainboard. BACKGROUND

[0002] At present, in the case that the host processes multiple tasks, the host needs to determine the execution order of the tasks, perform priority management, allocate resources required by the tasks, and the like. These scheduling management operations will occupy the memory, computing power, bandwidth and other resources of the host processor, affecting the execution of the tasks by the host processor.

[0003] Therefore, how to improve the efficiency of the execution of the tasks by the host processor is a problem to be solved by those skilled in the art. SUMMARY

[0004] Therefore, how to improve the efficiency of the execution of the tasks by the host processor is a problem to be solved by those skilled in the art.

[0005] In a first aspect, the present application provides a task scheduling device, comprising: a command interface circuit, a first buffer, a second buffer, a task management circuit and a resource management circuit; the command interface circuit, the first buffer and the second buffer are all connected to a host; the task management circuit is connected to the command interface circuit and the first buffer; the resource management circuit is connected to the command interface circuit and the second buffer; the command interface circuit is configured to: acquire a scheduling command from the host, and transmit the scheduling command to the task management circuit and the resource management circuit; the task management circuit is configured to: in response to the scheduling command, manage task information cached by the first buffer, and synchronize a corresponding task management result to the host; and the resource management circuit is configured to: in response to the scheduling command, manage resource information cached by the second buffer, and synchronize a corresponding resource management result to the host.

[0006] In a second aspect, the present application provides a task scheduling system, comprising: a host and the aforementioned task scheduling device.

[0007] In a third aspect, the present application provides a task scheduling method applied to the aforementioned task scheduling device, comprising: receiving, by a command interface circuit in the task scheduling device, a scheduling command sent by a host, and transmitting the scheduling command to a task management circuit in the task scheduling device and a resource management circuit in the task scheduling device; managing, by the task management circuit, task information cached by a first buffer in the task scheduling device in response to the scheduling command, and synchronizing a corresponding task management result to the host; and managing, by the resource management circuit, resource information cached by a second buffer in the task scheduling device in response to the scheduling command, and synchronizing a corresponding resource management result to the host.

[0008] In a fourth aspect, the present application provides an electronic device, comprising: a memory for storing a computer program; and a processor for executing the computer program to implement the task scheduling method disclosed above.

[0009] In a fifth aspect, the present application provides a non-volatile storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the task scheduling method disclosed above.

[0010] In a sixth aspect, the present application provides a computer program product comprising computer programs / instructions which, when executed by a processor, implement the steps of the task scheduling method disclosed above.

[0011] In a seventh aspect, the present application provides a mainboard integrated with a processor and the task scheduling device of any one of the above aspects; the processor and the task scheduling device are connected through a cache coherency protocol.

[0012] According to the above scheme, the present application provides a task scheduling device, comprising: a command interface circuit, a first cache, a second cache, a task management circuit, and a resource management circuit; the command interface circuit, the first cache, and the second cache are all connected to a host; the task management circuit is connected to the command interface circuit and the first cache; the resource management circuit is connected to the command interface circuit and the second cache; the command interface circuit is configured to: obtain a scheduling command from the host, and transmit the scheduling command to the task management circuit and the resource management circuit; the task management circuit is configured to: in response to the scheduling command, manage task information cached by the first cache, and synchronize corresponding task management results to the host; and the resource management circuit is configured to: in response to the scheduling command, manage resource information cached by the second cache, and synchronize corresponding resource management results to the host.

[0013] It can be seen that the task scheduling device implemented by hardware helps the host to perform management operations related to task scheduling, and the scheduling efficiency is relatively high. Specifically, the command interface circuit in the task scheduling device obtains a scheduling command from the host, and transmits the scheduling command to the task management circuit and the resource management circuit; the task management circuit, in response to the scheduling command, manages task information cached by the first cache, and synchronizes corresponding task management results to the host; and the resource management circuit, in response to the scheduling command, manages resource information cached by the second cache, and synchronizes corresponding resource management results to the host. This task scheduling device as an assistant of the host does not need to determine the task execution order, manage the task priority, and allocate the required resources for the task, etc., thereby saving the host resources such as the memory, computing power, and bandwidth of the host processor, so that the host processor has more resources to execute tasks, and thus the efficiency of the host processor in executing tasks can be improved.

[0014] Correspondingly, the task scheduling system, method, medium, program product and mainboard provided by the present application also have the above technical effects. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description only constitute a part of the embodiments of the present application, and all other drawings obtained by those skilled in the art without creative labor based on the provided drawings also belong to the protection scope of the present application.

[0016] Figure 1 A task scheduling system schematic diagram disclosed by the present application is shown in the figure.

[0017] Figure 2 A second task scheduling system schematic diagram disclosed by the present application is shown in the figure.

[0018] Figure 3 A queue structure schematic diagram disclosed by the present application is shown in the figure.

[0019] Figure 4 A logic design schematic diagram of a task management circuit module disclosed by the present application is shown in the figure.

[0020] Figure 5 A task state flow diagram disclosed by the present application is shown in the figure.

[0021] Figure 6 A task priority dynamic change schematic diagram disclosed by the present application is shown in the figure.

[0022] Figure 7 A logic design schematic diagram of a resource management circuit module disclosed by the present application is shown in the figure.

[0023] Figure 8 A resource state flow diagram disclosed by the present application is shown in the figure.

[0024] Figure 9 A server structure diagram provided by the present application is shown in the figure.

[0025] Figure 10 A terminal structure diagram provided by the present application is shown in the figure. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments only constitute a part of the embodiments of the present application, and not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor also belong to the protection scope of the present application.

[0027] It should be noted that in the description of the present application, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or apparatus that includes a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or apparatus. The terms "first", "second" and the like in the present application are used to distinguish similar objects, not to describe a specific order or sequence.

[0028] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below in conjunction with the drawings and specific embodiments.

[0029] At present, in the case of host processing multiple tasks, the host needs to determine the execution order of these tasks, perform priority management, allocate resources required by the tasks, etc. These scheduling management operations will occupy the memory, computing power, bandwidth and other resources of the host processor, affecting the execution of the host processor. Therefore, the present application provides a task scheduling scheme, which can improve the efficiency of the host processor in executing tasks.

[0030] Referring to Figure 1 The embodiment of the present application discloses a task scheduling device, which comprises a command interface circuit, a first buffer, a second buffer, a task management circuit and a resource management circuit. Each of these circuit modules can be implemented based on a logic circuit.

[0031] The command interface circuit, the first buffer and the second buffer are all connected to the host; the task management circuit is connected to the command interface circuit and the first buffer; and the resource management circuit is connected to the command interface circuit and the second buffer. The host can include a processor and other main control devices.

[0032] The command interface circuit is configured to obtain a scheduling command from the host and transmit the scheduling command to the task management circuit and the resource management circuit.

[0033] The task management circuit is configured to manage the task information cached in the first buffer in response to the scheduling command and synchronize the corresponding task management result to the host.

[0034] The resource management circuit is configured to manage the resource information cached in the second buffer in response to the scheduling command and synchronize the corresponding resource management result to the host.

[0035] In this embodiment, after the host obtains the task, the host records the overall information of the task in the memory of the host, including: the task type of all tasks to be processed, the required resources, etc. That is, the memory area of the host stores a complete set of task information and a complete set of corresponding resource information. When it is necessary to determine the related task scheduling operation based on the information, the host sends a scheduling command to the task scheduling device, so that the task scheduling device completes the scheduling based on the scheduling command by using each functional circuit in the task scheduling device, and feeds back the corresponding scheduling result to the host; then the host executes the corresponding task according to the scheduling result. It can be seen that the host end mainly implements: comprehensive information recording of the task, execution and processing of the task; the task scheduling device end mainly implements the scheduling management operation of the task through the hardware circuit. The task scheduling device end can be implemented based on a logic circuit such as FPGA.

[0036] In an embodiment, the command interface circuit, the first cache and the second cache are all connected to the host through a cache consistency protocol. Correspondingly, the command interface circuit interacts with the host through an input / output sub-protocol in the cache consistency protocol; the first cache and the second cache interact with the host through a cache sub-protocol in the cache consistency protocol. Correspondingly, the first cache is configured to synchronize the task management result to the host through the cache sub-protocol; and the second cache is configured to synchronize the resource management result to the host through the cache sub-protocol.

[0037] It should be noted that the task running, the resource consumption and the scheduling command will influence each other. For example, a user initiates a scheduling command to add memory for a target task, and accordingly, the task information of the target task, the allocated resources, etc. are all changed; for another example, during the running of the target task, the bandwidth resource is insufficient, and the bandwidth resource needs to be added to the target task, which causes the update of the resource information and the update of the task information of the target task. Therefore, in an embodiment, the task management circuit is configured to: determine a to-be-run task in response to the scheduling command; and update the task information of the to-be-run task to the first cache; and the resource management circuit is configured to: allocate resource information for the to-be-run task in response to the scheduling command; and update the resource information of the to-be-run task to the second cache.

[0038] Correspondingly, the resource management circuit is configured to: update the resource information cached by the second cache according to the actual use of the resource, and synchronize the corresponding resource update information to the host; and the task management circuit is configured to: update the corresponding task information cached by the first cache according to the resource update information, and synchronize the corresponding task update information to the host.

[0039] Correspondingly, the task management circuit is configured to update the corresponding task information cached by the first cache according to the actual running condition of the task, and synchronize the corresponding task update information to the host; and the resource management circuit is configured to update the resource information cached by the second cache according to the task update information, and synchronize the corresponding resource update information to the host.

[0040] The task scheduling device can update the scheduling command, the task information and the resource information by means of the timer. In an embodiment, the task scheduling device further comprises a timer; the timer is connected to the command interface circuit, the task management circuit and the resource management circuit; the timer is configured to transmit a first clock signal to the task management circuit and the resource management circuit, so that the task management circuit and the resource management circuit perform command response based on the first clock signal; and the timer is configured to transmit a second clock signal to the command interface circuit, so that the command interface circuit transmits the second clock signal to the host.

[0041] The resource management circuit is configured to maintain at least one of the resource identification information, the resource type, the resource state and the task list in any piece of resource information. That is, a piece of resource information comprises the resource identification information, the resource type, the resource state and the task list. The resource state comprises idle, use, write and read; and the resource management circuit is configured to update the resource state to one of idle, use, write and read according to a resource state machine.

[0042] The first cache caches any piece of task information, which comprises task identification information, task state, task priority, task sub-priority, task required resource list and an extendable item. That is, a piece of task information comprises task identification information, task state, task priority, task sub-priority, task required resource list and an extendable item; the task state comprises running, sleeping, ready, zombie and death; and the task management circuit is configured to update the task state to one of running, sleeping, ready, zombie and death according to a task state machine. The task management circuit is configured to maintain at least one of the task identification information, the task state, the task priority, the task sub-priority, the task required resource list and the extendable item in any piece of task information.

[0043] In an embodiment, the task management circuit is configured to update the task sub-priority according to the task waiting time length. One task priority A can comprise a plurality of task sub-priorities A1-A5; the task sub-priorities of all tasks in the same task priority A can be dynamically changed among A1-A5, specifically according to the task waiting time length. The longer the waiting time is, the higher the task sub-priority is, but not exceeding the task priority A.

[0044] In this embodiment, the task scheduling device implemented by hardware helps the host to perform the management operation related to task scheduling, and the scheduling efficiency is relatively high. Specifically, the command interface circuit in the task scheduling device obtains the scheduling command from the host, and transmits the scheduling command to the task management circuit and the resource management circuit; the task management circuit manages the task information cached in the first buffer in response to the scheduling command, and synchronizes the corresponding task management result to the host; the resource management circuit manages the resource information cached in the second buffer in response to the scheduling command, and synchronizes the corresponding resource management result to the host. As an assistant of the host, the task scheduling device does not need to determine the task execution order, manage the task priority, and allocate the required resources for the task, thereby saving the host resources such as the memory, computing power, and bandwidth of the host processor, so that the host processor has more resources to execute tasks, and thus the efficiency of the host processor in executing tasks can be improved.

[0045] Please refer to Figure 2 , the host end includes a DDR (Double Data Rate, double rate synchronous dynamic random access memory) memory and a processor; the DDR memory stores a task information set, a command queue, and a resource information set. The scheduling device includes a task information cache (first buffer), a command interface circuit module, a resource information cache (second buffer), a task management circuit module, and a resource management circuit module, which are implemented based on FPGA; the FPGA is connected to the DDR, which is used to store task management data and resource management data.

[0046] It should be noted that the "task information cache" is the cached data of the "task information", and the "task information" is stored on the DDR Memory of the CPU side, which can be directly accessed by the CPU. The "task information cache" is saved in the on-chip RAM of the scheduling device, connected to the host through the CXL.Cache interface, and the task management circuit on the scheduling device can modify the task information cache, and then the modified information is synchronized to the "task information" on the CPU side through the CXL.Cache interface. The "task information" on the CPU side can be considered as the full set of the "task information cache" on the scheduling device side.

[0047] Similarly, the "resource information cache" is the cached data of the "resource information", and the "resource information" is stored on the DDR Memory of the CPU side, which can be directly accessed by the CPU. The "resource information cache" is saved in the on-chip RAM of the scheduling device, connected to the host through the CXL.Cache interface, and the resource management circuit on the scheduling device can modify the resource information cache, and then the modified information is synchronized to the "resource information" on the CPU side through the CXL.Cache interface. The "resource information" on the CPU side can be considered as the full set of the "resource information cache" on the scheduling device side.

[0048] The CPU can only read task and resource information, not directly modify it. It needs to send commands to the scheduling device for modification. The "command queue" is stored on the CPU-side DDR Mempry and is accessed by the scheduling device's command interface circuit through the CXL.IO interface, which then forwards the commands to other functional modules in the scheduling device for processing.

[0049] On the scheduling device side, task management data is accessed by the task management circuit module and stored in the scheduling device's DDR memory. Resource management data is accessed by the resource management circuit module and stored in the scheduling device's DDR memory.

[0050] like Figure 2 As shown, the CPU interacts with the scheduling device via the CXL.IO interface. To increase concurrency, a pair of Submission Queues (SQ) and Completion Queues (CQ) are used. The SQ stores submission commands, while the CQ stores completion information. Queue status information is monitored via the Door Bell (DB) register. Both queues use a circular queue structure, meaning they can be mapped to any CXL.IO-accessible memory location, including CPU-side memory. For the Submission Queue, the CPU acts as the producer, and the scheduling device as the consumer. The Completion Queue follows the opposite pattern. Therefore, the SQ Tail pointer and the CQ Head pointer are updated by the CPU, while the other two pointers are updated by the scheduling device.

[0051] For information on the circular queue structure and its mapped physical memory, please refer to [link / reference]. Figure 3 The queue depth is fixed, and the head and tail positions are indicated by Tail and Head, respectively. The actual usable size of the queue is the queue size minus 1. The queue is empty when the head pointer equals the tail pointer. The queue is full when the head pointer has one more tail pointer than the tail pointer.

[0052] In this embodiment, the queues are divided into management queues and scheduling command queues based on command type. The management queue is used to cache management commands, such as retrieving the attributes of the scheduling device and creating scheduling command queues. The scheduling command queue is used to cache scheduling commands. A scheduling device has only one pair of management SQ / CQ, but can have multiple pairs of scheduling command SQ / CQ. The management SQ / CQ is only used for management command interaction, and the scheduling command SQ / CQ is only used for scheduling command interaction. For multi-core systems, although each core has only one scheduling command CQ, multiple scheduling command SQs can exist. The entry size for both management commands and scheduling commands (SQ) is 64 bytes, while the entry size for a CQ is 16 bytes.

[0053] In an example, the management command queue can be used to record: information for creating a scheduling completion, information for creating a scheduling request, information for deleting a scheduling completion, information for deleting a scheduling request, information for reading a scheduling device configuration, and information for setting a scheduling device configuration parameter.

[0054] The scheduling of the scheduling device side for a task includes creating a task: finding an idle space from a task information list and returning a task ID (an index of task information). Obtaining a task ID to be run: finding a task with the highest priority value from a ready queue (a task to be scheduled on the device) and returning it to the CPU. Aborting a task: after the task is aborted, the task information is cleared to be idle task information, and the task ID can be assigned to a newly created task. Modifying task information: when the CPU wants to modify the task information, an update task information command is sent, and the scheduling device modifies the corresponding task information buffer according to the requirements of the command and flushes it to the corresponding task information saved on the CPU side DDR Memory.

[0055] The scheduling of the scheduling device side for a resource includes creating a resource, deleting a resource, updating a resource state, and modifying resource information: when the CPU wants to modify the resource information, an update resource information command is sent, and the scheduling device modifies the corresponding resource information buffer according to the requirements of the command and flushes it to the corresponding resource information saved on the CPU side DDR Memory.

[0056] Please refer to Figure 4 , the following logical functions can be implemented in the task management circuit module: a timer generates a clock signal to the task state machine, the task priority queue, and in addition, the clock signal is sent to the CPU through CXL.IO. The task state machine updates the task state after receiving the clock signal and arranges the task into the corresponding queue according to the task state. In the ready state, the priority queue updates the priority value of the task after receiving the clock signal, and arranges the task into the corresponding priority queue. The scheduling of the task is performed through the beat determined by the clock signal. The CPU can send a task scheduling command to the scheduling device after receiving the clock signal. The CPU has multiple CPU cores, and can send task scheduling commands to the device at the same time. In addition, the change of the resource state will cause the change of the task state. For example, after the resource state is changed to idle, the task waiting for the resource is arranged into the ready priority queue and waits for scheduling and running.

[0057] Please refer to Table 1, the task information is stored in the CPU side DDR Memory in the format shown in Table 1. The "X" in Table 1 serves as the value of each item, and the specific value can be flexibly set according to the actual situation.

[0058] Table 1 Task Information Table

[0059]

[0060] Wherein each task corresponds to a task information, in order to facilitate access, the size of the task information is designed to be a multiple of 64 bytes, and the data bus width is 512 bits. All task information is stored in a CPU-side memory space with a continuous physical address. The maximum number of supported task information is 65536. The storage starting address of the task information must be aligned with 64 bytes.

[0061] The task information lookup is performed concurrently, and the 65536 task information can be divided into 4096 groups, each group containing 16 task information. The task information is searched by group, and the corresponding task information can be found in a maximum of 16 searches. The scheduling device has a task information cache, and the cache is stored on the on-chip RAM of the FPGA, and the size of the cache is also aligned with 64 bytes. Specifically, the task ID is its subscript. The state of the task has five states: running, sleeping, ready, zombie, and death. The priority of the task ranges from 0 to 79, with 79 being the highest priority and 0 being the lowest priority. The level is divided into four levels, corresponding to 0 (0-19), 1 (20-39), 2 (40-59), and 3 (60-79). Each priority level contains 20 sub-priority levels, represented by NICE, which ranges from 0 to 19. The default priority of the task is 2, and the NICE value is 0, so the default priority value is 40.

[0062] Please refer to Figure 5 , the task state machine according to Figure 5 updates and manages the state of the task. The state of the task has five states: running, sleeping, ready, zombie, and death. Among them, sleeping is divided into interruptable sleep and non-interruptable sleep. Interruptable sleep can be interrupted at any time and is used for short waiting time; non-interruptable sleep needs to be awakened first and is used for long waiting time. The state of the task changes, triggered by the clock signal sent by the timer. Specifically, when creating a task, the priority of the task (the sub-priority level is set to NICE=0 by default) is determined; the task is sorted into the corresponding ready queue according to the priority value; the task gets a running opportunity and is sorted into the running queue; if the task needs to wait for a signal indicating that the resource is available during running, depending on the type of the resource signal, if it is an interruptable signal, the task is sorted into the interruptable sleep queue; if it is a non-interruptable signal, the task is sorted into the non-interruptable sleep queue; once a resource is available, the task waiting for the resource is sorted into the ready queue according to its priority value and waits for scheduling. When the task is completed, if the parent process of the task is concerned about the task, the task is sorted into the zombie task queue, otherwise, the task is sorted into the death task queue and waits for unregistration. Once the parent process of the zombie task is determined to be unnecessary to query the task termination reason, the task is sorted into the death task queue and waits for unregistration.

[0063] It should be noted that each task has a priority, which is in the range of 0~79, the greater the value, the higher the priority. The priority can be specified when creating a task, but the NICE value cannot be specified, and the NICE is initially 0. The scheduling device can dynamically adjust the NICE value, and the NICE value is in the range of 0~19. If the default priority of a task is level 2 and the NICE value is 0, then the initial priority value of the task is 20 (level 0) + 20 (level 1) + NICE (level 2) = 40. Only tasks in the ready state are queued according to the priority value, and the scheduling queue maintains 80 priority queues for the ready state, with priority values (0~79), each value corresponding to a queue. When a scheduling request arrives, the scheduling management module returns the task ID of the first task in the highest priority queue.

[0064] Please refer to Figure 6 , Figure 6 The dynamic updating of the task priority mechanism of the embodiment is illustrated. Taking the priority evolution process of the task queue of level 0 as an example, the NICE of the task in the ready state is increased by 1 every clock interval, and the maximum value is 19. Therefore, the priority level of the task does not change after the task is created, but the priority value of the task gradually increases by 19, and the greater the priority value, the higher the priority, and the task is more likely to be scheduled and executed. The scheduling device first queries whether the queue is empty according to the priority value from high to low, and if not, the task in the queue is executed. Every time interval, the NICE value of each task is increased by 1, and if the NICE value is 19, it remains unchanged. After the NICE of the task changes, the task needs to be taken out of the current queue and placed at the end of the queue with the previous priority value. When the task is scheduled and executed, the NICE value of the task is set to 0 after the running time of the task is used up, and the task is placed at the end of the related queue, such as a task with a priority of 2, which is placed at the end of the queue with a priority of 40.

[0065] Please refer to Figure 7 The following logical functions can be implemented in the resource management circuit module: communication with the communication CPU through CXL.IO and CXL.Cache. Obtain commands through CXL.IO and process them, and update the resource state machine accordingly. The update of the resource state machine will cause the update of the task state machine and the update of the resource information cache.

[0066] Please refer to Table 2, the resource information is stored in the CPU side DDR Memory in the format shown in Table 2. The "Y" in Table 2 serves as the value of each item, and the specific value can be flexibly set according to the actual situation.

[0067] Table 2 Resource Information Table

[0068]

[0069] Wherein, each resource corresponds to a piece of resource information, in order to facilitate access, the size of the resource information is designed to be a multiple of 64 bytes (the data bus width is 512 bits), and all the resource information is stored in a piece of CPU-side memory space with a continuous physical address. The maximum number of supported task information is 4096. The resource information lookup is performed concurrently, and the 4096 pieces of resource information can be divided into 256 groups, each group having 16 pieces. The resource information is looked up by group, and the corresponding resource information can be found in a maximum of 16 lookups. Resource ID: subscript of resource array. Resource types include: character device; control class byte access; block device; network device: network card, etc.; virtual device. Resource status includes: idle, use, write, read. The task list represents a list of all tasks using the resource.

[0070] Please refer to Figure 8 , the resource state is updated and managed according to the resource state machine shown in Figure 8 . The change of the resource state is driven by the resource state change command sent by the CPU, including: after the resource is created, the resource is in the "idle" state; the task must obtain the resource ID before using the resource, and after obtaining the task ID, the resource becomes "use" state, and the ID of the task is added to the task list of the resource; the same resource can be used by multiple tasks at the same time, and if there are tasks in the task list, the resource is in the use state. At the same time, only one task can execute the write operation on the resource, and at this time, the state of the resource is "write". When the task executes the write operation, other tasks using the resource can only wait for the completion of the operation of the task. Multiple tasks can execute read on the resource at the same time, and when a task reads the resource, the resource is in the "read" state.

[0071] It can be seen that the embodiment realizes the management operation of task scheduling by FPGA hardware, and the scheduling efficiency is relatively high. As an assistant of the host, the FPGA hardware does not need to determine the task execution order, manage the task priority, and allocate the required resources of the task, thereby saving the host resources such as memory, computing power, and bandwidth of the host processor, so that the host processor has more resources to execute tasks, and thus the efficiency of the host processor in executing tasks can be improved.

[0072] A task scheduling system provided by the embodiment of the application will be described below. The task scheduling system described below can be mutually referred to with other embodiments described herein.

[0073] The embodiment of the application discloses a task scheduling system, comprising: a host and a task scheduling device described in other embodiments. The host comprises at least one processor core; any one processor core is configured to: call the task scheduling device to perform task scheduling according to a management queue pair and a scheduling command queue pair; and execute a corresponding task according to a task scheduling result fed back by the task scheduling device.

[0074] In an embodiment, the task scheduling device comprises: a command interface circuit, a first cache, a second cache, a task management circuit and a resource management circuit; the command interface circuit, the first cache and the second cache are connected to the host; the task management circuit is connected to the command interface circuit and the first cache; the resource management circuit is connected to the command interface circuit and the second cache; specifically, the command interface circuit, the first cache and the second cache are connected to the host through a cache consistency protocol; accordingly, the command interface circuit interacts with the host through an input / output sub-protocol in the cache consistency protocol; the first cache and the second cache interact with the host through a cache sub-protocol in the cache consistency protocol.

[0075] In an embodiment, the first cache is configured to synchronize the task management result to the host through the cache sub-protocol; accordingly, the second cache is configured to synchronize the resource management result to the host through the cache sub-protocol.

[0076] In an embodiment, the task management circuit is configured to determine the to-be-run task in response to the scheduling command; and update the task information of the to-be-run task to the first cache; the resource management circuit is configured to allocate the resource information for the to-be-run task in response to the scheduling command; and update the resource information of the to-be-run task to the second cache.

[0077] In an embodiment, the resource management circuit is configured to update the resource information cached by the second cache according to the actual resource usage, and synchronize the corresponding resource update information to the host; and the task management circuit is configured to update the corresponding task information cached by the first cache according to the resource update information, and synchronize the corresponding task update information to the host.

[0078] In an embodiment, the task management circuit is configured to update the corresponding task information cached by the first cache according to the actual task running condition, and synchronize the corresponding task update information to the host; and the resource management circuit is configured to update the resource information cached by the second cache according to the task update information, and synchronize the corresponding resource update information to the host.

[0079] In an embodiment, the task scheduling device further comprises a timer; the timer is connected to the command interface circuit, the task management circuit and the resource management circuit; the timer is configured to transmit a first clock signal to the task management circuit and the resource management circuit, so that the task management circuit and the resource management circuit respond to the command based on the first clock signal; and the timer is configured to transmit a second clock signal to the command interface circuit, so that the command interface circuit transmits the second clock signal to the host.

[0080] In an embodiment, the resource management circuit is configured to maintain at least one of resource identification information, resource type, resource state, and a task list in any piece of resource information; and update the resource state to one of idle, in use, writing, and reading according to a resource state machine.

[0081] In an embodiment, the task management circuit is configured to maintain at least one of task identification information, task state, task priority, task sub-priority, a task required resource list, and an extendable item in any piece of task information; update the task state to one of running, sleeping, ready, zombie, and death according to a task state machine; and update the task sub-priority according to a task waiting time length.

[0082] The more specific working processes of the various modules and units in this embodiment can refer to the corresponding content disclosed in the foregoing embodiments, which will not be described in detail here.

[0083] It can be seen that the present embodiment provides a task scheduling system, and the task scheduling device in the system serves as an assistant of the host computer. The host computer does not need to determine the task execution order, manage the task priority, and allocate the required resources of the task, thereby saving the host computer resources such as memory, computing power, and bandwidth of the host processor, so that the host processor has more resources to execute tasks, and the efficiency of the host processor in executing tasks can be improved.

[0084] A task scheduling method provided by the present embodiment will be described below. The task scheduling method described below can be mutually referred to with other embodiments described herein.

[0085] The present embodiment discloses a task scheduling method applied to the task scheduling device described in other embodiments, which includes: receiving a scheduling command sent by a host computer through a command interface circuit in the task scheduling device, and transmitting the scheduling command to a task management circuit in the task scheduling device and a resource management circuit in the task scheduling device; managing task information cached in a first buffer in the task scheduling device in response to the scheduling command through the task management circuit, and synchronizing the corresponding task management result to the host computer; and managing resource information cached in a second buffer in the task scheduling device in response to the scheduling command through the resource management circuit, and synchronizing the corresponding resource management result to the host computer.

[0086] In an embodiment, the task scheduling device comprises a command interface circuit, a first cache, a second cache, a task management circuit and a resource management circuit; the command interface circuit, the first cache and the second cache are connected to the host; the task management circuit is connected to the command interface circuit and the first cache; the resource management circuit is connected to the command interface circuit and the second cache; specifically, the command interface circuit, the first cache and the second cache are connected to the host through a cache consistency protocol; accordingly, the command interface circuit interacts with the host through an input / output sub-protocol in the cache consistency protocol; the first cache and the second cache interact with the host through a cache sub-protocol in the cache consistency protocol.

[0087] In an embodiment, the first cache is configured to synchronize the task management result to the host through the cache sub-protocol; accordingly, the second cache is configured to synchronize the resource management result to the host through the cache sub-protocol.

[0088] In an embodiment, the task management circuit is configured to determine the to-be-run task in response to the scheduling command; and update the task information of the to-be-run task to the first cache; the resource management circuit is configured to allocate the resource information for the to-be-run task in response to the scheduling command; and update the resource information of the to-be-run task to the second cache.

[0089] In an embodiment, the resource management circuit is configured to update the resource information cached by the second cache according to the actual resource usage, and synchronize the corresponding resource update information to the host; the task management circuit is configured to update the corresponding task information cached by the first cache according to the resource update information, and synchronize the corresponding task update information to the host.

[0090] In an embodiment, the task management circuit is configured to update the corresponding task information cached by the first cache according to the actual task running condition, and synchronize the corresponding task update information to the host; the resource management circuit is configured to update the resource information cached by the second cache according to the task update information, and synchronize the corresponding resource update information to the host.

[0091] In an embodiment, the task scheduling device further comprises a timer; the timer is connected to the command interface circuit, the task management circuit and the resource management circuit; the timer is configured to transmit a first clock signal to the task management circuit and the resource management circuit, so that the task management circuit and the resource management circuit respond to the command based on the first clock signal; the timer is configured to transmit a second clock signal to the command interface circuit, so that the command interface circuit transmits the second clock signal to the host.

[0092] In an embodiment, the resource management circuit is configured to maintain at least one of resource identification information, resource type, resource state, and a task list in any piece of resource information, and update the resource state to one of idle, in use, writing, and reading according to a resource state machine. Any piece of task information cached by the first cache includes task identification information, task state, task priority, task sub-priority, a task required resource list, and an extendable item.

[0093] In an embodiment, the task management circuit is configured to maintain at least one of task identification information, task state, task priority, task sub-priority, a task required resource list, and an extendable item in any piece of task information, update the task state to one of running, sleeping, ready, zombie, and death according to a task state machine, and update the task sub-priority according to a task waiting time length.

[0094] The more specific working processes of the modules and units in this embodiment can refer to the corresponding content disclosed in the foregoing embodiments, which will not be described in detail here.

[0095] It can be seen that the task scheduling method provided in this embodiment makes the task scheduling device serve as an assistant of the host, and the host does not need to determine the task execution sequence, manage the task priority, and allocate the required resources of the task, thereby saving the host resources such as the memory, computing power, and bandwidth of the host processor, and enabling the host processor to have more resources to execute tasks, and thus the efficiency of the host processor in executing tasks can be improved.

[0096] The electronic device provided in the embodiments of the present application will be described below. The electronic device described below can be mutually referred to with other embodiments described herein. The electronic device can be a task scheduling device, can be any circuit module in the task scheduling device, or can be a host or other devices.

[0097] The embodiments of the present application disclose an electronic device, including a memory configured to store a computer program, and a processor configured to execute the computer program to implement the method disclosed in any of the embodiments.

[0098] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: data interaction with the host through an input / output sub-protocol in a cache consistency protocol.

[0099] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: data interaction with the host through a cache sub-protocol in a cache consistency protocol.

[0100] In the embodiment, the processor executes the computer program stored in the memory, and the following steps can be implemented: synchronizing the task management result to the host through the cache sub-protocol.

[0101] In the embodiment, the processor executes the computer program stored in the memory, and the following steps can be implemented: synchronizing the resource management result to the host through the cache sub-protocol.

[0102] In the embodiment, the processor executes the computer program stored in the memory, and the following steps can be implemented: determining the to-be-run task in response to the scheduling command; and updating the task information of the to-be-run task to the first cache.

[0103] In the embodiment, the processor executes the computer program stored in the memory, and the following steps can be implemented: allocating the resource information to the to-be-run task in response to the scheduling command; and updating the resource information of the to-be-run task to the second cache.

[0104] In the embodiment, the processor executes the computer program stored in the memory, and the following steps can be implemented: updating the resource information cached by the second cache according to the actual resource usage, and synchronizing the corresponding resource update information to the host.

[0105] In the embodiment, the processor executes the computer program stored in the memory, and the following steps can be implemented: updating the corresponding task information cached by the first cache according to the resource update information, and synchronizing the corresponding task update information to the host.

[0106] In the embodiment, the processor executes the computer program stored in the memory, and the following steps can be implemented: updating the corresponding task information cached by the first cache according to the actual task running, and synchronizing the corresponding task update information to the host.

[0107] In the embodiment, the processor executes the computer program stored in the memory, and the following steps can be implemented: updating the resource information cached by the second cache according to the task update information, and synchronizing the corresponding resource update information to the host.

[0108] In the embodiment, the processor executes the computer program stored in the memory, and the following steps can be implemented: transmitting the first clock signal to the task management circuit and the resource management circuit.

[0109] In the embodiment, the processor executes the computer program stored in the memory, and the following steps can be implemented: responding to the command based on the first clock signal.

[0110] In the embodiment, the processor, when executing the computer program stored in the memory, can specifically implement the following steps: transmitting the second clock signal to the command interface circuit.

[0111] In the embodiment, the processor, when executing the computer program stored in the memory, can specifically implement the following steps: transmitting the second clock signal to the host.

[0112] In the embodiment, the processor, when executing the computer program stored in the memory, can specifically implement the following steps: maintaining at least one of the resource identification information, the resource type, the resource state and the task list in any piece of resource information; and updating the resource state to one of the idle, the use, the write and the read according to the resource state machine.

[0113] In the embodiment, the processor, when executing the computer program stored in the memory, can specifically implement the following steps: maintaining at least one of the task identification information, the task state, the task priority, the task sub-priority, the task required resource list and the expandable item in any piece of task information; updating the task state to one of the running, the sleeping, the ready, the zombie and the death according to the task state machine; and updating the task sub-priority according to the task waiting time length.

[0114] Further, the embodiment of the present application also provides an electronic device. Figure 9 The electronic device can be a server as shown in Figure 10 or a terminal as shown in Figure 9 and Figure 10 are structural diagrams of electronic devices according to an exemplary embodiment, and the contents in the diagrams should not be considered as any limitation on the use range of the present application.

[0115] Figure 9 A structural diagram of a server according to an exemplary embodiment is shown in the figure. The server can specifically include at least one processor, at least one memory, a power supply, a communication interface, an input / output interface and a communication bus. The memory is used to store a computer program, the computer program is loaded and executed by the processor to implement the related steps in the task scheduling disclosed in any of the preceding embodiments.

[0116] In the embodiment, the power supply is used to provide working voltage for each hardware device on the server; the communication interface can create a data transmission channel between the server and external devices, and the communication protocol followed by the communication interface is any communication protocol applicable to the technical solution of the present application, which is not limited specifically herein; the input / output interface is used to obtain external input data or output data to the outside, and the specific interface type can be selected according to the specific application needs, which is not limited specifically herein.

[0117] In addition, the memory as a carrier for storing resources can be a read-only memory, a random access memory, a magnetic disk or an optical disk, etc., and the resources stored thereon include an operating system, computer programs and data, etc. The storage mode can be temporary storage or permanent storage.

[0118] The operating system is used to manage and control each hardware device and computer program on the server, so as to realize the operation and processing of the processor on the data in the memory. The operating system can be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program capable of completing the task scheduling method disclosed in any of the preceding embodiments, the computer program can further include a computer program capable of completing other specific work. In addition to the data including the update information of the application program, the data can further include the developer information of the application program.

[0119] Figure 10 A structure schematic diagram of a terminal is provided in the embodiment of the present application. The terminal can specifically include, but is not limited to, a smart phone, a tablet computer, a notebook computer or a desktop computer, etc.

[0120] Generally, the terminal in the embodiment includes a processor and a memory.

[0121] The processor can include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor can be implemented in at least one hardware form of a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array) and a PLA (Programmable Logic Array). The processor can also include a main processor and a coprocessor. The main processor is a processor for processing data in a wake-up state, also known as a CPU (Central Processing Unit). The coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor can be integrated with a GPU (Graphics Processing Unit). The GPU is used to be responsible for the rendering and drawing of the content required to be displayed on the display screen. In some embodiments, the processor can further include an AI (Artificial Intelligence) processor. The AI processor is used to process the computing operation related to machine learning.

[0122] The memory can include one or more computer non-volatile storage media, which can be non-transitory. The memory can also include a high-speed random access memory, and a non-volatile memory such as one or more disk storage devices, flash storage devices. In the embodiment, the memory is used at least to store the following computer programs, wherein the computer programs are loaded and executed by the processor, and can realize the related steps in the task scheduling method executed by the terminal side disclosed in any of the preceding embodiments. In addition, the resources stored by the memory can also include an operating system and data, etc., and the storage mode can be temporary storage or permanent storage. The operating system can include Windows, Unix, Linux, etc. The data can include but is not limited to application update information.

[0123] In some embodiments, the terminal can also include a display screen, an input / output interface, a communication interface, a sensor, a power supply, and a communication bus.

[0124] Those skilled in the art can understand that the structure shown in the above embodiments is not a limitation on the terminal, and the terminal can include more or fewer components than those shown in the figure. Figure 10

[0125] A non-volatile storage medium provided by the embodiments of the present application is introduced below, and the non-volatile storage medium described below can be referred to with other embodiments described herein.

[0126] A non-volatile storage medium for saving a computer program, wherein the computer program is executed by a processor to realize the task scheduling method disclosed in the preceding embodiments. The non-volatile storage medium is a computer-readable non-volatile storage medium, which is a carrier for storing resources, and can be a read-only memory, a random access memory, a magnetic disk or an optical disk, etc. The resources stored thereon include an operating system, a computer program and data, etc., and the storage mode can be temporary storage or permanent storage.

[0127] A computer program product provided by the embodiments of the present application is introduced below, and the computer program product described below can be referred to with other embodiments described herein.

[0128] A computer program product, including computer programs / instructions, which are executed by a processor to realize the steps of the task scheduling method disclosed above.

[0129] The embodiments of the present application also provide another computer program product, including a non-volatile computer readable storage medium, the non-volatile computer readable storage medium is used to store a computer program, the computer program is executed by a processor to realize the steps in any of the preceding embodiments.

[0130] ​The following describes a mainboard according to an embodiment of the present application. The mainboard described below can be used in conjunction with other embodiments described herein.

[0131] An embodiment of the present application provides a mainboard integrated with a processor and a task scheduling device as described in other embodiments; the processor and the task scheduling device are connected through a cache coherency protocol. The mainboard is a mainboard of a host, i.e., the mainboard of the host is provided with the processor and the task scheduling device, and the task scheduling device is in the form of an integrated circuit chip and is connected to the processor through a CXL protocol.

[0132] That is, the cache coherency protocol can use CXL (Compute Express Link), which is a high-speed interface protocol that can optimize the interaction between computing, storage, and communication resources in a data center. CXL actually consists of three sub-protocols, namely CXL.io, CXL.cache, and CXL.mem. CXL.io is used for initialization, linking, device identification and enumeration, and register access, and provides a non-coherent load / store interface for devices. CXL.cache is used to access the cache and can define the interaction between the processor and the device, allowing the connected CXL device to use the request and response method to efficiently cache the processor memory with very low latency. CXL.mem is used to access the memory and provides access to the device's additional memory for the processor using load and store commands, where the processor acts as the master device and the CXL device acts as the slave device, and can support volatile and persistent memory architectures. After these protocols are dynamically multiplexed together, data transmission can be performed at a speed of 32 GT / s through the standard PCIe 5.0 physical layer, thereby achieving high-speed data transmission between the processor and the task scheduling device on the mainboard.

[0133] The embodiments in the present specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. For the same or similar parts between the embodiments, mutual reference can be made.

[0134] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, software modules executed by a processor, or a combination of the two. The software modules can be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of non-volatile storage medium known in the art.

[0135] The principles and implementation manners of the present application are described by using specific examples in the present application, and the above examples are only applicable to help understand the method and core idea of the processor of the present application; meanwhile, for the general technical personnel in the field, the specific implementation manners and application ranges will be changed according to the idea of the present application, and the above description should not be understood as the limitation of the present application.

Claims

1. A task scheduling device, characterized in that, include: Command interface circuit, first buffer, second buffer, task management circuit and resource management circuit; The command interface circuit, the first buffer, and the second buffer are all connected to the host. The task management circuit is connected to the command interface circuit and the first buffer; The resource management circuit is connected to the command interface circuit and the second buffer; The command interface circuit is used to: obtain scheduling commands from the host and transmit the scheduling commands to the task management circuit and the resource management circuit; The task management circuit is used to: in response to the scheduling command, manage the task information cached in the first buffer, so as to maintain at least one of the following in any task information: task identification information, task status, task priority, task sub-priority, list of resources required by the task, and expandable items, and synchronize the corresponding task management results to the host. The resource management circuit is used to: in response to the scheduling command, manage the resource information cached in the second buffer, maintain at least one of the resource identification information, resource type, resource status and task list in any resource information, and synchronize the corresponding resource management results to the host, without the host needing to determine the task execution order, manage task priority and allocate the resources required for the task; The host includes at least one processor core; Any processor core is used to: divide the command queue into management queue pairs and scheduling command queue pairs according to the command type; invoke the task scheduling device to perform task scheduling according to the management queue pairs and scheduling command queue pairs; execute the corresponding task according to the task scheduling result fed back by the task scheduling device; the processor core interacts with the task scheduling device through the CXL.IO interface; The management queue is used to record: information on scheduling completion, information on scheduling request creation, information on scheduling completion deletion, information on scheduling request deletion, information on reading the configuration of the task scheduling device, and information on setting the configuration parameters of the task scheduling device. The host includes DDR memory, which stores a complete set of task information, a command queue, and a complete set of resource information. The host can only read the complete set of task information and the complete set of resource information; it cannot directly modify them. Instead, it needs to send commands to the task scheduling device for modification. The command queue consists of a paired submission queue and a completion queue. The submission queue stores submission commands, and the completion queue stores completion information. Both queues use a circular queue structure. The tail pointer of the submission queue and the head pointer of the completion queue are updated by the host, while the other two pointers are updated by the task scheduling device.

2. The task scheduling device according to claim 1, characterized in that, The command interface circuit, the first buffer, and the second buffer are all connected to the host via a cache coherence protocol; Accordingly, the command interface circuit interacts with the host through the input / output sub-protocol in the cache coherence protocol; The first cache and the second cache interact with the host through the cache sub-protocol in the cache consistency protocol.

3. The task scheduling device according to claim 2, characterized in that, The first buffer is used to: synchronize the task management results to the host via the caching sub-protocol; Accordingly, the second cache is used to: synchronize the resource management results to the host via the cache sub-protocol.

4. The task scheduling device according to claim 1, characterized in that, The task management circuit is used to: in response to the scheduling command, determine the task to be run; and update the task information of the task to be run to the first buffer; The resource management circuit is used to: in response to the scheduling command, allocate resource information to the task to be run; and update the resource information of the task to be run to the second buffer.

5. The task scheduling device according to claim 1, characterized in that, The resource management circuit is used to: update the resource information cached in the second cache according to the actual resource usage, and synchronize the corresponding resource update information to the host; The task management circuit is used to: update the corresponding task information cached in the first cache according to the resource update information, and synchronize the corresponding task update information to the host.

6. The task scheduling device according to claim 1, characterized in that, The task management circuit is used to: update the corresponding task information cached in the first buffer according to the actual task operation status, and synchronize the corresponding task update information to the host. The resource management circuit is used to: update the resource information cached in the second cache according to the task update information, and synchronize the corresponding resource update information to the host.

7. The task scheduling device according to claim 1, characterized in that, The task scheduling device further includes a timer; the timer is connected to the command interface circuit, the task management circuit, and the resource management circuit; The timer is used to: transmit a first clock signal to the task management circuit and the resource management circuit, so that the task management circuit and the resource management circuit can respond to commands based on the first clock signal; The timer is used to: transmit a second clock signal to the command interface circuit, so that the command interface circuit transmits the second clock signal to the host.

8. The task scheduling device according to any one of claims 1 to 7, characterized in that, The resource management circuit is used to update the resource status to one of idle, used, write, and read according to the resource state machine.

9. The task scheduling device according to any one of claims 1 to 7, characterized in that, The task information cached by the first cache includes: task identifier information, task status, task priority, task sub-priority, list of resources required by the task, and expandable items.

10. The task scheduling device according to claim 9, characterized in that, The task management circuit is used to update the task status to one of running, sleeping, ready, zombie, and dead according to the task state machine.

11. The task scheduling device according to claim 9, characterized in that, The task management circuit is used to update the task sub-priority based on the task waiting time.

12. A task scheduling system, characterized in that, include: The host computer and the task scheduling device as described in any one of claims 1 to 11; The host includes at least one processor core; Any processor core is used to: invoke the task scheduling device to perform task scheduling according to the management queue pair and the scheduling command queue pair; execute the corresponding task according to the task scheduling result fed back by the task scheduling device; the management queue pair is used to record: information on the creation of scheduling completion, information on the creation of scheduling request, information on the deletion of scheduling completion, information on the deletion of scheduling request, information on reading the configuration of the task scheduling device, and information on setting the configuration parameters of the task scheduling device.

13. A task scheduling method, characterized in that, Applied to the task scheduling device as described in any one of claims 1 to 11, comprising: The task scheduling device receives scheduling commands sent by the host through the command interface circuit and transmits the scheduling commands to the task management circuit and the resource management circuit in the task scheduling device. The task management circuit responds to the scheduling command and manages the task information cached in the first buffer of the task scheduling device to maintain at least one of the following in any task information: task identification information, task status, task priority, task sub-priority, list of resources required by the task, and expandable items, and synchronizes the corresponding task management results to the host. The resource management circuit responds to the scheduling command and manages the resource information cached in the second buffer of the task scheduling device to maintain at least one item in the task list, including resource identification information, resource type, resource status, and resource status of any resource information. The corresponding resource management results are synchronized to the host without the host determining the task execution order, managing task priority, or allocating the resources required for the task. The host includes at least one processor core; Any processor core is used to: divide the command queue into management queue pairs and scheduling command queue pairs according to the command type; invoke the task scheduling device to perform task scheduling according to the management queue pairs and scheduling command queue pairs; execute the corresponding task according to the task scheduling result fed back by the task scheduling device; the processor core interacts with the task scheduling device through the CXL.IO interface; The management queue is used to record: information on scheduling completion, information on scheduling request creation, information on scheduling completion deletion, information on scheduling request deletion, information on reading the configuration of the task scheduling device, and information on setting the configuration parameters of the task scheduling device. The host includes DDR memory, which stores a complete set of task information, a command queue, and a complete set of resource information. The host can only read the complete set of task information and the complete set of resource information; it cannot directly modify them. Instead, it needs to send commands to the task scheduling device for modification. The command queue consists of a paired submission queue and a completion queue. The submission queue stores submission commands, and the completion queue stores completion information. Both queues use a circular queue structure. The tail pointer of the submission queue and the head pointer of the completion queue are updated by the host, while the other two pointers are updated by the task scheduling device.

14. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the method as described in claim 13.

15. A non-volatile storage medium, characterized in that, Used to store a computer program, wherein the computer program, when executed by a processor, implements the method as described in claim 13.

16. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor, they implement the method of claim 13.

17. A motherboard, characterized in that, The motherboard integrates a processor and a task scheduling device as described in any one of claims 1 to 11; the processor and the task scheduling device are connected via a cache coherence protocol.

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