Fault detection method and chip, storage medium and electronic device

Abstract

The application discloses a fault detection method and chip, a storage medium and an electronic device, and relates to the technical field of computers.The application comprises the following steps: performing edge detection on a pulse signal received from a fault counting pin of a processor, accumulating the number of pulse signals received at a first level when a first edge of the pulse signal at the first level is detected, so that the number of fault occurrences can be accurately counted.Subsequently, an interrupt signal is generated based on the first edge, and the interrupt signal and the accumulated number of pulse signals are sent to a controller unit, so that the controller unit can timely trigger an interrupt program and store the accumulated number in real time, which not only enables quick fault processing when a fault is detected, but also enables real-time storage of the accumulated number of faults, improves the fault detection accuracy and fault processing efficiency, and solves the technical problem of low fault detection accuracy.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computers, in particular to the field of fault detection. BACKGROUND

[0002] With the rapid development of cloud computing, big data and artificial intelligence applications, data center servers are bearing increasingly heavy data processing and storage tasks. These servers are usually equipped with high-performance processors and memories to meet the high concurrency and high throughput business requirements. However, long-term operation of server hardware inevitably encounters various types of faults, among which, correctable error (CE) faults of memory and peripheral component interconnect express (PCIe) devices are particularly worth attention.

[0003] At present, for the CE faults occurring in the server architecture, most of them use a general counting method to count. That is, although the types of CE faults are different, the commonly used counting method is to count all the occurring CE faults, and it is impossible to distinguish the situations of different CE fault types, thereby causing the problem that it is difficult to accurately locate the CE faults. SUMMARY

[0004] The present application provides a fault detection method and chip, a storage medium and an electronic device to at least solve the problem of low fault detection accuracy in related technologies.

[0005] The present application provides a fault detection method, comprising: performing edge detection on a pulse signal received from a fault count pin of a processor; in response to detecting that the pulse signal is at a first edge of a first level, accumulating the number of pulse signals received at the first level; generating an interrupt signal based on the first edge and sending the interrupt signal to a controller unit, wherein the interrupt signal is used to trigger an interrupt program of the controller unit; in response to a data read request sent by the controller unit, sending the accumulated number of pulse signals at the first level to the controller unit, so that the controller unit stores the accumulated number in a statistical register matched with a fault type.

[0006] The application further provides another fault detection method, comprising: disabling a global interrupt of a controller unit in response to an interrupt program triggered by an interrupt signal sent by a programmable logic control device; obtaining fault state information from a processor, wherein the fault state information comprises an identification of a fault type of a fault; obtaining count information from the programmable logic control device, wherein the count information is used to indicate an accumulated number of pulse signals sent by a fault count pin of the processor at a first level; and storing the accumulated number into a statistical register matched with the fault type.

[0007] The application further provides still another fault detection method, comprising: detecting a current running time; sending a data synchronization request to a controller unit in response to the current running time reaching a data synchronization period; obtaining count information stored in each statistical register of a statistical register group of the controller unit according to the data synchronization request, wherein the count information is used to indicate an accumulated number of pulse signals sent by a fault count pin of a processor at a first level, and each statistical register in the statistical register group corresponds to a fault type.

[0008] The application further provides still another fault detection method, comprising: a processor sending a pulse signal to a programmable logic control device through a fault count pin; the programmable logic control device performing edge detection on the detected pulse signal and accumulating the number of pulse signals at the first level, wherein the edge detection is used to detect a first edge of the pulse signal at the first level; the programmable logic control device generating an interrupt signal based on the first edge and sending the interrupt signal to a controller unit, wherein the interrupt signal is used to trigger an interrupt program of the controller unit; the controller unit obtaining fault state information from the processor, wherein the fault state information comprises an identification of a fault type of a fault; the controller unit obtaining count information from the programmable logic control device, wherein the count information is used to indicate an accumulated number of pulse signals sent by the processor at the first level; and the controller unit storing the accumulated number into a statistical register matched with the fault type, and each statistical register corresponds to a fault type; a baseboard management controller obtaining count information stored in each statistical register of the controller unit in response to the current running time reaching a data synchronization period, and displaying and storing the count information.

[0009] The application further provides a fault detection chip, comprising: a processor configured to send a pulse signal to a programmable logic control device through a fault count pin; the programmable logic control device is configured to perform edge detection on the detected pulse signal, and accumulate the number of the detected pulse signals at a first level, wherein the edge detection is configured to detect a first edge of the pulse signal at the first level; the programmable logic control device is further configured to generate an interrupt signal based on the first edge, and send the interrupt signal to a controller unit, wherein the interrupt signal is configured to trigger an interrupt program of the controller unit; the controller unit is configured to obtain fault state information from the processor, wherein the fault state information comprises an identification of a fault type of the fault; the controller unit is further configured to obtain count information from the programmable logic control device, wherein the count information is configured to indicate the accumulated number of the pulse signals at the first level sent by the processor; the controller unit is further configured to store the accumulated number into a statistical register matched with the fault type, and each statistical register corresponds to one fault type; and a baseboard management controller is configured to obtain the count information stored in each statistical register by the controller unit in response to that the current running time reaches a data synchronization period, and display and store the count information.

[0010] The application further provides an electronic device, comprising: a memory configured to store a computer program; and a processor configured to execute the computer program to implement the steps of any of the fault detection methods.

[0011] The application further provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of any of the fault detection methods.

[0012] The application further provides a computer program product, comprising a computer program, and the computer program is executed by a processor to implement the steps of any of the fault detection methods.

[0013] According to the application, the pulse signal received from the fault count pin of the processor is subjected to edge detection, and when the first edge of the pulse signal at the first level is detected, the number of the received pulse signals at the first level is accumulated, so that the number of faults can be accurately counted. Then, the interrupt signal is generated based on the first edge, and the interrupt signal and the accumulated number of the pulse signals are sent to the controller unit, so that the controller unit can timely trigger the interrupt program and store the accumulated number in real time. The application not only enables the fault processing to be quickly completed when the fault is detected, but also enables the accumulated number of the fault to be stored in real time, improves the fault detection accuracy and the fault processing efficiency, and solves the technical problem of low fault detection accuracy. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings described in the following embodiments are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor based on these drawings.

[0015] Figure 1 The schematic diagram of the application environment of a fault detection method according to an embodiment of the present application;

[0016] Figure 2 The flow chart of an optional fault detection method according to an embodiment of the present application;

[0017] Figure 3 The flow chart of another optional fault detection method according to an embodiment of the present application;

[0018] Figure 4 The flow chart of still another optional fault detection method according to an embodiment of the present application;

[0019] Figure 5 The flow chart of still another optional fault detection method according to an embodiment of the present application;

[0020] Figure 6 The flow chart of still another optional fault detection method according to an embodiment of the present application;

[0021] Figure 7 The flow chart of still another optional fault detection method according to an embodiment of the present application;

[0022] Figure 8 The schematic diagram of an optional fault detection method according to an embodiment of the present application;

[0023] Figure 9 The structural block diagram of a fault detection chip according to an embodiment of the present application;

[0024] Figure 10 The schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, but not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0026] It should be noted that in the description of the present application, the terms "comprising", "containing" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or apparatus that includes a series of elements includes not only those elements, but also other elements not explicitly listed or inherent to such a process, method, article or apparatus. The terms "first", "second" and the like in the present application are used to distinguish similar objects, not to describe a specific order or sequence.

[0027] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below in conjunction with the drawings and specific embodiments.

[0028] Optionally, the fault detection method provided by the embodiment can be applied to a fault detection system in an application environment as shown in Figure 1 The programmable logic control device 102 can be, but is not limited to, a complex programmable logic device (CPLD) and the like, which can provide high-density, complex-function logic programming capability. Optionally, the programmable logic control device 102 can internally include, but is not limited to, programmable logic units and programmable interconnection resources to realize the combination of programmability and logic design capability, so that those skilled in the art can configure its logic function according to the needs. For example, the programmable logic control device 102 can be programmed into various digital logic circuits, such as combinational logic, sequential logic, state machine, etc., to realize signal processing, control logic, data path control, etc. For another example, the programmable logic control device 102 can be used for real-time signal processing and monitoring, or for controlling and managing multiple interfaces to realize data reading, sending and conversion.

[0029] Optionally, the controller unit 104 can be, but is not limited to, a microcontroller unit (MCU) and the like, which integrates a central processing unit (CPU), random access memory (RAM), read-only memory (ROM), and various input / output (I / O) interfaces and peripherals on a single chip to perform data acquisition, signal processing, device control and other control tasks.

[0030] Those skilled in the art can understand that Figure 1The shown structure is only schematic and does not limit the structure of the fault detection system. For example, the fault detection system can further include more or less components than those shown, or have a different configuration of components than those shown. Figure 1 The shown structure is only schematic and does not limit the structure of the fault detection system. For example, the fault detection system can further include more or less components than those shown, or have a different configuration of components than those shown. Figure 1 The shown structure is only schematic and does not limit the structure of the fault detection system. For example, the fault detection system can further include more or less components than those shown, or have a different configuration of components than those shown.

[0031] Optionally, as shown in step S102, the programmable logic control device 102 can be configured to perform edge detection on the pulse signal received from the fault count pin of the processor, where the processor can include, but is not limited to, a central processing unit (CPU), a microcontroller unit (MCU), or a field programmable gate array (FPGA) and the like. As shown in step S104, the programmable logic control device 102 can be configured to accumulate the number of pulse signals at the first level in response to detecting a first edge of the pulse signal at the first level. Subsequently, as shown in step S106, the programmable logic control device 102 can be configured to generate an interrupt signal based on the first edge. As shown in step S108, the programmable logic control device 102 can be configured to send the interrupt signal to the controller unit 104. Upon receiving the interrupt signal, as shown in step S110, the controller unit 104 can be configured to trigger an interrupt program. Further, as shown in step S112, the controller unit 104 can be configured to send a data read request to the programmable logic control device 102, where the data read request can be configured to read the accumulated number. As shown in step S114, the programmable logic control device 102 can be configured to send the accumulated number to the controller unit 104 in response to the received data read request, so that the controller unit 104 can be configured to store the accumulated number in a statistical register corresponding to the fault type.

[0032] In this embodiment, a fault detection method is provided, as shown in Figure 2 The fault detection method includes:

[0033] S202, performing edge detection on the pulse signal received from the fault count pin of the processor;

[0034] Optionally, in the embodiment, the fault count pin can be, but is not limited to, a physical connection point on the processor (Central Processing Unit, CPU) for indicating or transmitting fault information. Further, the fault count pin is usually connected to the error detection circuit inside the processor. When an error or abnormal situation is detected, the fault count pin will be activated and send out a pulse signal to monitor and diagnose hardware failures in the system in real time. For example, in the processor, the fault count pin can be used to report correctable errors (CE) of memory or Peripheral Component Interconnect Express (PCIe) devices.

[0035] Optionally, the pulse signal can be a short, non-continuous electrical signal emitted by the fault count pin, which can rise to a peak value in a short time and then fall to the initial state. The pulse signal usually shows a series of high and low level changes in discrete time intervals, which can be used to transmit information or trigger specific electronic device actions. For example, in the signal detection and processing scenario, the signal attribute information (such as pulse width, frequency, amplitude) of the pulse signal can be used to analyze and identify specific events, such as detecting fault occurrence and counting fault occurrence times.

[0036] Further, edge detection is a digital signal processing technique used to identify signal level changes, such as changes from low to high or from high to low. In electronic devices, edge detection is often used to trigger interrupts, count pulses, or synchronize signals. In the embodiment, edge detection is used to detect the edge of the pulse signal to quickly trigger the interrupt of the controller unit when the pulse signal is abnormal.

[0037] S204, in response to detecting that the pulse signal is at the first edge of the first level, counting the number of received pulse signals at the first level;

[0038] Optionally, in the embodiment, the first level can be used to indicate the reference level of the pulse signal abnormality, such as high level (e.g. 5V) or low level (e.g. 0V). The first edge can be, but is not limited to, the first change of the pulse signal from the first level to its opposite level, for example, the first edge can be a rising edge or a falling edge. As an optional solution, when the first level is low, the first edge can be a rising edge; when the first level is high, the first edge can be a falling edge.

[0039] S206, generating an interrupt signal based on the first edge, and sending the interrupt signal to the controller unit, wherein the interrupt signal is used to trigger an interrupt procedure of the controller unit;

[0040] It can be understood that the interrupt signal is a signal used to pause the normal execution sequence of the CPU in the computer hardware, and to execute a specific interrupt processing program instead. When an external event occurs, the hardware (such as an interrupt controller) will send an interrupt signal to the processor to inform the processor that the external event needs to be handled immediately, where the external event can be keyboard input, hardware failure, or the occurrence of a pulse detected by the edge, etc. The interrupt signal is usually transmitted through a specific hardware pin or bus. After receiving the interrupt signal, the processor will immediately save the current execution state, then execute the interrupt service program, and after handling the interrupt event, resume the execution of the interrupted program. In the embodiment, in the case of the event that the pulse signal is at the first level, the above-mentioned interrupt signal can be but not limited to be sent to the controller unit to trigger the interrupt procedure of the controller unit, so as to realize the timely response and processing of the fault event.

[0041] In the embodiment, the sending operation of the above-mentioned interrupt signal can be realized through a serial bus (Inter-Integrated Circuit, IIC for short). The serial bus is a serial bus protocol for data transmission between integrated circuits, and full-duplex communication between multiple devices is realized through two wires, which can be a serial data line (Serial Data, SDA for short) and a serial clock line (Serial Clock, SCL for short). The serial bus supports master-slave communication of multiple devices, allows one master device to exchange data with multiple slave devices, and supports an addressing mechanism to allow the master device to select communication with a specific slave device. The I2C bus is usually used to connect integrated circuits such as sensors, microcontrollers, electrically erasable programmable read-only memories (Electrically Erasable Programmable Read-Only Memory, EEPROM), etc.

[0042] In the embodiment, the above-mentioned interrupt procedure can be but not limited to an interrupt service program (Interrupt Service Routine, ISR) for interrupting the current task executed by the controller unit. After receiving the above-mentioned interrupt signal, the controller unit can but not limited to trigger the interrupt procedure, and read each register in the processor through a platform environment control interface (Platform Environment Control Interface, PECI) to determine which component has failed and determine the specific fault type.

[0043] S208, in response to the data read request sent by the controller unit, sending the accumulated number of pulse signals at the first level to the controller unit, so that the controller unit stores the accumulated number into a statistical register matched with the fault type.

[0044] Optionally, in the embodiment, the data read request described above can be but is not limited to transmitted through the serial bus described above to read the accumulated number. The accumulated number can be but is not limited to the total number of pulse signals at the first level. The statistical register can be but is not limited to a programmable logic control device existing in the fault detection system as shown. Figure 1

[0045] In the embodiment, the fault type described above can be but is not limited to the type of fault occurred in each component in the server, and the fault can include but is not limited to memory device fault, bus device fault. For example, the memory device fault can be single-bit fault, multi-bit fault, etc., the single-bit fault is that there is only one bit of information in a memory cell of the memory device to send correctable error, and the multi-bit fault is that multiple bits of information in a memory cell of the memory device occur information error at the same time. For another example, the bus device fault can be replay timer timeout error, replay counter overflow error, receiver error, etc., the replay timer timeout error means that the data packet retransmission on the bus link exceeds the specified time limit, the replay counter overflow error means that the bus device retransmits the same data packet too many times so that the counter overflows, and the receiver error means that the physical layer of the bus device has signal quality abnormal problems such as voltage fluctuation, noise interference or signal attenuation when transmitting signals.

[0046] Through the embodiment of the application, the pulse signal received from the fault count pin of the processor is edge detected, and when the first edge of the pulse signal at the first level is detected, the number of the received pulse signal at the first level is accumulated, so that the number of fault occurrences can be accurately counted. Subsequently, the interrupt signal is generated based on the first edge, and the interrupt signal and the accumulated number of the pulse signal are sent to the controller unit, so that the controller unit timely triggers the interrupt program and stores the accumulated number in real time, which not only quickly completes the fault processing when the fault is detected, but also stores the accumulated number of the fault in real time, improves the fault detection accuracy and the fault processing efficiency, and solves the technical problem of low accuracy of fault detection.

[0047] As an optional implementation, the edge detection of the pulse signal received from the fault count pin of the processor includes:

[0048] ​The pulse signal received by the input pin in communication with the fault count pin is edge detected by the built-in fault detection program, where the edge detection is used to detect a first edge of the pulse signal at the first level.

[0049] Optionally, in the embodiment, the fault detection program can be but is not limited to a programmable logic control device built-in in the fault detection system as shown in Figure 1 The fault detection program (FDP) is a software program used to automatically identify and report faults or abnormal conditions in computer hardware or software systems, and in the embodiment, the fault detection program is used to perform real-time edge detection on the pulse signal to determine whether the received pulse signal is at the first edge of the first level.

[0050] It can be understood that the input pin is a physical contact point in an electronic device or integrated circuit for receiving external signals or data, used to transmit external electrical signals (such as changes in voltage and current) to internal circuits for processing, and in the embodiment, the input pin is used to communicate with the fault count pin to receive the pulse signal from the fault count pin.

[0051] Through the embodiments of the present application, the received pulse signal is edge detected by the built-in fault detection program, and then the fault is automatically detected by detecting the pulse signal, reducing the information demand in the fault detection process, improving the fault detection efficiency, and reducing the fault detection delay.

[0052] As an optional implementation, in response to detecting the first edge of the pulse signal at the first level, the number of the received pulse signal at the first level is accumulated, including:

[0053] In the case of detecting the first edge of the pulse signal at the first level, the accumulated number currently stored in the local register is incremented by one to obtain an updated accumulated number.

[0054] It can be understood that the register is a high-speed storage device in computer hardware, used to temporarily store data or instructions for quick access by the processor or other hardware components. The register can be used to connect the arithmetic unit of the processor and the main memory, to facilitate data exchange between the processor and I / O devices and other hardware. In the embodiment, the local register used to store the accumulated number can be a register in the programmable logic control device in the fault detection system as shown in Figure 1 Further, in the embodiment, the accumulated number can be but is not limited to stored in the form of a binary number in the local register, which is not limited in the embodiments of the present application.

[0055] Through the embodiment of the present application, the value of the accumulated quantity stored in the local register is updated in the case of detecting the abnormal pulse signal, so that the dynamic statistics of the fault occurrence times is realized through the update of the accumulated quantity, and the real-time and accuracy of the fault time recording and detection are improved.

[0056] As an optional implementation, in response to the data read request sent by the controller unit, sending the accumulated quantity of the pulse signal at the first level to the controller unit comprises:

[0057] In response to the data read request, reading the stored accumulated quantity from the local register;

[0058] Sending the accumulated quantity to the controller unit and performing the zero clearing processing on the local register.

[0059] Optionally, in the embodiment, the data read request can be but is not limited to a read command for reading the accumulated quantity in the register sent by the controller unit, and the read command can be but is not limited to indicating the register address to be read by the controller unit. The local register can be but is not limited to a counting register with a read-zero feature, and the read-zero feature can be but is not limited to indicating that the counting register will clear the stored value after the value is read, so that the data read in the next read operation is new data. In the embodiment, after the accumulated quantity in the local register is read, the data stored in the local register is cleared, so that the accumulated quantity is the new quantity counted after the current read operation is performed in the next read operation.

[0060] Optionally, in the embodiment, the read operation of the accumulated quantity can be but is not limited to being performed according to a certain read period, and the read period is the time interval between adjacent two read operations when the controller unit reads the accumulated quantity stored in the local register. Optionally, a timer for indicating the read period can exist in the main program in the controller unit, so that the read operation of the accumulated quantity is performed in real time according to the preset read period, and the time delay of the read process of the accumulated quantity is reduced.

[0061] Through the embodiment provided in the present application, in response to the data read request sent by the controller unit, the accumulated quantity stored in the local register is read from the local register, and after the read accumulated quantity is sent to the controller unit, the local register is cleared, which not only avoids repeated counting through the real-time zero clearing mechanism of the local register, improves the utilization rate of the local register resource, but also reduces unnecessary communication times and reduces communication load.

[0062] Optionally, the fault detection method can be but is not limited to being applied to, for example,Figure 1 The programmable logic control device in the application environment shown. As an optional solution, the fault detection process of the programmable logic control device can be as shown in Figure 3 As shown in step S302, the programmable logic control device acquires a pulse signal, where the pulse signal is sent from the fault count pin of the processor; as shown in step S304, the programmable logic control device performs edge detection on the pulse signal and accumulates the number of pulse signals detected at the first level to obtain an accumulated number, where the accumulated number can be stored in a local register in the programmable logic control device; then, as shown in step S306, the programmable logic control device generates an interrupt signal based on the first edge, where the interrupt signal can be sent to the controller unit; further, as shown in step S308, the programmable logic control device reads the stored accumulated number from the local register in response to a data read request; as shown in step S310, the programmable logic control device sends the accumulated number to the controller unit and clears the local register.

[0063] As an optional embodiment, another fault detection method is also provided in the embodiment, as shown in Figure 4 The above fault detection method includes:

[0064] S402, in response to the interrupt program triggered by the interrupt signal sent by the programmable logic control device, disabling the global interrupt of the controller unit;

[0065] Optionally, in the embodiment, the global interrupt refers to a mechanism in the controller unit that can suspend all or most of the interrupt processing, where the interrupt refers to a mechanism that allows external events (such as hardware signal changes) to interrupt the current program execution flow of the controller unit at any point in time and process other tasks.

[0066] In the embodiment, the controller unit disables the global interrupt after receiving the interrupt signal to maintain the consistency and stability of the data processing process. Specifically, the controller unit can save the current register state before executing the interrupt program to prevent the data from being chaotic or lost when processing the interrupt is interrupted by other interrupts; then, the controller unit sets a specific interrupt control register bit, such as a global interrupt enable bit, to achieve the disabling of the global interrupt.

[0067] S404, obtaining fault status information from the processor, where the fault status information includes the identification of the fault type of the fault;

[0068] Optionally, in the embodiment, the controller unit obtains the fault status information such as the identification of the fault type from the processor after executing the global interrupt disable, so as to determine the fault type of the current fault. Optionally, the identification of the fault type can be but is not limited to a code or a value for distinguishing different types of faults, so as to process different types of faults by the software or hardware system. Further, the fault status information can further include but is not limited to the fault occurrence time stamp, the fault occurrence frequency, the fault severity, the specific hardware device or system location of the fault, the fault duration, the fault resolution strategy, etc.

[0069] S406, obtaining the count information from the programmable logic control device, wherein the count information is used to indicate the cumulative number of the pulse signals at the first level sent by the fault count pin of the processor;

[0070] Optionally, in the embodiment, the count information can also be used to indicate the count frequency, the count duration period, the number of zero clearings, etc. of the count register. The count register can be a register for storing the cumulative number and located locally in the programmable logic control device.

[0071] S408, storing the cumulative number into the statistical register matched with the fault type.

[0072] Optionally, in the embodiment, the statistical register is a hardware register in the computer system for storing and recording the number of occurrences of a specific type of event or state, which can be used to accumulate and maintain the number of correctable errors or other fault events of a specific component or system level, so as to be analyzed and processed subsequently. In the embodiment, the statistical register can set an independent storage unit for each fault type, so as to independently store the fault data of different types of faults, thereby improving the security of fault data storage. That is, each fault type can match an independent storage unit in the statistical register, and the storage units matched by different fault types can be different. It can be understood that, in the embodiment, the cumulative number stored in the statistical register can be dynamically updated. For example, when the cumulative number changes, the cumulative number stored in the statistical register can be dynamically updated according to the change, so as to maintain the real-time and integrity of the data stored in the statistical register.

[0073] According to the embodiments provided in the present application, the global interruption of the controller unit is disabled in response to the interruption procedure triggered by the interruption signal sent by the programmable logic control device, so as to avoid the data from being disturbed in the fault detection process, and the stability of the fault detection process is improved; after the fault state information is obtained from the processor, the counting information is obtained from the programmable logic control device, and the cumulative number is stored in the statistical register matched with the fault type, which realizes the matched storage of the fault type information and the fault counting information, perfects the storage process of the fault information in the fault detection process, simplifies the fault data analysis process, and enhances the readability and traceability of the fault data.

[0074] As an optional implementation, obtaining the fault state information from the processor comprises:

[0075] The fault state information comprises: first type fault state information stored in a first register of the processor, and second type fault state information stored in a second register of the processor.

[0076] Optionally, in the embodiment, the platform environment control interface bus (PECI) can be but is not limited to a low-delay and high-performance communication protocol, which is mainly used for the communication between the processor and the embedded controller (EC) or other management controllers, such as the baseboard management controller (BMC) in the modern server system. In the embodiment, the platform environment control interface bus is used to obtain the fault state information from the processor, so as to realize the unified management of different types of fault data. The first register and the second register can be the same type of register or different types of register in the processor for storing information. Optionally, in the embodiment, the register in the processor for storing information can be but is not limited to: a data register (DR) for temporarily storing data and operation results, an accumulator register (AR) for storing operation results, a stack pointer register (SPR) for storing local variables, a general-purpose register (GPR) for storing operands, addresses or intermediate results, etc.

[0077] According to the embodiments provided in the present application, the different types of fault state information are obtained from different registers in the processor through the platform environment control interface bus, so that the classification and management of the fault state information are realized, the information transmission time is reduced, and the accuracy and timeliness of the fault state information are improved, so as to provide high-quality fault data basis for fault analysis and fault warning.

[0078] As an optional implementation, the fault state information is obtained from the processor through the platform environment control interface bus, and the obtaining includes:

[0079] The first type of fault state information stored in a first register in a memory controller of the processor is obtained through the platform environment control interface bus, and the first type of fault state information is used to indicate a single-bit fault or a multi-bit fault.

[0080] Optionally, in the embodiment, the memory controller is a component responsible for managing communication with a memory device in a computer system, which is usually integrated in a central processing unit or in a chip on a mainboard, or directly built in the processor. In the fault detection process, the memory controller can be used to read and write data, and dynamically refresh the data stored in the register, so as to realize real-time storage and dynamic update of the fault data.

[0081] Optionally, in the embodiment, the single-bit fault refers to that a certain position in the memory or a bit in the data transmission stream changes, for example, the information changes from 1 to 0 or from 0 to 1. The multi-bit fault refers to that two or more bits of information in the memory or the data transmission change at the same time. It can be understood that the single-bit fault can be repaired by the error correction code (ECC), but the multi-bit fault cannot be repaired.

[0082] According to the embodiments provided in the present application, the first type of fault state information stored in the first register in the processor is directly obtained through the platform environment control interface bus, so that the resource consumption in the transmission process of the fault state information is reduced, and the fault detection cost is saved.

[0083] As an optional implementation, the fault state information is obtained from the processor through the platform environment control interface bus, and the obtaining includes:

[0084] The second type of fault state information stored in a second register corresponding to a root port of the processor is obtained through the platform environment control interface bus, and the second type of fault state information is used to indicate a plurality of faults triggered in an interaction process based on an expansion bus, and the plurality of faults occur at different interaction levels in the interaction process.

[0085] Optionally, in the embodiment, a root port (RP) is a high-speed differential serial controller located inside the processor to configure the operation parameters of the high-speed differential serial device and communicate with the high-speed differential serial device. An expansion bus (EB) refers to a set of signal channels extending the high-speed differential serial signals from the root port to a plurality of downstream ports for signal transmission through a switch, hub or other connection device. The above-mentioned interaction layer (IL) refers to the different data operation processing levels experienced by the data during the transmission of the data from the source device to the destination device.

[0086] In the embodiment, the interaction process based on the expansion bus can be but is not limited to implemented through a peripheral component interconnect express (PCIE) architecture. The PCIE architecture here can include but is not limited to at least one of the following: a transaction layer (TL) for generating and analyzing transaction layer packets (TLPs), processing logical transactions of data interaction such as memory reading and writing, configuration access, etc.; a data link layer (DLL) for transmitting and confirming TLPs at both ends of the link, managing data integrity, flow control and retransmission mechanism, etc.; and a physical layer (PL) for transmitting electrical signals, including data encoding, clock recovery and establishment and maintenance of physical connection.

[0087] In the embodiment, the above-mentioned interaction process based on the expansion bus can be but is not limited to initiated by a data transmission instruction initiated by the root port, which is converted into a transaction layer packet; then, the data packet enters the data link layer to be encoded, flow controlled and integrity checked by the data link layer, so that the data packet is correctly transmitted through the bus; finally, the data packet reaches the physical layer, which is converted into an electrical signal by the physical layer and transmitted through the bus to the corresponding layer of the target device for decoding and processing, thereby completing the data interaction from the source device to the target device.

[0088] Through the embodiments provided in the application, the second type of fault state information stored in the second register corresponding to the root port of the processor is acquired through the platform environment control interface bus to realize the differentiated processing of the fault state information corresponding to different types of faults, thereby improving the robustness of the fault detection process.

[0089] As an optional implementation, acquiring the count information from the programmable logic control device includes:

[0090] sending a fault count reading request to the programmable logic control device through a preset communication protocol;

[0091] obtaining count information read out from a local register of the programmable logic control device in response to the fault count reading request.

[0092] Optionally, in the embodiment, the communication protocol refers to a set of rules and standards followed when data is exchanged between two or more communication entities in a computer network, electronic device or software application. The communication protocol can be used to define the format, order, rate, error detection method and control mechanism of data communication. Further, the communication protocol can enable different devices or systems to correctly and efficiently exchange information, and is the basis for realizing network interconnection and inter-system communication. For example, the communication protocol can be an Inter-Integrated Circuit (IIC) protocol, which allows multiple devices to share the same bus and distinguishes each device by different addresses, each device has a unique address, and the master device can use the address to select communication with the slave device, where the master device is used to control the data line and the clock line to initiate data transmission and stop transmission in time, and the slave device is used to respond to the command of the master device to send or receive data.

[0093] Through the embodiments provided in the present application, the reading of count information is realized by sending a fault count reading request to the programmable logic control device, which realizes the reading of count information through a preset communication protocol, not only can avoid the communication error caused by unclear protocol, improve the stability of the information reading process, but also can avoid the loss or repetition of information, enhance the data integrity and accuracy.

[0094] As an optional implementation, as shown in Figure 5 After obtaining the count information from the programmable logic control device, it further includes:

[0095] S502, in the case that the count information indicates that the accumulated number is a non-zero value, sending a fault count reading request to the programmable logic control device through a preset communication protocol again;

[0096] S504, in the case that the count information indicates that the accumulated number is zero, stopping sending the fault count reading request.

[0097] Optionally, in the embodiment, the register in the programmable logic control device for storing the accumulated number can, but is not limited to, clear the accumulated number after the accumulated number is read. Further, when the controller unit sends a fault count reading request to the programmable logic control device, if the accumulated number is zero, the accumulated number stored in the register in the programmable logic control device has been read and cleared, thus, when the count information indicates that the accumulated number is zero, the sending of the fault count reading request can be stopped; if the accumulated number is not zero, the sending of the fault count reading request can be continued to continuously obtain the accumulated number.

[0098] Through the embodiments provided in the present application, the cyclic reading of the accumulated number is realized by continuously sending the fault count reading request when the accumulated number is not zero until the accumulated number is zero, which realizes the dynamic incremental update of the accumulated number and reduces the burden of data transmission through the dynamic pause mechanism of the request sending process, and improves the data transmission efficiency.

[0099] As an optional implementation, as shown in Figure 6 storing the accumulated number into the statistical register matched with the fault type includes:

[0100] S602, determining, from the statistical register group, a statistical register matched with the identification of the fault type indicated by the fault state information, wherein each statistical register in the statistical register group corresponds to a fault type respectively;

[0101] S604, storing the accumulated number into the statistical register.

[0102] Optionally, in the embodiment, the statistical register group can be a storage unit set for collecting and uniformly managing the number of specific events or state changes in the hardware device. In the computer system, the statistical register group can be applied to monitor the hardware performance parameters, fault frequency, operation count, etc. to facilitate system health monitoring, performance analysis and fault diagnosis.

[0103] In the embodiment, each statistical register in the statistical register group can correspond to a different fault type and be used to store the fault state information of the corresponding fault type. When a fault event of each type occurs, the statistical register corresponding to the fault type can automatically update the accumulated number of the fault type event stored in the statistical register.

[0104] According to the embodiments provided in the present application, when storing the accumulated number, a statistical register matched with the identification of the fault type indicated by the fault status information is determined from the statistical register group, and the accumulated number is stored in the determined statistical register, so as to realize the classified management of the accumulated numbers corresponding to different types of faults by using the mapping relationship between the fault type identification and the statistical register, thereby reducing the coupling degree between the fault data of different types and improving the independence and security of the fault data management.

[0105] As an optional implementation, after obtaining the count information from the programmable logic control device, the method further comprises:

[0106] In response to a data synchronization request of the baseboard management controller, the count information stored in each statistical register of the statistical register group is sent to the baseboard management controller.

[0107] Optionally, in the present embodiment, the baseboard management controller (BMC for short) is a microcontroller embedded on a server motherboard, which is used to monitor the hardware state and environmental parameters of the server, such as temperature, voltage, fan speed, power state, etc., and can perform functions such as system startup, fault diagnosis, log recording and remote management. The baseboard management controller communicates with other components in the system through various communication standards, such as the Intelligent Platform Management Interface (IPMI for short), which allows system administrators to manage the server without running the host operating system. The baseboard management controller can also be used for fault handling of the server, automatically taking measures such as restarting when the server fails, or notifying the remote management system, etc.

[0108] It can be understood that the data synchronization request refers to a request initiated by a node or device in a distributed system or network environment in order to realize the data consistency on different nodes or devices, so as to require other nodes to compare, update or synchronize data with the node initiating the data synchronization request. For example, in the present embodiment, the baseboard management controller can realize data synchronization with the controller unit by sending a data synchronization request, so as to realize data update of the server health state data displayed by the baseboard management controller.

[0109] Through the embodiments provided in the present application, the substrate management controller can realize synchronization of the count information by sending a data synchronization request to the controller unit, which not only promotes the cooperation between devices and enhances the automation degree of the fault detection process through the data synchronization mechanism between the substrate management controller and the controller unit, but also realizes that the substrate management controller can continuously obtain real-time and complete fault count information in the fault detection process, thereby improving the management uniformity of the fault data.

[0110] As an optional implementation, in the present embodiment, another fault detection method is also provided, as shown in Figure 7 The fault detection method includes the following steps.

[0111] S702, detecting a current running time;

[0112] S704, in response to the current running time reaching a data synchronization period, sending a data synchronization request to the controller unit;

[0113] S706, according to the data synchronization request, obtaining count information stored in each statistical register of a statistical register group of the controller unit, wherein the count information is used to indicate the cumulative number of pulse signals at a first level sent by a fault count pin of a processor, and each statistical register in the statistical register group corresponds to a fault type.

[0114] Optionally, in the present embodiment, the current running time can be a time point corresponding to the execution of the current fault detection operation. The data synchronization period refers to a time interval for data synchronization update between two or more systems, devices or components in a distributed system or network environment, which can be used to determine when to initiate a data synchronization request to realize data consistency or dynamic update between different devices for fault detection. Optionally, in the present embodiment, when the time interval between the current running time and the sending time of the last data synchronization request is greater than or equal to the data synchronization period, it can be determined that the current running time reaches the data synchronization period.

[0115] In the present embodiment, the data synchronization request refers to a request initiated by a node or device in a distributed system or network environment in order to realize data consistency on different nodes or devices, so as to require other nodes to compare, update or synchronize data with the node initiating the data synchronization request. For example, in the present embodiment, the substrate management controller can realize data synchronization with the controller unit by sending a data synchronization request, so as to realize data update of the server health status data displayed by the substrate management controller.

[0116] Optionally, the statistical register group can be a set of storage units for collecting and uniformly managing the number of specific events or state changes in the hardware device. In a computer system, the statistical register group can be applied to monitor hardware performance parameters, fault frequency, operation count, etc., to facilitate system health monitoring, performance analysis and fault diagnosis. In the present embodiment, each statistical register in the statistical register group can correspond to a different fault type and be used to store fault state information of the corresponding fault type. When each type of fault event occurs, the statistical register corresponding to the fault type can automatically update the cumulative number of fault type events stored in the statistical register.

[0117] Optionally, in the present embodiment, the fault count pin mentioned above can be, but is not limited to, a physical connection point on the processor (Central Processing Unit, CPU) for indicating or transmitting fault information. Further, the fault count pin is usually connected to the error detection circuit inside the processor. When an error or abnormal situation is detected, the fault count pin will be activated and send out a pulse signal to monitor and diagnose hardware faults in the system in real time. For example, in the processor, the fault count pin can be used to report correctable errors (CE) of memory or Peripheral Component Interconnect Express (PCIE) devices.

[0118] Optionally, the pulse signal mentioned above can be a short, non-continuous electrical signal emitted by the fault count pin, which can rise to a peak value in a short time and then drop to the initial state. The pulse signal usually shows a series of high and low level changes in discrete time intervals and can be used to transmit information or trigger specific electronic device actions. For example, in the signal detection and processing scenario, the signal attribute information (such as pulse width, frequency, amplitude) of the pulse signal can be used to analyze and identify specific events, which can be fault occurrence detection, fault occurrence counting, etc.

[0119] According to the embodiments provided in the present application, in the case that the detected current running time reaches the data synchronization period, a data synchronization request is sent to the controller unit, so as to obtain the count information stored in each statistical register of the statistical register group of the controller unit according to the data synchronization request, and then the continuous synchronization of the count information can be completed according to the data synchronization period, the real-time performance and accuracy of the count information are improved, and the problem of low data quality caused by the omission of fault data and the update delay is avoided. Further, the above fault detection method can also improve the automation degree of fault detection by associating the count information with the fault type, and reduce the operation complexity in the fault troubleshooting and fault repair process.

[0120] As an optional implementation, after obtaining the count information stored in each statistical register of the statistical register group of the controller unit according to the data synchronization request, the following at least one is further included:

[0121] The count information is converted into structured data supporting interface display, or the count information is stored in the non-volatile memory of the baseboard management controller.

[0122] Optionally, in the present embodiment, the structured data refers to data with uniform format and in accordance with certain data storage rules or patterns, and the structured data can be stored in a database table, a spreadsheet or other pre-defined data structure. Further, the structured data is data that has been formatted into specific fields and records, such as dates, numbers, text strings, etc., so that the structured data can be recognized and processed by computer programs, and each piece of data has a clear name and type, and can be indexed, searched, sorted and analyzed. For example, in the present embodiment, the structured data can be a database table, a spreadsheet, JSON data, an XML file, a CSV file, etc.

[0123] Optionally, in the present embodiment, the non-volatile memory is a storage device that can retain data when the power is off, and can be used to store system configuration, fault history record, log file and other key information, so as to realize the continuous detection of hardware fault trend and perform fault analysis and prediction. In the present embodiment, the non-volatile memory can be a magnetoresistive random access memory (MRAM), an electrically erasable programmable read-only memory (EEPROM), a read-only memory (ROM), etc.

[0124] Through the embodiments provided in the present application, the counting information can be converted into structured data that can be displayed on a visualization interface, so as to display fault information in real time, improve the intuitive visibility of the fault condition, and facilitate rapid fault warning and fault response; or the counting information can be stored in a non-volatile memory, so as to realize persistent storage of fault data, improve the security of the fault data, and provide a data basis for long-term fault trend analysis.

[0125] As an optional implementation, after the counting information is converted into structured data that supports interface display, the following at least one is further included:

[0126] The counting information in each statistical register is displayed according to fault types; or fault warning is triggered when the cumulative number indicated by the counting information of at least one statistical register reaches a preset threshold; or a fault report is generated based on the counting information stored in each statistical register in the statistical register group.

[0127] Optionally, in the present embodiment, the counting information of different fault types can be respectively displayed in different display areas of the visualization interface, or displayed in different visualization interfaces. Optionally, the visualization interface or the visualization display area can be matched with the fault type, and fault data of the same type can be displayed in the same visualization interface or in the same display area of the visualization interface.

[0128] Optionally, in the present embodiment, the fault warning is a warning notification automatically triggered when the system detects an abnormal condition that may affect normal operation. Optionally, the fault warning can be issued in the form of a pop-up window on the visualization interface, an email, or the like.

[0129] Optionally, the fault report can include, but is not limited to, fault occurrence time, fault type, device or component that has failed, fault frequency, fault trend analysis, fault repair strategy, and the like.

[0130] Through the embodiments provided in the present application, the display mode of each counting information can be determined according to fault types, so as to realize independent display of fault data of different types and reduce resource waste in the counting information display process; or warning can be triggered when the cumulative number indicated by the counting information reaches a threshold, so as to quickly trigger a fault handling process and avoid problems such as reduced information security or wasted data resources caused by failure to respond to faults in time; or a fault report can be generated and exported based on the counting information stored in each statistical register in the statistical register group, which can realize persistent recording of fault data and facilitate fault analysis using the recorded fault data.

[0131] As an optional implementation, another fault detection method is further provided in the present embodiment, and the above fault detection method includes:

[0132] The processor sends a pulse signal to the programmable logic control device through a fault count pin;

[0133] The programmable logic control device performs edge detection on the detected pulse signal, and accumulates the number of detected pulse signals at the first level, wherein the edge detection is used to detect the first edge of the pulse signal at the first level;

[0134] The programmable logic control device generates an interrupt signal based on the first edge, and sends the interrupt signal to the controller unit, wherein the interrupt signal is used to trigger the interrupt program of the controller unit;

[0135] The controller unit obtains fault state information from the processor, wherein the fault state information includes the identification of the fault type of the fault;

[0136] The controller unit obtains count information from the programmable logic control device, wherein the count information is used to indicate the accumulated number of pulse signals at the first level sent by the processor;

[0137] The controller unit stores the accumulated number into a statistical register matched with the fault type, and each statistical register corresponds to one fault type respectively;

[0138] The baseboard management controller obtains the count information stored in each statistical register from the controller unit in response to the current running time reaching a data synchronization period, and displays and stores the count information.

[0139] Optionally, in the embodiment, the above-mentioned fault count pin can be, but is not limited to, a physical connection point on the above-mentioned processor (Central Processing Unit, CPU) for indicating or transmitting fault information. Further, the above-mentioned fault count pin is usually connected with the error detection circuit inside the processor, when an error or abnormal condition is detected, the fault count pin will be activated and send a pulse signal outward, to monitor and diagnose the hardware fault in the system in real time. For example, in the processor, the fault count pin can be used to report the correctable error (Correctable Errors, CE) of the memory or peripheral component interconnect express (Peripheral Component Interconnect Express, PCIe) device.

[0140] Optionally, the pulse signal can be a short, non-continuous electrical signal emitted by the fault count pin, which rises to a peak value in a short time and then falls to the initial state. The pulse signal usually exhibits a series of discrete high-low level changes in time intervals, which can be used to transmit information or trigger specific electronic device actions. For example, in the context of signal detection and processing, the signal attribute information of the pulse signal (such as pulse width, frequency, amplitude) can be used to analyze and identify specific events, such as detecting fault occurrence, counting fault occurrence times, etc.

[0141] Optionally, the programmable logic control device 102 can be, but is not limited to, a complex programmable logic device (CPLD) that can provide high-density, complex logic programming capabilities. Optionally, the programmable logic control device can internally include, but is not limited to, programmable logic units and programmable interconnection resources to realize the combination of programmability and logic design capabilities, so that those skilled in the art can configure its logic functions as needed. For example, the programmable logic control device can be programmed into various digital logic circuits, such as combinational logic, sequential logic, state machines, etc., to implement signal processing, control logic, data path control, etc. For another example, the programmable logic control device can be used for real-time signal processing and monitoring, or for controlling and managing multiple interfaces to realize data reading, sending and conversion. The device can be, but is not limited to, a complex programmable logic device (CPLD) that can provide high-density, complex logic programming capabilities. Optionally, the programmable logic control device can internally include, but is not limited to, programmable logic units and programmable interconnection resources to realize the combination of programmability and logic design capabilities, so that those skilled in the art can configure its logic functions as needed. For example, the programmable logic control device can be programmed into various digital logic circuits, such as combinational logic, sequential logic, state machines, etc., to implement signal processing, control logic, data path control, etc. For another example, the programmable logic control device can be used for real-time signal processing and monitoring, or for controlling and managing multiple interfaces to realize data reading, sending and conversion.

[0142] In this embodiment, edge detection is a digital signal processing technique used to identify the process of signal level change, such as the change from low to high or from high to low. In electronic devices, edge detection is often used to trigger interrupts, count pulses or synchronize signals. In this embodiment, edge detection is used to detect the edges of the pulse signal to quickly trigger the interrupt of the controller unit when the pulse signal is detected to be abnormal.

[0143] Optionally, in this embodiment, an interrupt signal is a signal in computer hardware used to suspend the normal execution sequence of the CPU and instead execute a specific interrupt handler. When an external event occurs, the hardware (such as an interrupt controller) sends an interrupt signal to the processor to notify the processor that the external event needs to be handled immediately. This external event can be keyboard input, hardware failure, or the occurrence of an edge-detected pulse, etc. Interrupt signals are typically transmitted via specific hardware pins or buses. Upon receiving an interrupt signal, the processor immediately saves its current execution state, then executes the interrupt service routine, handles the interrupt event, and then resumes execution of the interrupted program. In this embodiment, in the event of an event where the pulse signal is at a first level, the aforementioned interrupt signal can, but is not limited to, be sent to the controller unit to trigger the controller unit's interrupt routine, enabling timely response and handling of fault events.

[0144] As an optional approach, in this embodiment, the number of processors can be one or more. For example, the above-described fault detection process can be performed by, for example, Figure 8 The fault detection system shown is implemented. The fault detection system may include, but is not limited to: a first processor 802, a second processor 804, a programmable logic controller 806, a controller unit 808, and a baseboard management controller 810. As shown in step S802, the first processor sends a first pulse signal; as shown in step S804, the second processor sends a second pulse signal. Here, the first pulse signal and the second pulse signal are transmitted to the programmable logic controller through an OR gate. Subsequently, as shown in step S806, the programmable logic controller sends an interrupt signal to the controller unit. The interrupt signal generation process is as follows: the programmable logic controller performs edge detection on the received pulse signal, accumulates the number of detected pulse signals at the first level, obtains the accumulated number, and generates an interrupt signal based on the first edge. Further, as shown in step S808, the first processor sends first fault status information to the controller unit; as shown in step S810, the second processor sends second fault status information to the controller unit; as shown in step S812, the programmable logic controller sends counting information to the controller unit, where the counting information indicates the cumulative number of pulse signals sent by the processor at the first level, which is stored by the controller unit in a statistical register matching the fault type; as shown in step S814, the controller unit sends counting information to the board management controller so that the board management controller can display and store the counting information.

[0145] Through the embodiments provided in the present application, the programmable logic control device performs edge detection on the pulse signal of the processor and counts the number of pulse signals in the first level, so as to realize the detection and counting of faults; the controller unit executes the interrupt program based on the interrupt signal sent by the programmable logic control device, thereby improving the timeliness and accuracy of fault response; the baseboard management controller stores and displays the counting information, which can realize long-term fault detection and fault data analysis, and improve the fault detection accuracy.

[0146] Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and necessary general hardware platforms, of course, it can also be realized by hardware, but in many cases, the former is a better embodiment.

[0147] The embodiments of the present application also provide a fault detection chip, as shown in Figure 9 The fault detection chip comprises:

[0148] The processor 902 is configured to send a pulse signal to the programmable logic control device through a fault counting pin;

[0149] The programmable logic control device 904 is configured to perform edge detection on the detected pulse signal, and accumulate the number of detected pulse signals in the first level, wherein the edge detection is used to detect the first edge of the pulse signal in the first level; and the programmable logic control device 904 is further configured to generate an interrupt signal based on the first edge, and send the interrupt signal to the controller unit, wherein the interrupt signal is used to trigger the interrupt program of the controller unit;

[0150] The controller unit 906 is configured to obtain fault state information from the processor, wherein the fault state information comprises the identification of the fault type of the fault; and the controller unit 906 is further configured to obtain counting information from the programmable logic control device, wherein the counting information is used to indicate the accumulated number of pulse signals in the first level sent by the processor; and the controller unit 906 is further configured to store the accumulated number into a statistical register matched with the fault type, and each statistical register corresponds to one fault type.

[0151] The baseboard management controller 908 is configured to obtain the counting information stored in each statistical register of the controller unit in response to that the current running time reaches a data synchronization period, and display and store the counting information.

[0152] As an optional solution, the programmable logic control device 904 comprises:

[0153] The detection unit is configured to perform edge detection on the pulse signal received from the fault counting pin of the processor;

[0154] an accumulation unit, configured to accumulate a number of the received pulse signals at the first level in response to detecting the first edge of the pulse signal at the first level;

[0155] a first processing unit, configured to generate an interrupt signal based on the first edge, and send the interrupt signal to the controller unit, where the interrupt signal is used to trigger an interrupt procedure of the controller unit;

[0156] a first sending unit, configured to send the accumulated number of the pulse signals at the first level to the controller unit in response to a data read request sent by the controller unit, so that the controller unit stores the accumulated number into a statistical register matched with the fault type.

[0157] As an optional solution, the detection unit comprises:

[0158] a detection module, configured to perform edge detection on the pulse signal received by the input pin in communication with the fault count pin through a built-in fault detection procedure, where the edge detection is used to detect the first edge of the pulse signal at the first level.

[0159] As an optional solution, the accumulation unit comprises:

[0160] a first processing module, configured to perform plus one processing on the accumulated number currently stored in the local register to obtain an updated accumulated number in response to detecting the first edge of the pulse signal at the first level.

[0161] As an optional solution, the sending unit comprises:

[0162] a reading module, configured to read the stored accumulated number from the local register in response to a data read request;

[0163] a second processing module, configured to send the accumulated number to the controller unit and perform zero clearing processing on the local register.

[0164] As an optional solution, the controller unit 906 comprises:

[0165] a second processing unit, configured to disable a global interrupt of the controller unit in response to an interrupt procedure triggered by the interrupt signal sent by the programmable logic control device;

[0166] a first obtaining unit, configured to obtain fault state information from the processor, where the fault state information comprises an identification of a fault type of a fault occurred;

[0167] a second obtaining unit, configured to obtain count information from the programmable logic control device, where the count information is used to indicate an accumulated number of the pulse signal at the first level sent by the fault count pin of the processor.

[0168] a storage unit, configured to store the accumulated number into a statistical register matched with the fault type.

[0169] As an optional solution, the first obtaining unit comprises:

[0170] a first obtaining module, configured to obtain the fault status information from the processor through a platform environment control interface bus, wherein the fault status information comprises first fault status information stored in a first register of the processor and second fault status information stored in a second register of the processor.

[0171] As an optional solution, the obtaining module comprises:

[0172] a first obtaining submodule, configured to obtain the first fault status information stored in the first register of the memory controller of the processor through the platform environment control interface bus, wherein the first fault status information is used to indicate a single-bit fault or a multi-bit fault.

[0173] As an optional solution, the obtaining module further comprises:

[0174] a second obtaining submodule, configured to obtain the second fault status information stored in the second register corresponding to the root port of the processor through the platform environment control interface bus, wherein the second fault status information is used to indicate a plurality of faults triggered in an interaction process based on an extension bus, and the plurality of faults occur at different interaction levels of the interaction process.

[0175] As an optional solution, the second obtaining unit comprises:

[0176] a sending module, configured to send a fault count reading request to the programmable logic control device through a preset communication protocol;

[0177] a second obtaining module, configured to obtain count information read out from a local register by the programmable logic control device in response to the fault count reading request.

[0178] As an optional solution, the controller unit 906 further comprises:

[0179] a second sending unit, configured to send the fault count reading request to the programmable logic control device through the preset communication protocol again in a case where the count information indicates that the accumulated number is a nonzero value;

[0180] a third processing unit, configured to stop sending the fault count reading request in a case where the count information indicates that the accumulated number is zero.

[0181] As an optional solution, the storage unit further comprises:

[0182] determining, from the set of statistical registers, a statistical register that matches the identification of the fault type indicated by the fault status information, wherein each statistical register in the set of statistical registers respectively corresponds to a fault type;

[0183] storing, by the storage module, the accumulated number into the statistical register.

[0184] As an optional solution, the controller unit 906 further includes:

[0185] The third sending unit is configured to send, in response to a data synchronization request of the baseboard management controller, the count information respectively stored in each statistical register in the set of statistical registers to the baseboard management controller.

[0186] As an optional solution, the baseboard management controller 908 further includes:

[0187] The second detection unit is configured to detect the current running time.

[0188] The fourth sending unit is configured to send, in response to the current running time reaching a data synchronization period, a data synchronization request to the controller unit.

[0189] The third obtaining unit is configured to obtain, according to the data synchronization request, the count information respectively stored in each statistical register in the set of statistical registers of the controller unit, wherein the count information is used to indicate an accumulated number of the pulse signal at the first level sent by the fault count pin of the processor, and each statistical register in the set of statistical registers respectively corresponds to a fault type.

[0190] As an optional solution, the baseboard management controller 908 further includes:

[0191] The fourth processing unit is configured to convert the count information into structured data that supports interface display, or store the count information into a non-volatile memory of the baseboard management controller.

[0192] As an optional solution, the baseboard management controller 908 further includes:

[0193] The fifth processing unit is configured to respectively display the count information in each statistical register according to the fault type, or trigger a fault alarm when the accumulated number indicated by the count information of at least one statistical register reaches a preset threshold, or generate a fault report based on the count information respectively stored in each statistical register in the set of statistical registers, and export the fault report.

[0194] The features of the embodiments corresponding to the fault detection chip can be referred to the related descriptions of the embodiments corresponding to the fault detection method, which will not be repeated here.

[0195] An embodiment of the present application further provides an electronic device, Figure 10 is a schematic diagram of an electronic device according to an embodiment of the present application, as Figure 10 shown, the electronic device comprises a memory and a processor, the memory stores a computer program, and the processor is configured to execute the computer program to perform the steps in any of the above-mentioned fault detection method embodiments.

[0196] An embodiment of the present application further provides a computer readable storage medium, which stores a computer program, wherein the computer program is configured to perform the steps in any of the above-mentioned fault detection method embodiments when executed.

[0197] In one exemplary embodiment, the above-mentioned computer readable storage medium can include, but is not limited to, a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media capable of storing computer programs.

[0198] An embodiment of the present application further provides a computer program product, which comprises a computer program, and the computer program is executed by a processor to implement the steps in any of the above-mentioned fault detection method embodiments.

[0199] An embodiment of the present application further provides another computer program product, which comprises a non-volatile computer readable storage medium, and the non-volatile computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps in any of the above-mentioned fault detection method embodiments.

[0200] The skilled person can further realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in the above description in a general manner. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0201] The above describes in detail the fault detection method provided by the present application. The principles and implementation manners of the present application are described by using specific examples, and the above description of the examples is only applicable to helping understand the method of the present application and the core idea thereof. It should be pointed out that, for those skilled in the art, some improvements and modifications can be made to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A fault detection method, characterized in that, include: The programmable logic controller performs edge detection on the pulse signal received from the processor's fault count pin; The programmable logic controller, in response to detecting that the pulse signal is at a first edge of a first level, accumulates the number of received pulse signals at the first level; The programmable logic controller generates an interrupt signal based on the first edge and sends the interrupt signal to the controller unit, wherein the interrupt signal is used to trigger the interrupt routine of the controller unit; In response to a data read request sent by the controller unit, the programmable logic controller sends the cumulative number of pulse signals at the first level to the controller unit. The controller unit stores the cumulative number in a statistical register matching the fault type according to the fault type identifier included in the fault status information, and sends the cumulative number stored in the statistical register to the board management controller in response to a data synchronization request sent by the board management controller. The board management controller stores and displays the cumulative number. The fault status information is obtained by the controller unit from the processor.

2. The fault detection method according to claim 1, characterized in that, The programmable logic controller performs edge detection on the pulse signal received from the processor's fault counting pin, including: The programmable logic controller uses a built-in fault detection program to perform edge detection on the pulse signal received by the input pin that communicates with the fault counting pin, wherein the edge detection is used to detect the first edge of the pulse signal at the first level.

3. The fault detection method according to claim 1, characterized in that, The programmable logic controller, in response to detecting that the pulse signal is at a first edge of a first level, accumulates the number of received pulse signals at the first level, including: When the pulse signal is detected to be at the first edge of the first level, the programmable logic controller increments the cumulative quantity currently stored in the local register by one to obtain the updated cumulative quantity.

4. The fault detection method according to claim 3, characterized in that, In response to a data read request sent by the controller unit, the programmable logic controller sends the cumulative number of pulse signals at the first level to the controller unit, including: In response to the data read request, the programmable logic controller reads the stored cumulative quantity from the local register; The programmable logic controller sends the accumulated amount to the controller unit and clears the local register.

5. A fault detection method, characterized in that, include: The controller unit disables global interrupts in response to the interrupt routine triggered by the interrupt signal sent by the programmable logic controller. The controller unit obtains fault status information from the processor, wherein the fault status information includes an identifier of the fault type in which the fault occurred; The controller unit obtains counting information from the programmable logic controller, wherein the counting information is used to indicate the cumulative number of pulse signals sent by the fault counting pin of the processor at the first level; The controller unit stores the accumulated quantity into a statistics register that matches the fault type; In response to a data read request sent by the baseboard management controller, the controller unit sends the cumulative quantity stored in each of the statistical registers, so that the baseboard management controller can display and store the cumulative quantity.

6. The fault detection method according to claim 5, characterized in that, The controller unit obtains fault status information from the processor, including: The controller unit obtains the fault status information from the processor through the platform environment control interface bus. The fault status information includes: a first type of fault status information stored in a first register of the processor, and a second type of fault status information stored in a second register of the processor.

7. The fault detection method according to claim 6, characterized in that, The controller unit obtains the fault status information from the processor via the platform environment control interface bus, including: The controller unit obtains the first type of fault status information stored in the first register in the memory controller of the processor through the platform environment control interface bus, wherein the first type of fault status information is used to indicate a single-bit fault or a multi-bit fault.

8. The fault detection method according to claim 6, characterized in that, The controller unit obtains the fault status information from the processor via the platform environment control interface bus, including: The controller unit obtains the second type of fault status information stored in the second register corresponding to the root port of the processor through the platform environment control interface bus. The second type of fault status information is used to indicate multiple faults triggered during the interaction process based on the extended bus. The multiple faults occur at different interaction levels of the interaction process.

9. The fault detection method according to claim 5, characterized in that, The controller unit obtains counting information from the programmable logic controller including: The controller unit sends a fault count read request to the programmable logic controller via a preset communication protocol; The controller unit acquires the counting information read from the local register by the programmable logic controller in response to the fault count read request.

10. The fault detection method according to claim 9, characterized in that, After the controller unit obtains the counting information from the programmable logic controller, the method further includes: When the counting information indicates that the cumulative number is non-zero, the controller unit sends the fault count read request to the programmable logic controller again through the preset communication protocol; When the counting information indicates that the cumulative number is zero, the controller unit stops sending the fault count read request.

11. The fault detection method according to claim 5, characterized in that, The controller unit stores the accumulated quantity into a statistics register that matches the fault type, including: The controller unit determines from the statistical register group the statistical register that matches the identifier of the fault type indicated by the fault status information, wherein each statistical register in the statistical register group corresponds to a fault type. The controller unit stores the cumulative quantity in the statistics register.

12. A fault detection method, characterized in that, include: The baseboard management controller detects the current running time; The baseboard management controller sends a data synchronization request to the controller unit in response to the current running time reaching the data synchronization cycle. According to the data synchronization request, the baseboard management controller obtains the counting information stored in each statistical register in the statistical register group of the controller unit. The counting information is used to indicate the cumulative number of pulse signals sent from the processor's fault counting pin to the programmable logic controller at the first level. Each statistical register in the statistical register group corresponds to a fault type. The substrate management controller stores the counting information in a non-volatile memory; The substrate management controller converts the counting information into structured data that supports interface display, so that the counting information can be displayed.

13. The fault detection method according to claim 12, characterized in that, After the substrate management controller converts the counting information into structured data that supports interface display, it also includes at least one of the following: The baseboard management controller displays the count information in each of the statistical registers according to the fault type; or, If the cumulative number indicated by the count information in at least one of the statistical registers reaches a preset threshold, the baseboard management controller triggers a fault alarm. or, The baseboard management controller generates a fault report based on the count information stored in each of the statistical registers in the statistical register group, and then exports the fault report.

14. A fault detection method, characterized in that, include: The processor sends pulse signals to the programmable logic controller via the fault counting pin; The programmable logic controller performs edge detection on the detected pulse signal and accumulates the number of detected pulse signals at the first level, wherein the edge detection is used to detect the first edge of the pulse signal at the first level; The programmable logic controller generates an interrupt signal based on the first edge and sends the interrupt signal to the controller unit, wherein the interrupt signal is used to trigger the interrupt routine of the controller unit; The controller unit obtains fault status information from the processor, wherein the fault status information includes an identifier of the fault type in which the fault occurred; The controller unit obtains counting information from the programmable logic controller, wherein the counting information is used to indicate the cumulative number of pulse signals sent by the processor at the first level; The controller unit stores the accumulated quantity into a statistical register that matches the fault type, with each statistical register corresponding to a fault type. When the current running time reaches the data synchronization cycle, the baseboard management controller obtains the count information stored in each of the statistical registers from the controller unit, and displays and stores the count information.

15. A fault detection chip, characterized in that, include: The processor is used to send pulse signals to the programmable logic controller via the fault counting pin; A programmable logic controller (PLC) is configured to perform edge detection on the detected pulse signal and accumulate the number of detected pulse signals at a first level, wherein the edge detection is used to detect a first edge of the pulse signal at the first level; and is further configured to generate an interrupt signal based on the first edge and send the interrupt signal to a controller unit, wherein the interrupt signal is used to trigger an interrupt routine of the controller unit. The controller unit is configured to acquire fault status information from the processor, wherein the fault status information includes an identifier of the fault type in which the fault occurred; it is also configured to acquire counting information from the programmable logic controller, wherein the counting information is used to indicate the cumulative number of pulse signals sent by the processor at the first level; and it is also configured to store the cumulative number in a statistical register that matches the fault type, wherein each statistical register corresponds to a fault type. The baseboard management controller is used to obtain the count information stored in each of the statistical registers from the controller unit in response to the current running time reaching the data synchronization cycle, and to display and store the count information.

16. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the fault detection method as described in any one of claims 1 to 14 when executing the computer program.

17. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the fault detection method as described in any one of claims 1 to 14.

18. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the fault detection method as described in any one of claims 1 to 14.

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