Memory system, memory controller, control method, and storage medium

Abstract

The embodiment of the invention provides a memory system, a memory controller, a control method and a storage medium. The method comprises the following steps: sending a first command segment of a first command; sending a second command in the idle time of the first command; and when the idle time of the first command ends, sending the second command segment of the first command. According to the method, the second command is sent by using the idle time between the first command segment and the second command segment of the first command, so that the transmission efficiency of the bus is improved while the normal transmission of the first command is ensured.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular, to a memory system, a storage controller, a control method and a storage medium. BACKGROUND

[0002] In a memory system, a storage controller and a storage device are connected through a bus. The bus is responsible for transmitting control commands, address information and read / write data between the storage controller and the storage device. As the data transmission rate in the memory system continues to increase, the demand for transmission rate on the bus also increases. However, based on the requirements of related specification protocols, the timing related to the commands transmitted on the bus does not correspondingly shorten. This makes the efficiency of transmitting commands on the bus relatively reduced as the data transmission rate in the memory system continues to increase. Therefore, there is room for further improvement in the efficiency of transmitting commands on the bus. SUMMARY

[0003] Embodiments of the present disclosure provide a memory system, a storage controller, a control method and a storage medium.

[0004] According to an aspect of an embodiment of the present disclosure, a memory system is provided, comprising: a storage device; the storage device comprising a storage chip; and a storage controller coupled to the storage device, wherein the storage controller is configured to: send a first command segment of a first command; the first command comprising a first command segment and a second command segment; an idle time is provided between the first command segment and the second command segment; within the idle time of the first command, a second command is sent; and after the idle time of the first command ends, the second command segment of the first command is sent.

[0005] In some example embodiments of the present disclosure, the storage controller is further configured to: a command occupation time corresponding to the second command is less than the idle time of the first command.

[0006] In some example embodiments of the present disclosure, the storage controller is further configured to: obtain a first to-be-sent command; determine whether a command occupation time of the first to-be-sent command is less than a first time threshold; the first time threshold is less than or equal to the idle time of the first command; and in response to the command occupation time of the first to-be-sent command being less than the first time threshold, determine that the first to-be-sent command is the second command.

[0007] In some example embodiments of the present disclosure, the second command is a status read command.

[0008] In some example embodiments of the present disclosure, the storage controller is further configured to: send a third command in the idle time of the first command; and a sum of command occupation times corresponding to the second command and the third command is less than the idle time of the first command.

[0009] In some example embodiments of the present disclosure, the storage controller is further configured to: start timing when the sending of the first command segment of the first command is completed; send the second command during the timing; and send the second command segment of the first command when the timing reaches the idle time of the first command.

[0010] In some example embodiments of the present disclosure, the storage controller is further configured to: obtain a second to-be-sent command; determine whether an idle time of the second to-be-sent command is greater than a second time threshold; and in response to the idle time of the second to-be-sent command being greater than the second time threshold, determine that the second to-be-sent command is the first command.

[0011] In some example embodiments of the present disclosure, the storage controller is further configured to: the idle time of the first command comprises a column address change time of the first command.

[0012] In some example embodiments of the present disclosure, the storage controller is further configured to: the first command corresponds to a first enable; and the second command corresponds to a second enable.

[0013] In some example embodiments of the present disclosure, the storage controller is further configured to: the first enable and the second enable correspond to storage chips located on the same physical channel, respectively.

[0014] According to another aspect of the embodiments of the present disclosure, a storage controller is provided, comprising: a controller memory configured to store control instructions; and a controller processor coupled to the controller memory and configured to execute the control instructions to perform a process, the process comprising: sending a first command segment of a first command; the first command comprising a first command segment and a second command segment; an idle time being provided between the first command segment and the second command segment; sending a second command in the idle time of the first command; and sending the second command segment of the first command when the idle time of the first command ends.

[0015] In some example embodiments of the present disclosure, the process further comprises: a command occupation time corresponding to the second command is less than the idle time of the first command.

[0016] In some example embodiments of the present disclosure, the processing further includes: obtaining a first to-be-sent command; determining whether a command occupation time of the first to-be-sent command is less than a first time threshold; the first time threshold is less than or equal to an idle time of the first command; in response to the command occupation time of the first to-be-sent command being less than the first time threshold, determining that the first to-be-sent command is the second command.

[0017] In some example embodiments of the present disclosure, the processing further includes: the second command is a status read command.

[0018] In some example embodiments of the present disclosure, the processing further includes: within the idle time of the first command, sending a third command; a sum of command occupation times corresponding to the second command and the third command is less than the idle time of the first command.

[0019] In some example embodiments of the present disclosure, the processing further includes: starting timing when the first command segment of the first command is sent; in the process of the timing, sending the second command; when the timing reaches the idle time of the first command, sending the second command segment of the first command.

[0020] In some example embodiments of the present disclosure, the processing further includes: obtaining a second to-be-sent command; determining whether an idle time of the second to-be-sent command is greater than a second time threshold; in response to the idle time of the second to-be-sent command being greater than the second time threshold, determining that the second to-be-sent command is the first command.

[0021] In some example embodiments of the present disclosure, the processing further includes: the idle time of the first command includes a column address change time of the first command.

[0022] In some example embodiments of the present disclosure, the processing further includes: the first command corresponds to a first enable; the second command corresponds to a second enable.

[0023] In some example embodiments of the present disclosure, the processing further includes: the first enable and the second enable respectively correspond to storage chips located on the same physical channel.

[0024] According to still another aspect of the embodiments of the present disclosure, a control method of a memory system is provided, including: sending a first command segment of a first command; the first command includes a first command segment and a second command segment; an idle time is set between the first command segment and the second command segment; within the idle time of the first command, sending a second command; when the idle time of the first command ends, sending the second command segment of the first command.

[0025] In some example embodiments of the present disclosure, the second command corresponds to a command occupation time less than an idle time of the first command.

[0026] In some example embodiments of the present disclosure, the method further comprises: obtaining a first to-be-sent command; determining whether a command occupation time of the first to-be-sent command is less than a first time threshold; the first time threshold is less than or equal to an idle time of the first command; in response to the command occupation time of the first to-be-sent command being less than the first time threshold, determining that the first to-be-sent command is the second command.

[0027] In some example embodiments of the present disclosure, the second command is a status read command.

[0028] In some example embodiments of the present disclosure, a third command is sent within the idle time of the first command; a sum of command occupation times corresponding to the second command and the third command is less than the idle time of the first command.

[0029] In some example embodiments of the present disclosure, the sending of the second command within the idle time of the first command comprises: starting timing when the sending of the first command segment of the first command is completed; sending the second command during the timing; and sending the second command segment of the first command when the timing reaches the idle time of the first command.

[0030] In some example embodiments of the present disclosure, a second to-be-sent command is obtained; it is determined whether an idle time of the second to-be-sent command is greater than a second time threshold; in response to the idle time of the second to-be-sent command being greater than the second time threshold, it is determined that the second to-be-sent command is the first command.

[0031] In some example embodiments of the present disclosure, the idle time of the first command comprises a column address change time of the first command.

[0032] In some example embodiments of the present disclosure, the first command corresponds to a first enable; and the second command corresponds to a second enable.

[0033] In some example embodiments of the present disclosure, the first enable and the second enable correspond to storage chips located on the same physical channel, respectively.

[0034] According to still another aspect of the embodiments of the present disclosure, a computer readable storage medium is provided, when control instructions in the computer readable storage medium are executed by a controller processor, the controller processor is enabled to perform any of the control methods.

[0035] The memory system, the memory controller and the control method provided by the embodiments of the present disclosure send a first command segment of a first command; in the idle time of the first command, a second command is sent; when the idle time of the first command ends, a second command segment of the first command is sent. The method uses the idle time between the first command segment and the second command segment of the first command to send the second command, which ensures the normal transmission of the first command and improves the transmission efficiency of the bus.

[0036] It should be understood that the general description above and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0037] The drawings incorporated into the specification and forming a part of the specification, show embodiments consistent with the present disclosure, and together with the specification, serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.

[0038] Figure 1A The schematic diagram of an exemplary system with a memory system for an embodiment of the present disclosure;

[0039] Figure 1B The schematic diagram of an exemplary memory card with a memory system for an embodiment of the present disclosure;

[0040] Figure 1C The schematic diagram of an exemplary solid state drive with a memory system for an embodiment of the present disclosure;

[0041] Figure 1D The schematic diagram of an exemplary memory controller with a memory system for an embodiment of the present disclosure;

[0042] Figure 1E The schematic diagram of an exemplary memory device including an array of memory cells and peripheral circuitry for an embodiment of the present disclosure;

[0043] Figure 1F The schematic diagram of an exemplary memory device architecture with a memory system for an embodiment of the present disclosure;

[0044] Figure 2 The flowchart of a control method of a memory system for an embodiment of the present disclosure;

[0045] Figure 3 The flowchart of a second command determination method for an embodiment of the present disclosure;

[0046] Figure 4 The flowchart of an idle time timing process for an embodiment of the present disclosure;

[0047] Figure 5 Flowchart of a first command determination method for an embodiment of the present disclosure;

[0048] Figure 6 Flowchart of a command sending process for an embodiment of the present disclosure;

[0049] Figure 7A Exemplary timing diagram of a command for an embodiment of the present disclosure;

[0050] Figure 7B Exemplary timing diagram of a command for another embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the several views.

[0052] The features, structures, or characteristics described in connection with the present disclosure can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the present disclosure. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the present disclosure.

[0053] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain principles of the present disclosure. In the drawings:

[0054] The flowcharts shown in the drawings are only exemplary illustrations, and do not necessarily include all contents and steps, nor are they necessarily executed in the order described. For example, some steps can be further divided, and some steps can be combined or partially combined, so the actual execution order can be changed according to actual conditions.

[0055] In this specification, the words "one", "an", "the", "said", and "at least one" are used to mean that there is at least one of something / constituent / part, etc.; the words "comprise", "include" and "have" are used to mean an open-ended inclusion of the elements / constituents / species / etc. listed, and that additional elements / constituents / species / etc. can be present; the words "first", "second", and "third", etc. are used only as labels, and do not limit the number of objects.

[0056] Figure 1A A schematic diagram of an exemplary system having a memory system is provided for an embodiment of the present disclosure. The system 100 can be a mobile phone, a desktop computer, a portable computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having a storage device therein. As shown in FIG. 1, the system 100 can include a host 108 and a memory system 102 having one or more storage devices 104 and a storage controller 106. Figure 1A

[0057] The host 108 can be a processor (e.g., a Central Processing Unit (CPU)) or a System on Chip (SoC) (e.g., an Application Processor (AP)) of an electronic device. The host 108 can be coupled to the storage controller 106 and configured to send data to or receive data from the storage device 104 through the storage controller 106. For example, the host 108 can send program data in a program operation or receive read data in a read operation. The host 108 is configured to receive and send instructions and commands from and to the storage controller 106 of the memory system 102, and perform or implement a plurality of functions and operations provided in the present disclosure, which will be described below.

[0058] ​The storage device 104 can be any storage device disclosed in the present disclosure, e.g., a NAND flash storage device, which includes a page buffer having multiple portions. Note that NAND flash is merely one example of a storage device for illustrative purposes. The storage device 104 can include any suitable non-volatile memory, e.g., NOR flash, Ferroelectric Random Access Memory (FeRAM), Phase Change Memory (PCM), Magnetic Random Access Memory (MRAM), Spin-Transfer Torque Random Access Memory (STT-RAM), or Resistive Random Access Memory (RRAM), among others. In some implementations, the storage device 104 includes a three-dimensional (3D) NAND flash memory.

[0059] The storage controller 106 can be implemented by a microprocessor, a microcontroller (also known as a Microcontroller Unit (MCU)), a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), a Programmable Logic Device (PLD), a state machine, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described below in the detailed description.

[0060] According to some implementations, a storage controller 106 is coupled to the storage device 104 and the host 108 and is configured to control the storage device 104. The storage controller 106 can manage data stored in the storage device 104 and communicate with the host 108. In some implementations, the storage controller 106 is designed for operation in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices (e.g., personal computers, digital cameras, mobile phones, etc.). In some implementations, the storage controller 106 is designed for operation in a high duty cycle environment, such as an SSD or an Embedded MultiMedia Card (eMMC) for use as data storage for mobile devices (e.g., smartphones, tablet computers, laptop computers, etc.) and enterprise storage arrays. The storage controller 106 can be configured to control the operation of the storage device 104, such as read, erase, and program operations, by providing instructions, such as read instructions, to the storage device 104. For example, the storage controller 106 can be configured to provide read instructions to the peripheral circuitry of the storage device 104 to control read operations. The storage controller 106 can also be configured to manage various functions with respect to data stored or to be stored in the storage device 104, including, but not limited to, bad block management, garbage collection (GC), logical to physical address translations, wear leveling, etc. In some implementations, the storage controller 106 is also configured to handle error correcting codes (ECC) with respect to data read from or written to the storage device 104. The storage controller 106 can also perform any other suitable functions, such as formatting the storage device 104.

[0061] The storage controller 106 can communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the storage controller 106 can communicate with the external device through at least one of various interface protocols, such as the USB protocol, the MMC (Multi Media Card) protocol, the Peripheral Component Interconnect (PCI) protocol, the PCI-Express (PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer System Interface (SCSI) protocol, the Enhanced Small Drive Interface (ESDI) protocol, the Integrated Drive Electronics (IDE) protocol, the FireWire protocol, and the like.

[0062] The storage controller 106 and the one or more storage devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products.

[0063] In such Figure 1B In one example shown in FIG, the storage controller 106 and the storage device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA (Personal Computer Memory Card International Association) card), a CF card, a Smart Media (SM) card, a memory stick, a MultiMediaCard (MMC), an SD card, a UFS, etc. The memory card 202 can also include a memory card connector 204 that couples the memory card to a host (e.g., the host 108 in FIG. 1 ).

[0064] In such Figure 1C In another example shown in FIG, the storage controller 106 and the plurality of storage devices 104 may be integrated into a solid-state drive 206. The solid-state drive 206 may also include a computer that connects the solid-state drive 206 to a host (e.g., Figure 1AThe solid state drive 206 is coupled to the memory card 202 via a solid state drive connector 208. In some implementations, the solid state drive 206 has a larger storage capacity and / or a faster operating speed than the memory card 202.

[0065] Figure 1D A schematic diagram of an exemplary storage controller having a memory system is shown for an embodiment of the present disclosure. As shown, the storage controller 106 is coupled to a host 108 and one or more storage devices 104, respectively, for controlling data sent by the host 108 to the storage devices 104 or read from the storage devices 104 back to the host 108. The storage controller 106 includes at least a processor 410, a host interface 411, a memory interface 412, an error checking and correcting (ECC) module 413, a garbage collection module 414, a wear leveling module 415, and a data buffer 416. Figure 1D

[0066] The processor 410 is the core part of the storage controller, which is used to execute the control logic and algorithms of the storage controller, and is responsible for processing command queues, address mapping, garbage collection, data compression, input / output control, and the like. The processor 410 can be implemented by an embedded processor or an FPGA.

[0067] The host interface 411 is coupled to the host 108 and the processor 410, respectively, and is a communication interface component between the host and the storage controller, which is responsible for data transmission between the host and the storage controller, including data reading and writing, and command receiving and sending. It usually supports various interfaces (such as SATA (Serial Advanced Technology Attachment), PCIe) and protocols (such as AHCI (Advanced Host Controller Interface), NVMe (Non-Volatile Memory Express)), and provides data transmission functions.

[0068] The memory interface 412 is coupled to the storage device 104 and the processor 410, respectively, and is a communication interface component between the storage device and the storage controller, which is responsible for implementing data reading and writing, erasing, and address mapping, and the like.

[0069] The error checking and correcting (ECC) module 413 is coupled to the processor 410, and is used for error correction protection of data integrity. It attaches specific redundancy check information when writing data, and decodes and checks when reading data, automatically corrects possible bit errors, thereby enhancing the reliability of data.

[0070] ​The garbage collection (GC) module 414 is coupled to the processor 410 and is used to release invalid or updated data blocks. It moves valid data on a data block to other data blocks so that the data block can be erased and reused.

[0071] The wear leveling (WL) module 415 is coupled to the processor 410 and is used to balance the number of erasures of each data block.

[0072] Data buffer 416, coupled to processor 410, is used to temporarily store data and can also cache instructions and data. It typically uses high-speed storage devices such as DRAM (Dynamic Random-Access Memory) and SRAM (Static Random-Access Memory) to improve the read and write performance of the storage controller and reduce latency.

[0073] The storage controller 106 is configured to receive commands from the host 108 and send commands to the storage device 104 , and to perform or implement a plurality of functions and operations provided in the present disclosure, which will be described below.

[0074] Figure 1E FIG. 1 is a schematic diagram of an exemplary memory device including a memory cell array and a peripheral circuit according to an embodiment of the present disclosure. Figure 1E As shown, the memory device 104 may include a memory cell array 501 and peripheral circuits coupled to the memory cell array 501. The peripheral circuits may include: a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, the peripheral circuits may also include: a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface 516, and a data bus 518. Figure 1E Additional peripheral circuits not shown.

[0075] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 501 and program (write) data to the memory cell array 501 according to the control signal from the control logic unit 512. In one example, the page buffer / sense amplifier 504 can store a page of programming data (write data) to be programmed into the memory cell array 501. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cells of the selected word line. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from a bit line representing a data bit stored in a memory cell and amplify a small voltage swing to a recognizable logic level in a read operation.

[0076] Column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and select one or more NAND memory strings by applying a bit line voltage generated from voltage generator 510. Data input from data bus 518 is directed (routed) to a desired memory cell region (e.g., bank) of memory cell array 501, and data output from the desired memory cell region is directed (routed) to data bus 518.

[0077] Row decoder / word line driver 508 can be configured to be controlled by control logic 512 and the selected block of memory cell array 501 and the word lines of the selected block. Row decoder / word line driver 508 can be further configured to drive the selected word lines using a word line voltage generated from voltage generator 510. Voltage generator 510 can be configured to be controlled by control logic 512 and generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, and verify voltages) supplied to memory cell array 501.

[0078] Control logic 512 can be coupled to each of the above-mentioned peripheral circuits and configured to control the operation of each peripheral circuit. Registers 514 can be coupled to control logic 512 and include status registers, command registers, and address registers for storing status information, command operation codes, and command addresses used to control the operation of each peripheral circuit. Interface 516 can be coupled to control logic 512 and act as a control buffer to buffer and relay control commands received from a host to control logic 512 and buffer and relay status information received from control logic 512 to the host. Interface 516 can also be coupled to column decoder / bit line driver 506 via data bus 518 and act as a data interface and data buffer to buffer and relay write data received from a host (not shown) to memory cell array 501 or relay or buffer data from memory cell array 501.

[0079] Figure 1F An exemplary storage device architecture for a memory system is provided for an embodiment of the present disclosure. As shown, a memory system 102 has one or more storage devices 104 and a storage controller 106. Figure 1F The storage controller 106 is coupled to the one or more storage devices 104 through a plurality of physical channels (Channels) to send control commands or transfer data with the storage devices 104. The storage device 104 includes one or more dies (also referred to as LUNs). The die is a basic storage unit in the storage device 104. One or more dies are connected on each physical channel. Each die corresponds to a corresponding chip enable (CE) signal.

[0080] The storage controller 106 is coupled to the one or more storage devices 104 through a plurality of physical channels (Channels) to send control commands or transfer data with the storage devices 104. The storage device 104 includes one or more dies (also referred to as LUNs). The die is a basic storage unit in the storage device 104. One or more dies are connected on each physical channel. Each die corresponds to a corresponding chip enable (CE) signal.

[0081] The control command sent by the storage controller 106 to the storage device 104 includes the enable signal, and the corresponding logical unit in the physical channel is selected through the enable signal, that is, the target logical unit of the control command is selected.

[0082] Figure 2 FIG. 1 is a flow chart of a method for controlling a memory system according to an embodiment of the present disclosure. Figure 2 As shown, the control method of the memory system provided in the embodiment of the present disclosure can be applied to Figure 1A 、 1B Or the storage controller shown in 1C.

[0083] The control method of an embodiment of the present disclosure may include S210. In S210, a first command segment of a first command is sent; the first command includes a first command segment and a second command segment; and an idle time is set between the first command segment and the second command segment.

[0084] exist Figure 1A In the memory system shown, the storage controller 106 and the storage device 104 are connected via a bus. The bus is responsible for transmitting control commands, address information, and read and write data between the storage controller and the storage device. The transmission process of control commands on the bus needs to comply with relevant industry protocols, such as the ONFI (Open NAND Flash Interface) protocol. The ONFI protocol was developed by the ONFI working group and is used to define the communication interface specifications between the storage device and the storage controller. In the ONFI protocol, control commands are implemented by combining basic instructions such as address latch instructions, command latch instructions, data input instructions, and data output instructions. Among them, the address latch instruction is used to send the row address and / or column address of the storage unit to be operated to the storage device; the command latch instruction is used to send the command code of the operation instruction to the storage device; the data input instruction and the data output instruction are used to transmit the data stream input or output to the storage device.

[0085] According to the ONFI protocol, a command consists of a first command phase (NAND CMD Phase) and a second command phase. The first and second command phases are each a continuous command instruction and require bus transmission resources. In the disclosed embodiment, the first command phase of the first command is sent first. The idle time specified by the ONFI protocol must be separated by the first and second command phases. Only when the timing specifications for address transmission, command transmission, and data transmission required by the ONFI protocol are met can a series of command operations such as reading data, programming data, and erasing data on a storage device be performed.

[0086] In an exemplary embodiment,Figure 7A FIG. 1 is an exemplary timing diagram of a command according to an embodiment of the present disclosure. Figure 7A As shown, in this command sequence, the command code 06h and the command code E0h of the command latch instruction are transmitted to the storage device. The command code 06h represents that the command is a change read column address (Change Read Column) command. Between the command codes 06h and E0h, the transmission address latch instruction includes column addresses C1, C2 and row addresses R1, R2, R3, R4, which are used to represent the storage unit addresses to be operated. According to the ONFI protocol, after the command latch instruction and the address latch instruction are transmitted, the data output timing must be executed after a specified time interval. The interval time varies depending on the command type. For the change read column address command, the ONFI protocol stipulates that the required interval is the column address change time tCCS (Change Column Setup time). In this example, the column address change time tCCS is specified to be 300ns. As Figure 7A As shown, after the column address change time tCCS, the data output instruction, including data D1, D2, D3, and D4, is sequentially output in this command sequence. The command latch instruction and address latch instruction constitute the first command segment of the command, while the data output instruction constitutes the second command segment. The column address change time tCCS, the required interval between the first and second command segments as specified by the ONFI protocol, is the idle time of the command. The time required to send the command, including the first and second command segments and the idle time, is the command occupied time.

[0087] In an exemplary embodiment, Figure 7B FIG. 1 is an exemplary timing diagram of a command according to another embodiment of the present disclosure. Figure 7B As shown, in this command sequence, the command code 70h of the command latch instruction is transmitted to the storage device. The command code 70h indicates that the command is a status read command. According to the ONFI protocol, after the command latch instruction is transmitted, the write hold recovery time tWHR (Write Hold Recovery time) must be exceeded before the data output timing can be executed. In this example, the write hold recovery time tWHR is specified to be 80ns. Figure 7BAs shown, after the write hold recovery time tWHR, the data output instruction in the command timing includes a data SR output. The first command segment of the command is constituted by the command latch instruction, and the second command segment of the command is constituted by the data output instruction. The write hold recovery time tWHR based on the necessary interval time specified in the ONFI protocol is the idle time of the command between the first command segment and the second command segment. The time required for sending the command, including the first command segment, the second command segment, and the idle time, is the command occupation time.

[0088] It can be seen that according to the ONFI protocol, the command must be separated by a predetermined idle time between the first command segment and the second command segment. However, according to the different types of commands, the idle time and the length of the command occupation time corresponding to the command are also different.

[0089] The control method of an embodiment of the present disclosure can include S220, in which a second command is sent in the idle time of the first command.

[0090] In the embodiment of the present disclosure, the second command is sent in the idle time of the first command. As described above, according to the ONFI protocol, the idle time must be separated between the first command segment and the second command segment. This part of the idle time is the waiting time of the second command segment, and does not occupy the bus to send command instructions during this period, causing waste of bus resources and affecting the efficiency of transmitting commands on the bus. Therefore, the embodiment of the present disclosure uses the idle time of the first command to send the second command to improve the utilization rate of bus resources.

[0091] In the embodiment of the present disclosure, the command occupation time corresponding to the second command is less than the idle time of the first command, to ensure that the transmission of the second command is completed before the transmission of the second command segment of the first command. In this way, the normal sending of the first command can not be affected. At the same time, the command instructions adjacent between the first command and the second command should leave time for the power level to recover, so the command occupation time of the second command should be less than the idle time of the first command.

[0092] In the exemplary embodiment, the first command is Figure 7A The second command is Figure 7BThe status read command is shown. As described above, the idle time of the column address change command is changed to the column address change time tCCS, i.e., 300 ns. The command occupation time of the second command includes the command latch instruction transmission time, the hold recovery time tWHR, and the data output instruction transmission time, i.e., slightly greater than 80 ns. It can be seen that the command occupation time of the second command is less than the idle time of the first command, and the second command can be sent within the column address change time tCCS of the idle time of the first command.

[0093] The control method of one embodiment of the present disclosure can include S230, in S230, the idle time of the first command ends, and the second command segment of the first command is sent.

[0094] In the embodiment of the present disclosure, the second command sent in the idle time of the first command in S220 does not affect the sending of the first command. Therefore, according to the ONFI protocol, after the idle time of the first command ends, the second command segment of the first command is sent to complete the transmission of the first command.

[0095] The control method provided by the embodiment of the present disclosure sends the first command segment of the first command; in the idle time of the first command, the second command is sent; and when the idle time of the first command ends, the second command segment of the first command is sent. The method uses the idle time between the first command segment and the second command segment of the first command to send the second command, which improves the transmission efficiency of the bus while ensuring the normal transmission of the first command.

[0096] In the control method of one embodiment of the present disclosure, the second command can be determined based on a comparison of the command occupation time of the to-be-sent command and the idle time of the first command.

[0097] Figure 3 A flowchart of a second command determination method of one embodiment of the present disclosure is shown. As shown in the figure, the second command determination method can include the following steps. It can be applied to Figure 1A The storage controller shown.

[0098] The control method of one embodiment of the present disclosure can include S310, in S310, the first to-be-sent command is obtained.

[0099] In the embodiment of the present disclosure, after the storage controller receives the data read / write request sent by the host, the corresponding command facing the storage device is generated, and the to-be-sent command pool is collected according to a certain processing rule. The storage controller arranges the transmission order of the command according to the preset timing, priority, and bus utilization rate and other factors.

[0100] In the embodiment of the present disclosure, when it is needed to insert the sending of the second command in the idle time of the first command as in the foregoing S220, a first to-be-sent command is obtained from the pool of to-be-sent commands to determine whether the first to-be-sent command can be sent as the second command in the idle time of the first command. The first to-be-sent command can be any command in the pool of commands.

[0101] The control method of one embodiment of the present disclosure can include S320, in which it is determined whether the command occupation time of the first to-be-sent command is less than a first time threshold; the first time threshold is less than or equal to the idle time of the first command.

[0102] In the embodiment of the present disclosure, the command occupation time of the first to-be-sent command is determined according to the command type of the first to-be-sent command. Since the command instruction transmission time in the command is short, an experienced time length can be added to the idle time of the command as an estimated value of the command occupation time.

[0103] In the embodiment of the present disclosure, it is determined whether the command occupation time of the first to-be-sent command is less than a first time threshold. The first time threshold can be the idle time of the first command, or a time threshold less than the idle time of the first command, to ensure that there should be time for power level recovery between the command instructions adjacent to the first command and the second command.

[0104] The control method of one embodiment of the present disclosure can include S330, in which, in response to the command occupation time of the first to-be-sent command being less than the first time threshold, the first to-be-sent command is determined as the second command.

[0105] In the embodiment of the present disclosure, in response to the command occupation time of the first to-be-sent command being less than the first time threshold, the first to-be-sent command is determined as the foregoing second command. Since the command occupation time of the first to-be-sent command is less than the idle time of the first command, sending the first to-be-sent command in the idle time of the first command does not affect the sending of the first command. Based on this, the first to-be-sent command can be the second command of the first command, and the sending of the command is completed in the idle time of the first command.

[0106] In the control method of the embodiment of the present disclosure, the second command can be determined based on the type of the to-be-sent command. Specifically, the second command is a status read command. When the second command needs to be inserted and sent in the idle time of the first command as in S220 described above, a to-be-sent command of the type of status read command is obtained from the pool of to-be-sent commands as the second command. The second command is determined by the type of the to-be-sent command, which can save the process of comparing the command occupation time of the to-be-sent command with the idle time of the first command, and can more efficiently perform the insertion operation of the second command. The reason for selecting the status read command as the second command is that the command occupation time of the status read command is relatively short, which can be suitable for the insertion and transmission operation in the idle time of multiple commands. At the same time, the status read command has a high probability of use in the memory system, and has more applicable insertion and transmission scenarios, which is beneficial to improve the overall transmission efficiency of the bus. In addition, the status read command has simple logic and is not prone to nesting problems.

[0107] The control method provided by the embodiment of the present disclosure can determine the second command by comparing the command occupation time of the to-be-sent command with the idle time of the first command, or by the type of the to-be-sent command. For different application scenarios, multiple embodiments of determining the second command are provided. Through the above method, the appropriate second command can be selected for transmission in the idle time of the first command. While ensuring the normal transmission of the first command, the overall transmission efficiency of the bus is improved.

[0108] In the control method of the embodiment of the present disclosure, multiple commands can be inserted and transmitted in the idle time of the first command to make full use of the idle time period and improve the transmission efficiency of the bus. Specifically, the method can include the following steps.

[0109] In the idle time of the first command, a third command is sent; and the sum of the command occupation times of the second command and the third command is less than the idle time of the first command.

[0110] In the embodiment of the present disclosure, a third command can also be inserted and transmitted in the idle time of the first command. The sum of the command occupation times of the second command and the third command is less than the idle time of the first command. Thus, the transmission of the second command and the third command is ensured to be completed before the transmission of the second command segment of the first command. In this way, the normal sending of the first command can not be affected.

[0111] It should be noted that the third command can be a command of the same type as the second command, or a command of a different type. At the same time, the "second" and "third" are only labels for different commands, and do not represent the transmission timing of the related commands.

[0112] In addition, the above embodiments do not limit the two commands of the second and third commands to be inserted and transmitted in the idle time of the first command. A plurality of commands can be inserted and transmitted in the idle time of the first command. It is only required to ensure that the sum of the command occupation time of the inserted plurality of commands is less than the idle time of the first command.

[0113] The control method provided by the embodiments of the present disclosure can transmit a plurality of commands in the idle time of the first command, so that the bus resources in the idle time are fully utilized, and the transmission efficiency of the bus is further improved.

[0114] Figure 4 A flowchart of the idle time timing process of an embodiment of the present disclosure is shown. As shown in the figure, the sending of the second command in the idle time of the first command can include the following steps. The method can be applied to Figure 1A the storage controller shown.

[0115] The control method of an embodiment of the present disclosure can include S410, in which the timing is started when the sending of the first command segment of the first command is completed.

[0116] In the embodiment of the present disclosure, when the sending of the first command segment of the first command is completed, the timing is started according to the ONFI protocol to time the length of the idle time required for the interval.

[0117] The control method of an embodiment of the present disclosure can include S420, in which the second command is sent during the timing.

[0118] In the embodiment of the present disclosure, during the timing of the S410, it is determined whether the second command needs to be inserted and transmitted in the idle time according to the type of the first command or the length of the idle time. When it is determined that the second command needs to be inserted and transmitted in the idle time of the first command, the second command is selected from the pool of to-be-sent commands and sent during the timing. The selection scheme of the second command can be selected according to any scheme given in the above embodiments, which will not be described here.

[0119] In the exemplary embodiment, after the sending of the second command is completed, a third command can be further selected from the pool of to-be-sent commands according to the remaining time of the timing, and the third command is sent in the remaining time. As described in the foregoing embodiments, the sum of the command occupation time corresponding to the second and third commands is less than the idle time of the first command.

[0120] The control method of an embodiment of the present disclosure can include S430, in which the second command segment of the first command is sent when the timing time reaches the idle time of the first command.

[0121] In the embodiment of the present disclosure, according to the ONFI protocol, the second command segment of the first command is sent in the idle time from the timing of the S410 to the first command, so as to complete the transmission of the first command.

[0122] In the control method of the embodiment of the present disclosure, the first command can be determined based on the length of the idle time of the to-be-sent command.

[0123] Figure 5 A flowchart of the first command determination method of the embodiment of the present disclosure is shown. As shown in the figure, the first command determination method can include the following steps. The method can be applied to Figure 1A the storage controller shown.

[0124] The control method of the embodiment of the present disclosure can include S510, in which a second to-be-sent command is obtained.

[0125] As described above, the storage controller collects the commands generated for the storage device into a to-be-sent command pool, and arranges the transmission order of the commands according to the preset timing, priority, bus utilization rate and other factors.

[0126] In the embodiment of the present disclosure, the storage controller obtains a second to-be-sent command from the to-be-sent command pool, and transmits the second to-be-sent command using the bus. The second to-be-sent command can be any command in the command pool.

[0127] The control method of the embodiment of the present disclosure can include S520, in which it is determined whether the idle time of the second to-be-sent command is greater than a second time threshold.

[0128] In the embodiment of the present disclosure, the length of the idle time of the second to-be-sent command is determined according to the type of the second to-be-sent command. Then, it is determined whether the idle time of the second to-be-sent command is greater than a second time threshold. The second time threshold is a time threshold set according to the actual product demand of the storage controller.

[0129] In the exemplary embodiment, the second time threshold is set to 100 ns.

[0130] The control method of the embodiment of the present disclosure can include S530, in which, in response to the idle time of the second to-be-sent command being greater than the second time threshold, the second to-be-sent command is determined as the first command.

[0131] In the embodiments of the present disclosure, in response to the idle time of the second to-be-sent command being greater than the second time threshold, the second to-be-sent command is determined as the first command. Since the idle time of the second to-be-sent command is greater than the second time threshold, other commands can be inserted for transmission using the idle time without affecting the transmission of the second to-be-sent command. Based on this, after the second to-be-sent command is determined as the first command, the corresponding second command is selected from the to-be-sent command pool according to any of the foregoing embodiments.

[0132] In the control method of an embodiment of the present disclosure, the first command can be determined based on the idle time of the to-be-sent command. Specifically, the idle time of the first command includes a column address change time tCCS. According to the ONFI protocol, the idle time of a command of a plurality of command types needs to include the column address change time tCCS, such as a change read column address command, a change write column address command (Change Write Column), and the like. Since the column address change time tCCS is relatively long, usually more than 200 ns, other commands can be inserted for transmission in this time. Based on this, whether the idle time of the to-be-sent command includes the column address change time tCCS can be determined according to the command type of the to-be-sent command, and then the to-be-sent command is determined as the first command. By determining the first command through the command type of the to-be-sent command, the process of comparing the idle time of the to-be-sent command with the second time threshold can be saved, and the determination of the first command that can be inserted for command can be more efficient.

[0133] The control method provided by the embodiments of the present disclosure can determine the first command based on the length of the idle time of the to-be-sent command, or through the command type of the to-be-sent command. For different application scenarios, a plurality of implementation schemes for determining the first command are provided. Through the foregoing method, a suitable to-be-sent command can be selected as the first command, and other commands can be transmitted using the idle time of the first command, thereby improving the overall transmission efficiency of the bus.

[0134] In the control method of an embodiment of the present disclosure, the first command corresponds to a first enable (Chip Enable, CE), and the second command corresponds to a second enable. The first enable and the second enable are different enables.

[0135] In a memory system, a plurality of memory chips are usually included in a memory device. A memory controller includes an enable signal in a control command sent to the memory device, by which a corresponding logical unit is gated, i.e. a target logical unit of the control command is selected. Based on this, the first command corresponds to a first enable, and the first target logical unit corresponding to the first command is determined. Since the second command is inserted and transmitted in the idle time of the first command, i.e. during the execution of the first command. Therefore, the second command should correspond to a second enable different from the first enable, i.e. a second target logical unit different from the first target logical unit, so as not to cause interference in the execution of the command.

[0136] In an exemplary embodiment, the first enable and the second enable corresponding to the first command and the second command correspond to different memory chips, respectively. The different memory chips are located in the same physical channel. In a memory system, a physical channel is usually a group of parallel data lines. Different memory chips located in the physical channel are gated by different enables on the physical channel.

[0137] Figure 6 A flowchart of a command sending process of an embodiment of the present disclosure is shown. As shown, the control method of the memory system provided in the embodiment of the present disclosure can include the following steps. It can be applied to Figure 1A The memory controller shown.

[0138] In S610, a to-be-sent command is obtained.

[0139] In the embodiment of the present disclosure, the memory controller obtains the to-be-sent command from a command pool to be sent, and transmits the to-be-sent command by using a bus. The to-be-sent command can be any command in the command pool.

[0140] In S620, a first command segment of the to-be-sent command is sent.

[0141] In the embodiment of the present disclosure, according to the ONFI protocol, the first command segment of the to-be-sent command is sent first.

[0142] In S630, it is determined whether the to-be-sent command is a first command.

[0143] In the embodiment of the present disclosure, it is determined whether the to-be-sent command is a first command according to the technical solution introduced in the foregoing embodiment, i.e. whether other commands can be inserted in the idle time of the to-be-sent command.

[0144] If the to-be-sent command is a first command, step S640 is performed.

[0145] If the to-be-sent command is not a first command, step S660 is performed.

[0146] In S640, in response to the to-be-sent command being the first command, it is determined whether there is a second command to be sent.

[0147] In the embodiment of the present disclosure, in response to the to-be-sent command being the first command, it is further determined whether there is a second command to be sent in the to-be-sent command pool. The determination method of the second command can be through the technical solutions introduced in the foregoing embodiments, which will not be repeated here.

[0148] If there is a second command to be sent in the to-be-sent command pool, step S650 is performed.

[0149] If there is no second command to be sent in the to-be-sent command pool, step S660 is performed.

[0150] In S650, in response to there being a second command to be sent, the second command is sent.

[0151] In the embodiment of the present disclosure, if there is a second command to be sent in the to-be-sent command pool, the second command is sent in the idle time of the first command.

[0152] In S660, the idle time of the to-be-sent command ends.

[0153] In the embodiment of the present disclosure, whether or not a second command is sent in the idle time of the to-be-sent command, when the idle time of the to-be-sent command ends, step S670 is performed.

[0154] In S670, the second command segment of the to-be-sent command is sent.

[0155] In the embodiment of the present disclosure, according to the ONFI protocol, when the idle time of the to-be-sent command ends, the second command segment of the to-be-sent command is sent.

[0156] Based on the same inventive concept, the embodiment of the present disclosure also provides a memory system, as described in the following embodiments. Since the principle of solving problems of the memory system embodiment is similar to that of the above-mentioned garbage collection method embodiment, the implementation of the memory system embodiment can be referred to the implementation of the above-mentioned method embodiment, and the repeated parts will not be repeated.

[0157] Figure 1A FIG. 1 is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure. The memory system 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage. Referring to FIG. 1, the memory system 100 includes a memory controller 110, a memory 120, and a bus 130. Figure 1AAs shown, the memory system 100 includes one or more storage devices 104 as in the above embodiments; and a storage controller 106 coupled to the storage device 104, wherein the storage controller 106 is configured to:

[0158] sending a first command segment of a first command; the first command includes the first command segment and a second command segment; an idle time is set between the first command segment and the second command segment;

[0159] sending a second command in the idle time of the first command;

[0160] ending the idle time of the first command, and sending the second command segment of the first command.

[0161] In an embodiment of the present disclosure, the storage controller 106 is further configured to: the command occupation time corresponding to the second command is less than the idle time of the first command.

[0162] In an embodiment of the present disclosure, the storage controller 106 is further configured to: acquire a first to-be-sent command; determine whether the command occupation time of the first to-be-sent command is less than a first time threshold; the first time threshold is less than or equal to the idle time of the first command; in response to the command occupation time of the first to-be-sent command being less than the first time threshold, determine that the first to-be-sent command is the second command.

[0163] In an embodiment of the present disclosure, the second command is a state reading command.

[0164] In an embodiment of the present disclosure, the storage controller 106 is further configured to: send a third command in the idle time of the first command; the sum of the command occupation times corresponding to the second command and the third command is less than the idle time of the first command.

[0165] In an embodiment of the present disclosure, the storage controller 106 is further configured to: start timing when the first command segment of the first command is sent; send the second command in the process of the timing; and send the second command segment of the first command when the timing time reaches the idle time of the first command.

[0166] In an embodiment of the present disclosure, the storage controller 106 is further configured to: acquire a second to-be-sent command; determine whether the idle time of the second to-be-sent command is greater than a second time threshold; in response to the idle time of the second to-be-sent command being greater than the second time threshold, determine that the second to-be-sent command is the first command.

[0167] In embodiments of the present disclosure, the storage controller 106 is further configured to: the idle time of the first command comprises a column address change time of the first command.

[0168] In embodiments of the present disclosure, the storage controller 106 is further configured to: the first command corresponds to a first enable; and the second command corresponds to a second enable.

[0169] In embodiments of the present disclosure, the storage controller 106 is further configured to: the first enable and the second enable correspond to storage chips located on a same physical channel, respectively.

[0170] Based on the same inventive concept, embodiments of the present disclosure also provide a storage controller, as described in the following embodiments. Since the principle of the storage controller embodiments to solve the problem is similar to the above-mentioned garbage collection method embodiments, the implementation of the storage controller embodiments can be referred to the implementation of the above-mentioned method embodiments, and the repeated parts will not be described here.

[0171] Figure 1A A schematic diagram of an exemplary system having a memory system is shown for an embodiment of the present disclosure. Referring to Figure 1A The memory system 100, as shown, includes one or more storage devices 104 as in the above embodiments; and a storage controller 106 coupled to the storage devices 104. The storage controller 106 includes a controller memory configured to store control instructions; and a controller processor coupled to the controller memory and configured to execute the control instructions to perform a process, the process including:

[0172] sending a first command segment of a first command; the first command includes a first command segment and a second command segment; an idle time is provided between the first command segment and the second command segment;

[0173] sending a second command in the idle time of the first command;

[0174] ending the idle time of the first command, and sending the second command segment of the first command.

[0175] In embodiments of the present disclosure, the process further includes: a command occupation time corresponding to the second command is less than the idle time of the first command.

[0176] In embodiments of the present disclosure, the process further includes: obtaining a first to-be-sent command; determining whether a command occupation time of the first to-be-sent command is less than a first time threshold; the first time threshold is less than or equal to the idle time of the first command; in response to the command occupation time of the first to-be-sent command being less than the first time threshold, determining that the first to-be-sent command is the second command.

[0177] In an embodiment of the present disclosure, the second command is a status read command.

[0178] In an embodiment of the present disclosure, the processing further comprises: sending a third command in the idle time of the first command; and a sum of command occupation times corresponding to the second command and the third command is less than the idle time of the first command.

[0179] In an embodiment of the present disclosure, the processing further comprises: starting timing when the sending of the first command segment of the first command is completed; sending the second command during the timing; and sending the second command segment of the first command when the timing reaches the idle time of the first command.

[0180] In an embodiment of the present disclosure, the processing further comprises: obtaining a second to-be-sent command; determining whether an idle time of the second to-be-sent command is greater than a second time threshold; and in response to the idle time of the second to-be-sent command being greater than the second time threshold, determining that the second to-be-sent command is the first command.

[0181] In an embodiment of the present disclosure, the processing further comprises: the idle time of the first command comprises a column address change time of the first command.

[0182] In an embodiment of the present disclosure, the processing further comprises: the first command corresponds to a first enable; and the second command corresponds to a second enable.

[0183] In an embodiment of the present disclosure, the processing further comprises: the first enable and the second enable correspond to storage chips located on the same physical channel, respectively.

[0184] In an exemplary embodiment, a computer readable storage medium including instructions, such as a controller memory including instructions, is also provided, and the above-mentioned method can be executed by a controller processor of a storage controller to complete the above-mentioned method. Optionally, the computer readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like.

[0185] In an exemplary embodiment, a computer program product is also provided, including a computer program / instruction, and the computer program / instruction is executed by a processor to implement the method in the above-mentioned embodiments.

[0186] It should be understood that, throughout the specification, "some embodiments" means that a specific feature, structure, or characteristic described is included in at least one embodiment of the disclosure. Therefore, "in some embodiments" or "in other embodiments" appearing in various places throughout the specification are not necessarily all referring to the same embodiments. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the magnitude of the sequence of processes described above does not mean the order of execution, and the execution order of the processes should be determined according to their functions and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the disclosure. The sequence numbers of the above embodiments of the disclosure are only for description, and do not represent the advantages or disadvantages of the embodiments.

[0187] It should be noted that, in this document, the terms "comprising", "containing", or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device that includes a list of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent in such a process, method, article, or device. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or device that includes the element.

[0188] In several embodiments provided by the disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The above-described device embodiments are only illustrative, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed components can be through some interface, indirect coupling or communication connection between devices or units, which can be electrical, mechanical or other forms.

[0189] The units described above as separate components can or can not be physically separated, and the components shown as units can or can not be physical units; they can be located in one place or distributed on multiple network units; some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0190] In addition, each functional unit in each embodiment of the disclosure can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be realized in the form of hardware or hardware plus software functional unit.

[0191] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A memory system, comprising: a storage device; the storage device comprises a storage chip; and a storage controller coupled to the storage device, wherein the storage controller is configured to: send a first command segment of a first command; the first command comprises the first command segment and a second command segment; a free time is provided between the first command segment and the second command segment; send a second command within the free time of the first command; the free time of the first command ends, send the second command segment of the first command.

2. The memory system of claim 1, wherein, the storage controller is further configured to: a command occupation time corresponding to the second command is less than the free time of the first command.

3. The memory system of claim 1, wherein, the storage controller is further configured to: obtain a first to-be-sent command; determine whether a command occupation time of the first to-be-sent command is less than a first time threshold; the first time threshold is less than or equal to the free time of the first command; in response to the command occupation time of the first to-be-sent command being less than the first time threshold, determine that the first to-be-sent command is the second command.

4. The memory system of claim 1, wherein, the second command is a status read command.

5. The memory system of claim 1, wherein, the storage controller is further configured to: send a third command within the free time of the first command; a sum of command occupation times corresponding to the second command and the third command is less than the free time of the first command.

6. The memory system of claim 1, wherein, the storage controller is further configured to: start timing when the first command segment of the first command is sent; send the second command in the process of the timing; when the timing time reaches the free time of the first command, send the second command segment of the first command.

7. The memory system of claim 1, wherein, the storage controller is further configured to: obtain a second to-be-sent command; determine whether a free time of the second to-be-sent command is greater than a second time threshold; in response to the free time of the second to-be-sent command being greater than the second time threshold, determine that the second to-be-sent command is the first command.

8. The memory system of claim 1, wherein, the storage controller is further configured to: the free time of the first command comprises a column address change time of the first command.

9. The memory system of claim 1, wherein, the storage controller is further configured to: the first command corresponds to a first enable; the second command corresponds to a second enable.

10. The memory system of claim 9, wherein, the storage controller is further configured to: the first enable and the second enable correspond to storage chips located on the same physical channel, respectively.

11. A storage controller comprising: a controller memory configured to store control instructions; and a controller processor coupled to the controller memory and configured to execute the control instructions to perform a process, the process comprising: sending a first command segment of a first command; the first command comprises the first command segment and a second command segment; a free time is provided between the first command segment and the second command segment; sending a second command within the free time of the first command; the free time of the first command ends, send the second command segment of the first command.

12. The storage controller of claim 11, wherein, the process further comprises: a command occupation time corresponding to the second command is less than the free time of the first command.

13. The storage controller of claim 12, wherein, the process further comprises: obtaining a first to-be-sent command; determining whether a command occupation time of the first to-be-sent command is less than a first time threshold; the first time threshold is less than or equal to an idle time of the first command; in response to the command occupation time of the first to-be-sent command being less than the first time threshold, determining that the first to-be-sent command is the second command.

14. The storage controller of claim 11, wherein, the second command is a status read command.

15. The storage controller of claim 11, wherein, the processing further comprises: sending a third command within the idle time of the first command; a sum of command occupation times corresponding to the second command and the third command is less than the idle time of the first command.

16. The storage controller of claim 11, wherein, the processing further comprises: starting timing when the first command segment of the first command is sent completely; sending the second command in the process of the timing; sending the second command segment of the first command when a timing time reaches the idle time of the first command.

17. The storage controller of claim 11, wherein, the processing further comprises: obtaining a second to-be-sent command; determining whether an idle time of the second to-be-sent command is greater than a second time threshold; in response to the idle time of the second to-be-sent command being greater than the second time threshold, determining that the second to-be-sent command is the first command.

18. The storage controller of claim 11, wherein, the processing further comprises: the idle time of the first command comprises a column address change time of the first command.

19. The storage controller of claim 11, wherein, the processing further comprises: the first command corresponds to a first enable; and the second command corresponds to a second enable.

20. The storage controller of claim 19, wherein, the processing further comprises: the first enable and the second enable correspond to storage chips located on a same physical channel.

21. A control method of a memory system, characterized by, comprises: sending a first command segment of a first command; the first command comprises the first command segment and a second command segment; an idle time is provided between the first command segment and the second command segment; sending a second command within the idle time of the first command; sending the second command segment of the first command when the idle time of the first command ends.

22. The control method according to claim 21, characterized by, further comprises: a command occupation time corresponding to the second command is less than the idle time of the first command.

23. The control method according to claim 22, wherein further comprises: obtaining a first to-be-sent command; determining whether a command occupation time of the first to-be-sent command is less than a first time threshold; the first time threshold is less than or equal to an idle time of the first command; in response to the command occupation time of the first to-be-sent command being less than the first time threshold, determining that the first to-be-sent command is the second command.

24. The control method according to claim 21, wherein the second command is a status read command.

25. The control method according to claim 21, wherein sending a third command within the idle time of the first command; a sum of command occupation times corresponding to the second command and the third command is less than the idle time of the first command.

26. The control method according to claim 21, wherein the sending of the second command within the idle time of the first command comprises: starting timing when the first command segment of the first command is sent completely; sending the second command in the process of the timing; sending the second command segment of the first command when a timing time reaches the idle time of the first command.

27. The control method according to claim 21, wherein acquiring a second to-be-sent command; determining whether an idle time of the second to-be-sent command is greater than a second time threshold value; in response to the idle time of the second to-be-sent command being greater than the second time threshold value, determining that the second to-be-sent command is the first command.

28. The control method according to claim 21, wherein the idle time of the first command comprises a column address change time of the first command.

29. The control method according to claim 21, wherein the first command corresponds to a first enable; and the second command corresponds to a second enable.

30. The control method according to claim 29, wherein the first enable and the second enable correspond to storage chips located on the same physical channel, respectively.

31. A computer readable storage medium, when control instructions in the computer readable storage medium are executed by a controller processor, the controller processor is enabled to perform the control method according to any one of claims 21 to 30.

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