Chip simulation verification acceleration method and device, equipment and storage medium

Abstract

The invention relates to the technical field of integrated circuit design and verification, and discloses a chip simulation verification acceleration method, device and equipment and a storage medium, and the method comprises the steps: obtaining simulation analysis of a tested design file and excitation, obtaining a corresponding simulation result, analyzing a module occupying the most simulation time and memory according to the simulation result, and obtaining a simulation result; the method comprises the following steps of: decomposing a simulation process of a whole chip into a plurality of simulation operation tasks by combining a design requirement and a function definition of the chip; distributing the disassembled operation tasks to a multi-core processor for block simulation; and setting a dynamic performance optimization option DPO, performing multiple tests to collect data, and generating a simulation verification result based on a simulation result and an original design expectation. According to the method, the to-be-tested design is disassembled for layered compiling simulation, and the DPO is set for dynamic performance optimization, so that the simulation speed is increased, the chip design period is shortened, the development cost is reduced, and the requirement for rapid development of modern large-scale chips is met.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit design and verification, for example to a chip simulation verification acceleration method, device, equipment and storage medium. BACKGROUND

[0002] With the continuous evolution of advanced process nodes, the scale and design complexity of chips grow exponentially. Chip design needs a large amount of simulation test work to verify whether the functions and performances of the chip meet the requirements. However, as the scale of the chip becomes larger and larger, the traditional verification method cannot meet the design requirements of large-scale chips. On the one hand, for the verification of large-scale chips, it may take several hours or even several days, which greatly prolongs the design cycle of the chip and increases the research and development cost. On the other hand, the traditional simulation method has a high demand for simulation resources, which increases the verification cost.

[0003] Therefore, the existing chip simulation verification method has the problems of poor verification efficiency and accuracy.

[0004] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present application. SUMMARY

[0005] To have a basic understanding of some aspects of the disclosed embodiments, a brief overview is given below. The overview is not a comprehensive review of the embodiments, nor is it intended to determine key / important elements or delineate the scope of the embodiments, but to serve as a prelude to the detailed description below.

[0006] The chip simulation verification acceleration method, device, equipment and storage medium provided by the embodiments of the present disclosure solve the problems of poor verification efficiency and accuracy in the traditional chip simulation verification process.

[0007] The chip simulation verification acceleration method in the embodiments of the present disclosure comprises:

[0008] Obtain the simulation analysis of the design-under-test file and the stimulus, obtain the corresponding simulation result, analyze the module that occupies the most simulation time and memory according to the simulation result, combine the design requirements and function definition of the chip, and divide the simulation process of the entire chip into multiple simulation operation tasks;

[0009] Pre-compile the stable basic module, and compile the frequently modified design part in real time during simulation;

[0010] Distribute each operation task after disassembly to the multi-core processor for block simulation, and preferentially allocate memory resources to the module that occupies the most simulation time and memory;

[0011] The simulation is performed by using the EDA tool VCS, the dynamic performance optimization option DPO is set, data is collected through multiple tests, the optimal parameters are determined by DPO according to historical data and simulation statistical results, the optimization strategy is updated each time the test is run, and the design simulation rules are adjusted adaptively;

[0012] The simulation results are verified and compared with the original design expectations, the interface timing and function of the design are automatically compared, and the simulation verification results are generated.

[0013] In some embodiments, the simulation analysis of the measured design file and the excitation is obtained, the corresponding simulation results are obtained, the modules that occupy the most simulation time and memory are analyzed according to the simulation results, the simulation process of the entire chip is divided into multiple simulation operation tasks according to the design requirements and function definition of the chip, including:

[0014] The measured design file is imported into the EDA simulation environment, and the corresponding verification environment and excitation file are loaded to perform preliminary simulation running on the measured design, and in the simulation process, the running time and memory occupation data of each module are recorded in real time, so as to obtain the corresponding simulation results;

[0015] Based on the obtained simulation results, a preset sorting algorithm and analysis logic are used to sort and analyze the simulation time and memory occupation of each module, to identify the modules that occupy the most simulation time and memory, to comprehensively evaluate the resource occupation of each module by counting the number of signal flips and data processing complexity factors, and to determine the overall function architecture of the chip and the interaction relationship between modules according to the chip design requirement document and function definition.

[0016] According to the resource occupation analysis results of the modules and the function definition of the chip, the simulation process of the entire chip is divided, and the design is divided into multiple simulation operation tasks that are independent of each other and have clear function boundaries according to the function correlation and data flow direction principles.

[0017] In some embodiments, the above method further includes:

[0018] For a chip including a processor, a memory and a peripheral interface, the chip is divided into a processor module simulation task, a memory module simulation task and a peripheral interface module simulation task, and in the division process, the granularity of each task is ensured to ensure the efficiency of parallel simulation and facilitate subsequent management and verification.

[0019] In some embodiments, the above method further includes:

[0020] Each module in the chip design is evaluated, and the modules are classified according to their stability and modification frequency.

[0021] For stable modules, pre-compilation is performed before the simulation starts;

[0022] For frequently modified design parts, real-time compilation is performed during the simulation run;

[0023] During the compilation process, the code is optimized according to the specific situation at runtime, and incremental compilation technology is used to recompile only the modified parts.

[0024] In some embodiments, the above-mentioned allocation of each operation task after disassembly to the multi-core processor is performed in block simulation, and for the module that occupies the most simulation time and memory, memory resources are allocated preferentially, including:

[0025] The disassembled simulation operation tasks are allocated to different cores or multiple computing nodes of the multi-core processor for block simulation; during the allocation process, according to the module resource occupation obtained by the previous analysis, for the module that occupies the most simulation time and memory, more memory resources and computing cores are allocated preferentially to ensure that these key modules can run efficiently;

[0026] On the multi-core processor, each task performs simulation in parallel, in order to ensure the correct interaction and timing consistency between tasks, a preset communication and synchronization mechanism is used; a message queue is used to transfer data and control signals between tasks to ensure accurate data transmission; through a clock synchronization algorithm, the simulation clocks of each task are kept consistent to avoid timing chaos; the execution state of each task is monitored in real time, and when a task appears abnormal or resource competition, timely adjustment and intervention is performed;

[0027] After each task completes the simulation, the simulation results are collected, and the collected results are preliminarily processed and verified to ensure the accuracy and integrity of the results.

[0028] In some embodiments, the above-mentioned simulation using EDA tool VCS sets dynamic performance optimization option DPO, performs multiple tests to collect data, and DPO automatically determines the optimal parameters according to historical data and simulation statistical results, updates the optimization strategy each time the test is completed, and adjusts the design simulation rules adaptively, including:

[0029] During the simulation using the EDA tool VCS, the dynamic performance optimization function DPO is enabled through specific configuration options, and necessary computing resources and data storage space are allocated to DPO in the initialization stage, so that it can effectively collect and process simulation data;

[0030] The DPO runs multiple tests during the simulation process. During each test, it collects various simulation performance-related data in real time, including the execution time of each module, the number of memory accesses, and CPU utilization. The collected data is analyzed using statistical analysis methods and machine learning algorithms to uncover patterns and trends hidden in the data and identify key factors affecting simulation performance.

[0031] Based on the results of data analysis, DPO automatically determines the optimal simulation parameter settings. After adjusting the parameters, DPO continues simulation testing and compares the simulation speed before and after the adjustment to evaluate the effect of the parameter adjustment. If the speed is improved, the new parameter settings are retained. If the performance does not improve, DPO reanalyzes the data and tries other parameter combinations until the optimal parameter configuration is found.

[0032] In some embodiments, the verification and comparison of simulation results to see if they are consistent with the original design expectations, and the automatic comparison of the designed interface timing and functionality, include:

[0033] Integrate the simulation results of each module obtained by block simulation. According to the overall architecture of the chip design and the connection relationship between modules, combine the results of each part into a complete system-level simulation result to ensure data consistency and accuracy. Verify and convert the interface data between different modules to make it meet the overall requirements of the system.

[0034] Compare the integrated simulation results with the original design expectations to verify whether the chip design functions meet the requirements;

[0035] Compare the designed interface timing to check whether the signal transmission between each module meets the timing requirements; analyze the chip's clock signal, data signal, etc. to detect whether there are problems with setup time failure or hold time violation.

[0036] The chip simulation verification acceleration device in the embodiment of the present disclosure includes:

[0037] The chip design disassembly module is used to obtain the simulation analysis of the design files and stimuli under test, obtain the corresponding simulation results, analyze the modules that occupy the most simulation time and memory based on the simulation results, and decompose the entire chip simulation process into multiple simulation operation tasks based on the chip's design requirements and functional definition;

[0038] Hierarchical compilation module, used to precompile stable basic modules and perform real-time compilation of frequently modified design parts during simulation;

[0039] The block simulation module is used to assign the disassembled operation tasks to the multi-core processor for block simulation, and give priority to allocating memory resources to the modules that occupy the most simulation time and memory;

[0040] a dynamic performance optimization module, configured to simulate by using an EDA tool VCS, set a dynamic performance optimization option DPO, collect data by multiple tests, and determine optimal parameters according to historical data and simulation statistics, update optimization strategies and adaptively adjust design simulation rules after each test;

[0041] a result integration and verification module, configured to verify whether simulation results and original design expectations are consistent, automatically compare interface timing and functions of the design, and generate simulation verification results.

[0042] The electronic device provided in the embodiments of the present disclosure includes at least one processor;

[0043] and a memory in communication connection with the at least one processor;

[0044] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the chip simulation verification acceleration method.

[0045] The storage medium provided in the embodiments of the present disclosure stores program instructions, and the program instructions perform the chip simulation verification acceleration method when running.

[0046] The chip simulation verification acceleration method, device, equipment and storage medium provided in the embodiments of the present disclosure can achieve the following technical effects:

[0047] Compared with the traditional verification method, the chip simulation time can be greatly shortened by the block simulation and dynamic performance optimization, the highest speed can be accelerated by several times, the single running simulation efficiency and the regression simulation efficiency are significantly improved. The memory and computing resources are accurately allocated, the high-load module is preferentially ensured to run, the resource utilization rate is fully utilized, and the running cost is reduced. The fast simulation verification makes the chip design iteration more efficient, shortens the chip design cycle, accelerates the process from design to production, and occupies the market opportunity. The block verification and system-level double verification can find internal and interface timing problems in advance, automatically compare to ensure the consistency of the simulation results and the design expectations, and improve the reliability of the final delivery of the chip.

[0048] The general description above and the following description below are merely exemplary and explanatory, and are not intended to limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0049] One or more embodiments are exemplarily illustrated by corresponding drawings, which are not intended to limit the embodiments, elements with the same reference numerals in the drawings are shown as similar elements, the drawings do not constitute a proportional limit, and wherein:

[0050] Figure 1 is a flowchart of a chip simulation verification acceleration method provided by an embodiment of the present disclosure;

[0051] Figure 2 is a flowchart of another chip simulation verification acceleration method provided by an embodiment of the present disclosure;

[0052] Figure 3 is a structural diagram of a chip simulation verification acceleration device provided by an embodiment of the present disclosure;

[0053] Figure 4 is a structural diagram of a chip simulation verification acceleration device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0054] In order to enable a person skilled in the art to more fully understand the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, which are only used for reference and do not limit the embodiments of the present disclosure. In the following technical description, in order to facilitate explanation, a plurality of details are provided to provide a full understanding of the disclosed embodiments. However, one or more embodiments can still be implemented without these details. In other cases, well-known structures and devices can be simplified to facilitate the drawings.

[0055] The terms "first", "second", and the like in the embodiments of the present disclosure are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present disclosure described herein can be implemented. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion.

[0056] Unless otherwise specified, the term "a plurality of" means two or more.

[0057] In the embodiments of the present disclosure, the character " / " represents an "or" relationship between the objects before and after it. For example, A / B represents: A or B.

[0058] The term "and / or" is a description of the association between objects, which means that there can be three relationships. For example, A and / or B means: A or B, or, A and B, the three relationships.

[0059] The term "corresponding" can refer to an association or binding relationship. A and B correspond to each other means that there is an association or binding relationship between A and B.

[0060] The chip simulation verification acceleration method, device, equipment and storage medium provided by the embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0061] Figure 1is a flowchart of a chip simulation verification acceleration method provided by the embodiments of the present disclosure.

[0062] As shown in Figure 1 The chip simulation verification acceleration method can include the following steps.

[0063] S101, obtain the simulation analysis of the design-under-test file and the stimulus, obtain the corresponding simulation result, analyze the module that occupies the most simulation time and memory according to the simulation result, decompose the simulation process of the whole chip according to the design requirements and function definition of the chip, and divide the simulation process into multiple simulation operation tasks;

[0064] S102, pre-compile the stable basic module, and compile the frequently modified design part in real time during simulation;

[0065] S103, distribute each operation task after decomposition to the multi-core processor for block simulation, and preferentially allocate memory resources to the module that occupies the most simulation time and memory;

[0066] S104, simulate by using the EDA tool VCS, set the dynamic performance optimization option DPO, perform multiple tests to collect data, and determine the optimal parameters according to the historical data and simulation statistical result, update the optimization strategy each time the test is run, and adaptively adjust the design simulation rule;

[0067] S105, verify whether the simulation result is consistent with the original design expectation, automatically compare the interface timing and function of the design, and generate the simulation verification result.

[0068] In some embodiments, the above-mentioned obtaining the simulation analysis of the design-under-test file and the stimulus, obtaining the corresponding simulation result, analyzing the module that occupies the most simulation time and memory according to the simulation result, decomposing the simulation process of the whole chip according to the design requirements and function definition of the chip, and dividing the simulation process into multiple simulation operation tasks include the following steps.

[0069] Import the design-under-test file into the EDA simulation environment, load the corresponding verification environment and stimulus file, and perform preliminary simulation running on the design-under-test, record the running time and memory occupation data of each module in real time during the simulation process, and thus obtain the corresponding simulation result;

[0070] Based on the obtained simulation result, the simulation time and memory occupied by each module are sorted and analyzed by using a preset sorting algorithm and analysis logic, the module that occupies the most simulation time and memory is identified, the resource occupation of each module is comprehensively evaluated by counting the number of signal flips and the complexity factors of data processing, the function architecture of the chip and the interaction relationship between modules are determined according to the design requirement document and the function definition of the chip, and

[0071] According to the resource occupation analysis result of the module and the function definition of the chip, the simulation process of the whole chip is decomposed, and the design is divided into multiple simulation operation tasks which are independent and have clear function boundaries according to the function correlation and data flow direction principle.

[0072] In some embodiments, the above method can further include:

[0073] For a chip including a processor, a memory and a peripheral interface, the chip is divided into a processor module simulation task, a memory module simulation task and a peripheral interface module simulation task, and in the division process, the granularity of each task is ensured, which can ensure the efficiency of parallel simulation and facilitate subsequent management and verification.

[0074] In some embodiments, the above pre-compilation is performed for stable basic modules, and real-time compilation is performed for frequently modified design parts such as algorithm logic and control path during simulation, including:

[0075] Each module in the chip design is evaluated, and classified according to the stability and modification frequency of the module;

[0076] For stable modules, pre-compilation is performed before simulation starts;

[0077] For frequently modified design parts, real-time compilation is performed during simulation running;

[0078] During the compilation process, the code is optimized according to the specific situation at runtime, and the incremental compilation technology is adopted to recompile only the modified part.

[0079] In some embodiments, the above each operation task after disassembly is allocated to a multi-core processor for block simulation, and memory resources are preferentially allocated to modules that occupy the most simulation time and memory, including:

[0080] Each simulation operation task after disassembly is allocated to different cores or multiple computing nodes of a multi-core processor for block simulation; during the allocation process, according to the module resource occupation obtained by the previous analysis, for the modules that occupy the most simulation time and memory, more memory resources and computing cores are preferentially allocated to them to ensure that these key modules can run efficiently;

[0081] On the multi-core processor, each task simultaneously and in parallel performs simulation, in order to ensure the correct interaction and timing consistency between tasks, a preset communication and synchronization mechanism is adopted; a message queue is used to transmit data and control signals between tasks to ensure accurate data transmission; through a clock synchronization algorithm, the simulation clocks of each task are kept consistent to avoid timing confusion; the execution state of each task is monitored in real time, and when a task appears abnormal or competes for resources, timely adjustment and intervention is performed;

[0082] After each task is completed, the simulation results are collected and preliminary processing and verification are performed on the collected results to ensure the accuracy and integrity of the results.

[0083] In some embodiments, the above-mentioned simulation using EDA tool VCS sets dynamic performance optimization option DPO, collects data through multiple tests, and DPO automatically determines the optimal parameters based on historical data and simulation statistics. The optimization strategy is updated after each test run to adaptively adjust the design simulation rules, including:

[0084] In the simulation using EDA tool VCS, the dynamic performance optimization function DPO is enabled through specific configuration options. In the initialization stage, DPO is allocated necessary computing resources and data storage space to effectively collect and process simulation data;

[0085] DPO runs multiple tests during the simulation process. During each test, DPO collects various simulation performance-related data in real time, including execution time, memory access times, and CPU utilization of each module. Statistical analysis methods and machine learning algorithms are used to analyze the collected data, uncover hidden patterns and trends, and identify key factors affecting simulation performance;

[0086] Based on the results of data analysis, DPO automatically determines the optimal simulation parameter settings. After adjusting the parameters, DPO continues simulation testing and compares the simulation speed before and after adjustment to evaluate the effectiveness of parameter adjustment. If the speed improves, the new parameter settings are retained. If performance does not improve, DPO reanalyzes the data and tries other parameter combinations until the optimal parameter configuration is found.

[0087] In some embodiments, the above-mentioned verification compares whether the simulation results and the original design expectations are consistent, automatically compares the interface timing and functionality of the design, including:

[0088] The simulation results of each module obtained by block simulation are integrated. According to the overall architecture of the chip design and the connection relationship between modules, the results of each part are combined into a complete system-level simulation result to ensure data consistency and accuracy. Interface data between different modules is checked and converted to meet the overall requirements of the system;

[0089] The integrated simulation results are compared with the original design expectations to verify whether the functionality of the chip design meets the requirements;

[0090] The interface timing of the design is compared to check whether the signal transmission between modules meets the timing requirements. The clock signal, data signal, etc. of the chip are analyzed to detect whether there are problems such as setup time not met and hold time violation.

[0091] It can be seen that, for chip design disassembly, to obtain the design-under-test file and the simulation analysis of the stimulus, obtain the corresponding simulation result, analyze the module occupying the most simulation time and memory according to the simulation result, combine the design requirements and function definition of the chip, and divide the simulation process of the whole chip into multiple simulation operation tasks.

[0092] For the layered compilation strategy, the stable basic modules are pre-compiled, that is, static compilation, and the frequently modified design parts such as algorithm logic and control path are compiled in real time, that is, dynamic compilation.

[0093] For the block simulation strategy, each operation task after disassembly is allocated to a multi-core processor for block simulation, and the module occupying the most simulation time and memory is preferentially allocated memory resources.

[0094] For dynamic performance optimization, simulation is performed by using the EDA tool VCS, the dynamic performance optimization option DPO is set, DPO runs several tests to collect data, DPO automatically determines the optimal parameters according to historical data and simulation statistical results, updates the optimization strategy each time the test is run, and adaptively adjusts the design simulation rules.

[0095] For result integration and verification, the system-level verification compares whether the simulation result and the original design expectation are consistent, and automatically compares the interface timing and function of the design.

[0096] Figure 2 is a flowchart of another chip simulation verification acceleration method provided by the embodiment of the disclosure, which further describes the chip simulation verification acceleration method in Figure 2 . Figure 1 .

[0097] Specifically, 1. Chip design disassembly

[0098] (1) Import the design-under-test file into the EDA simulation environment, load the corresponding verification environment and stimulus file, and perform preliminary simulation running on the design-under-test. In the simulation process, the running time, memory occupation and other data of each module are recorded in real time, so as to obtain the corresponding simulation result.

[0099] (2) Module analysis: based on the obtained simulation result, a specific sorting algorithm and analysis logic are used to sort and analyze the simulation time and memory occupation of each module, and the module occupying the most simulation time and memory is identified. By counting the number of signal flips, data processing complexity and other factors in each module, the resource occupation is comprehensively evaluated. At the same time, combined with the design requirement document and function definition of the chip, the function architecture of the whole chip and the interaction relationship between modules are deeply understood.

[0100] (3) Task division: According to the resource occupation analysis results of the modules and the function definition of the chip, the entire chip simulation process is decomposed. According to the principles of functional correlation, data flow direction, etc., the design is divided into multiple simulation operation tasks that are independent of each other and have clear functional boundaries. For example, for a chip containing a processor, a memory and a peripheral interface, it can be divided into processor module simulation tasks, memory module simulation tasks and peripheral interface module simulation tasks, etc. In the division process, it is ensured that each task has a reasonable granularity, which can not only ensure the efficiency of parallel simulation, but also facilitate subsequent management and verification.

[0101] 2. Hierarchical compilation strategy

[0102] (1) Module classification: Each module in the chip design is evaluated, and classified according to the stability and modification frequency of the module. For those basic modules that are relatively stable throughout the design cycle and whose functions and structures do not change much, such as standard cell library, fixed function IP core, etc., they are classified as stable modules; while for algorithm logic, control path, etc. which may be frequently modified during the design process, they are classified as frequently modified modules.

[0103] (2) Static compilation (pre-compilation): For stable modules, pre-compilation, i.e. static compilation, is performed before simulation begins. The specific operation is to use the compilation function of the EDA tool to compile the code of the stable module into a binary file or intermediate code form that can be directly executed, and store it as a pre-compiled library. In the subsequent simulation process, the contents in the pre-compiled library are directly called without the need for re-compilation, thereby saving compilation time. For example, for a commonly used GPIO interface IP core, after it is compiled into a pre-compiled library, it can be quickly loaded during each simulation, avoiding the time consumption caused by repeated compilation.

[0104] (3) Dynamic compilation (real-time compilation): For frequently modified design parts, real-time compilation, i.e. dynamic compilation, is performed during simulation runtime. When the simulation execution reaches the code involving these modules, the EDA tool will compile them immediately. During the compilation process, the code can be optimized according to the specific situation at runtime, such as the type of data, the frequency of operation, etc. For example, for an image processing algorithm module, the optimal algorithm implementation method can be selected according to the size and format of the input image during dynamic compilation to improve simulation efficiency. At the same time, in order to further speed up the compilation, incremental compilation technology can be used to re-compile only the modified part, rather than performing full-amount compilation on the entire module every time.

[0105] 3. Block simulation

[0106] (1) Task allocation: After disassembling, each simulation operation task is allocated to different cores of multi-core processors or multiple computing nodes for block simulation. During the allocation process, according to the module resource occupation obtained by previous analysis, for the modules that occupy the most simulation time and memory, more memory resources and computing cores are allocated to them to ensure that these key modules can run efficiently. For example, for a complex neural network computing module, multiple CPU cores and larger memory space are allocated to ensure that it does not appear to be stuck or waiting due to insufficient resources during simulation.

[0107] (2) Parallel simulation execution: On a multi-core processor, each task is executed in parallel. In order to ensure the correct interaction and timing consistency between tasks, a specific communication and synchronization mechanism is used. Message queues are used to transfer data and control signals between tasks to ensure accurate data transmission; clock synchronization algorithms are used to ensure that the simulation clocks of each task remain consistent to avoid timing chaos. At the same time, the execution status of each task is monitored in real time, and when an exception or resource competition occurs in a task, it is adjusted and intervened in time, such as reallocating resources or pausing part of the task, to ensure the smooth progress of the entire simulation process.

[0108] (3) Simulation result collection: After each task completes simulation, its simulation results are collected in a timely manner. The collected results are preliminarily processed and verified to ensure the accuracy and integrity of the results. For example, check if there are data errors, signal abnormalities, etc. in the results. Then, integrate the simulation results of each task to form a simulation result set of the entire chip design, providing a data basis for subsequent result integration and verification.

[0109] 4. Dynamic performance optimization

[0110] (1) DPO setting and initialization: When using EDA tool VCS for simulation, enable dynamic performance optimization function DPO through specific configuration options. In the initialization phase, allocate necessary computing resources and data storage space for DPO so that it can effectively collect and process simulation data.

[0111] (2) Data collection and analysis (learn mode): Let DPO run several tests during simulation. During each test, DPO collects various simulation performance-related data in real time, including but not limited to execution time, memory access times, CPU utilization of each module, etc. Analyze the collected data in depth, use statistical analysis methods and machine learning algorithms to mine the hidden rules and trends in the data, and find out the key factors affecting simulation performance. For example, through analysis, it is found that the high memory access delay of a certain module is the main reason for the slow overall simulation speed.

[0112] (3) Parameter adjustment and optimization (apply mode): According to the results of data analysis, DPO automatically judges the optimal simulation parameter setting. For example, if it is found that increasing the number of threads can significantly improve the simulation speed, DPO will automatically adjust the thread number parameter of VCS. After adjusting the parameters, DPO continues to perform simulation testing and compares the simulation speed before and after adjustment to evaluate the effect of parameter adjustment. If the speed is improved, the new parameter setting is retained; if the performance is not improved or even decreased, DPO will re-analyze the data and try other parameter combinations until the optimal parameter configuration is found. After each test is completed, DPO updates the optimization strategy and incorporates new experiences and data into the subsequent optimization process, so that it can adaptively adjust the design simulation rules to continuously improve the simulation speed.

[0113] 5. Result integration and verification

[0114] (1) Result integration: The simulation results of each module obtained by the partitioned simulation are integrated, and the results of each part are combined into a complete system-level simulation result according to the overall architecture of the chip design and the connection relationship between the modules. In the integration process, the consistency and accuracy of the data are ensured, and the interface data between different modules are checked and converted to meet the overall requirements of the system. For example, for the data transmission results between the processor module and the memory module, the format, order and content of the data are checked to see if they match correctly.

[0115] (2) Functional verification: The integrated simulation results are compared with the original design expectations to verify whether the functions of the chip design meet the requirements. By writing specific test scripts and assertion statements, each function of the chip is checked one by one. For example, for a processor chip, the correctness of instruction execution and the accuracy of data processing are verified. If the simulation results do not match the design expectations, the modules and function points with problems are marked, and detailed error reports are generated to facilitate designers to debug and modify.

[0116] (3) Timing verification: Automatically compare the interface timing of the design to check whether the signal transmission between each module meets the timing requirements. Analyze the clock signals and data signals of the chip to detect whether there are problems such as setup time not met and hold time violation. For the timing problems found, detailed reports are also generated, and relevant timing waveforms are provided to help designers intuitively understand the problems and timely adjust and optimize the timing to ensure the reliability of the final delivery of the chip.

[0117] The chip simulation verification acceleration method provided by the embodiments of the present disclosure improves the simulation speed, shortens the chip design cycle and reduces the development cost by disassembling the design under test for hierarchical compilation simulation and setting DPO for dynamic performance optimization, to meet the needs of the rapid development of modern large-scale chips.

[0118] The present application at least includes the following benefits:

[0119] 1. Accelerate simulation efficiency: Compared with traditional verification methods, chip simulation time can be greatly shortened by block simulation and dynamic performance optimization, which can achieve several times acceleration, significantly improve single run simulation efficiency and regression simulation efficiency.

[0120] 2. Reduce resource consumption: Accurate allocation of memory and computing resources, priority protection of high load module operation, full use of resource utilization, and reduction of operation cost.

[0121] 3. Shorten the development cycle: Fast simulation verification makes chip design iteration more efficient, shortens the chip design cycle, accelerates the process from product design to production, and occupies the market opportunity.

[0122] 4. Improve verification quality: Block verification and system-level double verification can find internal and interface timing problems in advance, automatically compare to ensure the consistency of simulation results and design expectations, and improve the reliability of the final delivery of the chip.

[0123] With Figure 1 Corresponding to the chip simulation verification acceleration method, the present application also provides a chip simulation verification acceleration device, as shown in Figure 3 The device can specifically include:

[0124] The chip design disassembly module 301 is used to obtain simulation analysis of the design file to be tested and excitation, obtain the corresponding simulation result, analyze the module with the most simulation time and memory occupation according to the simulation result, combine the design requirements and function definition of the chip, and divide the simulation process of the whole chip into multiple simulation operation tasks;

[0125] The hierarchical compilation module 302 is used for pre-compiling the stable basic module and real-time compiling the frequently modified design part during simulation;

[0126] The block simulation module 303 is used for allocating the disassembled operation tasks to the multi-core processor for block simulation, and preferentially allocating memory resources to the module with the most simulation time and memory occupation;

[0127] The dynamic performance optimization module 304 is used for simulating by using the EDA tool VCS, setting the dynamic performance optimization option DPO, collecting data by multiple tests, judging the optimal parameters by DPO according to the historical data and simulation statistical result, updating the optimization strategy every time the test is run, and adaptively adjusting the design simulation rule;

[0128] The result integration and verification module 305 is configured to verify whether the simulation result is consistent with the original design expectation, automatically compare the interface timing and function of the design, and generate a simulation verification result.

[0129] In some embodiments, the simulation analysis of the design-under-test file and the stimulus is performed, the corresponding simulation result is obtained, the module occupying the most simulation time and memory is analyzed according to the simulation result, the simulation process of the entire chip is divided into multiple simulation operation tasks according to the design requirement and the function definition of the chip, including:

[0130] The design-under-test file is imported into the EDA simulation environment, and the corresponding verification environment and stimulus file are loaded to perform preliminary simulation running, and the running time and memory occupation data of each module are recorded in real time during the simulation process, so that the corresponding simulation result is obtained.

[0131] Based on the obtained simulation result, a preset sorting algorithm and analysis logic are used to sort and analyze the simulation time and memory occupation of each module, identify the module occupying the most simulation time and memory, and comprehensively evaluate the resource occupation of each module by counting the number of signal flips and the complexity of data processing, determine the function architecture of the chip and the interaction relationship between modules according to the design requirement document and the function definition of the chip.

[0132] According to the resource occupation analysis result of the module and the function definition of the chip, the simulation process of the entire chip is divided, and the design is divided into multiple simulation operation tasks which are independent of each other and have clear function boundaries according to the function correlation and data flow direction principle.

[0133] In some embodiments, for a chip including a processor, a memory and a peripheral interface, the chip is divided into a processor module simulation task, a memory module simulation task and a peripheral interface module simulation task, and the granularity of each task is ensured to ensure the efficiency of parallel simulation and facilitate subsequent management and verification.

[0134] In some embodiments, the stable basic module is pre-compiled, and the frequently modified design part such as algorithm logic and control path is compiled in real time during simulation, including:

[0135] Each module in the chip design is evaluated, and the modules are classified according to the stability and modification frequency of the modules.

[0136] For stable modules, pre-compilation is performed before simulation starts.

[0137] For frequently modified design parts, real-time compilation is performed during simulation running.

[0138] In the compilation process, the code is optimized according to the specific situation of the runtime, and the incremental compilation technology is adopted to recompile only the modified part.

[0139] In some embodiments, the above-mentioned allocation of each operation task after disassembly to the multi-core processor is divided into block simulation, and for the module that occupies the most simulation time and memory, memory resources are preferentially allocated, including:

[0140] Each simulation operation task after disassembly is allocated to different cores or multiple computing nodes of the multi-core processor for block simulation. During the allocation process, according to the module resource occupation obtained by the previous analysis, for the module that occupies the most simulation time and memory, more memory resources and computing cores are preferentially allocated to ensure that these key modules can run efficiently;

[0141] On the multi-core processor, each task simultaneously and in parallel performs simulation, in order to ensure the correct interaction and timing consistency between tasks, a preset communication and synchronization mechanism is used; a message queue is used to transmit data and control signals between tasks to ensure accurate data transmission; through a clock synchronization algorithm, the simulation clock of each task is kept consistent to avoid timing chaos; the execution state of each task is monitored in real time, and when a task appears abnormal or resource competition, timely adjustment and intervention is carried out;

[0142] After each task completes the simulation, the simulation results are collected, and the collected results are preliminarily processed and verified to ensure the accuracy and integrity of the results.

[0143] In some embodiments, the above-mentioned simulation using EDA tool VCS sets dynamic performance optimization option DPO, performs multiple tests to collect data, and DPO automatically judges the optimal parameters according to historical data and simulation statistical results. Each time the test is completed, the optimization strategy is updated, and the design simulation rules are adaptively adjusted, including:

[0144] In the simulation using EDA tool VCS, the dynamic performance optimization function DPO is enabled through specific configuration options, and necessary computing resources and data storage space are allocated to DPO in the initialization stage, so that it can effectively collect and process simulation data;

[0145] Let DPO run multiple tests during simulation, and in each test process, DPO collects various simulation performance-related data in real time, including the execution time of each module, the number of memory accesses, and CPU utilization; analyze the collected data, use statistical analysis methods and machine learning algorithms to mine the hidden rules and trends in the data, and find out the key factors affecting simulation performance;

[0146] According to the result of data analysis, the DPO automatically determines the optimal simulation parameter setting; after adjusting the parameters, the DPO continues to perform simulation testing, and compares the simulation speed before and after adjustment to evaluate the effect of parameter adjustment. If the speed is improved, the new parameter setting is retained; if the performance is not improved, the DPO reanalyzes the data and tries other parameter combinations until the optimal parameter configuration is found.

[0147] In some embodiments, the above-mentioned verification compares whether the simulation result is consistent with the original design expectation, automatically compares the interface timing and function of the design, including:

[0148] The simulation results of each module obtained by the block simulation are integrated, and the results of each part are combined into a complete system-level simulation result according to the overall architecture of the chip design and the connection relationship between the modules, to ensure the consistency and accuracy of the data, and to check and convert the interface data between different modules to meet the overall requirements of the system;

[0149] The integrated simulation result is compared with the original design expectation to verify whether the function of the chip design meets the requirements;

[0150] The interface timing of the design is compared to check whether the signal transmission between each module meets the timing requirements; the clock signal, data signal and the like of the chip are analyzed to detect whether there is a problem of not meeting the setup time or hold time violation.

[0151] In combination with Figure 4 As shown in FIG. 4, the chip simulation verification acceleration device 400 provided by the embodiment of the present disclosure includes a processor 404 and a memory 401. Optionally, the system can further include a communication interface 402 and a bus 403. The processor 404, the communication interface 402 and the memory 401 can complete mutual communication through the bus 403. The communication interface 402 can be used for information transmission. The processor 404 can invoke the logic instructions in the memory 401 to execute the chip simulation verification acceleration method of the above-mentioned embodiments.

[0152] In addition, the logic instructions in the memory 401 described above can be implemented in the form of a software function unit and sold or used as an independent product, which can be stored in a computer readable storage medium.

[0153] The memory 401 as a computer readable storage medium can be used to store software programs, computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 404 executes the function application and data processing by running the program instructions / modules stored in the memory 401, that is, implements the chip simulation verification acceleration method in the above-mentioned embodiments.

[0154] The memory 401 can include a program storage area and a data storage area, where the program storage area can store an operating system, application programs required by at least one function; the data storage area can store data created according to the use of the terminal device, etc. In addition, the memory 401 can include a high-speed random access memory, and can also include a nonvolatile memory.

[0155] The embodiment of the present disclosure provides a computer readable storage medium, which stores computer executable instructions, and the computer executable instructions are set to execute a chip simulation verification acceleration method.

[0156] The computer readable storage medium described above can be a transitory computer readable storage medium or a non-transitory computer readable storage medium.

[0157] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes one or more instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method of the embodiment of the present disclosure. The aforementioned storage medium can be a non-transitory storage medium, including a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, etc. various media that can store program codes, or can be a transitory storage medium.

[0158] The above description and drawings are illustrative of embodiments of the present disclosure and are not intended to be limiting. Other embodiments can include structural, logical, electrical, process, and other changes. Embodiments are illustrative only. Individual components and functions are optional, and the order of operations can vary. Portions and features of some embodiments can be included or replaced in or by other embodiments. As used in the description of the embodiments, the article "a" is intended to include one or more items unless otherwise clear from the context of the statement. Likewise, the article "the" is intended to include one or more items unless otherwise clear from the context of the statement. Similarly, the term "and / or" as used in the application refers to any and all possible combinations of one or more of the associated listed items. In addition, the term "comprise" and variations of the term, such as "comprises" and / or "comprising," as used in this application, does not exclude the presence of one or more other features, integers, steps, operations, elements, and / or groups that are mentioned throughout this application. The term "include," along with its derivatives, is used in an open-ended fashion, meaning that an item or process that is "included" need not be limited to only those items that are specifically listed. Each embodiment is intended to cover its own variations and alternatives. For embodiments of methods, products, and the like, if they correspond to parts of the embodiments of methods, then the relevant parts can be found in the description of the methods.

[0159] Those skilled in the art can understand that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized in electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of the present disclosure. Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, devices, and units can refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

[0160] In the embodiments disclosed herein, the disclosed methods, products (including but not limited to apparatuses, devices, etc.) can be implemented in other manners. For example, the apparatus embodiments described above are merely schematic. For example, the division of the units is merely logical function division. There can be other division manners in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, apparatuses, or units, and can be in electrical, mechanical, or other forms.

[0161] The flowcharts and block diagrams in the drawings show the possible implementation architectures, functions, and operations of the systems, methods, and computer program products according to the embodiments of the present disclosure. In this regard, each block in the flowcharts and block diagrams can represent a module, a program segment, or a part of code that contains one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks can occur in an order different from that noted in the drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and sometimes can be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the drawings, the operations or steps corresponding to different blocks can also occur in an order different from that disclosed in the descriptions, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and sometimes can be executed in reverse order, depending on the functions involved. Each block in the block diagrams and / or flowcharts, and the combination of blocks in the block diagrams and / or flowcharts, can be implemented by a dedicated hardware-based system that performs the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0162] The various embodiments of the systems and techniques described above can be implemented in digital electronic circuitry, integrated circuitry, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SOC), a load programmable logic device (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0163] Program code for carrying out methods of the present disclosure can be written in any combination of one or more programming languages. The program code can be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the program code, when executed by the processor or controller, produces the functions / operations specified in the flowcharts and / or the block diagrams. The program code can be executed entirely on a machine, partially on a machine, partially on a machine as a stand-alone software package, and partially on a remote machine or entirely on a remote machine or server.

[0164] In the context of the present disclosure, a machine-readable medium can be a tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include but is not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the machine-readable storage medium will include one or more lines of electrical connections, portable computer disks, hard disk drives, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash memory), optical fibers, portable compact disc read-only memories (CD-ROMs), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0165] To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0166] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0167] The computer system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server can arise by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0168] It should be understood that various forms of flow shown above can be used, with steps reordered, added, or removed. For example, the steps recited in the present disclosure can be performed in parallel, in series, or in a different order, without limitation herein, so long as the desired results of the technical solutions of the present disclosure are achieved.

[0169] The specific embodiments described above are not intended to be limiting, and persons skilled in the art will appreciate that various modifications, combinations, sub-combinations and alternatives can be made to the specific embodiments without departing from the spirit and principles of the disclosure. Any further modifications, equivalents, alternatives, and / or improvements made to the specific embodiments described above are intended to fall within the scope of the disclosure.

Claims

1. A chip emulation verification acceleration method, characterized by, The method comprises: Obtaining simulation analysis of the design-under-test file and the stimulus, obtaining corresponding simulation results, analyzing the modules occupying the most simulation time and memory according to the simulation results, decomposing the whole chip simulation process according to the design requirements and function definition of the chip, and dividing the simulation process into multiple simulation operation tasks; Pre-compiling stable basic modules and real-time compiling frequently modified design parts during simulation; Assigning each operation task after decomposition to a multi-core processor for block simulation, and preferentially allocating memory resources to the module occupying the most simulation time and memory; Using EDA tool VCS for simulation, setting dynamic performance optimization option DPO, collecting data through multiple tests, judging the optimal parameters according to historical data and simulation statistics, updating the optimization strategy and adaptively adjusting the design simulation rules every time the test is run; Verifying whether the simulation results are consistent with the original design expectations, automatically comparing the interface timing and function of the design, and generating simulation verification results.

2. The method of claim 1, wherein, The method comprises: Importing the design-under-test file into the EDA simulation environment, loading the corresponding verification environment and stimulus file, and performing preliminary simulation on the design-under-test, recording the running time and memory occupation data of each module in real time during the simulation process, and thus obtaining corresponding simulation results; Based on the obtained simulation results, using a preset sorting algorithm and analysis logic to sort and analyze the simulation time and memory occupation of each module, identifying the module occupying the most simulation time and memory, comprehensively evaluating the resource occupation of each module by counting the number of signal flips and data processing complexity factors, and determining the overall function architecture of the chip and the interaction relationship between modules according to the chip design requirement document and function definition; According to the resource occupation analysis results of the modules and the function definition of the chip, the whole chip simulation process is decomposed, and the design is divided into multiple simulation operation tasks that are independent of each other and have clear functional boundaries according to the functional correlation and data flow direction principles.

3. The method of claim 2, wherein, The method further comprises: For a chip containing a processor, a memory and a peripheral interface, the chip is divided into a processor module simulation task, a memory module simulation task and a peripheral interface module simulation task, and the granularity of each task is ensured during the division process to ensure the efficiency of parallel simulation and facilitate subsequent management and verification.

4. The method of claim 1, wherein, The method further comprises: For a chip containing a processor, a memory and a peripheral interface, the chip is divided into a processor module simulation task, a memory module simulation task and a peripheral interface module simulation task, and the granularity of each task is ensured during the division process to ensure the efficiency of parallel simulation and facilitate subsequent management and verification. The method further comprises: For a chip containing a processor, a memory and a peripheral interface, the chip is divided into a processor module simulation task, a memory module simulation task and a peripheral interface module simulation task, and the granularity of each task is ensured during the division process to ensure the efficiency of parallel simulation and facilitate subsequent management and verification. In the compilation process, according to the specific circumstances of runtime, the code is optimized, and the incremental compilation technology is adopted, only the modified part is recompiled.

5. The method of claim 1, wherein, The simulation of the decomposed operation tasks is allocated to the different cores or multiple computing nodes of the multi-core processor; during the allocation process, according to the module resource occupation obtained by the previous analysis, the module occupying the most simulation time and memory is preferentially allocated more memory resources and computing cores to ensure that the key module can run efficiently; On the multi-core processor, each task simultaneously and in parallel performs simulation, in order to ensure the correct interaction and timing consistency between tasks, a preset communication and synchronization mechanism is adopted; a message queue is used to transmit data and control signals between tasks to ensure accurate data transmission; through a clock synchronization algorithm, the simulation clock of each task is kept consistent to avoid timing confusion; the execution state of each task is monitored in real time, and when the task appears abnormal or resource competition, timely adjustment and intervention is carried out; After each task completes the simulation, the simulation results are collected, and the collected results are preliminarily processed and verified to ensure the accuracy and integrity of the results. The simulation is performed by using the EDA tool VCS, the dynamic performance optimization option DPO is set, and data is collected through multiple tests; DPO can automatically determine the optimal parameters according to historical data and simulation statistical results, update the optimization strategy every time the test is run, and adaptively adjust the design simulation rules, including:

6. The method of claim 1, wherein, In the simulation using the EDA tool VCS, the dynamic performance optimization function DPO is enabled through specific configuration options, and necessary computing resources and data storage space are allocated to DPO in the initialization stage, so that it can effectively collect and process simulation data; Let DPO run multiple tests during simulation, in each test process, DPO collects various simulation performance-related data in real time, including the execution time of each module, memory access times, CPU utilization; analyze the collected data, use statistical analysis methods and machine learning algorithms to mine the hidden rules and trends in the data, and find out the key factors affecting simulation performance; According to the results of data analysis, DPO automatically determines the optimal simulation parameter settings; after adjusting the parameters, DPO continues to perform simulation tests and compares the simulation speed before and after adjustment to evaluate the effect of parameter adjustment; if the speed is improved, the new parameter settings are retained; if the performance is not improved, DPO reanalyzes the data and tries other parameter combinations until the optimal parameter configuration is found. The simulation results are verified and compared with the original design expectations to automatically compare the interface timing and function of the design, including:

7. The method of claim 1, wherein, ​ The simulation results of each module obtained by the block simulation are integrated, the results of each part are combined into a complete system-level simulation result according to the overall architecture of the chip design and the connection relationship between the modules, the consistency and accuracy of the data are ensured, the interface data between different modules are checked and converted, and the interface data are made to meet the overall requirements of the system; The integrated simulation result is compared with the original design expectation, and whether the function of the chip design meets the requirements is verified; The interface timing of the design is compared, whether the signal transmission between each module meets the timing requirements is checked, and whether there is a problem of not meeting the setup time or violating the hold time is detected by analyzing the clock signal and the data signal of the chip.

8. A chip emulation verification acceleration device, comprising: The device comprises: A chip design disassembly module configured to obtain simulation analysis of a design-under-test file and an excitation, obtain corresponding simulation results, analyze a module that occupies the most simulation time and memory according to the simulation results, and disassemble the simulation process of the entire chip into multiple simulation operation tasks according to design requirements and function definitions of the chip; A hierarchical compilation module configured to pre-compile stable basic modules and compile frequently modified design parts in real time during simulation; A block simulation module configured to distribute each operation task after disassembly to a multi-core processor for block simulation, and preferentially allocate memory resources to a module that occupies the most simulation time and memory; A dynamic performance optimization module configured to use an EDA tool VCS to perform simulation, set a dynamic performance optimization option DPO, perform multiple tests to collect data, determine optimal parameters according to historical data and simulation statistical results, update optimization strategies each time a test is run, and adaptively adjust design simulation rules; A result integration and verification module configured to verify whether simulation results and original design expectations are consistent, automatically compare interface timing and functions of the design, and generate simulation verification results.

9. An electronic device, comprising: Comprise: At least one processor; And a memory in communication connection with the at least one processor; The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method in any one of claims 1-7. 10.A non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable the computer to perform the method in any one of claims 1-7. 10.A non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable the computer to perform the method in any one of claims 1-7.

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