Display device and electronic device including the same

Abstract

The invention provides a display device and electronic equipment comprising the same. The display device includes: a display panel including pixels; a data driver generating a first data voltage for a low driving frequency based on the low-frequency gamma voltage, generating a second data voltage for a high driving frequency based on the high-frequency gamma voltage, and supplying the first data voltage or the second data voltage to the pixel; and a scan driver generating a first scan signal having a low-frequency scan-on time for a low driving frequency, generating a second scan signal having a high-frequency scan-on time for a high driving frequency, and supplying the first scan signal or the second scan signal to the pixels. A low frequency scan-on time may be determined when a difference between a low frequency gamma voltage range of the low frequency gamma voltage and a target gamma voltage range is within a reference range.

Description

TECHNICAL FIELD

[0001] Embodiments of the disclosure relate to a display apparatus. More particularly, the disclosure relates to a display apparatus improving display quality with a variable driving frequency and an electronic device including the display apparatus. BACKGROUND

[0002] The display apparatus can include a display panel displaying an image, a data driver providing a data voltage to the display panel, a scan driver providing a scan signal to the display panel, and an emission driver providing an emission signal to the display panel. Recently, a variable refresh rate (VRR) driving method adjusting a driving frequency of the display panel has been developed to improve the quality of an image displayed on the display apparatus and reduce power consumption of the display apparatus, etc.

[0003] During a transition of the driving frequency of the display apparatus, or when the display apparatus switches from a display-off state to a display-on state, flicker in which image brightness is increased or decreased can be recognized due to different driving conditions based on the driving frequency, a change in the number of emission cycles of the emission signal and an emission-off time, etc. As a result, the image quality of the display apparatus can be deteriorated. SUMMARY

[0004] Embodiments of the disclosure provide a display apparatus having improved image quality during a transition of a driving frequency or when switching from a display-off state to a display-on state, and an electronic device including the display apparatus.

[0005] According to embodiments of the disclosure, the display apparatus includes a display panel including a pixel, a data driver connected to the pixel through a data line, and a scan driver connected to the pixel through a gate line. The data driver can generate a first data voltage for a low driving frequency based on a low-frequency gamma voltage, generate a second data voltage for a high driving frequency higher than the low driving frequency based on a high-frequency gamma voltage, and provide the first data voltage or the second data voltage to the pixel. The scan driver can generate a first scan signal having a low-frequency scan-on time for the low driving frequency, generate a second scan signal having a high-frequency scan-on time different from the low-frequency scan-on time for the high driving frequency, and provide the first scan signal or the second scan signal to the pixel. The low-frequency scan-on time can be determined when a difference between a low-frequency gamma voltage range of the low-frequency gamma voltage and a target gamma voltage range calculated based on a high-frequency gamma voltage range of the high-frequency gamma voltage range is within a reference range.

[0006] In an embodiment, the target gamma voltage range can be equal to the high-frequency gamma voltage range.

[0007] In an embodiment, the low-frequency gamma voltage range can be defined as from a first reference low-frequency gamma voltage corresponding to a first reference gray level to a second reference low-frequency gamma voltage corresponding to a second reference gray level higher than the first reference gray level, and the target gamma voltage range can be defined as from a first reference high-frequency gamma voltage corresponding to the first reference gray level to a second reference high-frequency gamma voltage corresponding to the second reference gray level.

[0008] In an embodiment, when the low-frequency gamma voltage range is higher than the target gamma voltage range, the low-frequency scan on-time can be reduced by a certain offset, and when the low-frequency gamma voltage range is lower than the target gamma voltage range, the low-frequency scan on-time can be increased by the offset.

[0009] In an embodiment, the offset can be determined based on a difference between the low-frequency gamma voltage range and the target gamma voltage range.

[0010] In an embodiment, the offset can have a predetermined value.

[0011] In an embodiment, the display apparatus can further include an emission driver connected to the pixels through an emission signal line and a controller generating an emission start signal. The emission driver can generate an emission signal based on the emission start signal having a number of emission cycles varying depending on a driving frequency, and provide the emission signal to the pixels.

[0012] In an embodiment, when the driving frequency is changed between a low driving frequency and a high driving frequency, a buffer frame can be inserted between a low-frequency frame driven at the low driving frequency and a high-frequency frame driven at the high driving frequency, and a buffer emission cycle number of the emission start signal in the buffer frame can be calculated based on a low-frequency emission cycle number of the emission start signal in the low-frequency frame and a high-frequency emission cycle number of the emission start signal in the high-frequency frame.

[0013] According to an embodiment of the disclosure, a display apparatus includes a display panel including pixels, an emission driver connected to the pixels through an emission signal line, and a controller generating an emission start signal. The emission driver can generate an emission signal based on the emission start signal having a number of emission cycles varying depending on a driving frequency, and provide the emission signal to the pixels. When the driving frequency is changed between a low driving frequency and a high driving frequency higher than the low driving frequency, a buffer frame can be inserted between a low-frequency frame driven at the low driving frequency and a high-frequency frame driven at the high driving frequency, and a buffer emission cycle number of the emission start signal in the buffer frame can be calculated based on a low-frequency emission cycle number of the emission start signal in the low-frequency frame and a high-frequency emission cycle number of the emission start signal in the high-frequency frame.

[0014] In an embodiment, the buffer emission cycle number can be an average of the low-frequency emission cycle number and the high-frequency emission cycle number.

[0015] In an embodiment, the number of buffer emission cycles can be obtained by multiplying a weighted value by an average of the number of low-frequency emission cycles and the number of high-frequency emission cycles.

[0016] In an embodiment, the number of buffer emission cycles when the driving frequency changes from the low driving frequency to the high driving frequency can be different from the number of buffer emission cycles when the driving frequency changes from the high driving frequency to the low driving frequency.

[0017] In an embodiment, the buffer frame can be inserted when a difference between the low driving frequency and the high driving frequency is higher than a threshold frequency.

[0018] In an embodiment, the buffer frame can be selectively inserted when the driving frequency changes from the low driving frequency to the high driving frequency, or when the driving frequency changes from the high driving frequency to the low driving frequency.

[0019] In an embodiment, an insertion time of the buffer frame can be delayed by a delay time length from a transition time of the driving frequency.

[0020] According to an embodiment of the disclosure, a display apparatus includes a display panel including pixels, an emission driver connected to the pixels through an emission signal line, and a controller generating an emission start signal. The emission driver can generate an emission signal based on the emission start signal and provide the emission signal to the pixels, the emission start signal having a number of emission cycles and an emission off time that vary depending on a driving frequency. When the display panel switches from a display off state to a display on state, a dummy frame can be inserted before a start frame driven at a start driving frequency, and at least one of the number of emission cycles and the emission off time can be different between the start frame and the dummy frame.

[0021] In an embodiment, a dummy emission off time of the emission start signal in the dummy frame can be greater than a start emission off time of the emission start signal in the start frame.

[0022] In an embodiment, a dummy number of emission cycles of the emission start signal in the dummy frame can be greater than a start number of emission cycles of the emission start signal in the start frame.

[0023] In an embodiment, the dummy frame can be inserted when the start driving frequency is lower than a threshold frequency.

[0024] In an embodiment, an insertion time of the dummy frame can be delayed by a delay time length from a start time of the display on state.

[0025] According to an embodiment of the present disclosure, an electronic device includes a display device for displaying an image and a processor for controlling the display device. The electronic device may include: a display panel including pixels, a data driver connected to the pixels via data lines, and a scan driver connected to the pixels via gate lines. The data driver may generate a first data voltage for a low driving frequency based on a low-frequency gamma voltage, generate a second data voltage for a high driving frequency higher than the low driving frequency based on a high-frequency gamma voltage, and supply the first data voltage or the second data voltage to the pixels. The scan driver may generate a first scan signal having a low-frequency scan-on time for the low driving frequency, generate a second scan signal having a high-frequency scan-on time different from the low-frequency scan-on time for the high driving frequency, and supply the first scan signal or the second scan signal to the pixels. The low-frequency scan-on time may be determined when a difference between a low-frequency gamma voltage range of the low-frequency gamma voltage and a target gamma voltage range calculated based on the high-frequency gamma voltage is within a reference range.

[0026] In the display device and electronic device according to the embodiment, the low-frequency scan-on time can be determined so that the gamma voltage range between the low driving frequency and the high driving frequency becomes similar during the transition of the driving frequency, or a buffer frame can be inserted between the low-frequency frame and the high-frequency frame, thereby improving image quality when the driving frequency changes. Furthermore, when the display device switches from the display-off state to the display-on state, a dummy frame can be inserted before the start frame, thereby improving image quality when switching from the display-off state to the display-on state. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other features of the embodiments of the present disclosure will become more apparent with reference to the following description and accompanying drawings.

[0028] Figure 1 is a block diagram illustrating a display device according to an embodiment.

[0029] Figure 2 It shows Figure 1 Circuit diagram of a pixel.

[0030] Figure 3 It shows the transmission to Figure 2 Timing diagram of the pixel signal.

[0031] Figure 4 is a view showing an image displayed when the driving frequency is switched from a low driving frequency to a high driving frequency according to a comparative example.

[0032] Figure 5 is a view showing an image displayed when the driving frequency is switched from a high driving frequency to a low driving frequency according to a comparative example.

[0033] Figure 6 is a flowchart showing a method of controlling a high-frequency gamma voltage range, a low-frequency gamma voltage range, and a low-frequency scan ON time.

[0034] Figure 7 is a graph describing a method of controlling a low-frequency gamma voltage range.

[0035] Figure 8 is a block diagram showing an example of a controller of Figure 1

[0036] Figure 9 is a timing chart showing emission start signals when a driving frequency is switched according to a comparative example.

[0037] Figure 10 is a timing chart showing luminance of an image when a driving frequency is switched according to a comparative example.

[0038] Figure 11 is a timing chart showing emission start signals when a driving frequency is switched according to an embodiment.

[0039] Figure 12 is a timing chart showing luminance of an image when a driving frequency is switched according to an embodiment.

[0040] Figure 13 is a block diagram showing an example of a controller of Figure 1

[0041] Figure 14 is a timing chart showing emission start signals when switching from a display OFF state to a display ON state according to a comparative example.

[0042] Figure 15 is a timing chart showing luminance of an image when switching from a display OFF state to a display ON state according to a comparative example.

[0043] Figure 16 is a timing chart showing emission start signals when switching from a display OFF state to a display ON state according to an embodiment.

[0044] Figure 17 is a timing chart showing luminance of an image when switching from a display OFF state to a display ON state according to an embodiment.

[0045] Figure 18 is a block diagram showing an electronic device according to an embodiment. DETAILED DESCRIPTION

[0046] Hereinafter, a display apparatus and an electronic device according to embodiments of the disclosure will be described in greater detail with reference to the accompanying drawings. The same or similar components are denoted by the same or similar reference numerals, and a repeated description of the same or similar components will be omitted.

[0047] ​​Figure 1 is a block diagram illustrating a display apparatus 100 according to an embodiment. Figure 2 is a circuit diagram illustrating a pixel PX of Figure 1 Figure 3 is a timing chart illustrating signals EM and SS transmitted to a pixel PX of Figure 2 Figure 4 is a view illustrating an image displayed when a driving frequency is switched from a low driving frequency FRQ_L to a high driving frequency FRQ_H according to a comparative example. Figure 5 is a view illustrating an image displayed when a driving frequency is switched from a high driving frequency FRQ_H to a low driving frequency FRQ_L according to a comparative example. Figure 6 is a flowchart illustrating a method of controlling a high-frequency gamma voltage range VRG_H, a low-frequency gamma voltage range VRG_L, and a low-frequency scan-on time. Figure 7 is a graph describing a method of controlling a low-frequency gamma voltage range VRG_L.

[0048] Referring to Figures 1 to 7 , the display apparatus 100 can include a display panel 110, a data driver 120, a gamma voltage generator 130, a scan driver 140, an emission driver 150, and a controller 160.

[0049] The display panel 110 can display an image. The display panel 110 can be driven by a variable refresh rate (VRR) method in which a driving frequency varies. The driving frequency means the number of times an image displayed on the display panel 110 is refreshed per second.

[0050] The display panel 110 can include a plurality of pixels PX. In an embodiment, as illustrated in Figure 2 , the pixel PX can include a light emitting element LED, a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor CST.

[0051] The light emitting element LED can emit light having a luminance corresponding to a driving current. The first transistor T1 can generate a driving current corresponding to a data voltage VDAT stored in the storage capacitor CST. The second transistor T2 can transmit the data voltage VDAT to a gate of the first transistor T1 in response to a scan signal SS. The third transistor T3 can form a current path through which a driving current flows from a first power voltage ELVDD to a second power voltage ELVSS in response to an emission signal EM. The storage capacitor CST can store the data voltage VDAT transmitted to the gate of the first transistor T1.

[0052] Although Figure 2 ​​Embodiments in which the pixel PX includes three transistors and one capacitor are illustrated, but the present disclosure is not limited thereto. For example, the pixel PX can include four or more transistors and / or two or more capacitors.

[0053] As shown in FIG. 1A, the second transistor T2 can be turned on during the scan-on time SOT in which the scan signal SS has a gate-on voltage (e.g., a gate low voltage), and the data voltage VDAT can be transmitted to the gate of the first transistor T1 through the second transistor T2. The storage capacitor CST can hold and store the data voltage VDAT transmitted to the gate of the first transistor T1 even after the second transistor T2 is turned off. Figure 3

[0054] During the emission-on time EOT in which the emission signal EM has a gate-on voltage (e.g., a gate low voltage), the third transistor T3 can be turned on, and a current path through which a drive current flows from the first power supply voltage ELVDD to the second power supply voltage ELVSS can be formed. The drive current can correspond to the data voltage VDAT stored in the storage capacitor CST, and the light emitting element LED can emit light having a luminance corresponding to the drive current.

[0055] The data driver 120 can provide the data voltage VDAT to each of the pixels PX through a plurality of data lines. The data driver 120 can generate the data voltage VDAT based on the second image data DAT2, a data control signal DCNT, and a gamma voltage. The data driver 120 can convert the second image data DAT2 into the data voltage VDAT based on the gamma voltage. The gamma voltage can vary depending on a driving frequency. The data driver 120 can generate the data voltage VDAT based on a low-frequency gamma voltage VGM_L at a low driving frequency FRQ_L, and can generate the data voltage VDAT based on a high-frequency gamma voltage VGM_H at a high driving frequency FRQ_H higher than the low driving frequency FRQ_L. The low-frequency gamma voltage VGM_L and the high-frequency gamma voltage VGM_H can be different from each other for the same gray level.

[0056] The gamma voltage generator 130 can provide the data driver 120 with a gamma voltage corresponding to a driving frequency. The gamma voltage generator 130 can provide the data driver 120 with a low-frequency gamma voltage VGM_L at a low driving frequency FRQ_L, and can provide the data driver 120 with a high-frequency gamma voltage VGM_H at a high driving frequency FRQ_H.

[0057] ​The scan driver 140 can provide a scan signal SS to each of the pixels PX through a plurality of gate lines. The scan driver 140 can generate the scan signal SS based on a scan control signal SCNT. The scan control signal SCNT can include a scan start signal, a scan clock signal, etc. A scan on time SOT of the scan signal SS can vary depending on a driving frequency. The scan on time SOT can be a time during which the scan signal SS has a gate on voltage. For example, the scan on time SOT can increase as the driving frequency decreases. The scan driver 140 can generate the scan signal SS having a low-frequency scan on time at a low driving frequency FRQ_L and can generate the scan signal SS having a high-frequency scan on time different from the low-frequency scan on time at a high driving frequency FRQ_H.

[0058] The emission driver 150 can provide an emission signal EM to each of the pixels PX through a plurality of emission signal lines. The emission driver 150 can generate the emission signal EM based on an emission control signal ECNT. The emission control signal ECNT can include an emission start signal ACL_FLM, an emission clock signal, etc. An emission cycle number and an emission off time of the emission start signal ACL_FLM can vary depending on a driving frequency. The emission cycle number can be a number of emission off periods (P_EOF) of the emission start signal ACL_FLM included in one frame. For example, the emission cycle number can increase as the driving frequency decreases. The emission off time can be a total duration of the emission off periods P_EOF in one frame, or can be a ratio of the total duration of the emission off periods P_EOF within one frame. The emission driver 150 can generate the emission signal EM having a low-frequency emission cycle number and a low-frequency emission off time at a low driving frequency FRQ_L and can generate the emission signal EM having a high-frequency emission cycle number and a high-frequency emission off time at a high driving frequency FRQ_H. Figure 9 、 Figure 11 、 Figure 14 and Figure 16 The emission driver 150 can provide an emission signal EM to each of the pixels PX through a plurality of emission signal lines. The emission driver 150 can generate the emission signal EM based on an emission control signal ECNT. The emission control signal ECNT can include an emission start signal ACL_FLM, an emission clock signal, etc. An emission cycle number and an emission off time of the emission start signal ACL_FLM can vary depending on a driving frequency. The emission cycle number can be a number of emission off periods (P_EOF) of the emission start signal ACL_FLM included in one frame. For example, the emission cycle number can increase as the driving frequency decreases. The emission off time can be a total duration of the emission off periods P_EOF in one frame, or can be a ratio of the total duration of the emission off periods P_EOF within one frame. The emission driver 150 can generate the emission signal EM having a low-frequency emission cycle number and a low-frequency emission off time at a low driving frequency FRQ_L and can generate the emission signal EM having a high-frequency emission cycle number and a high-frequency emission off time at a high driving frequency FRQ_H.

[0059] The controller 160 can provide the second image data DAT2 and a data control signal DCNT to the data driver 120, can provide a scan control signal SCNT to the scan driver 140, and can provide an emission control signal ECNT to the emission driver 150. The controller 160 can generate the second image data DAT2, the data control signal DCNT, the scan control signal SCNT, and the emission control signal ECNT based on the first image data DAT1 and the control signal CTRL.

[0060] When the driving frequency is switched, the gamma voltage, the scan on time SOT, and the emission cycle number of the emission start signal ACL_FLM and the emission off time can vary based on the driving frequency. Accordingly, in a comparison example, when the driving frequency is changed, the first frame 1 st The luminance of the FRM can decrease or increase.

[0061] As shown in Figure 4 As shown in st The luminance of the FRM can be lower than the luminance of the last frame among the low frequency frames driven at the low driving frequency FRQ_L and the second frame 2 nd The luminance of the FRM.

[0062] As shown in Figure 5 As shown in st The luminance of the FRM can be higher than the luminance of the last frame among the high frequency frames driven at the high driving frequency FRQ_H and the second frame 2 nd The luminance of the FRM. Further, since the frame length increases as the driving frequency decreases, the change in the luminance can be easily recognized in the low frequency frames compared to the high frequency frames.

[0063] The change in the luminance occurring during the transition of the driving frequency can be recognized as flicker, and thus, the image quality can be deteriorated when the driving frequency is changed. To reduce or substantially prevent the deterioration of the image quality occurring when the driving frequency is switched, in an embodiment of the disclosure, the low frequency scan on time can be determined when a difference between a low frequency gamma voltage range VRG_L of a low frequency gamma voltage VGM_L and a target gamma voltage range calculated based on a high frequency gamma voltage range VRG_H of a high frequency gamma voltage VGM_H is within a reference range, when the driving frequency is changed. Hereinafter, a method of controlling the low frequency gamma voltage range VRG_L and the low frequency scan on time will be described with reference to Figure 6 and Figure 7 A method of controlling the low frequency gamma voltage range VRG_L and the low frequency scan on time is described.

[0064] As shown in Figure 6As illustrated in FIG. 10, multiple programming (MTP) can be performed for the reference grays at a high drive frequency FRQ_H (step S110). By performing the multiple programming at the high drive frequency FRQ_H, a high-frequency gamma voltage VGM_H for each of the reference grays and a high-frequency gamma voltage range VRG_H of the high-frequency gamma voltage VGM_H can be determined. The high-frequency gamma voltage range VRG_H can be defined as from a first reference high-frequency gamma voltage HV_REF1 corresponding to a first reference gray G_REF1 among the reference grays to a second reference high-frequency gamma voltage HV_REF2 corresponding to a second reference gray G_REF2 higher than the first reference gray G_REF1 among the reference grays.

[0065] A target gamma voltage range can be calculated (step S120). The target gamma voltage range can be calculated based on the high-frequency gamma voltage range VRG_H. In an embodiment, the target gamma voltage range can be equal to the high-frequency gamma voltage range VRG_H. For example, the target gamma voltage range can be defined as from the first reference high-frequency gamma voltage HV_REF1 corresponding to the first reference gray G_REF1 to the second reference high-frequency gamma voltage HV_REF2 corresponding to the second reference gray G_REF2.

[0066] The low-frequency gamma voltage range VRG_L and the low-frequency scan on-time can be determined such that a difference between the low-frequency gamma voltage range VRG_L and a high-frequency gamma voltage range VRG_H, which is a target gamma voltage range, is within a reference range. A first reference low-frequency gamma voltage LV_REF1 corresponding to a first reference gray scale G_REF1 can be searched based on an initial low-frequency scan on-time (step S130), and the searched first reference low-frequency gamma voltage LV_REF1 can be compared with a first reference high-frequency gamma voltage HV_REF1 (step S140). When a difference between the searched first reference low-frequency gamma voltage LV_REF1 and the first reference high-frequency gamma voltage HV_REF1 is not within the reference range, the low-frequency scan on-time can be changed (step S150), and the first reference low-frequency gamma voltage LV_REF1 can be searched again based on the changed low-frequency scan on-time (step S130). When the difference between the searched first reference low-frequency gamma voltage LV_REF1 and the first reference high-frequency gamma voltage HV_REF1 is within the reference range, a second reference low-frequency gamma voltage LV_REF2 corresponding to a second reference gray scale G_REF2 can be searched based on the low-frequency scan on-time (step S160), and the searched second reference low-frequency gamma voltage LV_REF2 can be compared with a second reference high-frequency gamma voltage HV_REF2 (step S170). When a difference between the searched second reference low-frequency gamma voltage LV_REF2 and the second reference high-frequency gamma voltage HV_REF2 is not within the reference range, the low-frequency scan on-time can be changed (step S150), and the first reference low-frequency gamma voltage LV_REF1 can be searched again based on the changed low-frequency scan on-time (step S130). When the difference between the searched second reference low-frequency gamma voltage LV_REF2 and the second reference high-frequency gamma voltage HV_REF2 is within the reference range, the low-frequency gamma voltage range VRG_L of the low-frequency gamma voltage VGM_L and the low-frequency scan on-time can be determined.

[0067] Multiple programming (MTP) can be performed for the remaining reference gray scales among the reference gray scales except for the first reference gray scale G_REF1 and the second reference gray scale G_REF2 at the low driving frequency FRQ_L (step S180). By performing the multiple programming at the low driving frequency FRQ_L, the low-frequency gamma voltage VGM_L for each of the remaining reference gray scales except for the first reference gray scale G_REF1 and the second reference gray scale G_REF2 can be determined.

[0068] In an embodiment, the low-frequency scan ON time can be decreased by an offset amount when the low-frequency gamma voltage range VRG_L is higher than the target gamma voltage range, and can be increased by the offset amount when the low-frequency gamma voltage range VRG_L is lower than the target gamma voltage range. The low-frequency scan ON time can be decreased by the offset amount when the difference between the first reference low-frequency gamma voltage LV_REF1 and the first reference high-frequency gamma voltage HV_REF1 is not within the reference range and the first reference low-frequency gamma voltage LV_REF1 is higher than the first reference high-frequency gamma voltage HV_REF1. The low-frequency scan ON time can be increased by the offset amount when the difference between the first reference low-frequency gamma voltage LV_REF1 and the first reference high-frequency gamma voltage HV_REF1 is not within the reference range and the first reference low-frequency gamma voltage LV_REF1 is lower than the first reference high-frequency gamma voltage HV_REF1. The low-frequency scan ON time can be decreased by the offset amount when the difference between the second reference low-frequency gamma voltage LV_REF2 and the second reference high-frequency gamma voltage HV_REF2 is not within the reference range and the second reference low-frequency gamma voltage LV_REF2 is higher than the second reference high-frequency gamma voltage HV_REF2. The low-frequency scan ON time can be increased by the offset amount when the difference between the second reference low-frequency gamma voltage LV_REF2 and the second reference high-frequency gamma voltage HV_REF2 is not within the reference range and the second reference low-frequency gamma voltage LV_REF2 is lower than the second reference high-frequency gamma voltage HV_REF2. As shown in FIG. 6, the low-frequency scan ON time can be increased by the offset amount when the low-frequency gamma voltage range VRG_L is lower than the target gamma voltage range. As a result, the increased first reference low-frequency gamma voltage LV_REF1 and the increased second reference low-frequency gamma voltage LV_REF2 can be searched. Figure 7

[0069] In an embodiment, the offset amount can be determined according to the difference between the low-frequency gamma voltage range VRG_L and the target gamma voltage range. For example, the offset amount can increase as the difference between the low-frequency gamma voltage range VRG_L and the target gamma voltage range increases, and can decrease as the difference between the low-frequency gamma voltage range VRG_L and the target gamma voltage range decreases.

[0070] In an embodiment, the offset amount can have a predetermined value. For example, the offset amount can have a constant value regardless of the difference between the low-frequency gamma voltage range VRG_L and the target gamma voltage range.

[0071] Figure 8 is a block diagram illustrating an example of the controller 160 of Figure 1 Figure 9 is a timing chart illustrating emission of the start signal ACL_FLM when the drive frequency is switched according to a comparative example. Figure 10 ​​is a timing chart showing luminance LUM of an image when a driving frequency is switched according to a comparative example. Figure 11 is a timing chart showing emission start signal ACL_FLM when a driving frequency is switched according to an embodiment. Figure 12 is a timing chart showing luminance LUM of an image when a driving frequency is switched according to an embodiment.

[0072] Reference Figures 8 to 12 When the driving frequency is changed between the low driving frequency FRQ_L and the high driving frequency FRQ_H, a buffer frame FRM_BF can be inserted between the low frequency frame FRM_L driven at the low driving frequency FRQ_L and the high frequency frame FRM_H driven at the high driving frequency FRQ_H. A buffer emission cycle number of the emission start signal ACL_FLM in the buffer frame FRM_BF can be calculated based on a low frequency emission cycle number of the emission start signal ACL_FLM in the low frequency frame FRM_L and a high frequency emission cycle number of the emission start signal ACL_FLM in the high frequency frame FRM_H. Further, a buffer emission off time of the emission start signal ACL_FLM in the buffer frame FRM_BF can be calculated based on a low frequency emission off time of the emission start signal ACL_FLM in the low frequency frame FRM_L and a high frequency emission off time of the emission start signal ACL_FLM in the high frequency frame FRM_H. To calculate the buffer emission cycle number and the buffer emission off time of the emission start signal ACL_FLM in the buffer frame FRM_BF, in an embodiment, the controller 160 can include a frequency block 161, a frequency look-up table (LUT) 162, and a buffer frame generation block 163.

[0073] When the driving frequency is switched, the frequency block 161 can transmit, to the buffer frame generation block 163, a first driving frequency FRQ1 which is the driving frequency before the driving frequency is changed and a second driving frequency FRQ2 which is the driving frequency after the change. The frequency LUT 162 can store predetermined emission cycle numbers and emission off times according to the driving frequencies. The frequency LUT 162 can transmit, to the buffer frame generation block 163, a first emission cycle number ECY1 and a first emission off time EOF1 corresponding to the first driving frequency FRQ1 and a second emission cycle number ECY2 and a second emission off time EOF2 corresponding to the second driving frequency FRQ2.

[0074] The buffer frame generation block 163 can calculate a buffer emission cycle number and a buffer emission off time of the emission start signal ACL_FLM in the buffer frame FRM_BF based on the first drive frequency FRQ1, the second drive frequency FRQ2, the first emission cycle number ECY1, the first emission off time EOF1, the second emission cycle number ECY2, the second emission off time EOF2, the threshold frequency FRQ_TH, the up / down selection signal U / D_SEL, the manual emission cycle number ECY_M, the manual emission off time EOF_M, and the delay time length T_DEL, and can generate the emission start signal ACL_FLM in the buffer frame FRM_BF based on the calculated buffer emission cycle number and buffer emission off time.

[0075] In an embodiment, the buffer emission cycle number can be an average of the low-frequency emission cycle number and the high-frequency emission cycle number. The buffer frame generation block 163 can calculate the buffer emission cycle number as an average of the first emission cycle number ECY1 and the second emission cycle number ECY2.

[0076] In an embodiment, the buffer emission off time can be an average of the low-frequency emission off time and the high-frequency emission off time. The buffer frame generation block 163 can calculate the buffer emission off time as an average of the first emission off time EOF1 and the second emission off time EOF2.

[0077] In an embodiment, the buffer emission cycle number can be a value obtained by multiplying a weighted value by an average of the low-frequency emission cycle number and the high-frequency emission cycle number. The buffer frame generation block 163 can calculate the buffer emission cycle number as a value obtained by multiplying a weighted value by an average of the first emission cycle number ECY1 and the second emission cycle number ECY2. For example, the weighted value is in a range from 0.5 to 2.

[0078] In an embodiment, the buffer emission off time can be a value obtained by multiplying a weighted value by an average of the low-frequency emission off time and the high-frequency emission off time. The buffer frame generation block 163 can calculate the buffer emission off time as a value obtained by multiplying a weighted value by an average of the first emission off time EOF1 and the second emission off time EOF2. For example, the weighted value is in a range from 0.5 to 2.

[0079] In an embodiment, the number of buffer transmission cycles during the transition from the low driving frequency FRQ_L to the high driving frequency FRQ_H can be different from the number of buffer transmission cycles during the transition from the high driving frequency FRQ_H to the low driving frequency FRQ_L. Further, the buffer transmission off time during the transition from the low driving frequency FRQ_L to the high driving frequency FRQ_H can be different from the buffer transmission off time during the transition from the high driving frequency FRQ_H to the low driving frequency FRQ_L. An external lookup table can store a first set of the number of manual transmission cycles ECY_M and the manual transmission off time EOF_M corresponding to the case where the driving frequency is switched from the low driving frequency FRQ_L to the high driving frequency FRQ_H, and a second set of the number of manual transmission cycles ECY_M and the manual transmission off time EOF_M corresponding to the case where the driving frequency is changed from the high driving frequency FRQ_H to the low driving frequency FRQ_L. When the driving frequency is changed from the low driving frequency FRQ_L to the high driving frequency FRQ_H, the buffer frame generation block 163 can refer to the first set of the number of manual transmission cycles ECY_M and the manual transmission off time EOF_M stored in the external lookup table. When the driving frequency is changed from the high driving frequency FRQ_H to the low driving frequency FRQ_L, the buffer frame generation block 163 can refer to the second set of the number of manual transmission cycles ECY_M and the manual transmission off time EOF_M stored in the external lookup table, and can determine the searched number of manual transmission cycles ECY_M and the manual transmission off time EOF_M in the second set as the number of buffer transmission cycles and the buffer transmission off time.

[0080] In an embodiment, the buffer frame FRM_BF can be inserted when the difference between the low driving frequency FRQ_L and the high driving frequency FRQ_H is higher than the threshold frequency FRQ_TH. In other words, the buffer frame FRM_BF can not be inserted when the difference between the low driving frequency FRQ_L and the high driving frequency FRQ_H is lower than the threshold frequency FRQ_TH. If the difference between the low driving frequency FRQ_L and the high driving frequency FRQ_H is lower than the threshold frequency FRQ_TH, no abnormal transmission can be recognized during the transition of the driving frequency, and thus, the insertion of the buffer frame FRM_BF can not be performed.

[0081] In an embodiment, the buffer frame FRM_BF can be selectively inserted when the driving frequency is switched from the low driving frequency FRQ_L to the high driving frequency FRQ_H or when the driving frequency is switched from the high driving frequency FRQ_H to the low driving frequency FRQ_L. The buffer frame generation block 163 can selectively insert the buffer frame FRM_BF based on an up / down selection signal U / D_SEL when the driving frequency is changed from the low driving frequency FRQ_L to the high driving frequency FRQ_H or when the driving frequency is changed from the high driving frequency FRQ_H to the low driving frequency FRQ_L.

[0082] In an embodiment, the insertion time of the buffer frame FRM_BF can be delayed by a predetermined delay time length T_DEL from the transition time of the drive frequency. The buffer frame generation block 163 can delay the start of the first emission-off period P_EOF in which the emission start signal ACL_FLM is emitted in the buffer frame FRM_BF based on the delay time length T_DEL to delay the insertion time of the buffer frame FRM_BF.

[0083] In a comparative example, as Figure 9 and Figure 10 shown, when the drive frequency is changed from the high drive frequency FRQ_H to the low drive frequency FRQ_L, an unexpected luminance waveform can occur in the first low frequency frame FRM_L1 among the low frequency frames FRM_L1 and FRM_L2. For example, the unexpected luminance waveform can occur at the beginning of the first low frequency frame FRM_L1, allowing a user to recognize the change in the drive frequency.

[0084] In an embodiment of the disclosure, as Figure 11 and Figure 12 shown, when the buffer frame FRM_BF is inserted between the high frequency frame FRM_H and the low frequency frame FRM_L, the occurrence of the unexpected luminance waveform can be mitigated. For example, as Figure 12 shown, as the number of buffer emission cycles of the emission start signal ACL_FLM in the buffer frame FRM_BF increases (as the number of buffer emission cycles of the emission start signal ACL_FLM in the buffer frame FRM_BF is greater than the high frequency emission cycle number of the emission start signal ACL_FLM in the high frequency frame FRM_H and the low frequency emission cycle number of the emission start signal ACL_FLM in the low frequency frame FRM_L), the unexpected luminance waveform at the beginning of the change in the drive frequency can be dispersed. As a result, a user can not perceive the transition of the drive frequency of the display device.

[0085] Figure 13 is a block diagram illustrating an example (i.e., the controller 160_1) of the controller 160 of Figure 1 . Figure 14 is a timing diagram illustrating the emission start signal ACL_FLM when switching from the display-off state DIS_OFF to the display-on state DIS_ON according to a comparative example. Figure 15 is a timing diagram illustrating the luminance LUM of an image when switching from the display-off state DIS_OFF to the display-on state DIS_ON according to a comparative example. Figure 16 is a timing diagram illustrating the emission start signal ACL_FLM when switching from the display-off state DIS_OFF to the display-on state DIS_ON according to an embodiment. Figure 17is a timing chart showing luminance LUM of an image when switching from a display-off state DIS_OFF to a display-on state DIS_ON according to an embodiment.

[0086] Referring to Figures 13 to 17 When the display panel 110 switches from the display-off state DIS_OFF to the display-on state DIS_ON, a dummy frame FRM_DM can be inserted before a start frame FRM_1 driven at a start driving frequency FRQ_ST. At least one of an emission cycle number and an emission-off time of emitting the start signal ACL_FLM can be different between the start frame FRM_1 and the dummy frame FRM_DM. To calculate the dummy emission cycle number and the dummy emission-off time of emitting the start signal ACL_FLM in the dummy frame FRM_DM, in an embodiment, the controller 160_1 can include a frequency block 161_1 and a dummy frame generation block 164.

[0087] The frequency block 161_1 can transmit the start driving frequency FRQ_ST of the start frame FRM_1 to the dummy frame generation block 164 when the display panel 110 switches from the display-off state DIS_OFF to the display-on state DIS_ON.

[0088] The dummy frame generation block 164 can calculate the dummy emission cycle number and the dummy emission-off time of emitting the start signal ACL_FLM in the dummy frame FRM_DM based on the start driving frequency FRQ_ST, the threshold frequency FRQ_TH, the manual emission cycle number ECY_M, the manual emission-off time EOF_M, and the delay time length T_DEL, and can generate the start signal ACL_FLM in the dummy frame FRM_DM based on the calculated dummy emission cycle number and dummy emission-off time.

[0089] In an embodiment, the dummy emission-off time of emitting the start signal ACL_FLM in the dummy frame FRM_DM can be greater than the start emission-off time of emitting the start signal ACL_FLM in the start frame FRM_1. In an embodiment, the dummy emission cycle number of emitting the start signal ACL_FLM in the dummy frame FRM_DM can be greater than the start emission cycle number of emitting the start signal ACL_FLM in the start frame FRM_1.

[0090] In an embodiment, the dummy frame generation block 164 can calculate the dummy emission cycle number and the dummy emission-off time in a manual mode. The dummy frame generation block 164 can determine the dummy emission cycle number and the dummy emission-off time in the manual mode as the manual emission cycle number ECY_M and the manual emission-off time EOF_M, respectively.

[0091] In an embodiment, the dummy frame generation block 164 can calculate the dummy emission cycle number and the dummy emission off-time in an automatic mode. In the automatic mode, the dummy frame FRM_DM can be inserted when the start driving frequency FRQ_ST is lower than the threshold frequency FRQ_TH. In other words, in the automatic mode, the dummy frame FRM_DM can not be inserted when the start driving frequency FRQ_ST is higher than the threshold frequency FRQ_TH. When the start driving frequency FRQ_ST is higher than the threshold frequency FRQ_TH, an abnormal emission can not be identified in the start frame FRM_1, and thus the insertion of the dummy frame FRM_DM can not be performed.

[0092] In an embodiment, the insertion time of the dummy frame FRM_DM can be delayed by a predetermined delay time length T_DEL from the start time of the display on state DIS_ON. The dummy frame generation block 164 can delay the start of the first emission off-period P_EOF of the emission start signal ACL_FLM in the dummy frame FRM_DM based on the delay time length T_DEL to delay the insertion time of the dummy frame FRM_DM.

[0093] In a comparative example, as shown in Figure 14 and Figure 15 , when the display panel is switched from the display off state DIS_OFF to the display on state DIS_ON, the luminance LUM of the image can increase in the first start frame FRM_1 among the start frames FRM_1 and FRM_2. For example, the luminance LUM of the image in the first start frame FRM_1 can be higher than the luminance LUM of the image in the second start frame FRM_2, and accordingly, the user can identify the start of the display on state DIS_ON.

[0094] In an embodiment of the disclosure, as shown in Figure 16 and Figure 17 , when the dummy frame FRM_DM is inserted before the start frame FRM_1, the increase in the luminance LUM of the image in the display on state DIS_ON can be prevented. For example, as shown in Figure 17 , as the dummy emission off-time of the emission start signal ACL_FLM in the dummy frame FRM_DM increases (as the dummy emission off-time of the emission start signal ACL_FLM in the dummy frame FRM_DM is greater than the initial emission off-time of the emission start signal ACL_FLM in the start frame FRM_1), the luminance LUM of the image in the display on state DIS_ON can not increase. Accordingly, the user can not perceive the start of the display on state DIS_ON.

[0095] Figure 18 is a block diagram illustrating an electronic device 1000 according to an embodiment.

[0096] Referring toFigure 18 The electronic device 1000 can include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The electronic device 1000 can further include a plurality of ports capable of communicating with a graphics card, a sound card, a memory card, or a USB device, etc., or communicating with other systems.

[0097] The processor 1010 can perform a specific computation or task. According to an embodiment, the processor 1010 can be a microprocessor or a central processing unit (CPU), etc. The processor 1010 can be connected to other components through an address bus, a control bus, or a data bus, etc. According to an embodiment, the processor 1010 can also be connected to an extension bus such as a peripheral component interconnect (PCI) bus.

[0098] The processor 1010 can control the display device 1060. In an embodiment, the processor 1010 can provide the display device 1060 with Figure 1 first image data DAT1 and Figure 1 a control signal CTRL.

[0099] The memory device 1020 can store data required for the operation of the electronic device 1000. For example, the memory device 1020 can include a non-volatile memory device such as an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase-change random access memory (PRAM), a resistive random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory, a magnetic random access memory (MRAM), or a ferroelectric random access memory, or a volatile memory device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), or a mobile DRAM.

[0100] The storage device 1030 can include a solid state drive (SSD), a hard disk drive (HDD), or a CD-ROM, etc. The I / O device 1040 can include an input device such as a keyboard, a keypad, a touchpad, a touch screen, or a mouse, and an output device such as a speaker or a printer. The power supply 1050 can provide power required for the operation of the electronic device 1000. The display device 1060 can be connected to other components through a bus or other communication link. The display device 1060 can correspond to the display device 100 of Figure 1 .

[0101] The display device according to an embodiment can be applied to a display device included in a computer (e.g., a notebook computer, a smart pad), a mobile phone, a smart phone, a smart watch, a PMP, a PDA, or an MP3 player, etc.

[0102] Although the display device and the electronic apparatus according to the embodiments have been described with reference to the accompanying drawings, the embodiments shown above are examples, and can be modified and changed by those skilled in the art with ordinary knowledge in the relevant technical fields without departing from the technical spirit described in the claims.

Claims

1. A display apparatus comprising: a display panel including a pixel; a data driver connected to the pixel through a data line, the data driver generating a first data voltage for a low driving frequency based on a low-frequency gamma voltage, generating a second data voltage for a high driving frequency higher than the low driving frequency based on a high-frequency gamma voltage, and supplying the first data voltage or the second data voltage to the pixel; and a scan driver connected to the pixel through a gate line, the scan driver generating a first scan signal having a low-frequency scan-on time for the low driving frequency, generating a second scan signal having a high-frequency scan-on time different from the low-frequency scan-on time for the high driving frequency, and supplying the first scan signal or the second scan signal to the pixel, wherein the low-frequency scan-on time is determined when a difference between a low-frequency gamma voltage range of the low-frequency gamma voltage and a target gamma voltage range calculated based on a high-frequency gamma voltage range of the high-frequency gamma voltage is within a reference range. The target gamma voltage range is equal to the high-frequency gamma voltage range.

2. The display device according to claim 1, wherein The low-frequency gamma voltage range is defined from a first reference low-frequency gamma voltage corresponding to a first reference gray level to a second reference low-frequency gamma voltage corresponding to a second reference gray level higher than the first reference gray level, and 3. The display device of claim 2, wherein, wherein the target gamma voltage range is defined from a first reference high-frequency gamma voltage corresponding to the first reference gray level to a second reference high-frequency gamma voltage corresponding to the second reference gray level. When the low-frequency gamma voltage range is higher than the target gamma voltage range, the low-frequency scan-on time is reduced by a certain offset, and 4. The display device according to claim 2, wherein wherein when the low-frequency gamma voltage range is lower than the target gamma voltage range, the low-frequency scan-on time is increased by the offset. 5.A display apparatus comprising: a display panel including a pixel; an emission driver connected to the pixel through an emission signal line, the emission driver generating an emission signal based on an emission start signal having a number of emission cycles varying depending on a driving frequency, and supplying the emission signal to the pixel; and a controller generating the emission start signal, wherein when the driving frequency is changed between a low driving frequency and a high driving frequency higher than the low driving frequency, a buffer frame is inserted between a low-frequency frame driven at the low driving frequency and a high-frequency frame driven at the high driving frequency, and wherein a buffer emission cycle number of the emission start signal in the buffer frame is calculated based on a low-frequency emission cycle number of the emission start signal in the low-frequency frame and a high-frequency emission cycle number of the emission start signal in the high-frequency frame. The buffer emission cycle number is an average of the low-frequency emission cycle number and the high-frequency emission cycle number. 7.A display apparatus comprising:

6. The display device of claim 5, wherein, a display panel including a pixel; ​ ​ an emission driver connected to the pixel through an emission signal line, the emission driver generating an emission signal based on an emission start signal and supplying the emission signal to the pixel, the emission start signal having a number of emission cycles and an emission-off time which vary depending on a driving frequency; and a controller generating the emission start signal, wherein, when the display panel switches from a display-off state to a display-on state, a dummy frame is inserted before a start frame which is driven at a start driving frequency, and wherein at least one of the number of emission cycles and the emission-off time is different between the start frame and the dummy frame.

8. The display device of claim 7, wherein, a dummy emission-off time of the emission start signal in the dummy frame is greater than a start emission-off time of the emission start signal in the start frame.

9. The display device of claim 7, wherein, a dummy number of emission cycles of the emission start signal in the dummy frame is greater than a start number of emission cycles of the emission start signal in the start frame.

10. An electronic device comprising: the display device according to any one of claims 1 to 9, displaying an image; and a processor controlling the display device. ​

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