A floating gate charge sharing type compute-in-memory cell and method of use

Abstract

The application discloses a floating gate charge sharing type memory-computing integrated unit and a use method thereof, and belongs to the field of semiconductor technology. The erasable and writable storage weight value brought by the floating gate structure is utilized, and the weight value is judged by utilizing an electric charge coupling mechanism. The memory-computing integrated unit can be used as a memory and can also be used as a memory-computer, has the characteristics of small size, high dynamic range, high computing accuracy and non-volatility. The memory-computing integrated unit can also be constituted into a common floating gate structure to further reduce the equivalent area of devices in an array.

Description

TECHNICAL FIELD

[0001] The application provides a floating gate charge sharing type memory-computing integrated unit and a use method thereof, and belongs to the technical field of semiconductors. BACKGROUND

[0002] The feature of the separation of storage and computing in the Von Neumann architecture has helped the independent high-speed iterative development of memory and processors in the past few decades, but brings many limitations when processing neural network algorithms today, among which the most severe is the large language model. The core weight matrix only performs one calculation after a large-scale data transfer, resulting in a delay and power consumption of memory access far greater than that of calculation. In addition, the bandwidth between the memory and the processor is limited, and as the size of the neural network continues to expand, the amount of data grows exponentially, and the limited memory access bandwidth also becomes the main factor limiting the speed of network reasoning. Due to the separation of storage and computing, frequent data transmission will cause a large amount of energy consumption, and when implementing neural network algorithms using the Von Neumann architecture, many operation units will be in an idle state, resulting in a low energy efficiency utilization of computing resources. At the same time, neural network computing requires a large number of matrix vector multiplication calculations, and traditional digital multipliers processing such calculations require tens of thousands of transistors, greatly affecting the integration and energy efficiency ratio of the traditional scheme when processing such algorithms.

[0003] In order to overcome this limitation, people have proposed a memory-computing integrated scheme, which directly utilizes storage units for data processing by integrating storage functions and computing functions in the same chip or tightly coupled chip set. The feature of this scheme is that it can store neural network weights in a memory-computing integrated array composed of memory-computing integrated units, and can apply an excitation vector to the array to complete matrix vector multiplication calculation locally, effectively solving the hardware acceleration bottleneck of neural networks.

[0004] The existing computing and storage integrated solutions mostly use current domain readout, because the existing mainstream storage media, such as RRAM, FLASH and MRAM, all use the size of current to represent the weight, the accumulation in the formula can be simply obtained through the principle of Kirchhoff's law of current, and the current has strong anti-interference ability, good linearity, and is easy to realize signal amplification and processing; therefore, it can be considered that the current domain readout is a simpler and more convenient way for storage media to realize storage and computing; the Chinese patent with publication number CN118629456A discloses a three-transistor memory with a buried gate and a composite medium gate structure, a readout and write-in method and a storage and computing array, a three-transistor structure is formed by adding a buried gate structure on the basis of the existing composite medium gate double-transistor photosensitive detector, the buried gate structure is used to control the writing and erasing of the weight to the storage device, and the storage and readout of the charge information are realized by using the principle of charge coupling, thereby inheriting the characteristics of small size, high dynamic range and strong weight retention of the composite medium gate double-transistor photosensitive detector; however, the solution adopts the current domain readout mode, and a certain bias current needs to be continuously provided to maintain the readout, which will cause additional power consumption; in addition, non-ideal effects such as IR-Drop caused by parasitic resistance and temperature drift caused by changes in carrier mobility will reduce the accuracy of the final simulation result.

[0005] In addition, in the existing charge sharing type storage and computing solution, a capacitor is usually arranged outside the SRAM unit to convert the output voltage of the SRAM into a charge sharing output, so as to realize the charge sharing type SRAM analog domain storage and computing; however, there is a matching difference between the capacitors outside different SRAM units, which will cause uneven charge distribution and affect the calculation accuracy; in addition, the SRAM unit is composed of at least six tubes, and a capacitor unit needs to be added to convert the output into charge, so that the entire unit becomes more bloated, and the SRAM is a volatile device, so that the data stored therein will be lost when the power is cut off, thereby causing the calculation task to be interrupted, and frequent restart and reinitialization are required, which affects the performance of the device.

[0006] Therefore, the solution is not suitable for some application scenarios that require non-volatile deployment, and there is a lack of a non-volatile, high-density charge readout type storage and computing integrated unit and storage and computing integrated solution at the present stage. SUMMARY

[0007] In order to solve the existing problems, the present application provides a floating gate charge sharing type storage and computing integrated unit and a use method, which are used to realize charge domain readout, save array power consumption, avoid non-ideal effects caused by current readout such as IR-Drop and temperature drift, and improve the accuracy of array inference.

[0008] The first object of the present application is to provide a floating gate charge sharing type memory and computing integrated unit, which comprises a substrate, a weight storage tube and a charge coupling tube.

[0009] Optionally, the substrate serves as the base of the memory and computing integrated unit.

[0010] Optionally, a weight storage gate structure is arranged on the substrate, which comprises, from bottom to top, a bottom dielectric layer, a first floating gate, a first top dielectric layer and a first control gate, and an excitation drain is arranged in the substrate, and the excitation drain and the weight storage gate structure jointly form the weight storage tube.

[0011] Optionally, a charge coupling gate structure is arranged on the substrate, which comprises, from bottom to top, a bottom dielectric layer, a second floating gate, a second top dielectric layer and a second control gate; wherein a through hole exists on the second control gate and the second top dielectric layer, the periphery of the through hole is an insulating sidewall, and a metal filling in the middle directly contacts the floating gate; the charge coupling gate structure and the substrate jointly form the charge coupling tube, and the charge coupling tube does not have a source and a drain in the substrate.

[0012] Optionally, the bottom dielectric layer, the first top dielectric layer, the second top dielectric layer and the insulating sidewall around the through hole are one of silicon dioxide and silicon nitride or a combination thereof; the first floating gate, the first control gate, the second floating gate and the second control gate are polycrystalline silicon.

[0013] The second object of the present application is to provide a use method of the floating gate charge sharing type memory and computing integrated unit, which comprises:

[0014] applying a positive high voltage to the first control gate applying voltages to the excitation drain and the substrate so that a positive bias is formed between the first control gate and the substrate, and the voltages of the excitation drain and the substrate do not need to be the same, at this time, a strong electric field exists between the first floating gate and the substrate, and the electrons in the substrate enter the first floating gate through a tunneling mechanism, thereby increasing the threshold voltage of the weight storage tube;

[0015] applying a negative high voltage to the first control gate applying voltages to the excitation drain and the substrate so that a negative bias is formed between the first control gate and the substrate surface, and the voltages of the excitation drain and the substrate do not need to be the same, at this time, a strong electric field exists between the first floating gate and the substrate, and the electrons in the first floating gate enter the substrate through a tunneling mechanism, thereby decreasing the threshold voltage of the weight storage tube;

[0016] applying a voltage to the second control gate applying a fixed positive voltage to the first control gate of the selected memory and computing integrated unit As excitation, if the threshold voltage of the weight storage tube is greater than , the weight storage tube cannot be opened, and if the threshold of the storage-computation integrated unit is less than , the weight storage tube can be opened;

[0017] The substrate and the excitation drain are first applied with for 10 ms, and then switched to a negative bias At this time, a depletion region appears in the substrate below the charge-coupled tube due to the bias of the gate substrate, and since the depletion region has just been formed, it has not had time to generate electrons through recombination.

[0018] If the weight storage tube can be opened, the depletion region in the substrate below the charge-coupled tube can quickly replenish electrons through the excitation drain, at which time the potential in the second floating gate is:

[0019]

[0020] wherein is the second floating gate-bottom layer dielectric layer-substrate capacitance, is the second top layer dielectric layer capacitance, is the surface potential of the substrate of the charge-coupled tube, and its value is approximately:

[0021]

[0022] wherein, is the Fermi potential of the semiconductor;

[0023] If the weight storage tube cannot be opened, the depletion region in the substrate below the charge-coupled tube is in a null well state, and the surface potential of the substrate is , and the potential in the second floating gate is Therefore, the weight of the storage-computation integrated unit can be determined by the size of the potential in the second floating gate.

[0024] A third object of the present application is to provide a scheme for forming a storage-computation integrated array using a substrate-isolated floating gate charge sharing type storage-computation integrated unit, in which the charge-coupled tubes of two storage-computation integrated devices in adjacent rows are adjacent, share the same substrate, and are separated by shallow trench isolation between the shared substrates, share a second floating gate, a second top layer dielectric layer, a second control gate, an excitation drain, and a floating gate via structure to save area; the write drains of all storage-computation integrated units in the array are connected to their substrates through metal lines; the floating gates of storage-computation integrated units in the same column are connected to form an FGL, and the first control gates of storage-computation integrated units in the same row are connected to form a word line WL.

[0025] A fourth object of the present application is to provide a use method for a substrate-isolated floating gate charge sharing type storage-computation integrated array, in which, during inference computation, different WLs are respectively excited with a voltage of 0 or Vw according to actual conditions, and the potential of the FGL in a certain column is:

[0026]

[0027] wherein is the number of the column of the storage and computing integrated unit, is the substrate surface potential of the first storage and computing integrated unit in the column, and the FGL potential is the multiplication and accumulation result of the column weight value and the applied excitation vector.

[0028] The beneficial effects of the present application are:

[0029] The floating gate charge sharing type storage and computing integrated unit and the use method thereof provided by the present application can use the tunneling mechanism to change the amount of charge and further change the threshold voltage characteristics of the transistor for weight storage by using the floating gate structure. The transistor is connected to a transistor capacitor, and the external potential can form a potential directly related to the weight size in the capacitor. The floating gate of the transistor capacitor has a via, and the potential thereof can be read out through the floating gate by using the charge coupling mechanism, and thus the weight value is determined. The structure device can be used as a memory and a storage and computing device. Compared with the classical current domain storage and computing integrated scheme, the storage and computing integrated unit with floating gate readout potential has the characteristics of small size, low power consumption, high dynamic range, high calculation accuracy, and non-volatility. The storage and computing integrated unit can also constitute a common floating gate structure to further reduce the equivalent area of the device in the array. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0031] Figure 1 is a cross-sectional view of a floating gate charge sharing type storage and computing integrated unit provided by the first embodiment of the present application;

[0032] Figure 2 is a schematic diagram of a floating gate charge sharing type storage and computing integrated unit provided by the first embodiment of the present application;

[0033] Figure 3 is an array structure diagram composed of floating gate charge sharing type storage and computing integrated units provided by the second embodiment of the present application;

[0034] Figure 4 is a cross-sectional view of a common excitation drain level and a common charge coupling gate structure in the array composed of four floating gate charge sharing type storage and computing integrated units described in the second embodiment of the present application;

[0035] Figure 5 is a structural schematic diagram in the WBL direction of an array composed of the floating gate charge sharing type memory and computing integrated unit described in embodiment two of the present application;

[0036] Figure 6 is a cross-sectional view and a top view of an array structure composed of the column substrate isolation type floating gate charge sharing type memory and computing unit described in embodiment three of the present application;

[0037] Figure 7 is a connection schematic diagram of an array composed of the column substrate isolation type floating gate charge sharing type memory and computing unit described in embodiment three of the present application. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the embodiments of the present application more obvious, each embodiment according to the present application will be described in detail below with reference to the drawings, in the specification and drawings, substantially the same steps and elements are denoted by the same reference signs, and repeated explanations of these steps and elements will be omitted.

[0039] It should be understood that the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments described in the present application, all other embodiments obtained by those skilled in the art without creative labor should fall within the protection scope of the present application. Moreover, in order to make the specification more concise, detailed descriptions of functions and structures well known in the art will be omitted.

[0040] Three preferred embodiments of the memory device and the manufacturing method of the device according to the present application will be described in detail below with reference to the drawings. The embodiments described in the present application are only examples and not limitations, the steps and devices in each embodiment in the present application are not limited to be implemented in only one embodiment, and those skilled in the art can combine and combine some steps and devices from the separately described embodiments to achieve the effects of the present application according to the concept of the present application, and some variations, modifications, changes, additions and sub-combinations of these embodiments form embodiments which are also included in the present application, which will not be described one by one here.

[0041] Embodiment one

[0042] The present embodiment provides a floating gate charge sharing type memory and computing integrated unit and a use method, the structure of the unit is shown in Figure 1The system includes a substrate, a weighted storage transistor, and a charge-coupled transistor (CCT). The substrate is a P-type substrate shared by two transistors in the in-memory computing unit. The weighted storage transistor includes an excitation drain and a weighted storage gate structure. The excitation drain is disposed in the substrate and is N-type doped. The weighted storage gate structure includes, from bottom to top, a bottom dielectric layer, a first floating gate, a first top dielectric layer, and a first control gate. The CCT includes a charge-coupled transistor structure, which includes, from bottom to top, a bottom dielectric layer, a second floating gate, a second top dielectric layer, and a second control gate. A via is provided on the second top dielectric layer and the second gate. The via is surrounded by insulating sidewalls and filled with metal in the middle to directly contact the floating gate.

[0043] Figure 2 This is the schematic diagram of the corresponding floating-gate charge-sharing in-memory computing unit, where the weight storage transistor is located. Figure 2 The image shows a floating-gate transistor pattern. Since charge-coupled transistors (CCTs) do not have source or drain electrodes within the substrate, and their primary function is charge coupling, therefore... Figure 2 The image in the middle shows the capacitor pattern, and the substrate surface of the charge-coupled device is... Figure 2 In the diagram, the capacitance sample below node X is the depletion region capacitance formed after applying a gate substrate bias voltage between the second control gate and the substrate. The two capacitors above node X represent the bottom dielectric layer capacitance and the second top dielectric layer capacitance, respectively. Node Y is a floating gate node connected by a via structure.

[0044] To map neural network weights to the device, the device needs to be programmed and erased. The weights of this floating gate charge-shared in-memory computing unit are stored in the first floating gate, which is physically represented by the number of electrons in the first floating gate.

[0045] When programming the device, a positive voltage of 5V is applied to the first control gate, 0V is applied to the second control gate, and -5V is applied to the excitation drain and substrate. At this time, there is a strong electric field between the first floating gate and the substrate pointing from the first floating gate to the substrate. Electrons in the substrate enter the first floating gate through the FN tunneling mechanism under the action of this strong electric field, increasing the number of electrons in the first floating gate. This makes the potential in the first floating gate lower under the same first control gate voltage, thereby reducing the inversion degree of the weighted storage tube, which is equivalent to increasing the threshold voltage of the device.

[0046] When the device needs to be erased, a negative high voltage of -10V is applied to the first control gate, and 0V is applied to the excitation drain, the second control gate, and the substrate. At this time, there is a strong electric field between the first floating gate and the substrate pointing from the substrate to the first floating gate. Electrons in the first floating gate enter the substrate through the FN tunneling mechanism under the action of this strong field, reducing the number of electrons in the first floating gate. This makes the potential of the first floating gate higher under the same first control gate, thereby making the inversion degree of the weighted storage tube higher, which is equivalent to reducing the threshold voltage of the device.

[0047] When reading the device, 0V is applied to the second control gate, and 3V is applied to the first control gate of the unit to be read as a logic 1 excitation. In the previous programming and erasing process, if the threshold voltage of the device is less than 3V, it is considered that the weight value 1 is written, and at this time, the weight storage tube of the unit is turned on; if the threshold voltage of the device is greater than 3V, it is considered that the weight value 0 is written, and the weight storage tube is not turned on. For example, in the case where the threshold voltage is greater than 3V (i.e. the weight value 0 is written), even if 3V excitation is applied to the first control gate, it will not be turned on; and if the excitation is 0V (logic 0), even if the threshold voltage is less than 3V (weight value 1 is written), it will not be turned on. After the excitation is applied, the substrate of the storage and calculation unit and the excitation drain are switched from 0V to -3V at the same time, and in this transient state, the depletion region under the charge-coupled tube is just formed, and the electrons are not generated in time through recombination, and the device is in the empty well state.

[0048] If the weight storage tube can be turned on, the device will provide electrons from the excitation drain (at this time, -3V) until the surface is inverted.

[0049] If the weight storage tube cannot be turned on, the device will remain in a depleted state, and at this time, the substrate surface potential coupled by the second floating gate of the charge-coupled tube is higher.

[0050] As can be seen from the above, if the device stores the weight value 1 (the threshold voltage of the weight storage tube is lower), and excitation 1 is given (positive voltage is applied to the first control gate), the potential on the second floating gate of the unit will decrease, and by measuring the potential on the second floating gate, the weight value written in the device previously can be determined, and the weight value and the excitation complete a 1-bit by 1-bit multiplication operation.

[0051] Embodiment Two

[0052] This embodiment provides a floating gate charge sharing type storage and calculation integrated array and a use method, the array is as shown in Figure 3 The first control gates of the storage and calculation units in the same row are connected to form a word line (shown as WL in the figure), and the second control gates of the whole array are connected to ground in Figure 3 , and since the potential of the second control gate is always the same and is always 0V in each mode, the second control gates of the whole array can be connected and grounded; the excitation drains of the storage and calculation units in the same column are connected to form a write bit line (shown as WBL in the figure), and the substrates of the whole array are connected in Figure 3 , and since the potential of the substrate is always the same, and the substrates of the array are not completely isolated for different units, the substrates of the whole array need to be connected; the floating gates of the storage and calculation units in the same column are connected to form a floating gate line (shown as FGL in the figure) by a through hole.

[0053] In actual manufacture, considering the reduction of device size, two devices can share the excitation drain or share the second floating gate and the second control gate, Figure 4 A connection mode of the same column floating gate sharing type device is shown, in which unit one shares the second floating gate and the second control gate with unit two, unit three and unit four respectively, the substrate depletion region isolation of different devices is realized by shallow trench isolation in the substrate, the substrate surface potential multiplication results of each other are not affected, and unit two and unit three share the excitation drain. The connection mode saves the unit area without affecting the actual function. The array structure formed by the connection mode is shown in Figure 5 .

[0054] Next, the methods of programming specific cells of the array, erasing the entire chip, reading out the weight of specific cells and array inference are introduced.

[0055] When programming specific cells, -5V is applied to the substrate of the entire array, 0V is applied to the second control gate of the entire array, in addition, 5V is applied to the WL corresponding to the selected cell, and 0V is applied to the WL corresponding to the non-selected cell, -5V is applied to the WBL corresponding to the selected cell, and 0V is applied to the WBL corresponding to the non-selected cell;

[0056] At this time, 5V is applied to the first control gate of the selected cell, the substrate and the excitation drain are connected to -5V, the gate substrate bias of the weight storage tube reaches 10V, which is sufficient to cause FN tunneling and write electrons into the first floating gate;

[0057] For the cell with WL selected and WBL not selected, at this time, 5V is applied to the first control gate, the substrate is -5V, the excitation drain is connected to 0V, the substrate surface of the device is clamped at 0V, and the gate substrate bias is only 5V, which is not enough to cause FN tunneling;

[0058] For the cell with WBL selected and WL not selected, at this time, 0V is applied to the first control gate, the substrate and the excitation drain are -5V, and the gate substrate bias is 5V, which is not enough to cause FN tunneling.

[0059] The erase operation is a global operation, 0V is applied to the second control gate of the entire array, 0V is applied to the substrate, -10V is applied to the WL, and 0V is applied to the excitation drain, at this time, the gate substrate bias of the weight storage tube of the entire array cell reaches -10V, which can cause FN tunneling to erase the electrons in the first floating gate.

[0060] Before the weight of a specific cell is read out, the reference potential of each FGL needs to be adjusted: 0V is applied to the second control gate of the whole array, 0V is applied to the first control gate of the whole array, and the write drain and the substrate of the whole array are switched together from 0V to -5V. After the switching is completed, the potential of each FGL in the array is detected, and the potential is adjusted to zero as the reference when all cells are not turned on. After that, the readout operation is performed on the specific cell. Similarly to determining the reference potential, 0V is applied to the second control gate of the whole array, 3V is applied to the WL of the selected cell, and 0V is applied to the WL of the unselected cell. Then, the write drain and the substrate of the whole array are switched together from 0V to -5V. If the weight of the device is 0 (the threshold voltage is greater than 3V), the weight storage tube is not turned on, the depletion region remains depleted, and the potential of the FGL corresponding to the selected cell does not change. If the weight of the device is 1 (the threshold voltage is less than 3V), the weight storage tube is turned on, the depletion region is filled with electrons from the stimulating drain in an instant, and the second floating gate potential of the charge-coupled tube is lowered by a fixed value , a potential drop of a fixed value can occur on the corresponding FGL potential, so the weight size of the selected device can be determined by the potential of the FGL.

[0061] When reasoning for the whole array, similarly to the weight readout of a single cell, 0V is applied to the second control gate of the whole array, 3V is applied to the WL corresponding to the stimulating, and 0V is applied to the WL of the unselected. Then, the write drain and the substrate of the whole array are switched together from 0V to -5V. At this time, the weight in the weight storage tube and the voltage on the WL of the whole array are multiplied, and are reflected on the substrate surface potential below the cell charge-coupled tube. The potential on the FGL is lowered to , , which is the number of cells with stimulating and weight of 1 on this column. Thus, the matrix vector multiplication calculation of the array is completed.

[0062] Embodiment Three

[0063] This embodiment provides a substrate-isolated floating gate charge-sharing type storage and calculation integrated array and a method for using the same. The structure of the substrate-isolated floating gate charge-sharing type storage and calculation integrated cell in the array is as shown in Figure 6 . The substrate is completely isolated between columns in the array using an insulating medium layer, so that different substrate voltages can be applied between different columns without short circuiting. The structure of the array is as shown in Figure 7 . The stimulating drain of the storage and calculation integrated cell in the same column in the array can be directly connected to the substrate of the column as the WBL, the second floating gate of the cell in the same column is connected through a via and forms the FGL, the first floating gate of the cell in the same row is directly connected to form the WL, and the second control gate of the whole array can be connected and grounded.

[0064] Next, the method for programming a specific cell, erasing the whole chip, reading out the weight of a specific cell, and reasoning for the array is introduced.

[0065] When programming a particular cell, 5V is applied to the WL corresponding to the selected cell, and 0V is applied to the WL corresponding to the unselected cell, -5V is applied to the WBL corresponding to the selected cell, and 0V is applied to the WBL corresponding to the unselected cell.

[0066] At this time, 5V is applied to the first control gate of the selected cell, -5V is applied to the substrate and the stimulating drain, and the gate-substrate bias of the weight storage tube reaches 10V, which is sufficient to cause FN tunneling to write electrons into the first floating gate.

[0067] For a cell in which the WL is selected and the WBL is not selected, at this time, 5V is applied to the first control gate, the substrate is 0V, the stimulating drain is connected to 0V, and the gate-substrate bias is only 5V, which is not sufficient to cause FN tunneling.

[0068] For a cell in which the WBL is selected and the WL is not selected, at this time, 0V is applied to the first control gate, the substrate and the stimulating drain are -5V, and the gate-substrate bias is 5V, which is not sufficient to cause FN tunneling.

[0069] The erase operation is a global operation, in which -10V is applied to the WL and 0V is applied to the WBL. At this time, the gate-substrate bias of the weight storage tube of the entire array of cells reaches -10V, which can cause FN tunneling to erase the electrons in the first floating gate.

[0070] Before reading out the weight of a particular cell, the reference potential of each FGL needs to be adjusted. 0V is applied to the WL of the entire array, and the WBL of the entire array is switched from 0V to -5V. After the switching is completed, the potential of each FGL in the array is detected, and the potential is adjusted to zero as the reference when all cells are not turned on. After that, the readout operation can be performed on a particular cell. Similarly to determining the reference potential, 3V is applied to the WL of the selected cell, and 0V is applied to the WL of the unselected cell. Then, the WBL of the entire array is switched from 0V to -5V. If the weight of the device is 0 (the threshold voltage is greater than 3V), the weight storage tube is not turned on, and the depletion region remains in a depleted state, and the potential of the FGL corresponding to the selected cell does not change. If the weight of the device is 1 (the threshold voltage is less than 3V), the weight storage tube is turned on, and the depletion region is filled with electrons from the stimulating drain in an instant, and the potential of the second floating gate of the charge-coupled tube is lowered by a fixed value , which can cause a potential drop of a fixed value on the corresponding FGL, so that the weight of the selected device can be determined by the potential of the FGL.

[0071] When reasoning the whole array, similarly to the single cell weight readout, 0V is applied to the second control gate of the whole array, 3V is applied to the corresponding excited WLs, 0V is applied to the unselected WLs, and the WBL is switched from 0V to -5V together, at this moment the weight in the weight storage tube and the voltage on the WL all realize multiplication, and are reflected to the potential of the substrate surface below the cell charge coupled tube, finally the potential on the FGL is pulled down to , is the number of cells with both excitation and weight being 1 on this column, at this time the array completes the matrix vector multiplication calculation.

[0072] The benefit of the substrate isolation is that the potential of the excitation drain of the storage and computing cell and the substrate can be the same in different modes without additional area, reducing the difficulty of controlling the array.

[0073] As mentioned above, the above specific embodiments described in the present application are only examples and not limitations, and those skilled in the art can combine and combine some steps and devices from the above separately described various embodiments according to the concept of the present application to achieve the effect of the present application, and such combined and combined embodiments are also included in the present application, and such combination and combination is not described here.

[0074] Note that the advantages, advantages, effects, etc. mentioned in the present application are only examples and not limitations, and these advantages, advantages, effects, etc. cannot be considered as the must-have of each embodiment of the present application. In addition, the above specific details of the application are only for the purpose of example and for the purpose of understanding, and not for the purpose of limitation, and the above details do not limit the present application to the above specific details.

[0075] The block diagrams of the devices, apparatuses, equipment, systems involved in the present application are only illustrative examples and are not intended to require or imply that the connection, arrangement, configuration shown in the block diagram must be connected, arranged, configured. As those skilled in the art will recognize, these devices, apparatuses, equipment, systems can be connected, arranged, configured in any manner. Words such as "include", "contain", "have" and the like are open-ended words, which mean "including but not limited to", and can be used interchangeably. The words "or" and "and" used herein mean the word "and / or", and can be used interchangeably unless the context clearly indicates otherwise. The word "such as" used herein means the phrase "such as but not limited to", and can be used interchangeably.

[0076] The flowcharts herein and above method descriptions are only meant to be exemplary examples and are not intended to require or imply that the steps of the various embodiments must be performed in the order presented. As will be appreciated by one of skill in the art, the order of the steps in the above embodiments can be changed, as can other implementations of the application. Words such as "thereafter", "then", "next", etc. are generally not intended to limit the order of the steps; these words are simply used to guide the reader through the description of the methods. Furthermore, any reference to singular also includes the plural unless otherwise clear from the context. For example, when a singular "a" or "an" is used herein, that is only to be understood as meaning "one or more" unless otherwise indicated from the context.

[0077] In addition, the steps and apparatuses in the various embodiments herein are not limited to being performed only in the embodiment in which they are described, but in fact, can be combined with related parts of steps and apparatuses in the various embodiments herein to conceive new embodiments in accordance with the concept of the present application, and these new embodiments are also included in the scope of the present application.

[0078] The methods of the present application include one or more acts for accomplishing the described methods. The methods and / or acts can be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of acts is specified, the order and / or use of specific acts can be modified without departing from the scope of the claims.

[0079] The above description of presented aspects is given for non- limiting example only and various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other aspects without departing from the scope of the application. Thus, the present application is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0080] Some steps in the embodiments of the present application can be realized by software, and the corresponding software program can be stored in a readable storage medium, such as an optical disc or a hard disk, etc.

[0081] The above description is merely the preferred embodiment of the present application, and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A floating gate charge sharing type compute-in-memory cell, characterized in that, The memory-computing integrated unit comprises a substrate, a weight storage tube and a charge-coupled tube; The substrate serves as the base of the memory-computing integrated unit and is provided with an excitation drain therein; The weight storage tube comprises an excitation drain and a weight storage gate structure, and the weight storage gate structure comprises, from bottom to top, a bottom dielectric layer, a first floating gate, a first top dielectric layer and a first control gate; The charge-coupled tube comprises a substrate and a charge-coupled gate structure, and the charge-coupled gate structure comprises, from bottom to top, a bottom dielectric layer, a second floating gate, a second top dielectric layer and a second control gate; a floating gate via is provided on the second control gate and the second top dielectric layer, an insulating sidewall is provided around the floating gate via, and a metal is filled in the floating gate via to directly contact the floating gate; the charge-coupled tube is not provided with a source and a drain in the substrate; The floating gate via is directly connected to the second floating gate, and the calculation of the weight stored in the memory-computing integrated unit is realized through the second floating gate. 2.The all-memory computing cell of claim 1, wherein, The bottom dielectric layer, the first top dielectric layer, the second top dielectric layer and the insulating sidewall around the via are one of silicon dioxide and silicon nitride or a combination thereof; The first floating gate, the first control gate, the second floating gate and the second control gate are polycrystalline silicon; and the via is one of titanium silicide, titanium nitride and tungsten or a combination thereof.

3. A method for using a floating-gate charge-sharing type in-memory computing unit, characterized in that, The method is realized based on the memory-computing integrated unit of claim 1 and 2; and the method realizes the programming operation, the erasing operation and the readout operation of the memory-computing integrated unit by respectively applying voltages to the control gates of the weight storage tube and the charge-coupled tube.

4. The method of claim 3, wherein, The method comprises: Weight programming: applying positive voltage to the first control gate Applying voltage to the stimulating drain and the substrate, so that the control gate and the substrate form a positive bias, under the action of the electric field between the first floating gate and the substrate, the electrons of the substrate enter the first floating gate through the tunneling mechanism, and then increase the threshold voltage of the weight storage tube, realizing the programming operation; Weight Erase: Apply negative voltage to first control gate , and apply voltage to the stimulating drain and the substrate, so that a negative bias is formed between the first control gate and the substrate, and under the action of the electric field between the first floating gate and the substrate, the electrons in the first floating gate enter the substrate through the tunneling mechanism, thereby reducing the threshold voltage of the weight storage tube, and realizing the erase operation; Weight readout: apply voltage to second control gate Apply fixed positive voltage to first control gate of the weight storage cell to be read out As an incentive, if the threshold voltage of the weight storage cell is greater than The weight storage cell cannot open; if the threshold voltage of the weight storage cell is less than The weight storage cell opens normally.

5. The method of claim 4, wherein, The weight readout comprises: The substrate and the excitation drain are first applied for 10 ms, and then switched to a negative voltage A depletion region appears in the substrate below the dynode due to the gate insulator bias, and no electrons are generated; If the weight storage tube is open, the depletion region in the substrate below the charge-coupled tube is supplemented with electrons through the excitation drain, and at this time, the potential in the second floating gate is: wherein, is the second floating gate-bottom layer dielectric layer-substrate capacitance, is the second top layer dielectric layer capacitance, is the surface potential of the charge coupled diode substrate, expressed as: wherein the Fermi potential of the semiconductor; If the weight storage tube cannot be opened, the depletion region in the substrate under the charge-coupled tube is in a hollow state, and the substrate surface potential of the charge-coupled tube is , the potential in the second floating gate , the weight of the storage and calculation integrated unit is judged by the size of the second floating gate potential, and the readout operation is realized.

6. A floating-gate charge-sharing in-memory computing cell array, characterized in that, The array is realized based on the memory-computing integrated unit of claim 1 and 2; The array of the storage-computation integrated unit is An array of Rows Columns, two adjacent storage-computation integrated devices in the same row form a group, share a substrate, a second floating gate, a second top dielectric layer, a second control gate, and a floating gate via structure; the shared substrates are separated by shallow trench isolation; two adjacent groups of storage-computation integrated devices share an excitation drain; and the weight storage tubes of the storage-computation integrated devices in the same row are an integral whole; The first control gates of the memory-computing integrated devices in the same row are connected to form a word line WL; the excitation drains and the substrates of the memory-computing integrated devices in the same column are connected through a metal line to form a WBL line; and the second floating gates of the memory-computing integrated devices in the same column are connected to form an FGL.

7. A substrate-isolated floating-gate charge-sharing type compute-in-memory cell array, comprising: The substrate-isolated floating gate charge sharing type memory-computing integrated unit array is realized based on the memory-computing integrated unit of claim 1 and 2; The substrate-isolated floating gate charge-sharing type memory-computing integrated unit array is composed of a row and a column array, two adjacent memory-computing integrated devices in the same row form a group, share one substrate, a second floating gate, a second top dielectric layer, a second control gate and a floating gate via structure; the shared substrates are disconnected through shallow trench isolation; two adjacent groups of memory-computing integrated devices share one excitation drain; and the weight storage tubes of the memory-computing integrated devices in the same row are an integral whole; In the substrate-isolated floating gate charge sharing type memory-computing integrated unit array, the memory-computing integrated devices in the same column are isolated from each other by an insulating layer to ensure that the substrates of different columns apply different voltages without short circuiting; the excitation drains and the substrates of the memory-computing integrated devices in the same column are connected through a metal line to form a WBL; the floating gates of the memory-computing integrated devices in the same column are connected to form an FGL; and the first control gates of the memory-computing integrated devices in the same row are connected to form a word line WL.

8. A method of using a substrate-isolated floating-gate charge-sharing compute-in-memory cell array, comprising: The method is realized based on the array of claim 6 and 7; The method respectively applies 0 or voltage excitation to different word lines WL according to an excitation vector when performing calculation, so that the weight storage tube is turned off or turned on, and the potential of the substrate surface under the charge coupling tube of different calculation and storage integrated units in the array is jointly modulated by the voltage on the first control gate and the stored weight in the weight storage tube. The potential of the FGL on a certain column is wherein, is the number of columns of the memory-computing integrated cells, is the substrate surface potential of the memory-computing integrated cell in the column, is the substrate surface potential of the memory-computing integrated cell in the column, and FGL is the multiplication-accumulation result of the column weight of the memory-computing integrated cell and the applied excitation vector.

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