Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and the method comprises the steps: injecting first ions with smaller mass into a corresponding region of a substrate to form a first non-crystallization part, and then injecting second ions with larger mass in an inclined manner at an angle to form a second non-crystallization part wrapping the bottom and at least the side wall of the first non-crystallization part, therefore, the transverse width of the non-crystallization area is increased and the overall boundary morphology of the non-crystallization area is optimized, so that the transverse width and the longitudinal thickness of the formed metal silicide are ensured, and the problem of point discharge or easy breakdown caused by peak existence of the metal silicide is avoided. And the problem that the leakage current of the device is increased due to the fact that the metal silicide is punctured in the transverse direction and the longitudinal direction when the contact hole is etched is solved, and the reliability of the device is improved. Furthermore, the lower contour of the formed metal silicide is a curved surface through the combination of the first non-crystallization part and the second non-crystallization part, the contact area between the contact plug and the corresponding area of the substrate is increased, and the contact resistance of the contact plug is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, and particularly relates to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] At present, metal silicide has been widely used in the manufacturing process of semiconductor devices. For example, a self-aligned metal silicide process (i.e. a chemical reaction between metal and substrate silicon) is used to form metal silicide on the surface of the source-drain region of a MOS transistor. Then, a contact plug is formed on the metal silicide by processes such as deposition of an interlayer dielectric layer (ILD), etching of a contact hole (CT) in the interlayer dielectric layer, and deposition of a conductive metal material such as tungsten (W) in the contact hole. The presence of the metal silicide can enhance the bonding force between the source-drain region and the contact plug, and effectively reduce the contact resistance of the source-drain region, thereby improving the performance of the semiconductor device.

[0003] However, with the continuous development of integrated circuit manufacturing technology, the critical dimension of the device is continuously reduced, and the existing self-aligned metal silicide process will accordingly have many problems. For example, the formed metal silicide is relatively thin, which makes it difficult to further reduce the contact resistance between the contact plug and the source-drain region. For another example, the etching of the contact hole can cause the device to have increased leakage current due to the penetration of the metal silicide. Or the outer surface of the formed metal silicide is not smooth (for example, the silicide forms a sharp peak structure at the boundary), which causes the metal silicide formed in the silicon substrate to have some problems such as sharp discharge or easy breakdown, and cannot meet the requirement of further improving the performance of the device. SUMMARY

[0004] The present application aims to provide a semiconductor device and a manufacturing method thereof, which can control the morphology of the formed metal silicide, reduce the contact resistance of the device, and improve the reliability of the device.

[0005] To achieve the above-mentioned purpose, the present application provides a manufacturing method of a semiconductor device, which comprises the following steps:

[0006] providing a substrate, and forming a patterned silicide barrier layer on the substrate to define a region where metal silicide is to be formed;

[0007] performing a first pre-amorphization implantation into the substrate of the region using a first ion under the mask of the silicide barrier layer to form a first amorphous portion;

[0008] under the mask of the silicide blocking layer, a second pre-amorphization implantation is performed to the substrate in the region by using a second ion with atomic mass greater than the first ion and in a tilted ion implantation mode, so as to form a second amorphous portion located outside the first amorphous portion, the second amorphous portion wrapping the bottom and at least part of the sidewall of the first amorphous portion and gradually thinning from top to bottom;

[0009] depositing a metal and annealing, so that the metal reacts with the first amorphous portion and the second amorphous portion to form a desired metal silicide.

[0010] Optionally, the step of providing a substrate comprises:

[0011] providing a semiconductor substrate, and forming a gate structure on the semiconductor substrate;

[0012] forming a gate sidewall on the sidewall of the gate structure;

[0013] forming source-drain regions in the semiconductor substrate on both sides of the gate structure, so as to obtain the substrate.

[0014] Optionally, the step of forming a patterned blocking layer on the substrate comprises: depositing a silicide blocking layer, and performing photolithography and etching on the silicide blocking layer to form a patterned silicide blocking layer; wherein the source-drain region exposed by the patterned silicide blocking layer is the region to be formed with a metal silicide, or the gate structure is a polysilicon gate structure and the source-drain region and the polysilicon gate structure exposed by the patterned silicide blocking layer are the regions to be formed with a metal silicide.

[0015] Optionally, the second ion of the second pre-amorphization implantation also thins the sidewall of the silicide blocking layer, so as to increase the line width of the region.

[0016] Optionally, the line width of the region defined by the patterned silicide blocking layer on the top of the gate structure is 70% to 80% of the line width of the top of the gate structure.

[0017] Optionally, under the mask of the silicide blocking layer, a first pre-amorphization implantation is performed to the substrate in the region by using the first ion and in a vertical ion implantation mode, so that the lower profile formed by the sidewall and the bottom surface of the first amorphous portion is a curved surface convex to the bottom surface of the substrate; or under the mask of the silicide blocking layer, a plurality of first pre-amorphization implantations are performed to the substrate in the region by using the first ion at different angles, so that the lower profile formed by the sidewall and the bottom surface of the first amorphous portion is a circular arc surface or an elliptical arc surface convex to the bottom surface of the substrate.

[0018] Optionally, the manufacturing method further comprises at least one of the following:

[0019] (1) the closer to the center of the bottom surface of the first amorphous portion, the thinner the thickness of the second amorphous portion;

[0020] (2) the lower profile of the sidewall and the bottom of the metal silicide forms a curved surface convex to the bottom surface of the substrate, the curved surface being a circular arc surface or an elliptical arc surface;

[0021] (3) the first ions include at least one of Si, Ge and Ar;

[0022] (4) the second ions include Xe and / or Kr;

[0023] (5) the tilt angle of the tilted ion implantation method is 5° to 15°;

[0024] (6) the implantation dose of the first ions is 5e14 / cm2 to 2e15 / cm2, and the implantation energy is 15KeV to 25KeV;

[0025] (7) the implantation dose of the second ions is 5e14 / cm2 to 1e15 / cm2, and the implantation energy is 18KeV to 30KeV;

[0026] (8) the metal includes at least one of Ti, Co, Ni, W and Pt;

[0027] (9) the lower profile of the metal silicide in the substrate is smooth.

[0028] Optionally, the step of depositing a metal and annealing to form the metal silicide includes: depositing a metal and performing a first annealing to make the metal react with the first amorphous portion and the second amorphous portion to form a high-resistance phase of metal silicide; removing unreacted metal and performing a second annealing to convert the high-resistance phase of metal silicide into a low-resistance phase of metal silicide.

[0029] Optionally, after depositing the metal and before performing the first annealing, a cap layer is further deposited on the metal; after completing the first annealing and before removing the unreacted metal, the cap layer is removed first.

[0030] Optionally, the manufacturing method further includes, after forming the low-resistance phase of metal silicide:

[0031] sequentially depositing a contact hole etching stop layer and an interlayer dielectric layer;

[0032] etching the interlayer dielectric layer and the contact hole etching stop layer to form a contact hole exposing the metal silicide;

[0033] filling a conductive material in the contact hole to form a contact plug.

[0034] Based on the same inventive concept, the present application also provides a semiconductor device comprising a substrate and a metal silicide; wherein the substrate has a region where the metal silicide is to be formed, and the region originally has a first amorphous portion formed by implantation of first ions and a second amorphous portion formed by oblique implantation of second ions, the second ions having an atomic mass greater than that of the first ions, the second amorphous portion being located outside the first amorphous portion and wrapping around the bottom and at least part of the sidewall of the first amorphous portion, and the second amorphous portion gradually thins from top to bottom; the metal silicide is formed by reaction of a metal covering the surface of the region with the first amorphous portion and the second amorphous portion.

[0035] Optionally, the semiconductor device further comprises at least one of the following:

[0036] (1) the lower profile of the sidewall and the bottom surface of the first amorphous portion forms a curved surface convex to the bottom surface of the substrate, and the curved surface comprises a circular arc surface or an elliptical arc surface;

[0037] (2) the closer to the center of the bottom surface of the first amorphous portion, the thinner the thickness of the second amorphous portion;

[0038] (3) the lower profile of the sidewall and the bottom of the metal silicide forms a curved surface convex to the bottom surface of the substrate, and the curved surface is a circular arc surface or an elliptical arc surface;

[0039] (4) the first ions comprise at least one of Si, Ge and Ar;

[0040] (5) the second ions comprise Xe and / or Kr;

[0041] (6) the metal comprises at least one of Ti, Co, Ni, W and Pt;

[0042] (7) the lower profile of the metal silicide in the substrate is smooth;

[0043] (8) the substrate comprises a semiconductor substrate, a gate structure formed on the semiconductor substrate, a gate sidewall formed on the sidewall of the gate structure, and a source / drain region formed in the semiconductor substrate on both sides of the gate structure, wherein the region where the metal silicide is to be formed comprises a partial region of the source / drain region, or the gate structure is a polysilicon gate structure and the region where the metal silicide is to be formed comprises a partial region of the source / drain region and a partial top region of the gate structure.

[0044] Optionally, the semiconductor device further comprises:

[0045] a contact hole etching stop layer covering the substrate and exposing the corresponding portion of the metal silicide;

[0046] an interlayer dielectric layer covering on the contact hole etching stop layer and having a contact hole penetrating through the interlayer dielectric layer and the contact hole etching stop layer and exposing the metal silicide;

[0047] a contact plug filled in the contact hole and electrically contacting with the metal silicide.

[0048] Compared with the prior art, the technical scheme of the present application has at least one of the following beneficial effects:

[0049] 1. First, a first amorphous portion is formed in the region where the metal silicide is to be formed by implanting first ions with a smaller mass, and then second ions with a larger mass are implanted at an angle to form a second amorphous portion covering the bottom and at least part of the sidewall of the first amorphous portion, thereby increasing the lateral width of the amorphous region formed by the second amorphous portion and optimizing the overall boundary morphology of the amorphous region, and further ensuring the lateral width and longitudinal thickness of the metal silicide formed, avoiding the problem of the metal silicide being pierced in the lateral and longitudinal directions during contact hole etching, thereby increasing the device leakage current and improving the reliability of the device. In addition, the use of ions with two masses, smaller and larger, to form the main body of the amorphous region can obtain a smoother boundary surface of the metal silicide in the substrate, and the use of fewer second ions with a larger mass to focus on processing the outer part of the first amorphous portion (formed by the implantation of ions with a smaller mass) can achieve a smooth boundary surface of the metal silicide with the least amount of large mass ions, which is cost-effective.

[0050] 2. The lower profile of the amorphous region formed by the combination of the first amorphous portion and the second amorphous portion is curved, which can make the lower profile of the metal silicide formed based on the first amorphous portion and the second amorphous portion also curved, thereby increasing the contact area between the contact plug and the corresponding region of the substrate (i.e. the source-drain region and the gate layer), and further reducing the contact resistance between the contact plug and the corresponding region of the substrate, thereby further improving the electrical performance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0051] Those skilled in the art will understand that the provided drawings are for better understanding of the present application and do not constitute any limitation on the scope of the present application. Among them:

[0052] Figure 1 is a flowchart of a manufacturing method of a semiconductor device according to an embodiment of the present application.

[0053] Figures 2 to 8 is a schematic diagram of a device cross-sectional structure in the manufacturing method of a semiconductor device according to an embodiment of the present application. DETAILED DESCRIPTION

[0054] In the following description, a large number of specific details are given to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, some technical features known in the art are not described to avoid confusion with the present invention. It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. The same reference numerals throughout represent the same elements. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly connected to" another element, there are no intervening elements. When used herein, the singular forms "a," "an," and "said / the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of certain features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0055] The technical solutions proposed by the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in a very simplified form and are not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present invention.

[0056] Please refer to Figure 1 An embodiment of the present invention provides a method for manufacturing a semiconductor device, which includes the following steps:

[0057] S1, providing a substrate, and forming a patterned silicide barrier layer on the substrate to define an area where metal silicide is to be formed;

[0058] S2, performing a first pre-amorphization implantation into the substrate of the region using first ions under the mask of the silicide barrier layer to form a first amorphized portion;

[0059] S3, under the mask of the silicide barrier layer, using second ions with an atomic mass greater than that of the first ions and performing a second pre-amorphization implantation into the substrate of the region in an inclined ion implantation manner, so as to form a second amorphized portion located outside the first amorphized portion, wherein the second amorphized portion wraps around a bottom portion and at least a portion of a sidewall of the first amorphized portion and gradually becomes thinner from top to bottom;

[0060] S4, depositing metal and annealing to cause the metal to react with the first and second amorphized portions to form a desired metal silicide.

[0061] Referring to Figure 2 In step S1, the step of providing a substrate includes:

[0062] First, a semiconductor substrate 100 is provided, which can be any suitable substrate material in the art, such as monocrystalline silicon (Si), silicon-on-insulator (SOI), monocrystalline germanium (Ge), germanium-on-insulator (GeOI), silicon carbide (SiC), gallium arsenide (GaAs), indium phosphide (InP), etc. The semiconductor substrate 100 can have shallow trench isolation structures (not shown) formed therein by a shallow trench isolation process (including shallow trench photolithography, etching, and filling with insulating material) to define a plurality of MOS regions and other device regions in the semiconductor substrate 100.

[0063] Next, a corresponding gate structure is formed on the surface of each MOS region of the semiconductor substrate 100 by any suitable gate-first or gate-last process in the art, which includes a gate oxide layer 101 and a gate layer 102. The gate oxide layer 101 can be formed on the surface of the semiconductor substrate 100 by any suitable process such as thermal oxidation or chemical vapor deposition, and can be silicon dioxide, silicon oxynitride, silicon nitride, or a high-K material (such as hafnium-based oxide, etc.) having a dielectric constant K higher than that of silicon dioxide, and combinations thereof. The gate layer 102 can be polysilicon or any other suitable gate material such as metal. At this time, the top surface of the gate structure is typically also covered with a hard mask layer (not shown), which can be silicon nitride or silicon oxynitride, and combinations thereof.

[0064] Then, a gate sidewall can be formed on the sidewall of each gate structure by any suitable gate sidewall process in the art (including steps such as sidewall dielectric material deposition and etching). The gate sidewall can be a single-layer film structure or a multi-layer film structure formed of different sidewall materials. For example, the gate sidewall includes an inner sidewall 103a and an outer sidewall 103b formed of two different sidewall materials. The inner sidewall 103a can be silicon oxide, etc., and the outer sidewall 103b can be silicon nitride, etc.

[0065] After that, LDD (i.e., light-doped drain) implantation, heavy-doped ion implantation, etc. can be performed on the semiconductor substrate on both sides of the gate structure using n-type ions or p-type ions to form source / drain regions (not labeled). When a metal silicide is to be subsequently formed on the gate layer 102, the hard mask layer on the gate layer 102 can be removed before depositing a silicide barrier layer 104.

[0066] Referring toFigure 2 In step S1, a patterned silicide blocking layer 104 is formed on the substrate to define the region where the metal silicide is to be formed, and the specific process includes: first, a suitable deposition process such as atomic layer deposition process or chemical vapor deposition process is used to deposit a dielectric material such as silicon dioxide to form the silicide blocking layer 104, and then the silicide blocking layer 104 is subjected to photolithography and etching to form the patterned silicide blocking layer 104, so as to shield the surface of the region where the metal silicide is not to be formed by the patterned silicide blocking layer 104, and expose the surface of the region where the metal silicide is to be formed. The region where the metal silicide is to be formed can be part of the source / drain region, can be part of the top region of the gate structure, or can be part of the source / drain region and part of the top region of the gate structure.

[0067] The line width D of the opening of the patterned silicide blocking layer 104 on the top surface of the gate layer 102 in the gate structure (i.e. the region on the top of the gate layer 102 where the metal silicide is to be formed) can be equal to or less than the line width W of the top surface of the gate layer 102 in the gate structure. In an example, D is 70%-80% of W, so as to provide a margin for the consumption of the silicide blocking layer 104 on the top surface of the gate layer 102 in the gate structure and the gate side wall on the sidewall of the silicide blocking layer 104 in the subsequent wet cleaning, first ion implantation and second ion implantation, so as to ensure that the silicide blocking layer and the gate side wall on the top end of the sidewall of the gate layer 102 in the gate structure are not excessively reduced, and thus ensure that the metal silicide 110b formed on the top surface of the gate layer 102 in the subsequent process does not extend downward from the top surface of the gate layer 102 to the sidewall of the gate layer 102 to form a sharp corner, thereby ensuring the electrical connection performance between the gate and the contact plug above it.

[0068] Please refer to Figure 2 In step S2, under the masking of the silicide blocking layer 104, a first pre-amorphization implantation PAI 1 is performed on the source / drain region and the gate layer 102 in the region defined by the silicide blocking layer 104 by using first ions, and the first ions implanted will cause atomic dislocation of the crystal surface of the source / drain region and the gate layer 102 in the region, so as to induce the corresponding part of the source / drain region and the gate layer 102 in the region to be amorphized, and form a first amorphous part 105a in the top region of the source / drain region and a first amorphous part 105b in the top region of the gate layer 102.

[0069] The atomic mass of the selected first ions is close to the atomic mass of silicon in the substrate, and is smaller than the atomic mass of the second ions in the subsequent step S3. The first amorphous portion 105a can be easily formed in a relatively large range of amorphization in the implantation region, and the degree of amorphization caused thereby can be easily controlled, so that the thickness of the a-Si (amorphous silicon) and c-Si (crystalline silicon) at the interface of the first amorphous portion 105a is in an acceptable range, and the injection of the first ions does not cause serious adverse effects on the saturation region threshold voltage Vtsat, the leakage current Ioff and other parameters of the device.

[0070] In other examples of the present application, the atomic mass of the selected first ions can not be limited to be close to the atomic mass of silicon in the substrate, but still needs to be smaller than the atomic mass of the second ions in the subsequent step S3. Thus, by reasonable control of the process parameters of the first amorphization injection, the required range of amorphization in the implantation region can be achieved to form the required first amorphous portion, and the injection of the first ions can avoid causing serious adverse effects on the saturation region threshold voltage Vtsat, the leakage current Ioff and other parameters of the device.

[0071] As an example, under the masking of the silicide barrier layer 104, the first pre-amorphization injection PAI 1 is performed in the region defined by the silicide barrier layer 104 (i.e., the source and drain regions and the gate layer 102 defined thereby) using the first ions and in a vertical ion implantation manner. Thus, the first amorphous portion 105a and the first amorphous portion 105b with a curved lower profile (i.e., a profile composed of a side wall and a bottom surface) are formed by the diffusion of the implanted first ions in the substrate (i.e., the source and drain regions and the gate layer 102 defined thereby) in the region. At this time, the line width of the first amorphous portion 105a and the first amorphous portion 105b gradually decreases from top to bottom. In this example, the curved topography of the lower profile of the first amorphous portion 105a and the first amorphous portion 105b can be considered to be self-formed, and the controllability is relatively low.

[0072] In another example, under the mask of the silicide blocking layer 104, multiple first pre-amorphization implants PAI 1 with different angles are performed in the region defined by the silicide blocking layer 104 (i.e. the defined source-drain region and the gate layer 102), including the angle of the vertical implantation direction and multiple different angles within 10° of the vertical implantation direction, so that the first ions of the multiple implants diffuse in the substrate (i.e. the defined source-drain region and the gate layer 102) of the region to form the first amorphous portions 105a and 105b with a circular or elliptical arc lower profile (i.e. the profile composed of the sidewall and the bottom surface), and the line width of the first amorphous portions 105a and 105b gradually and accurately controllably decreases from top to bottom, and the thinning rate is relatively slow, preventing the metal silicide from being pierced from the side during the subsequent contact hole etching. The scheme of this example is more conducive to controlling the boundary morphology of the subsequently formed metal silicide.

[0073] In an example, Si (silicon) is selected as the first ion because the atomic mass of Si is relatively large compared to impurity ions such as C (carbon), P (phosphorus), B (boron), etc., which can better control the amorphization degree, form the first amorphous portions 105a and 105b with a relatively good lower profile curved surface morphology, and participate in the subsequent metal silicide reaction to form part of the metal silicide, thereby compensating for the consumption of intrinsic silicon in the substrate and the gate layer 102 when forming the metal silicide without introducing other ions, and avoiding the problem of uneven surface of the metal silicide due to excessive consumption of intrinsic silicon when forming the metal silicide, thereby reducing the adverse effects on device performance. At the same time, because more silicon ions are provided, when the metal silicide is formed by the deposited metal and silicon elements in the subsequent step S4, the formed metal silicide does not excessively penetrate into the substrate, so that the consumption of area and volume in the substrate due to the formation of the metal silicide is reduced, and the influence of the formation of the metal silicide on the electric field distribution in the substrate is reduced.

[0074] In other examples, in step S2, a mixture of one or more of Ge, Ar and Si ions can also be selected as the first ion for forming the first amorphous portions 105a and 105b.

[0075] In an example, the implantation dose of the first ion is 5e14 / cm 2 ~ 2e15 / cm 2 (e.g. 6e14 / cm 2 , 8e14 / cm 2 , 1e15 / cm 2 , 1.2e15 / cm 2 , 1.5e15 / cm 2The implantation energy is 15 KeV-25 KeV (for example, 18 KeV, 20 KeV, 22 KeV, etc.), and the implantation energy of the second ions is 15 KeV-25 KeV (for example, 18 KeV, 20 KeV, 22 KeV, etc.).

[0076] Reference is made to Figure 3 In step S3, under the mask of the silicide blocking layer 104, a second pre-amorphization implantation PAI 2 is performed on the source / drain region and the gate layer 102 in the region defined by the silicide blocking layer 104 by using second ions with atomic mass greater than the first ions in a tilted ion implantation manner. The implanted second ions will be implanted into the source / drain region outside (or periphery) of the first amorphous portion 105a and the gate layer 102 outside (or periphery) of the first amorphous portion 105b, causing atomic dislocation of the crystal surface in the implantation region, thereby inducing amorphization of the source / drain region and the gate layer 102 in the implantation region, so as to form a second amorphous portion 106a outside the first amorphous portion 105a in the source / drain region and a second amorphous portion 106b outside the first amorphous portion 105b in the top of the gate layer 102. The second amorphous portion 106a and the first amorphous portion 105a constitute an amorphous region in the top of the source / drain region (the bottom depth of which is mainly adjusted by the implantation energy and dose of the first ions), and the second amorphous portion 106b and the first amorphous portion 105b constitute an amorphous region in the top of the gate layer 102 (the bottom depth of which is mainly adjusted by the implantation energy and dose of the first ions).

[0077] In step S4, the oblique ion implantation method can implant most of the second ions into the source-drain region outside the first amorphous portion 105a and into the gate layer 102 outside the first amorphous portion 105b, and because the atomic mass of the second ions is greater than that of the first ions, the first amorphous portions 105a, 105b have a blocking effect on the implanted second ions, so the second amorphous portion 106a formed covers the bottom and at least part of the sidewall of the first amorphous portion 105a and gradually thins from top to bottom, the second amorphous portion 106b formed covers the bottom and at least part of the sidewall of the first amorphous portion 105b and gradually thins from top to bottom, the second amorphous portion 106a and the second amorphous portion 106b respectively form a thin α-Si and c-Si at the interface between the amorphous region and the crystalline region of the source-drain region and the gate layer 102, so as to cover the thicker α-Si and c-Si generated by the first amorphous portions 105a, 105b respectively, thereby improving the saturation threshold voltage Vtsat, drain current Ioff and other parameter performances of the device. Moreover, the gradually thinning thickness of the second amorphous portion from top to bottom can also increase the overall lateral width of the amorphous region formed and optimize the overall boundary morphology of the amorphous region, ensure the lateral width and longitudinal thickness of the metal silicide formed subsequently, avoid the problem of piercing the metal silicide in the lateral and longitudinal directions during the subsequent contact hole etching, thereby causing the device to have increased leakage current, and improve the reliability of the device. At the same time, because the second amorphous portion formed by the second ions with a larger mass covers the region outside the first amorphous portion formed by the first ions with a smaller mass, a thin layer of large-mass ion covering layer is formed, which not only improves the edge morphology of the metal silicide formed subsequently (can make the lower profile morphology of the metal silicide smoother and clearer, thereby preventing the sharp tip discharge or leakage caused by the sharp peak structure), but also, the main part of the amorphous region is the superposition of the amorphous portions formed by ions of different masses, which has a lower cost compared to using only large-mass ions to form the amorphous portion.

[0078] In an example, the lower profile of the first amorphous portion 105a and the second amorphous portion 105b is a curved surface such as a circular arc surface or an elliptical arc surface, and the side thickness of the first amorphous portion 105a and the second amorphous portion 105b gradually increases from top to bottom, and the blocking effect of the injected second ions gradually increases, and the blocking effect of the central bottom of the first amorphous portion 105a and the second amorphous portion 105b to the second ions is the largest, thereby making the thickness of the formed second amorphous portions 106a and 106b gradually thin from top to bottom. At this time, the second amorphous portion 106a can only wrap on the side wall of the first amorphous portion 105a (can cover the entire side wall surface of the first amorphous portion 105a, or can only cover the surface of the upper part of the side wall of the first amorphous portion 105a), or can wrap on the entire side wall surface and part or all of the bottom surface of the first amorphous portion 105a, and the second amorphous portion 106a gradually thins from top to bottom along the lower profile curved surface of the first amorphous portion 105a, and the thickness of the second amorphous portion 106a located at the central bottom of the first amorphous portion 105a is the thinnest. Similarly, the second amorphous portion 106b can only wrap on the side wall of the first amorphous portion 105b (can cover the entire side wall surface of the first amorphous portion 105b, or can only cover the surface of the upper part of the side wall of the first amorphous portion 105b), or can wrap on the entire side wall surface and part or all of the bottom surface of the first amorphous portion 105b, and the second amorphous portion 106b gradually thins from top to bottom along the lower profile curved surface of the first amorphous portion 105b, and the thickness of the second amorphous portion 106b located at the central bottom of the first amorphous portion 105b is the thinnest.

[0079] Therefore, by controlling the formation of the first amorphous portions 105a and 105b and the second amorphous portions 106a and 106b, and using the blocking effect of the first ions on the second ions at a lower cost, an amorphous region with ideal topography can be formed, the lateral width of the amorphous region is increased and the side thickness gradually thickens along the curved surface, thereby effectively preventing the problem of piercing the metal silicide during contact hole etching, and avoiding the problem of increasing device leakage current.

[0080] In addition, the second ions are preferably ions of elements that do not participate in the metal silicidation reaction. On one hand, the second ions are relatively more difficult to diffuse during the annealing process of the subsequent step S4, and thus the distribution of the second ions is more controllable than that of the first ions and silicon atoms, etc. The boundary of the second amorphous region formed by the second ions is more ideal, and thus the metal silicidation reaction in the subsequent step S4 can be limited to the range defined by the second amorphous region, and the boundary and morphology of the lower profile of the metal silicide formed can be optimized. For example, the lower profile of the metal silicide region (i.e., the boundary formed by the bottom surface and the sidewall) can be a smooth curved surface, and the metal silicide formed can not have a sharp peak that causes a sharp end discharge or a breakdown problem. At the same time, the thickness and width of the metal silicide formed can be ensured, and the problem of the metal silicide being pierced during the contact hole etching can be avoided. On the other hand, the thickness of the sidewall of the silicide barrier layer 104 (i.e., the silicide barrier layer 104 on the gate sidewall is thinned, as shown by the dashed line in Figure 3 ), and thus the silicide barrier layer 104 can be less shielded by the second ion implantation, the second ion implantation window can be increased, the lateral width of the amorphous region can be further increased, and the wrapping area of the second amorphous region around the first amorphous region can be increased. It should be understood that, although the silicide barrier layer 104 is thinned to a certain extent by the second ion implantation, the silicide barrier layer 104 can still cover the regions that do not need to form metal silicide, and thus the metal silicide formed on the surface of the regions in the subsequent step S4 can be avoided.

[0081] In an example, the second ions include at least one inert element of Xe and Kr, the implantation dose of the second ions is smaller than that of the first ions, and the implantation energy of the second ions is greater than that of the first ions. For example, the implantation dose of the second ions is 5e14 / cm 2 ~1e15 / cm 2 , and the implantation energy of the second ions is 18KeV~30KeV.

[0082] It should be understood that the first ions and the second ions in the embodiment can be plasma generated by plasma treatment of corresponding gases. The first ions and the second ions are neutral relative to the electrons and positive charges flowing between the source and the drain after the MOS transistor is turned on, and thus the performance of the MOS transistor formed can be avoided.

[0083] Please refer to Figures 4 to 6 , the self-aligned metal silicidation process is performed in step S4 to form the metal silicides 110a and 110b. The specific process is as follows:

[0084] First, please refer to Figure 4 , any suitable pre-cleaning process in the art can be used to pre-clean the substrate to remove the natural oxide on the surface of the source and drain region and the gate layer 102, so as to avoid affecting the formation of the metal silicide.

[0085] Next, refer to Figure 4 The metal 107 can be deposited on the silicide barrier 104 and the exposed surface of the region by any suitable process such as sputter deposition (ALPS), PVD, etc. The metal 107 can include at least one of Ti, Co, Ni, W, Pt, etc.

[0086] Next, refer to Figure 4 The cap layer 108 can be deposited by any suitable process such as PVD, etc. The cap layer 108 can include at least one of Ti, W, or TiN, etc. The cap layer 108 does not react in the subsequent annealing process and is used to prevent the metal 107 from flowing in the subsequent annealing process to cause the thickness of the metal silicide to be uneven and the resistance to be locally non-uniform, and to protect the surface of the metal 107 from being oxidized and removed later. The cap layer 108 can be removed together with the excess metal after the first annealing.

[0087] Next, refer to Figure 5 The first annealing can be performed by any suitable annealing process such as conventional soak annealing (e.g., furnace tube annealing), RTA, FLA, spike annealing, or LSA, etc. The metal 107 on the source / drain region diffuses into the first amorphous portion 105a and the second amorphous portion 106a and reacts with Si to form the high resistance phase of the metal silicide 109a, and the metal 107 on the gate layer 102 diffuses into the first amorphous portion 105b and the second amorphous portion 106b and reacts with Si to form the high resistance phase of the metal silicide 109b. In this process, the second ions are more difficult to diffuse relatively, and the distribution position is more controllable than the first ions and Si atoms of smaller mass, so that the boundaries and topography of the first amorphous portion and the second amorphous portion limit the boundaries and topography of the metal silicide 109a and the metal silicide 109b, making the boundaries and topography of the metal silicide 109a and the metal silicide 109b smoother, avoiding the problem of the metal silicide having a sharp peak structure, and further avoiding the problem of the low resistance phase of the metal silicide formed based on the metal silicide 109a and the metal silicide 109b having a sharp peak to cause the sharp end to discharge or be prone to breakdown, while ensuring the thickness and width of the formed metal silicide to avoid the problem of the metal silicide being etched through during the subsequent contact hole etching.

[0088] In one example, the lower profile of the metal silicide 109a and the metal silicide 109b is a curved surface, such as a circular arc surface or an elliptical arc surface, and the sidewall of the metal silicide in the substrate is smooth. In addition, the upper profile (i.e., the upper surface) of the metal silicide 109a is determined by the upper surface profile of the source / drain region, and the upper profile (i.e., the upper surface) of the metal silicide 109b is determined by the upper surface profile of the gate layer 102, which is not limited in the present application.

[0089] Next, please refer to Figure 6 The cap layer 108 and the unreacted metal 107 can be removed by any suitable process, such as etching, and a second annealing is performed by any suitable annealing process, such as ordinary immersion annealing (e.g., furnace tube annealing), rapid thermal annealing (RTA), flash lamp annealing (FLA), spike annealing, laser spike annealing (LSA), or dynamic surface annealing (DSA), and the annealing temperature of the second annealing is generally higher than that of the first annealing, so as to convert the high-resistance phase metal silicide 109a into a low-resistance phase metal silicide 110a, and convert the high-resistance phase metal silicide 109b into a low-resistance phase metal silicide 110b.

[0090] In one example, after the metal silicides 110a, 110b are formed, the etching and filling process of the contact hole can be continued. The specific process is as follows:

[0091] First, please refer to Figure 7 The silicide barrier layer 104 can be retained or removed as needed, and the contact hole etching stop layer 111 and the interlayer dielectric layer 112 are sequentially deposited on the substrate and the metal silicides 110a, 110b by any suitable process, such as atomic layer deposition or chemical vapor deposition, wherein the contact hole etching stop layer 111 can be a single film or multiple films including silicon dioxide, silicon nitride, silicon oxynitride, silicon oxycarbide, etc.; the interlayer dielectric layer 112 can include silicon dioxide, low-k dielectric with a dielectric constant k lower than that of silicon dioxide, etc. The thickness of the deposited contact hole etching stop layer 111 is relatively thin, and the thickness of the interlayer dielectric layer 112 is relatively thick, and the chemical mechanical polishing (CMP) process can be used to planarize the top of the deposited interlayer dielectric layer 112 to provide a better process surface for subsequent processes.

[0092] Next, please continue to refer to Figure 7The interlayer dielectric layer 112 and the contact hole etching stop layer 113 are etched by lithography and etching process (i.e. contact hole etching) to form a contact hole 113a exposing a partial region of the metal silicide 110a and a contact hole 113b exposing a partial region of the metal silicide 110b. In this step, over-etching can be performed to some extent during the contact hole etching to etch away a partial thickness of the metal silicides 110a and 110b, so that the bottom of the contact hole 113a reaches into the metal silicide 110a and the bottom of the contact hole 113b reaches into the metal silicide 110b. Since the lateral width and the vertical thickness of the metal silicides 110a and 110b are in accordance with the manufacturing requirements in the previous steps, the metal silicides 110a and 110b will not be penetrated during the contact hole etching in this step, and thus the leakage current at the contact plug position can be avoided.

[0093] Then, referring to Figure 8 A diffusion barrier layer (not shown) is formed by sputtering deposition, physical vapor deposition or chemical vapor deposition, etc. using at least one material selected from Ti, Ta, TiN and TaN, and a conductive material such as Cu, W, etc. is deposited by electroplating, sputtering, evaporation, etc. to fill the contact holes 113a and 113b. The conductive material and the diffusion barrier layer outside the contact holes 113a and 113b are removed by chemical mechanical polishing, etc. to form a contact plug 114a (i.e. source / drain contact plug) in the contact hole 113a and a contact plug 114b (i.e. gate contact plug) in the contact hole 113b. Optionally, the lower profile of the metal silicides 110a and 110b is curved, which increases the contact area between the metal silicides 110a and the source / drain region below and between the metal silicides 110b and the gate layer 102 below, and thus reduces the contact resistance between the contact plug 114a and the source / drain region and between the contact plug 114b and the gate layer 102.

[0094] In summary, the method for manufacturing the semiconductor device of the present embodiment first implants first ions with a small mass to form a first amorphous portion with a small width, a thick thickness and a controllable amorphous degree in a region where a metal silicide is to be formed, then implants second ions with a large mass at an angle to form a second amorphous portion with a thin thickness and covering at least the sidewall of the first amorphous portion, and further uses the second amorphous portion to increase the lateral width of the amorphous region and optimize the overall boundary morphology of the formed amorphous region (the larger the ion mass, the easier to form a metal silicide with a good boundary morphology), thereby avoiding the problems of tip discharge or easy breakdown caused by the existence of a sharp peak of the metal silicide, and avoiding the problem of increased device leakage current caused by the metal silicide being pierced in the lateral and longitudinal directions during contact hole etching, and improving the reliability of the device. In addition, the lower profile of the amorphous region formed by the first amorphous portion and the second amorphous portion is a curved surface, which can make the lower profile of the metal silicide formed based on the first amorphous portion and the second amorphous portion also a smooth curved surface, thereby increasing the contact area between the contact plug and the corresponding region of the substrate (i.e. the source / drain region and the gate layer), reducing the contact resistance between the contact plug and the corresponding region of the substrate (i.e. the source / drain region and the gate layer), and further improving the electrical performance of the device.

[0095] Based on the same inventive concept, please refer to Figures 2 to 8 An embodiment of the present application further provides a semiconductor device which can be formed by using the method for manufacturing the semiconductor device of the present application or other suitable manufacturing method. The semiconductor device comprises a substrate and metal silicides 110a and 110b formed in a part of the substrate.

[0096] Optionally, the semiconductor device further comprises a contact hole etching stop layer 111 and an interlayer dielectric layer 112 which are sequentially stacked on the substrate and the metal silicide layer, and contact plugs 114a and 114b formed in the interlayer dielectric layer 112.

[0097] The substrate comprises a semiconductor base 100, a gate structure formed on the semiconductor base 100, a gate sidewall formed on the sidewall of the gate structure, and a source / drain region (not labeled) formed in the semiconductor base 100 on both sides of the gate structure. The gate structure comprises a gate oxide layer 101 formed on the semiconductor base 100 and a gate layer 102 formed on the gate oxide layer 101.

[0098] The region of the substrate where the metal silicide is to be formed comprises a part of the source / drain region. Alternatively, the gate structure is a polysilicon gate structure (i.e. the gate layer 102 is a polysilicon layer), and the region where the metal silicide is to be formed comprises a part of the source / drain region and a part of the top region of the gate layer 102.

[0099] The first amorphous portions 105a, 105b formed by the first ion implantation and the second amorphous portions 106a, 106b formed by the second ion oblique implantation in the region of the substrate where the metal silicide is to be formed (i.e. at least one of the source / drain regions and the gate layer 102), the atomic mass of the second ion being greater than the atomic mass of the first ion, and the second amorphous portion 106a being located outside the first amorphous portion 105a and wrapping around the bottom and at least the sidewall of the first amorphous portion 105a, and the second amorphous portion 106b being located outside the first amorphous portion 105b and wrapping around the bottom and at least part of the sidewall of the first amorphous portion 105b. The second amorphous portions 106a, 106b are gradually thinned from top to bottom. The second amorphous portion 106a covers a portion of the bottom surface of the first amorphous portion 105a, and the closer to the center of the bottom surface of the first amorphous portion 105a, the thinner the thickness; the second amorphous portion 106b covers a portion of the bottom surface of the first amorphous portion 105b, and the closer to the center of the bottom surface of the first amorphous portion 105b, the thinner the thickness.

[0100] Optionally, the first ion comprises at least one of Si, Ge and Ar; and the second ion comprises Xe and / or Kr.

[0101] The metal silicide 110a is formed in the source / drain region by the metal covering the surface of the source / drain region reacting with the first amorphous portion 105a and the second amorphous portion 106a, and can completely occupy or partially occupy from top to bottom the position of the first amorphous portion 105a and the second amorphous portion 106a; and the metal silicide 110b is formed in the gate layer 102 by the metal covering the top surface of the gate layer 102 reacting with the first amorphous portion 105b and the second amorphous portion 106b, and completely occupies or partially occupies from top to bottom the position of the first amorphous portion 105b and the second amorphous portion 106b.

[0102] In an example, the lower profile of the sidewall and the bottom surface of the first amorphous portion 105a is a curved surface, such as a circular arc surface or an elliptical arc surface, convex to the bottom surface of the semiconductor substrate 100, and the second amorphous portion 106a wraps around the bottom and at least the sidewall (e.g. the entire sidewall) of the first amorphous portion 105a and is gradually thinned from top to bottom. The lower profile of the sidewall and the bottom surface of the metal silicide 110a formed thereby is a smooth curved surface, convex to the bottom surface of the semiconductor substrate 100. The lower profile of the sidewall and the bottom surface of the first amorphous portion 105b is a curved surface, such as a circular arc surface or an elliptical arc surface, convex to the bottom surface of the semiconductor substrate 100, and the second amorphous portion 106b wraps around the bottom and at least the sidewall (e.g. the entire sidewall) of the first amorphous portion 105b and is gradually thinned from top to bottom. The lower profile of the sidewall and the bottom surface of the metal silicide 110b formed thereby is a smooth curved surface, convex to the bottom surface of the semiconductor substrate 100.

[0103] Optionally, the metal in the metal silicide includes at least one of Ti, Co, Ni, W, and Pt.

[0104] Optionally, the semiconductor device further includes a contact hole etching stop layer 111, an interlayer dielectric layer 112, and contact plugs 114a and 114b. The contact hole etching stop layer 111 covers the substrate and exposes the respective portions of the metal silicides 110a and 110b. The interlayer dielectric layer 112 covers the contact hole etching stop layer 111 and has contact holes 113a and 113b that penetrate the interlayer dielectric layer 112 and the contact hole etching stop layer 111 and expose the partial surfaces of the metal silicides 110a and 110b. The contact plug 114a fills the contact hole 113a and has a bottom in electrical contact with the metal silicide 110a, and the contact plug 114b fills the contact hole 113b and has a bottom in electrical contact with the metal silicide 110b.

[0105] It should be understood that the materials of the parts of the semiconductor device of the present embodiment can be selected according to the corresponding content of the above-mentioned method for manufacturing the semiconductor device of the present application, which will not be described here again.

[0106] In summary, the semiconductor device of the present embodiment has the metal silicide formed by the reaction of the metal on the surface of the corresponding region (i.e., at least one of the source / drain region and the gate layer) of the substrate with the first and second amorphous regions in the corresponding region, so that the boundary morphology of the metal silicide is good, the lateral line width and the vertical thickness can be guaranteed, and the problems of sharp peak discharge or easy breakdown due to the existence of the sharp peak of the metal silicide, and the problem of increased device leakage current due to the penetration of the metal silicide during contact hole etching can be avoided, and the contact resistance between the contact plug and the source / drain region is further reduced, improving the reliability of the device. In addition, when the lower profile of the amorphous region formed by the first and second amorphous regions is a curved surface, the lower profile of the metal silicide formed based on the first and second amorphous regions is also a curved surface, so that the contact area between the contact plug and the corresponding region of the substrate can be increased, and the contact resistance between the contact plug and the corresponding region of the substrate is reduced, further improving the electrical performance of the device.

[0107] The above description is only a description of the preferred embodiments of the present application, and does not limit the scope of the present application in any way. Any modification or modification of the above-mentioned disclosure by a person skilled in the art falls within the protection scope of the technical solution of the present application.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises the following steps: providing a substrate and forming a patterned silicide blocking layer on the substrate to define a region to be formed with metal silicide; performing a first pre-amorphization implantation into the substrate in the region with a first ion under the mask of the silicide blocking layer to form a first amorphous portion; performing a second pre-amorphization implantation into the substrate in the region with a second ion having an atomic mass greater than the first ion and in a tilted ion implantation mode under the mask of the silicide blocking layer to form a second amorphous portion outside the first amorphous portion, the second amorphous portion wrapping around the bottom and at least part of the sidewall of the first amorphous portion and gradually thinning from top to bottom; depositing a metal and annealing to make the metal react with the first amorphous portion and the second amorphous portion to form the desired metal silicide.

2. The production method according to claim 1, wherein The step of providing a substrate comprises: providing a semiconductor substrate and forming a gate structure on the semiconductor substrate; forming a gate sidewall on the sidewall of the gate structure; forming source-drain regions in the semiconductor substrate on both sides of the gate structure to obtain the substrate; and the step of forming a patterned blocking layer on the substrate comprises: depositing a silicide blocking layer and performing photolithography and etching on the silicide blocking layer to form a patterned silicide blocking layer; wherein the source-drain regions exposed by the patterned silicide blocking layer are the regions to be formed with metal silicide, or the gate structure is a polysilicon gate structure and the source-drain regions and the polysilicon gate structure exposed by the patterned silicide blocking layer are the regions to be formed with metal silicide.

3. The production method according to claim 2, wherein The second ion of the second pre-amorphization implantation also thins the sidewall of the silicide blocking layer to increase the line width of the region.

4. The production method according to claim 2, wherein The line width of the region defined by the patterned silicide blocking layer on the top of the gate structure is 70% to 80% of the top line width of the gate structure.

5. The production method according to claim 1, wherein The first pre-amorphization implantation into the substrate in the region with the first ion and in a vertical ion implantation mode under the mask of the silicide blocking layer makes the lower profile formed by the sidewall and the bottom surface of the first amorphous portion convex to the surface of the substrate; or the first pre-amorphization implantation into the substrate in the region with the first ion and in different angles multiple times under the mask of the silicide blocking layer makes the lower profile formed by the sidewall and the bottom surface of the first amorphous portion a circular arc surface or an elliptical arc surface convex to the surface of the substrate.

6. The production method according to any one of claims 1 to 5, wherein Further comprising at least one of the following: (1) the closer to the center of the bottom surface of the first amorphous portion, the thinner the thickness of the second amorphous portion; (2) the lower profile formed by the sidewall and the bottom of the metal silicide is a curved surface convex to the surface of the substrate, which is a circular arc surface or an elliptical arc surface; (3) the first ion comprises at least one of Si, Ge and Ar; (4) the second ion comprises Xe and / or Kr; (5) the tilt angle of the tilted ion implantation mode is 5° to 15°; (6) the first ion has an implantation dose of 5e14 / cm 2 ~ 2e15 / cm 2 and an implantation energy of 15 KeV ~ 25 KeV; (7) the second ion has an implantation dose of 5e14 / cm 2 ~1e15 / cm 2 and an implantation energy of 18KeV~30KeV; (8) the metal comprises at least one of Ti, Co, Ni, W and Pt. (9) the metal silicide in the substrate has a smooth lower profile.

7. The production method according to claim 1, wherein The step of depositing a metal and annealing to form the metal silicide includes: depositing a metal and performing a first anneal to cause the metal to react with the first amorphized portion and the second amorphized portion to form a high resistance phase of metal silicide; removing unreacted metal and performing a second anneal to convert the high resistance phase of metal silicide to a low resistance phase of metal silicide.

8. The production method according to claim 7, wherein After depositing the metal and before performing the first anneal, a cap layer is also deposited on the metal; after completing the first anneal and before removing the unreacted metal, the cap layer is removed first.

9. The production method according to claim 7, wherein After forming the low resistance phase of metal silicide, further comprising: sequentially depositing a contact hole etch stop layer and an interlayer dielectric layer; etching the interlayer dielectric layer and the contact hole etch stop layer to form a contact hole exposing the metal silicide; filling the contact hole with a conductive material to form a contact plug.

10. A semiconductor device, characterized by comprising: comprising a substrate and a metal silicide; wherein the substrate has a region where the metal silicide is to be formed, and the region originally has a first amorphized portion formed by implantation of first ions and a second amorphized portion formed by oblique implantation of second ions, the second ions having an atomic mass greater than that of the first ions, the second amorphized portion being located outside the first amorphized portion and wrapping around the bottom and at least part of the sidewall of the first amorphized portion, and the second amorphized portion gradually thins from top to bottom; the metal silicide is formed by the metal covering the surface of the region reacting with the first amorphized portion and the second amorphized portion.

11. The semiconductor device of claim 10, wherein, further comprising at least one of: (1) the lower profile formed by the sidewall and bottom surface of the first amorphized portion is a curved surface convex to the bottom surface of the substrate, and the curved surface comprises a circular arc surface or an elliptical arc surface; (2) the closer to the center of the bottom surface of the first amorphized portion, the thinner the thickness of the second amorphized portion; (3) the lower profile formed by the sidewall and bottom of the metal silicide is a curved surface convex to the bottom surface of the substrate, and the curved surface is a circular arc surface or an elliptical arc surface; (4) the first ions comprise at least one of Si, Ge and Ar; (5) the second ions comprise Xe and / or Kr; (6) the metal comprises at least one of Ti, Co, Ni, W and Pt; (7) the metal silicide in the substrate has a smooth lower profile; (8) the substrate comprises a semiconductor substrate, a gate structure formed on the semiconductor substrate, a gate sidewall formed on the sidewall of the gate structure, and source-drain regions formed in the semiconductor substrate on both sides of the gate structure, wherein the region where the metal silicide is to be formed comprises a partial region of the source-drain region, or the gate structure is a polysilicon gate structure and the region where the metal silicide is to be formed comprises a partial region of the source-drain region and a partial top region of the gate structure.

12. The semiconductor device of claim 10, wherein, further comprising: a contact hole etch stop layer covering the substrate and exposing the corresponding portion of the metal silicide; an interlayer dielectric layer overlying the contact hole etch stop layer and having a contact hole therethrough that exposes the metal silicide; a contact plug filled in the contact hole and in electrical contact with the metal silicide.

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