Chip against latch-up effect and configuration method, device and medium thereof

Abstract

The application provides a chip against latch-up effect and a configuration method, device and medium thereof. The chip comprises: a power supply classification module comprising at least one sub power supply; a power supply supply module, an input end of which is connected to an output end of the power supply classification module, the power supply supply module comprising at least one latch-up current limiting module and at least one power management unit, an output end of the latch-up current limiting module being connected to an input end of the power management unit; and a power domain module, an input end of which is connected to an output end of the power supply supply module, the power domain module comprising at least one sub power domain module, the chip comprising a plurality of voltage domain circuits, the sub power domain module being obtained by splitting the voltage domain circuits, and the voltage domain circuits being composed of the plurality of sub power domain modules. According to the technical scheme of the embodiment of the application, the plurality of voltage domain circuits of the chip are split into the plurality of sub power domain modules, and the latch-up current limiting module more accurately controls the power management unit to power off the sub power domain module to protect the chip circuit, thereby meeting the anti-latch-up effect requirement of any chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of anti-latch-up chip, and particularly relates to an anti-latch-up chip and a configuration method, device and medium thereof. BACKGROUND

[0002] Latch up refers to a positive feedback low impedance path caused by mutual influence of a parasitic PNP bipolar junction transistor and an NPN bipolar junction transistor in a complementary metal-oxide-semiconductor (CMOS) wafer between a power line and a ground line (GND).

[0003] In the space environment, there are various particles such as protons, electrons, alpha particles, heavy ions and gamma particles. The radiation effects caused by these particles, especially single particle effects, affect the reliability of electronic devices. Generally, the parasitic transistor is in a high-resistance off state. When a high-energy particle irradiates on a device provided with a CMOS, an electron-hole pair is generated in the substrate, causing the transistor to conduct, and current flows. Since the parasitic transistor works in the positive amplification zone, the current flowing through the parasitic transistor is always increasing, causing a large current regeneration state through the positive feedback loop, i.e. latch up; a large current of the order of milliamperes is generated between the supply voltage (Volt Current Condenser, VCC) and the GND of the parasitic transistor, the local temperature of the device is too high, and the device is permanently damaged.

[0004] At present, an anti-latch-up current limiting protection chip is added to a chip that needs to be protected against latch up. However, the chip that needs to be protected against latch up must meet the application requirements to use the anti-latch-up current limiting protection chip, and the chip that does not meet the application requirements cannot be protected against latch up. SUMMARY

[0005] The present application aims to at least solve one of the technical problems existing in the prior art. To this end, the present application provides an anti-latch-up chip and a configuration method, device and medium thereof, which split the voltage domain circuit of the chip into a plurality of sub-power domain modules of the power domain module, and realize precise power-off of the sub-power domain through a latch current limiting module to protect the chip, thereby meeting the anti-latch-up effect requirements of any chip.

[0006] In a first aspect, an embodiment of the present application provides an anti-latch-up chip, comprising:

[0007] A power classification module, the power classification module comprising at least one sub-power supply;

[0008] a power supply module, an input end of the power supply module being connected to an output end of the power classification module, the power supply module comprising at least one latch current limiting module and at least one power management unit, an output end of the latch current limiting module being connected to an input end of the power management unit, the latch current limiting module being used for detecting current passing through the power management unit, the latch current limiting module being capable of cutting off power supply of the sub power supply to the power management unit;

[0009] a power domain module, an input end of the power domain module being connected to an output end of the power supply module, the power domain module comprising at least one sub power domain module, an output end of the power management unit being connected to an input end of at least one of the sub power domain modules, the power management unit being used for providing voltage for the sub power domain module, the chip comprising a plurality of voltage domain circuits, the sub power domain module being split by the voltage domain circuits, the voltage domain circuits being composed of a plurality of the sub power domain modules.

[0010] According to some embodiments of the present application, when the sub power domain module has a ruggedized design, an input end of the power management unit connected to the sub power domain module is directly connected to the sub power supply, or when the sub power domain module does not have a ruggedized design, an input end of the power management unit connected to the sub power domain module is connected to the sub power supply through the latch current limiting module.

[0011] According to some embodiments of the present application, the chip further comprises:

[0012] a storage module, the storage module being connected to the power supply module, the storage module storing configuration parameters, the storage module being used for providing the configuration parameters for all the power management units and all the latch current limiting modules.

[0013] According to some embodiments of the present application, the chip further comprises:

[0014] a chip pin power module, an output end of the chip pin power module being connected to an input end of the power classification module, the chip pin power module comprising at least one chip pin power supply, the chip pin power supply being connected to at least one of the sub power supplies.

[0015] In a second aspect, embodiments of the present application provide a configuration method of a chip resistant to latch-up effect, applied to the chip of the first aspect, the method comprising:

[0016] Obtaining specification information and functions of a chip, performing voltage domain division on the chip based on the specification information and functions of the chip to obtain a plurality of voltage domain circuits, performing work current estimation and latch leakage target value estimation on all the voltage domain circuits respectively to obtain a plurality of voltage domain work currents and a plurality of latch leakage target values respectively, wherein the voltage domain work current is a current when the voltage domain circuit is in a normal working state, and the latch leakage target value is a current when a local circuit of the voltage domain circuit has a latch effect;

[0017] Based on any one of the voltage domain circuits, obtaining detection accuracy of the latch current limiting module, dividing the latch leakage target value by the detection accuracy to obtain a sub-power domain maximum current, and when the voltage domain work current is greater than the sub-power domain maximum current, splitting the voltage domain circuit into a plurality of sub-power domain modules, wherein the work current of the sub-power domain module is less than or equal to the sub-power domain maximum current;

[0018] Connecting input ends of all the sub-power domain modules to output ends of a power management unit of a power supply module, connecting input ends of the power supply module to output ends of a power classification module, and obtaining the chip.

[0019] According to some embodiments of the present application, the chip further comprises a chip pin power module, an output end of the chip pin power module being connected to an input end of the power classification module, the chip pin power module comprising at least one chip pin power supply, and the chip pin power supply being connected to at least one sub-power supply.

[0020] Connecting input ends of the power supply module to output ends of the power classification module to obtain the chip, comprising:

[0021] Based on any one of the sub-power domain modules, when the sub-power domain module does not have a reinforcement design, connecting an input end of the power management unit to an output end of the latch current limiting module, and connecting an output end of the sub-power supply to an input end of the latch current limiting module, or when the sub-power domain module has a reinforcement design, connecting an output end of the sub-power supply to an input end of the power management unit.

[0022] Performing mapping optimization on all sub-power supplies of the power classification module and the chip pin power supply, connecting the power classification module to the chip pin power supply, and obtaining the chip, wherein the chip pin power supply is connected to at least one sub-power supply.

[0023] According to some embodiments of the present application, the chip further comprises a storage module connected to the power supply module, the storage module storing configuration parameters, and the storage module being configured to provide the configuration parameters to all the power management units and all the latch current limiting modules;

[0024] After obtaining the chip, the method further comprises:

[0025] Based on the power supply module connected to any of the sub-power domain modules, the chip is powered on, the dynamic range of the operating current of the sub-power domain module is obtained, the configuration parameters are read from the storage module, and the power management units and the latch current limiting modules are configured based on the configuration parameters and the dynamic range by the power-on configuration function of the chip, wherein the parameters of the latch current limiting module include automatic restart function configuration parameters and restart delay values.

[0026] After the chip completes the parameter configuration, the chip enters a normal working state.

[0027] According to some embodiments of the present application, after the power management units and the latch current limiting modules are configured based on the configuration parameters and the dynamic range by the power-on configuration function of the chip, the method further comprises:

[0028] The chip pin power supply is powered on, the chip pin power supply supplies power to the power classification module, and the power classification module supplies power to the power domain module through the power supply module.

[0029] For any of the sub-power domain modules, when the operating current of the sub-power domain is greater than or equal to the maximum current of the sub-power domain, the latch current limiting module controls the power management unit to power off the sub-power domain module.

[0030] When the latch current limiting module is configured with an automatic restart function, the latch current limiting module restarts after the restart delay value, and the latch current limiting module controls the power management unit to restore power supply to the sub-power domain module.

[0031] In a third aspect, embodiments of the present application provide a configuration device of a chip resistant to latch-up effect, comprising at least one control processor and a memory in communication connection with the at least one control processor; the memory stores instructions executable by the at least one control processor, and the instructions are executed by the at least one control processor to enable the at least one control processor to execute the configuration method of the chip resistant to latch-up effect as described in the second aspect.

[0032] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium storing computer executable instructions for implementing the configuration method of the latch-up resistant chip according to the second aspect.

[0033] According to the latch-up resistant chip, the power supply classification module includes at least one sub power supply; the input end of the power supply supply module is connected to the output end of the power supply classification module, the power supply supply module includes at least one latch-up current limiting module and at least one power management unit, the output end of the latch-up current limiting module is connected to the input end of the power management unit, the latch-up current limiting module is used for detecting the current passing through the power management unit, and the latch-up current limiting module can cut off the power supply of the sub power supply to the power management unit; the input end of the power supply domain module is connected to the output end of the power supply supply module, the power supply domain module includes at least one sub power supply domain module, the output end of the power management unit is connected to the input end of at least one sub power supply domain module, and the power management unit is used for providing voltage for the sub power supply domain module; the chip includes a plurality of voltage domain circuits, the sub power supply domain module is obtained by splitting the voltage domain circuit, and the voltage domain circuit is composed of a plurality of sub power supply domain modules. According to the technical scheme of the embodiment of the present application, the plurality of voltage domain circuits of the chip are split into a plurality of sub power supply domain modules, so that the working current of the voltage domain circuit is split into a plurality of sub power supply domain working currents, the proportion of the current in the sub power supply domain working current when the latch-up effect occurs is greater than the proportion of the current in the voltage domain working current when the latch-up effect occurs under the condition that the detection accuracy of the latch-up current limiting module remains unchanged, so that the latch-up current limiting module can more accurately detect whether the sub power supply domain module occurs the latch-up effect, the power management unit is controlled by the latch-up current limiting module to realize the accurate power-off of the sub power supply domain module to protect the chip circuit, and the anti-latch-up effect demand of any chip can be met. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 is a structural schematic diagram of the latch-up resistant chip provided by an embodiment of the present application;

[0035] Figure 2 is a flow chart of the configuration method of the latch-up resistant chip provided by another embodiment of the present application;

[0036] Figure 3 is a structural diagram of the configuration device of the latch-up resistant chip provided by another embodiment of the present application. DETAILED DESCRIPTION

[0037] Embodiments of the present application are described below in detail with reference to the drawings, examples of which are shown in the accompanying drawings, wherein the same or similar components have the same or similar designations throughout the several figures. The embodiments described below are exemplary only, and are not to be construed as limiting the present application.

[0038] In the description of the present application, it is to be understood that the orientation description, such as the orientation or position relationship indicated by up, down, front, back, left, right, etc. is based on the orientation or position relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.

[0039] In the description of the present application, several meanings are one or more, and the meaning of multiple is two or more, greater than, less than, more than, etc. are understood as not including the number, above, below, etc. are understood as including the number. If the first, second is described, it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features or the order of the indicated technical features.

[0040] In the description of the present application, unless otherwise explicitly limited, the words such as setting, installing, connecting, etc. should be broadly understood, and the person skilled in the art can reasonably determine the specific meaning of the above words in the present application in combination with the specific content of the technical solution.

[0041] The chip against latch-up effect provided by the embodiment of the present application comprises: a power supply classification module, the power supply classification module comprising at least one sub power supply; a power supply supply module, the input end of the power supply supply module being connected to the output end of the power supply classification module, the power supply supply module comprising at least one latch-up current limiting module and at least one power management unit, the output end of the latch-up current limiting module being connected to the input end of the power management unit, the latch-up current limiting module being used for detecting the current passing through the power management unit, and the latch-up current limiting module being capable of cutting off the power supply of the sub power supply to the power management unit; and a power supply domain module, the input end of the power supply domain module being connected to the output end of the power supply supply module, the power supply domain module comprising at least one sub power supply domain module, the output end of the power management unit being connected to the input end of at least one sub power supply domain module, and the power management unit being used for providing voltage for the sub power supply domain module, wherein the chip comprises a plurality of voltage domain circuits, the sub power supply domain module being obtained by splitting the voltage domain circuits, and the voltage domain circuits being composed of a plurality of sub power supply domain modules. According to the technical scheme of the embodiment of the present application, the plurality of voltage domain circuits of the chip are split into a plurality of sub power supply domain modules, so that the working current of the voltage domain circuit is split into a plurality of sub power supply domain working currents, the proportion of the current in the sub power supply domain working current when the latch-up effect occurs is greater than the proportion of the current in the voltage domain working current when the latch-up effect occurs under the condition that the detection accuracy of the latch-up current limiting module remains unchanged, the latch-up current limiting module can more accurately detect whether the sub power supply domain module has the latch-up effect, the latch-up current limiting module controls the power management unit to realize the accurate power-off of the sub power supply domain module to protect the chip circuit, and the anti-latch-up effect demand of any chip can be met.

[0042] Firstly, referring to Figure 1 , Figure 1 is a structural schematic diagram of the chip against latch-up effect provided by an embodiment of the present application, and the chip against latch-up effect provided by the embodiment of the present application comprises:

[0043] The power supply classification module 10 comprises at least one sub power supply 11.

[0044] The power supply supply module 20 comprises at least one latch-up current limiting module 21 and at least one power management unit 22, the output end of the latch-up current limiting module 21 being connected to the input end of the power management unit 22, the latch-up current limiting module 21 being used for detecting the current passing through the power management unit 22, and the latch-up current limiting module 21 being capable of cutting off the power supply of the sub power supply 11 to the power management unit 22.

[0045] The power supply domain module 30 has an input end connected to an output end of the power supply module 20, and includes at least one sub-power supply domain module 31. An output end of the power management unit 22 is connected to an input end of the at least one sub-power supply domain module 31, and the power management unit 22 is configured to provide a voltage for the sub-power supply domain module 31. The chip includes a plurality of voltage domain circuits, and the sub-power supply domain module 31 is split from the voltage domain circuits, and the voltage domain circuits are composed of the plurality of sub-power supply domain modules 31.

[0046] It should be noted that the power supply classification module 10 is configured to provide a voltage for the power supply module 20. One sub-power supply 11 can be connected to one power management unit 22, and one latch current limiting module 21 is connected to one power management unit 22.

[0047] It should be noted that the power management unit 22 generates a voltage required by the sub-power supply domain module 31 connected thereto based on a voltage value of the sub-power supply 11 connected in series thereto. The latch current limiting module 21 is connected in series between the power management unit 22, and the latch current limiting module 21 is configured to detect a current passing through the power management unit 22. When a latch effect occurs in a circuit of the chip, the current passing through the power management unit 22 increases, that is, the current passing through the latch current limiting module 21 increases. When a fluctuation of the current exceeds a preset range of the latch current limiting module 21, the latch current limiting module 21 cuts off a power supply for the power management unit 22, thereby protecting a subsequent circuit from being burned by the current generated when the latch effect occurs.

[0048] It should be noted that a plurality of voltage domain circuits are obtained based on specifications, functions, power consumptions, and different voltages of the chip, and the plurality of sub-power supply domain modules 31 are obtained based on any voltage domain circuit. All the sub-power supply domain modules 31 constitute the power supply domain module 30.

[0049] It should be noted that in a large or medium chip, a working current of the chip is large. When a latch effect occurs in a local circuit of the chip, a fluctuation of the current accounts for a small proportion of a normal working current. The latch current limiting module 21 cannot correctly determine whether the fluctuation of the current is a normal fluctuation of the current of the chip or a current change caused by the latch effect, and thus cannot accurately cut off the voltage supply for the power management unit 22.

[0050] For example, when the chip normally works, a current on the VCC is 6 ampere (A), and a fluctuation range of the current when the chip normally works is 5 A to 7 A. When a local circuit of the chip has the latch effect, the current increases by 200 mA (milliampere) than the normal working current, which is obviously smaller than the fluctuation range of the current when the chip normally works. The latch current limiting module 21 cannot determine whether the fluctuation of the current by 200 mA is a normal fluctuation of the current or the latch effect occurs in the circuit of the chip.

[0051] Exemplarily, the voltage domain circuit of 6A is split into 6 sub-power domain modules 31, the current of the sub-power domain module 31 is 1A, considering that the current fluctuation range of the sub-power domain module 31 is 0.85A to 1.15A, in the case that the detection accuracy of the latch current limiting module 21 is unchanged, when the supply current of the sub-power domain module 31 exceeds 1.3A, the local circuit of the chip has a latch effect, and the latch current limiting module 21 cuts off the voltage supply to the power management unit 22; when the sub-power domain module 31 has a latch effect, the power-off protection measure of the latch current limiting module 21 is more accurate.

[0052] It should be noted that the same voltage domain circuit is split into multiple sub-power domain modules 31, and the multiple sub-power domain modules 31 belong to the same voltage category, but are divided due to different circuit functions of the sub-power domain modules 31. If the working power consumption of the sub-power domain modules 31 divided only due to the circuit function is small, the same power supply module 20 can provide power for multiple sub-power domain modules 31 with the same voltage category but different circuit functions, so that there is a mapping relationship between one power management unit 22 and multiple sub-power domain modules 31.

[0053] It should be noted that since the circuit of the chip can have a latch effect, in the prior art, an anti-latch current limiting protection chip is added outside the chip, but the chip needs to meet the application requirements to be used, and the current control of the anti-latch current limiting protection chip is not accurate, the configuration is not flexible, and the implementation cost of the circuit is high; or, a special process is selected, the resistance to power and ground on the layout is reduced, and a protection ring is added, but this method is only applicable to small chips, cannot be applied to large and medium-sized chips, and is not suitable for process conversion.

[0054] It should be noted that, in the present application, according to the specifications and functions of the chip, the chip is divided into different voltage domain circuits, the voltage domain circuits are split to obtain a plurality of sub-power supply domain modules 31, so as to split a larger voltage domain working current into a plurality of smaller sub-power supply domain module 31 working currents, under the condition that the detection accuracy of the latch current limiting module 21 is unchanged and the working current of the local circuit when the latch effect occurs is unchanged, the proportion of the latch working current in the normal working current is improved, so that the latch current limiting module 21 more accurately detects whether the sub-power supply domain module 31 has the latch effect, so as to cut off the voltage supply to the power management unit 22, so as to power off the sub-power supply domain module 31, thereby protecting the sub-power supply domain module 31 from being burned by the large current generated by the latch effect, and protecting the chip from being burned by the large current generated by the latch effect. Through the anti-latch effect chip of the present application, the latch current limiting module 21 realizes accurate control of the current passing through the power management unit 22, thereby realizing current control of the sub-power supply domain module 31, and the latch current limiting module 21 can timely cut off the voltage supply to the power management unit 22 and the like. The circuit of the chip is effectively protected; and it is suitable for any size specification of the chip, and does not need to consider the size specification and application requirement limitation of the chip when used, and can be applied to the process, and meets the anti-latch effect requirement of any chip.

[0055] In addition, in an embodiment, referring to Figure 1 When the sub-power supply domain module 31 has a rugged design, the input end of the power management unit 22 connected to the sub-power supply domain module 31 is directly connected to the sub-power supply 11, or when the sub-power supply domain module 31 does not have a rugged design, the input end of the power management unit 22 connected to the sub-power supply domain module 31 is connected to the sub-power supply 11 through the latch current limiting module 21.

[0056] It should be noted that the rugged design is a prior art, for example, selecting a special process, reducing the resistance to power and ground on the layout, increasing the protection ring and the like, and the present application does not improve the rugged design of the chip in any form, and will not be described here.

[0057] It should be noted that the number of power management units 22 and latch current limiting modules 21 in the power supply module 20 is not necessarily the same, and the actual situation of the sub-power supply domain module 31 can be determined whether the power supply module 20 connected to the sub-power supply domain module 31 needs the latch current limiting module 21 to protect the circuit when the sub-power supply domain module 31 has the latch effect.

[0058] In addition, in an embodiment, it further includes a storage module, the storage module is connected to the power supply module 20, the storage module stores configuration parameters, and the storage module is used to provide configuration parameters for all power management units 22 and all latch current limiting modules 21.

[0059] It should be noted that the parameters of the latch current limiting module 21 include a large current judgment reference value, an automatic restart function configuration parameter and a restart delay value; the parameters of the power management unit 22 include an output voltage value, a current driving capability and a key component parameter in the chip circuit; and the parameters of the power supply module 20 are flexibly configured based on the actual application of the chip. The configuration parameters stored in the storage module include the parameters of the latch current limiting module 21, the parameters of the power management unit 22 and the parameters of the power supply module 20.

[0060] It should be noted that the configuration parameters of the power supply module 20 are usually stored in a small-capacity storage module, which can be a one-time programmable non-volatile memory, an electrically erasable programmable read-only memory or an embedded flash memory, etc. The loading of the configuration parameters in the storage module is realized by a hardened circuit, for example, in space applications, a hardened circuit obtained by using anti-radiation hardening is used; the function of loading the configuration parameters from the storage module to the power supply module 20 after the power-on of the chip is realized by the hardened circuit (Configuration from memory).

[0061] In addition, in an embodiment, it further includes a chip pin power module, the output end of the chip pin power module is connected to the input end of the power classification module 10, and the chip pin power module includes at least one chip pin power, and the chip pin power is connected to at least one sub-power supply 11.

[0062] It should be noted that the chip includes a plurality of chip pin powers, and each chip pin power has an input power signal. Each sub-power supply 11 selects one from all the chip pin powers as its supply power, so as to realize that the sub-power supply 11 provides power for the power supply module and the power domain module 30. From the mapping relationship, one chip pin power is connected to at least one sub-power supply 11.

[0063] In addition, the embodiment of the application provides a configuration method of the latch effect resistant chip. Figure 1 The latch effect resistant chip of the embodiment is described with reference to Figure 2 , Figure 2 The latch effect resistant chip of the embodiment is described with reference to

[0064] S10, obtaining specification information of the chip, dividing the chip into a plurality of voltage domain circuits based on the specification information, respectively estimating working currents of all the voltage domain circuits and latch leakage target values of the voltage domain circuits, and respectively obtaining a plurality of voltage domain working currents and a plurality of latch leakage target values, wherein the voltage domain working current is a current of the voltage domain circuit in a normal working state, and the latch leakage target value is a current of the voltage domain circuit when a local circuit of the voltage domain circuit has a latch effect.

[0065] S20, based on any voltage domain circuit, obtaining the detection accuracy of the latch current limiting module, dividing the latch leakage target value by the detection accuracy to obtain the maximum current of the sub-power domain, when the working current of the voltage domain is greater than the maximum current of the sub-power domain, splitting the voltage domain circuit into multiple sub-power domain modules, wherein the working current of the sub-power domain module is less than or equal to the maximum current of the sub-power domain;

[0066] S30, connecting the input end of all sub-power domain modules to the output end of the power management unit of the power supply module, and connecting the input end of the power supply module to the output end of the power classification module to obtain a chip.

[0067] It should be noted that the working current estimation and the latch leakage target value estimation of the voltage domain circuit are both estimated by the characteristics of the existing process design library to estimate the current consumption of each voltage domain circuit under normal working condition and the current consumption of the voltage domain circuit under latch effect. Different process design libraries are used in chip design, and the P-cells (physical cells) in the library have different latch leakage values.

[0068] Exemplarily, under the 0.18um BCD (Bipolar-CMOS-DMOS) process of a certain wafer factory, the maximum current of a single normal Metal-Oxide-Semiconductor Field-Effect Transistor (MOS) under continuous working condition is 5mA, and it is roughly estimated that 20 to 30 MOSs are involved in the latch effect of the local circuit of the chip, and the current of the local circuit is 100mA to 150mA.

[0069] It should be noted that if the maximum working current of the voltage domain exceeds the maximum current of the sub-power domain, it means that when the voltage domain circuit produces latch effect, the latch current limiting module cannot accurately determine whether the current fluctuation is caused by the normal working of the voltage domain circuit or the latch effect of the voltage domain circuit, which leads to the failure of accurately performing power-off operation on the subsequent circuit, thereby failing to protect the chip circuit.

[0070] It should be noted that, by the chip configuration method of the present application, the voltage domain circuit with a voltage domain maximum working current exceeding a sub-power domain maximum current is split into multiple sub-power domain modules, so as to split the voltage domain working current into multiple sub-power domain working currents, the sub-power domain working current being less than or equal to the sub-power domain maximum current, the proportion of the latch leakage target value in the voltage domain working current being less than the proportion of the latch leakage target value in the sub-power domain working current, and the detection accuracy of the latch current limiting module being unchanged, so that the latch current limiting module is maintained, and whether the latch effect occurs in the sub-power domain module is more accurately detected, the latch current limiting module controls the power management unit to accurately power off the sub-power domain module to protect the chip circuit, thereby meeting the anti-latch effect requirements of chips of various specifications and sizes.

[0071] Exemplarily, the working current of a certain voltage domain circuit has a certain fluctuation range, the voltage domain maximum working current is 1.9A, the latch leakage target value is 100mA, the detection accuracy of the latch current limiting module for current overrun is 10%, the sub-power domain maximum current is 100mA / (10%) = 1A, the maximum working current of the voltage domain circuit is greater than the sub-power domain maximum current, and the proportion of the latch leakage target value in the voltage domain working current is 100mA / 1.9A < 10%. When the voltage domain current occurs the latch effect, the latch leakage target value cannot be detected, so the voltage domain circuit is split into two sub-power domain modules, and the working currents of the two sub-power domains can be 1A and 0.9A respectively. Therefore, 100mA / 1A = 10%, 100mA / 0.9A > 10%, and the accuracy of the latch current limiting module can detect that the working current is too large when the latch effect occurs in the local circuit, so that the latch current limiting module powers off the power management unit to protect the subsequent circuit from being burned out by the large current.

[0072] It should be noted that the voltage domain circuit is split into multiple sub-power domain modules based on the function of the voltage domain circuit, the working current of the sub-power domain module is less than or equal to the maximum current of the sub-power domain module, and if the voltages of the multiple sub-power domains are the same, only different functions are divided, and the multiple sub-power domains are connected to one power management unit. The power domain module includes multiple sub-power domain modules split from multiple voltage domain circuits.

[0073] In addition, in an embodiment, in step S30, the input end of the power supply module is connected to the output end of the power classification module to obtain a chip, and specifically further includes but is not limited to the following steps:

[0074] S31, based on any sub-power domain module, when the sub-power domain module does not have a rugged design, connecting the input end of the power management unit to the output end of the latch current limiting module, connecting the output end of the sub-power to the input end of the latch current limiting module, or when the sub-power domain module has a rugged design, connecting the output end of the sub-power to the input end of the power management unit;

[0075] S32, mapping optimization is performed on all sub-powers of the power classification module and the chip pin power supply, the power classification module is connected to the chip pin power supply, and a chip is obtained, wherein the chip pin power supply is connected to at least one sub-power.

[0076] It should be noted that the input end of the power supply module is connected to the output end of the power supply module, the input end of the power supply module is connected to the output end of the power supply module, and then the input end of the power supply module is connected to the output end of the chip pin power supply. After mapping optimization of the power supply source of the power supply module and the chip pin power supply, the connection is performed. The power supply source of the power supply module and the chip pin power supply are top-level power supplies, and after the top-level power supplies are sorted, the circuit of the power classification module consistent with the actual application is obtained.

[0077] In addition, in an embodiment, after step S32 is performed, the following steps are further included but are not limited to:

[0078] S41, based on the power supply module connected to any sub-power domain module, the chip is powered on, the dynamic range of the working current of the sub-power domain module is obtained, the configuration parameters are read from the storage module, and the power management unit and the latch current limiting module are parameter configured based on the configuration parameters and the dynamic range through the power-on configuration function of the chip, wherein the parameters of the latch current limiting module include automatic restart function configuration parameters and restart delay values;

[0079] S42, the chip completes parameter configuration, and the chip enters a normal working state.

[0080] It should be noted that because the working currents of different sub-voltage domain modules are different, the current dynamic ranges of different sub-voltage domain modules are also different, and therefore the power management unit and the latch current limiting module in the power supply module corresponding thereto need to be parameter configured. The current comparison threshold, output voltage value, current driving capability and other characteristics of the power supply module are changed through the power-on configuration function of the chip to meet the requirements of the anti-latch effect of the sub-power domain module connected to the power supply module.

[0081] It should be noted that the chip is powered on, and the chip pin power supply is powered by an external power supply during this process. The chip pin power supply is powered on; after the chip power-on is completed, the chip configuration loading function reads the configuration parameters from the storage module, and the power management unit and the latch current limiting module are configured with parameters, especially the large current judgment reference value of the latch current limiting module, whether to start the automatic restart function, the restart delay value and other parameters are configured.

[0082] In addition, in an embodiment, after step S41 is performed, the following steps are further included, but are not limited to:

[0083] S43, the chip pin power supply is powered on, and the chip pin power supply supplies power to the power supply classification module, and the power supply classification module supplies power to the power supply domain module through the power supply module;

[0084] S44, for any sub-power domain module, when the working current of the sub-power domain is greater than or equal to the maximum current of the sub-power domain, the latch current limiting module controls the power management unit to power off the sub-power domain module;

[0085] S45, when the latch current limiting module is configured with an automatic restart function, the latch current limiting module restarts after the restart delay value, and the latch current limiting module controls the power management unit to restore power supply to the sub-power domain module.

[0086] It should be noted that after the parameter configuration of the chip is completed, the chip enters a normal working state. During the normal working process of the chip, if any sub-power domain module of the chip produces a latch effect, the latch current limiting module in the power supply module connected with the sub-power domain controls the voltage supply to the power management unit to be cut off, so that the sub-power domain is powered off.

[0087] For example, the latch current of the local circuit is 100mA, the accuracy of the latch current limiting module detecting the over-limit current is 10%, and the maximum current consumption of each voltage domain circuit is 100mA / (10%) = 1A. When the local latch current of the voltage domain circuit increases to 1A+1A*10% = 1.1A, the latch current limiting module will cut off the current of the voltage domain circuit.

[0088] It should be noted that if the latch current limiting module in the power supply module connected with the sub-power domain is configured with an automatic restart function configuration parameter to realize the automatic restart function, the power supply to the power management unit is reopened after the restart delay value, the sub-power domain module returns to the normal working state, or when the latch current limiting module is not configured with the automatic restart function and the restart delay value, the latch current limiting module keeps the power supply to the power management unit off until the operator intervenes manually restarts, and the latch current limiting module restores the voltage supply to the power management unit.

[0089] In order to better understand the technical solutions of the present application, the following specific embodiments are provided.

[0090] S501, obtaining specification information of the chip, performing voltage domain division on the chip based on the specification information to obtain a plurality of voltage domain circuits, performing working current estimation and latch leakage target value estimation on all voltage domain circuits respectively to obtain a plurality of voltage domain working currents and a plurality of latch leakage target values, wherein the voltage domain working current is the current when the voltage domain circuit is in a normal working state, and the latch leakage target value is the current when the local circuit of the voltage domain circuit has a latch effect;

[0091] S502, based on any voltage domain circuit, obtaining the detection accuracy of the latch current limiting module, dividing the latch leakage target value by the detection accuracy to obtain a sub-power domain maximum current, and when the voltage domain working current is greater than the sub-power domain maximum current, splitting the voltage domain circuit into a plurality of sub-power domain modules, wherein the working current of the sub-power domain module is less than or equal to the sub-power domain maximum current;

[0092] S503, connecting the input ends of all sub-power domain modules to the output end of the power management unit of the power supply module;

[0093] S504, based on any sub-power domain module, when the sub-power domain module does not have a rugged design, connecting the input end of the power management unit to the output end of the latch current limiting module, and connecting the output end of the sub-power to the input end of the latch current limiting module, or when the sub-power domain module has a rugged design, connecting the output end of the sub-power to the input end of the power management unit;

[0094] S505, mapping optimization is performed on all sub-powers of the power classification module and the chip pin power supply, and the power classification module is connected to the chip pin power supply to obtain a chip, wherein the chip pin power supply is connected to at least one sub-power;

[0095] S506, based on the power supply module connected to any sub-power domain module, the chip is powered on, the dynamic range of the working current of the sub-power domain module is obtained, the configuration parameters are read from the storage module, and the power management unit and the latch current limiting module are parameter configured based on the configuration parameters and the dynamic range through the power-on configuration function of the chip, wherein the parameters of the latch current limiting module include automatic restart function configuration parameters and restart delay values;

[0096] S507, the chip completes parameter configuration, the chip enters a normal working state, the chip pin power supply is powered on, the chip pin power supply supplies power to the power classification module, and the power classification module supplies power to the power domain module through the power supply module;

[0097] S508, for any sub-power domain module, when the working current of the sub-power domain is greater than or equal to the maximum current of the sub-power domain, the latch current limiting module controls the power management unit to power off the sub-power domain module;

[0098] S509, when the latch current limiting module is configured with an automatic restart function, the latch current limiting module restarts after the restart delay value, the latch current limiting module controls the power management unit to restore power supply to the sub-power domain module, or when the latch current limiting module is not configured with an automatic restart function, the latch current limiting module keeps the power supply of the power management unit off until the operator intervenes manually restart, the latch current limiting module restores the voltage supply to the power management unit, thereby restoring the voltage supply of the sub-power domain module.

[0099] By the configuration method of the anti-latch effect chip of the application, the circuit structure of the chip is configured, the chip is divided into multiple voltage domain circuits by voltage domain division, the voltage domain circuits are split into multiple sub-power domain modules, the circuit structure of the chip is divided into a power classification module, a power supply module and a power domain module, the power classification module includes at least one sub-power, the power supply module includes a latch current limiting module and a power management unit, the power domain module includes multiple sub-power domain modules, and the parameters of the power supply module are flexibly configured inside the chip. By splitting the multiple voltage domain circuits of the chip into multiple sub-power domain modules, the larger voltage domain current is split into multiple smaller sub-power domain working currents. In the case that the detection accuracy of the latch current limiting module remains unchanged and the latch effect current of the local circuit remains unchanged, i.e. the latch leakage target value remains unchanged, the proportion of the latch leakage target value in the voltage domain current is less than the proportion of the latch leakage target value in the sub-power domain working current, so that the latch current limiting module more accurately detects whether the sub-power domain module has a latch effect, and cuts off the voltage supply to the power management unit to power off the sub-power domain module, thereby protecting the subsequent circuit and avoiding the chip from being burned by the large current generated by the latch effect. The anti-latch effect chip and the configuration method of the anti-latch effect chip of the application can be compatible with chips of different size specifications, the chip does not need to select a special process, and the sub-power domain does not need to be excessively strict in layout reinforcement, which is convenient for process design and production, and the latch current limiting module and the power management unit read the configuration parameters from the storage module through the power-on configuration function and the configuration loading function of the chip. The configuration parameters in the storage module can be changed by programming, so that the latch current limiting module and the power management unit have more configurable items and flexible configuration. The sub-power domain module does not need to be excessively strict in layout reinforcement, which reduces the implementation cost of the circuit, and the larger the chip size, the more obvious the cost advantage. In the space environment, compared with the system-level solution, the chip-level solution has a smaller area and is less affected by radiation, thereby improving the reliability of the anti-latch effect chip of the application.

[0100] AsFigure 3 as shown, Figure 3 is a structural diagram of a configuration device of an anti-latching effect chip provided by another embodiment of the application. The application further provides a configuration device of an anti-latching effect chip, comprising:

[0101] The processor 601 can be implemented in a manner of a general central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute related programs to implement the technical solutions provided by the embodiments of the application.

[0102] The memory 602 can be implemented in a form of a read only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 602 can store an operating system and other application programs. When the technical solutions provided by the embodiments of the application are implemented by software or firmware, related program codes are stored in the memory 602 and are called and executed by the processor 601 to implement the configuration method of the anti-latching effect chip of the embodiments of the application.

[0103] The input / output interface 603 is used to realize information input and output.

[0104] The communication interface 604 is used to realize communication interaction between the device and other devices. The communication can be realized in a wired manner (for example, a USB, a network cable, etc.) or in a wireless manner (for example, a mobile network, WIFI, Bluetooth, etc.).

[0105] The bus 605 is used to transmit information between various components (for example, the processor 601, the memory 602, the input / output interface 603, and the communication interface 604) of the device.

[0106] The processor 601, the memory 602, the input / output interface 603, and the communication interface 604 are connected to each other in the device through the bus 605.

[0107] The embodiments of the application further provide a storage medium, which is a computer readable storage medium. The storage medium stores a computer program. When the computer program is executed by a processor, the configuration method of the anti-latching effect chip is implemented.

[0108] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. In addition, the memory can include a high-speed random access memory, and can also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some embodiments, the memory can optionally include a memory disposed remotely with respect to the processor, which can be connected to the processor through a network. Examples of the above network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The above-described device embodiments are only illustrative, and units described as separate components can or can not be physically separated, implemented in one place, or distributed to multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the present embodiment.

[0109] Those of ordinary skill in the art can understand that all or some steps in the above disclosed method and system can be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As known to those of ordinary skill in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. In addition, as known to those of ordinary skill in the art, communication media generally includes computer readable instructions, data structures, program modules or other data in modulated data signals such as carrier waves or other transport mechanisms, and can include any information delivery medium.

[0110] The above is a specific description of the preferred embodiment of the present application, but the present application is not limited to the above-described embodiments, and those skilled in the art can make various equivalent modifications or replacements without departing from the spirit of the present application. These equivalent modifications or replacements are all included in the scope defined by the claims of the present application.

Claims

1. A latch-up resistant chip, characterized by The chip comprises: a power supply classification module comprising at least one sub-power supply; a power supply supply module, an input end of which is connected to an output end of the power supply classification module, the power supply supply module comprising at least one latch current limiting module and at least one power management unit, an output end of the latch current limiting module being connected to an input end of the power management unit, the latch current limiting module being used for detecting current passing through the power management unit, and the latch current limiting module being capable of cutting off power supply of the sub-power supply to the power management unit; a power supply domain module, an input end of which is connected to an output end of the power supply supply module, the power supply domain module comprising at least one sub-power supply domain module, an output end of the power management unit being connected to an input end of at least one of the sub-power supply domain modules, the power management unit being used for providing voltage for the sub-power supply domain module, the chip comprising a plurality of voltage domain circuits, the sub-power supply domain module being split by the voltage domain circuits, and the voltage domain circuits being composed of a plurality of the sub-power supply domain modules; wherein, when the sub-power supply domain module has a rugged design, an input end of the power management unit connected to the sub-power supply domain module is directly connected to the sub-power supply, or, when the sub-power supply domain module does not have a rugged design, the input end of the power management unit connected to the sub-power supply domain module is connected to the sub-power supply through the latch current limiting module.

2. The anti-latching chip of claim 1, wherein, Further comprising: a storage module connected to the power supply supply module, the storage module storing configuration parameters, and the storage module being used for providing the configuration parameters for all the power management units and all the latch current limiting modules.

3. The anti-latch-up chip of claim 1, wherein, Further comprising: a chip pin power supply module, an output end of which is connected to an input end of the power supply classification module, the chip pin power supply module comprising at least one chip pin power supply, and the chip pin power supply being connected to at least one of the sub-power supplies.

4. A configuration method of a chip against latch-up effect, characterized by, The chip for resisting latch effect according to any one of claims 1-3 comprises: obtaining specification information and functions of a chip, performing voltage domain division on the chip based on the specification information and functions of the chip to obtain a plurality of voltage domain circuits, performing working current estimation and latch leakage target value estimation on all the voltage domain circuits respectively to obtain a plurality of voltage domain working currents and a plurality of latch leakage target values respectively, wherein the voltage domain working current is a current of the voltage domain circuit in a normal working state, and the latch leakage target value is a current of a local circuit of the voltage domain circuit when latch effect occurs; based on any one of the voltage domain circuits, obtaining detection accuracy of the latch current limiting module, dividing the latch leakage target value by the detection accuracy to obtain a sub-power supply domain maximum current, and splitting the voltage domain circuit into a plurality of sub-power supply domain modules when the voltage domain working current is greater than the sub-power supply domain maximum current, wherein a working current of the sub-power supply domain module is less than or equal to the sub-power supply domain maximum current; connecting an input end of the power supply module to an output end of a power management unit of the power supply module, and connecting an input end of the power supply module to an output end of a power classification module to obtain the chip.

5. The method of claim 4, wherein, The chip further comprises a chip pin power module, an output end of the chip pin power module being connected to an input end of the power classification module, and the chip pin power module comprising at least one chip pin power supply connected to at least one of the sub power supplies. connecting an input end of the power supply module to an output end of a power classification module to obtain the chip, comprising: based on any one of the sub power domain modules, when the sub power domain module does not have a rugged design, connecting an input end of the power management unit to an output end of the latch current limiting module, and connecting an output end of the sub power supply to an input end of the latch current limiting module, or when the sub power domain module has a rugged design, connecting an output end of the sub power supply to an input end of the power management unit; mapping and optimizing all sub power supplies of the power classification module and the chip pin power supply, connecting the power classification module to the chip pin power supply to obtain the chip, wherein the chip pin power supply is connected to at least one of the sub power supplies.

6. The method of claim 5, wherein, The chip further comprises a storage module connected to the power supply module, the storage module storing configuration parameters, and the storage module being configured to provide the configuration parameters to all of the power management units and all of the latch current limiting modules. After obtaining the chip, further comprising: based on the power supply module connected to any one of the sub power domain modules, the chip is powered on, the dynamic range of the operating current of the sub power domain module is obtained, the configuration parameters are read from the storage module, and the power management unit and the latch current limiting module are configured by the power-on configuration function of the chip based on the configuration parameters and the dynamic range, wherein the parameters of the latch current limiting module include automatic restart function configuration parameters and restart delay values; the chip completes parameter configuration, and the chip enters a normal working state.

7. The method of claim 6, wherein, After the power management unit and the latch current limiting module are configured by the power-on configuration function of the chip based on the configuration parameters and the dynamic range, further comprising: the chip pin power supply is powered on, the chip pin power supply supplies power to the power classification module, and the power classification module supplies power to the power domain module through the power supply module; for any one of the sub power domain modules, when the operating current of the sub power domain module is greater than or equal to the maximum current of the sub power domain module, the latch current limiting module controls the power management unit to power off the sub power domain module; when the latch current limiting module is configured with an automatic restart function, the latch current limiting module restarts after the restart delay value, and the latch current limiting module controls the power management unit to restore power supply to the sub power domain module.

8. An anti-latch-up chip configuration device, comprising: comprising at least one control processor and a memory communicatively connected to the at least one control processor; the memory storing instructions executable by the at least one control processor, the instructions being executed by the at least one control processor to enable the at least one control processor to perform the method of configuring a chip against latch-up effects as claimed in any one of claims 4 to 7.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer executable instructions for causing a computer to perform the method of configuring a chip against latch-up effects as claimed in any one of claims 4 to 7.

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