Dual-threshold signal detection circuit for improving signal detection stability

Abstract

The invention discloses a dual-threshold signal detection circuit for improving signal detection stability, and belongs to the field of signal detection. The hysteresis interval of the high-speed signal detection circuit is reduced through sequential logic judgment, the problems of jittering and trailing of detection signals caused by noise generated by environmental factors and device characteristics in the design process are solved, and the signal detection speed is further increased while the signal detection stability is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of signal detection, in particular to a double-threshold signal detection circuit for improving signal detection stability. BACKGROUND

[0002] In high-frequency circuits, it takes a certain time for a signal to be fully established, and signal detection needs to be completed within a specified time. Due to the presence of jitter on the signal or the tailing phenomenon of the signal, the hysteresis interval of signal detection (the input amplitude interval that is responded to after exceeding the specified time) is relatively large.

[0003] The traditional architecture does not specially process the hysteresis interval, but mainly makes a compromise in filtering. If the filtering frequency is high, the signal establishment speed is fast, but the jitter will increase (when the signal amplitude is close to the threshold, the detection signal will respond to the jitter, and the detection will randomly respond to the same input amplitude). If the filtering frequency is low, the response time is long, which will delay the response time and also increase the hysteresis interval.

[0004] The compromise design determines the upper limit of the design, and greatly increases the design difficulty and uncertainty. SUMMARY

[0005] In view of the above deficiencies in the prior art, the present application provides a double-threshold signal detection circuit for improving signal detection stability.

[0006] In order to achieve the above-mentioned application purposes, the technical scheme adopted by the present application is as follows: A double-threshold signal detection circuit for improving signal detection stability, comprising an amplitude detection circuit, a first comparator, a second comparator, a logic output circuit, a threshold generation circuit and a delay circuit; the amplitude detection circuit is connected with the threshold generation circuit and the first comparator, and the amplitude detection circuit is also connected with the threshold generation circuit and the second comparator, the second comparator is connected with the delay circuit, and the delay circuit is connected with the first comparator and the logic output circuit.

[0007] Further, the amplitude detection circuit is configured to receive a differential input signal and convert it into a single-ended signal for outputting a detection signal.

[0008] Further, the threshold generation circuit is used to generate a high threshold voltage and a low threshold voltage, and the high threshold voltage and the low threshold voltage are output to the first comparator and the second comparator, respectively.

[0009] Further, the first comparator is configured to compare the output signal of the amplitude detection circuit with the high threshold voltage and output the comparison result to the logic output circuit; and the second comparator is configured to compare the output signal of the amplitude detection circuit with the low threshold voltage and output the comparison result to the delay circuit.

[0010] Further, the delay circuit is configured to perform fixed delay processing on the output signal of the second comparator, generate a delay signal, and output the delay signal to the logic output circuit to control the detection time of the signal valid.

[0011] Further, the logic output circuit is configured to output a high-level detection signal when the output signal of the delay circuit and the output signal of the first comparator are both high-level, and output a low-level detection signal otherwise.

[0012] Further, the delay circuit reduces the hysteresis interval of signal detection by delaying the output signal of the second comparator, avoids the influence of noise and jitter, and ensures the consistency of signal establishment time and effective detection time under different process angles.

[0013] The present application has the following advantages: The circuit detects signals through a double signal detection circuit and ensures that the response slower detection signal can be filtered when receiving data through a logic circuit design, reduces the detection trigger caused by signal jitter when the input signal is close to the threshold voltage, and ensures the consistency of signal establishment time and effective detection time under different process angles, avoids the super-high design difficulty caused by the compromise of detection delay, noise jitter and other problems. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 It is a traditional single threshold signal detection architecture.

[0015] Figure 2 It is a double threshold signal detection architecture of the present application.

[0016] Figure 3 It is a logic output circuit schematic of an embodiment of the present application.

[0017] Figure 4 It is the relationship between the output and the threshold under different input amplitudes of the traditional single threshold.

[0018] Figure 5 It is the response time relationship between the output and the threshold under different input amplitudes of the present application. DETAILED DESCRIPTION

[0019] The specific embodiments of the present application are described below to facilitate the understanding of those skilled in the art of the present application, but it should be clear that the present application is not limited to the scope of the specific embodiments, and for those skilled in the art, it is obvious that various changes are within the spirit and scope of the present application defined and determined by the appended claims, all the inventions utilizing the concept of the present application are within the scope of protection.

[0020] A double-threshold signal detection circuit for improving signal detection stability, comprising an amplitude detection circuit, a first comparator, a second comparator, a logic output circuit, a threshold generation circuit and a delay circuit; as shown in Figure 2 The amplitude detection circuit is connected with the threshold generation circuit and the first comparator, and the amplitude detection circuit is also connected with the threshold generation circuit and the second comparator, the second comparator is connected with the delay circuit, and the delay circuit is connected with the first comparator and the logic output circuit.

[0021] The amplitude detection circuit in the present application is configured to receive a differential input signal and convert it into a single-ended signal for outputting a detection signal.

[0022] The threshold generation circuit is used to generate a high threshold voltage and a low threshold voltage, and the high threshold voltage and the low threshold voltage are output to the first comparator and the second comparator respectively.

[0023] The first comparator is used to compare the output signal of the amplitude detection circuit with the high threshold voltage, and output the comparison result to the logic output circuit; the second comparator is used to compare the output signal of the amplitude detection circuit with the low threshold voltage, and output the comparison result to the delay circuit.

[0024] The delay circuit is used to perform fixed delay processing on the output signal of the second comparator, generate a delay signal, and output it to the logic output circuit to control the detection time of the signal effective.

[0025] The logic output circuit is configured to output a high-level detection signal when the output signal of the delay circuit and the output signal of the first comparator are both high, and output a low-level detection signal otherwise.

[0026] The delay circuit reduces the hysteresis interval of signal detection by delaying the output signal of the second comparator, avoids the influence of noise and jitter, and ensures the consistency of signal establishment time and effective detection time under different process angles.

[0027] In the prior art, as shown in Figure 1 The circuit converts the received differential pair signal into a single-ended signal by the amplitude detection circuit, the threshold generation circuit outputs a high threshold and a low threshold, the signal output by the amplitude detection circuit is compared with the high threshold by the comparator, and the output result is input to the logic output circuit.

[0028] The signal outputted by the threshold generating circuit is compared with the low threshold by a comparator, the output signal of the comparator is passed through a delay circuit, and the output signal of the delay circuit and the output signal of the comparator are inputted into a logic output circuit.

[0029] When the input of the logic output circuit is all high, the output signal is high; otherwise, the output signal is low.

[0030] The link mainly controls the detection time of the signal validity by the delay of the output signal of the comparator by the delay circuit.

[0031] Figure 4 The response time relationship between the output and the threshold under different input amplitudes in the traditional architecture. Due to the RC filtering, the closer the output is to the peak value, the slower the response speed is, so the closer the input amplitude is to the threshold, the longer the time for the filtered signal to exceed the threshold is. The output flip after exceeding the specified time Tvht belongs to the hysteresis range.

[0032] The input amplitude 1 signal exceeds the threshold within the specified time Tvth, the output amplitude 3 signal does not exceed the threshold due to the low amplitude, and no abnormality is generated in the application system. The input amplitude 2 signal exceeds the threshold outside the specified time Tvth, and the application system may have an abnormal response. Especially when the signal is close to the threshold, the signal may be jittered above the threshold due to noise in a short time, further increasing the hysteresis range. The larger the hysteresis range of the abnormal response is, the more difficult it is to make relevant configurations on the system.

[0033] Figure 5 The response time relationship between the output and the threshold under different input amplitudes in the architecture of the patent. As follows, the input amplitude 1 signal exceeds the threshold voltage 1 at time T0, generates a fixed delay at time T0D, exceeds the threshold voltage 2 at time T0A, and time T0A is between time T0 and T0D, so it can be determined that the signal exceeds the threshold. Similarly, as the amplitude 2 signal, the generated time T1A is outside the time T1 and T1D, so it is determined that the signal does not exceed the threshold. Under the same input signal amplitude, the architecture of the patent determines that the part of the signal close to the threshold is not detected, greatly reducing the influence of noise on the determination signal. Figure 2 、 Figure 3 All are first-order filtering step responses under different input signal amplitudes.

[0034] The principles and implementation manners of the present application are described by using specific examples in the present application, and the above examples are only used for helping to understand the method of the present application and its core idea; meanwhile, for the ordinary skilled in the art, according to the idea of the present application, the specific implementation manners and application ranges can be changed, and the above description should not be understood as the limitation of the present application.

[0035] Those skilled in the art will appreciate that the examples described herein are presented for purposes of aiding the reader in understanding the principles of the present application and are not intended to limit the scope of the present application to just such specifically recited examples and embodiments. Various modifications and alterations of the present application are possible and within the scope of the present application as would be understood by those skilled in the art, and it is intended to encompass all such modifications and alterations as fall within the scope of the present application.

Claims

1. A dual threshold signal detection circuit for improving signal detection stability, comprising an amplitude detection circuit, a first comparator, a second comparator, a logic output circuit, a threshold generation circuit and a delay circuit; characterized in that, The amplitude detection circuit is connected with the threshold generation circuit and the first comparator, and is also connected with the threshold generation circuit and the second comparator, the second comparator is connected with the delay circuit, and the delay circuit is connected with the first comparator and the logic output circuit.

2. The dual-threshold signal detection circuit to improve signal detection stability according to claim 1, characterized in that, The amplitude detection circuit is configured to receive a differential input signal and convert it into a single-ended signal for outputting a detection signal.

3. The dual-threshold signal detection circuit to improve signal detection stability of claim 1, wherein, The threshold generation circuit is configured to generate a high threshold voltage and a low threshold voltage, which are output to the first comparator and the second comparator, respectively.

4. The dual-threshold signal detection circuit to improve signal detection stability of claim 1, wherein, The first comparator is configured to compare the output signal of the amplitude detection circuit with the high threshold voltage and output a comparison result to the logic output circuit, and the second comparator is configured to compare the output signal of the amplitude detection circuit with the low threshold voltage and output a comparison result to the delay circuit.

5. The dual-threshold signal detection circuit to improve signal detection stability of claim 1, wherein, The delay circuit is configured to perform fixed delay processing on the output signal of the second comparator, generate a delay signal, and output the delay signal to the logic output circuit to control the detection time of a signal active state.

6. The dual-threshold signal detection circuit to improve signal detection stability of claim 1, wherein, The logic output circuit is configured to output a high-level detection signal when the output signal of the delay circuit and the output signal of the first comparator are both high-level signals, and output a low-level detection signal otherwise.

7. The dual-threshold signal detection circuit to improve signal detection stability of claim 1, wherein, The delay circuit reduces the hysteresis interval of signal detection by delaying the output signal of the second comparator, avoids the influence of noise and jitter, and ensures the consistency of signal establishment time and effective detection time under different process corners.

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