Communication method and device

Abstract

The invention provides a communication method and device, which are used for reducing the blind detection complexity of a PDCCH (Physical Downlink Control Channel). According to the method, under the condition that the PDCCH supports self-decoding (that is, the length of an information bit sequence is smaller than a threshold value), a coding structure (that is, information bits / frozen bits) of the PDCCH with a high aggregation level (for example, AL = 4 / 8 / 16 and the like) comprises a coding structure (that is, information bits / frozen bits) of the PDCCH with a low aggregation level (for example, AL = 2 / 4 / 8 and the like), and therefore even if the aggregation level of the PDCCH is high, the coding structure of the PDCCH can be decoded automatically. In this way, a receiving end can decode a small number of CCEs to obtain data, and does not need to continue decoding other CCEs, so that blind detection and early stop are achieved, and the complexity of a receiver is reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of communication, and in particular, to a communication method and device. BACKGROUND

[0002] A physical downlink control channel (PDCCH) is used to carry downlink control information (DCI). The scheduling unit of the PDCCH is a control channel element (CCE). Currently, the aggregation level that can be supported by the PDCCH is 1 / 2 / 4 / 8 / 16, that is, the PDCCH can include 1 / 2 / 4 / 8 / 16 CCEs.

[0003] Currently, the terminal device needs to decode all the PDCCHs before stopping decoding, that is, the terminal device cannot obtain the data sent by the network device through the PDCCH when decoding part of the code blocks of the PDCCH, and the terminal device can only stop blind detection after decoding all the code blocks of the PDCCH. For example, the network device sends a PDCCH with an aggregation level of 8 to the terminal device, and the terminal device cannot obtain the data sent by the network device through the PDCCH when decoding the first 4 CCEs, and can only stop blind detection after decoding all the 8 code blocks. SUMMARY

[0004] The present application provides a communication method and device to reduce the blind detection complexity of the PDCCH.

[0005] In a first aspect, a communication method is provided, which can be executed by a sending end. The sending end can be a network device, or a chip / chip system applied to the network device. Taking the network device as an example, in the method, the network device determines information bits corresponding to a first coded bit sequence according to the length of an information bit sequence, wherein if the length of the information bit sequence is less than or equal to a threshold value, the information bits corresponding to the first coded bit sequence include information bits corresponding to a second coded bit sequence, the first coded bit sequence and the second coded bit sequence are carried in a PDCCH, and the aggregation level of the first coded bit sequence is higher than that of the second coded bit sequence. The network device maps the information bit sequence to the information bits corresponding to the first coded bit sequence, generates the first coded bit sequence according to the bit sequence to which the information bit sequence is mapped, and then sends the first coded bit sequence.

[0006] The application supports self-decoding in the PDCCH, so that the coding structure (i.e. information bits / frozen bits) of part of bits in the PDCCH with a high aggregation level (e.g. AL=4 / 8 / 16, etc.) is the same as the coding structure (i.e. information bits / frozen bits) of the PDCCH with a low aggregation level (e.g. AL=2 / 4 / 8, etc.), so that even if the aggregation level of the PDCCH is high, the receiving end can decode a small number of CCEs to obtain data without continuing to decode other CCEs, thereby realizing early stopping of blind detection and reducing the complexity of the receiver.

[0007] In a possible design, the information bits corresponding to the first coded bit sequence include:

[0008] The first information bit set, the second information bit set and the third information bit set.

[0009] The first information bit set is composed of the same information bits in the fourth information bit set and the fifth information bit set.

[0010] The second information bit set is composed of the information bits different between the fourth information bit set and the fifth information bit set in the fourth information bit set.

[0011] The third information bit set is composed of the information bits different between the fourth information bit set and the fifth information bit set in the fifth information bit set.

[0012] The fourth information bit set is composed of the bit positions corresponding to the H subchannels with high reliability in the E subchannels, and the fifth information bit set is composed of the bit positions corresponding to the H subchannels with high reliability in the E / 2 subchannels.

[0013] The second information bit set and the third information bit set are used to carry the same first information bits, and the first information bit set is used to carry the information bits other than the first information bits in the information bit sequence.

[0014] E is the length of the first coded bit sequence, and H is an integer greater than 0.

[0015] The above design includes the information bits corresponding to the H subchannels with high reliability in the E / 2 subchannels in the information bits of the coded bit sequence with a high aggregation level, so that the information bits of the coded bit sequence with a high aggregation level can include the information bits of the coded bit sequence with a low aggregation level.

[0016] In a possible design, the information bits corresponding to the second coded bit sequence are composed of the first information bit set and the third information bit set. In this way, the information bits of the coded bit sequence with a high aggregation level can include the information bits of the coded bit sequence with a low aggregation level.

[0017] In a possible design, if the length of the information bit sequence is greater than a threshold value, the information bits corresponding to the first coded bit sequence include bit positions corresponding to H sub-channels with high reliability among E sub-channels, E is the length of the first coded bit sequence, and H is an integer greater than 0.

[0018] In a possible design, H is equal to the length of the information bit sequence, or H is equal to the sum of the length of the information bit sequence and the length of the CRC bit sequence.

[0019] In a possible design, if the aggregation level of the first coded bit sequence is 4, the threshold value is 70; or if the aggregation level of the first coded bit sequence is greater than or equal to 8, the threshold value is 140.

[0020] In a possible design, if the aggregation level of the first coded bit sequence is 4, the threshold value is 94; or if the aggregation level of the first coded bit sequence is greater than or equal to 8, the threshold value is 164.

[0021] In a possible design, the threshold value is related to at least one of the following: the aggregation level of the first coded bit sequence, the size of a CCE in the PDCCH, a switching threshold of a rate matching manner, and the length of the CRC bit sequence of the first coded bit sequence.

[0022] In a possible design, the threshold value is related to at least one of the following: the aggregation level of the first coded bit sequence, the size of a CCE in the PDCCH, and a switching threshold of a rate matching manner.

[0023] In a possible design, the threshold value satisfies the following formula:

[0024] Th=floor(AL / 2×CCE size ×R-CRC size );

[0025] where Th is the threshold value, AL is the aggregation level of the first coded bit sequence, CCE size is the size of a CCE in the PDCCH, CRC size is the length of the CRC bit sequence of the first coded bit sequence, R is the switching threshold of the rate matching manner, and floor() is a floor function.

[0026] In a possible design, the threshold value satisfies the following formula:

[0027] Th=floor(AL / 2×CCE size ×R);

[0028] where Th is the threshold value, AL is the aggregation level of the first coded bit sequence, CCE sizeis the size of CCE in PDCCH, R is the switching threshold of rate matching mode, and floor() is rounded down.

[0029] The design of the above three threshold values ​​can enable most PDCCHs to support self-decoding, thereby enabling blind detection of early stopping.

[0030] In one possible design, some bits in the first coded bit sequence are mapped to the same CCEs as those in the second coded bit sequence, and the information bits corresponding to some bits are the same as those corresponding to the second coded bit sequence. This design allows the receiver to decode a small number of CCEs to obtain data without further decoding other CCEs, thereby achieving blind detection and early stopping and reducing receiver complexity.

[0031] In one possible design, the starting point of the bit selection corresponding to the first coded bit sequence is related to at least one of the following parameters: the aggregation level of the first coded bit sequence, the code rate of the first coded bit sequence, and the rate matching method of the first coded bit sequence.

[0032] In one possible design, the first coded bit sequence satisfies the following formula:

[0033]

[0034] Among them, e k is the bit numbered k in the first coded bit sequence, E is the length of the first coded bit sequence, N is the length of the corresponding mother code, d n is the bit numbered n in the third coded bit sequence, where the third coded bit sequence is a bit sequence obtained by encoding the information bit sequence.

[0035] Through the above design, some of the bits carried by the PDCCH with a higher AL are the same as the bits carried by the PDCCH with a lower AL, and the mapped CCEs are also the same. Therefore, if the communication environment of the terminal device is relatively good, data can be obtained by decoding this part of the CCE without decoding all the CCEs of the PDCCH with a higher AL.

[0036] In one possible design, the first coded bit sequence is obtained by interleaving with the fourth coded bit sequence, and the fourth coded bit sequence is a bit sequence obtained by encoding and bit selection of the information bit sequence. This design enables the receiver to decode a small number of CCEs using the decoding method corresponding to the second coded bit sequence, thereby implementing blind detection and early stopping after acquiring the data.

[0037] In a possible design, the first M bits in the first coded bit sequence are the same as the last M bits in the fourth coded bit sequence, where M is the length of the second coded bit sequence. With the above design, the part of bits carried by the PDCCH with a higher AL are the same as the bits carried by the PDCCH with a lower AL, and the mapped CCEs are also the same, so that if the communication environment of the terminal device is good, the data can be obtained by decoding the part of CCEs, without decoding all the CCEs of the PDCCH with a higher AL.

[0038] In a possible design, the rate matching manner of the first coded bit sequence is repetition or puncturing.

[0039] In a possible design, the first coded bit sequence is generated according to the bit sequence mapped with the information bit sequence, including: encoding the bit sequence mapped with the information bit sequence to obtain a coded bit sequence; performing bit selection on the coded bit sequence; and generating the first coded bit sequence according to the bit sequence obtained after the bit selection.

[0040] In a possible design, the aggregation level of the second coded bit sequence is 4 or 2.

[0041] In a second aspect, a communication method is provided, which can be performed by a receiving end. The receiving end can be a terminal device, or a chip / chip system applied to the terminal device. Taking the terminal device as an example, in the method, the terminal device receives a first symbol sequence, and the first symbol sequence is carried in a PDCCH; determines information bits corresponding to the first symbol sequence according to the length of an information bit sequence, and if the length of the information bit sequence is less than or equal to a threshold value, the information bits corresponding to the first symbol sequence include information bits corresponding to a second symbol sequence, and the aggregation level of the first symbol sequence is higher than the aggregation level of the second symbol sequence; and decodes the first symbol sequence according to the information bits.

[0042] The present application supports self-decoding in the PDCCH, so that the coding construction (i.e., information bits / frozen bits) of part of bits in the PDCCH with a higher aggregation level (for example, AL=4 / 8 / 16, etc.) is the same as the coding construction (i.e., information bits / frozen bits) of the PDCCH with a lower aggregation level (for example, AL=2 / 4 / 8, etc.), so that even if the aggregation level of the PDCCH is high, the receiving end can decode a small number of CCEs to obtain data, without continuing to decode other CCEs, thereby realizing early stopping of blind detection and reducing the complexity of the receiver.

[0043] In a possible design, the information bits corresponding to the first symbol sequence include:

[0044] The first information bit set, the second information bit set, and the third information bit set.

[0045] The first information bit set is composed of the same information bits in the fourth information bit set and the fifth information bit set.

[0046] The second information bit set is composed of the different information bits in the fourth information bit set and the fifth information bit set.

[0047] The third information bit set is composed of the different information bits in the fourth information bit set and the fifth information bit set.

[0048] The fourth information bit set is composed of the bit positions corresponding to the H sub-channels with high reliability in the E sub-channels, and the fifth information bit set is composed of the bit positions corresponding to the H sub-channels sorted according to reliability in the E / 2 sub-channels.

[0049] The second information bit set and the third information bit set are used to carry the same first information bits, and the first information bit set is used to carry the information bits in the information bit sequence other than the first information bits.

[0050] E is the length of the first coded bit sequence, and H is an integer greater than 0.

[0051] The above design includes the information bits corresponding to the H sub-channels with high reliability in the E / 2 sub-channels in the information bits of the coded bit sequence with high aggregation level, so that the information bits of the coded bit sequence with high aggregation level can include the information bits of the coded bit sequence with low aggregation level.

[0052] In a possible design, the information bits corresponding to the second symbol sequence are composed of the first information bit set and the third information bit set. In this way, the information bits of the coded bit sequence with high aggregation level can include the information bits of the coded bit sequence with low aggregation level.

[0053] In a possible design, if the length of the information bit sequence is greater than a threshold value, the information bits corresponding to the first symbol sequence include the bit positions corresponding to the H sub-channels with high reliability in the E sub-channels, E is the length of the first coded bit sequence, and H is an integer greater than 0.

[0054] In a possible design, H is equal to the length of the information bit sequence, or H is equal to the sum of the length of the information bit sequence and the length of the CRC bit sequence.

[0055] In a possible design, if the aggregation level of the first symbol sequence is 4, the threshold value is 70; or if the aggregation level of the first symbol sequence is greater than or equal to 8, the threshold value is 140.

[0056] In a possible design, the threshold value is related to at least one of the following: the aggregation level of the first coded bit sequence, the size of the CCE in the PDCCH, the switching threshold of the rate matching manner, and the length of the CRC bit sequence of the first symbol sequence.

[0057] In a possible design, the threshold value is related to at least one of the following: the aggregation level of the first coded bit sequence, the size of the CCE in the PDCCH, the switching threshold of the rate matching manner, and the length of the CRC bit sequence of the first symbol sequence.

[0058] In a possible design, the threshold value is related to at least one of the following: the aggregation level of the first coded bit sequence, the size of the CCE in the PDCCH, and the switching threshold of the rate matching manner.

[0059] In a possible design, the threshold value satisfies the following formula:

[0060] Th=floor(AL / 2×CCE size ×R-CRC size );

[0061] wherein Th is the threshold value, AL is the aggregation level of the first coded bit sequence, CCE size is the size of the CCE in the PDCCH, CRC size is the length of the CRC bit sequence of the first symbol sequence, R is the switching threshold of the rate matching manner, and floor() is a floor function.

[0062] The three threshold values described above can enable most PDCCHs to support self-decoding, thereby enabling early stopping of blind detection.

[0063] In a possible design, the threshold value satisfies the following formula:

[0064] Th=floor(AL / 2×CCE size ×R);

[0065] wherein Th is the threshold value, AL is the aggregation level of the first coded bit sequence, CCE size is the size of the CCE in the PDCCH, and R is the switching threshold of the rate matching manner.

[0066] In a possible design, part of the coded bits in the first symbol sequence are mapped to the same control channel element (CCE) as the second symbol sequence, and the information bits corresponding to the part of the coded bits are the same as the information bits corresponding to the second symbol sequence. Through the above design, the receiver can decode a small amount of CCEs to obtain data, without continuing to decode other CCEs, thereby achieving early stopping of blind detection and reducing the complexity of the receiver.

[0067] In a possible design, the starting point of bit selection corresponding to the first symbol sequence is related to at least one of the following parameters: an aggregation level of the first symbol sequence, a code rate of the first symbol sequence, and a rate matching manner of the first symbol sequence.

[0068] In a possible design, the starting point of bit selection corresponding to the first symbol sequence is the same as the starting point of bit selection corresponding to the second symbol sequence. Through the foregoing design, the receiving end can decode a small amount of CCEs by using a decoding manner corresponding to the second encoded bit sequence, so that blind detection early stopping can be implemented after data is acquired.

[0069] In a possible design, the first encoded bit sequence satisfies the following formula:

[0070]

[0071] wherein e k is a bit numbered k in the first encoded bit sequence, E is a length of the first encoded bit sequence, N is a length of a corresponding mother code, d n is a bit numbered n in the third encoded bit sequence, and the third encoded bit sequence is a bit sequence obtained by encoding an information bit sequence.

[0072] Through the foregoing design, part of bits carried by a PDCCH with a higher AL is the same as bits carried by a PDCCH with a lower AL, and the mapped CCEs are also the same, so that if the communication environment of a terminal device is relatively good, data can be acquired by decoding the part of CCEs, without the need to decode all CCEs of the PDCCH with the higher AL.

[0073] In a possible design, the encoded bit sequence corresponding to the first symbol sequence is obtained by interleaving a fourth encoded bit sequence, and the fourth encoded bit sequence is a bit sequence obtained by encoding and bit selection on an information bit sequence. Through the foregoing design, the receiving end can decode a small amount of CCEs by using a decoding manner corresponding to the second encoded bit sequence, so that blind detection early stopping can be implemented after data is acquired.

[0074] In a possible design, the first M bits in the encoded bit sequence corresponding to the first symbol sequence are the same as the last M bits in a fourth encoded bit sequence, wherein M is a length of the second symbol sequence. Through the foregoing design, part of bits carried by a PDCCH with a higher AL is the same as bits carried by a PDCCH with a lower AL, and the mapped CCEs are also the same, so that if the communication environment of a terminal device is relatively good, data can be acquired by decoding the part of CCEs, without the need to decode all CCEs of the PDCCH with the higher AL.

[0075] In a possible design, the rate matching manner of the first symbol sequence is repetition or puncturing.

[0076] In a possible design, the decoding of the first symbol sequence according to the information bits comprises: recovering the first symbol sequence according to a bit selection method corresponding to the first symbol sequence to obtain a third symbol sequence; decoding the third symbol sequence according to the information bits; and obtaining the information bit sequence from the decoded bit sequence.

[0077] In a possible design, the aggregation level of the second encoded bit sequence is 4 or 2.

[0078] In a third aspect, the present application provides a communication apparatus, which is a network device or a chip in a network device. The communication apparatus has the function of implementing any method provided in the first aspect. The communication apparatus can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more units or modules corresponding to the above functions.

[0079] In a possible design, the communication apparatus includes a processor configured to support the communication apparatus to perform the corresponding functions of the network device in the above methods. The communication apparatus can further include a memory coupled to the processor, which stores program instructions and data necessary for the communication apparatus. Optionally, the communication apparatus further includes an interface circuit, which is configured to support the communication apparatus to communicate with devices such as terminal devices, for example, to transmit or receive data or signals. Exemplarily, the communication interface can be a transceiver, a circuit, a bus, a module or other types of communication interfaces.

[0080] In a possible design, the communication apparatus includes corresponding functional modules for implementing the steps in the above methods. The functions can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

[0081] In a possible design, the structure of the communication apparatus includes a processing unit (or a processing module) and a communication unit (or a communication module), which can perform the corresponding functions in the above method examples, and details are described in the method provided in the first aspect, which will not be repeated here.

[0082] In a fourth aspect, the present application provides a communication apparatus, which is a terminal device or a chip in a terminal device. The communication apparatus has the function of implementing any method provided in the second aspect. The communication apparatus can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more units or modules corresponding to the above functions.

[0083] In a possible design, the communication apparatus includes a processor configured to support the communication apparatus to perform the corresponding functions of the terminal device in the above-described method. The communication apparatus can further include a memory coupled to the processor, which stores program instructions and data necessary for the communication apparatus. Optionally, the communication apparatus further includes an interface circuit configured to support the communication apparatus to perform communication, such as data or signal transmission and reception, with another device, such as a network device. For example, the communication interface can be a transceiver, a circuit, a bus, a module, or another type of communication interface.

[0084] In a possible design, the communication apparatus includes corresponding functional modules for implementing the steps in the above-described method. The functions can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-described functions.

[0085] In a possible design, the structure of the communication apparatus includes a processing unit (or a processing module) and a communication unit (or a communication module), which can perform the corresponding functions in the above-described method, details of which can be referred to the description of the method in the second aspect, which will not be repeated here.

[0086] In the fifth aspect, a communication apparatus is provided, which includes a processor and an interface circuit. The interface circuit is configured to receive a signal from another communication apparatus outside the communication apparatus and transmit the signal to the processor, or send a signal from the processor to another communication apparatus outside the communication apparatus. The processor is configured to implement the method in the first aspect and any possible design by means of a logic circuit or by executing code instructions.

[0087] In the sixth aspect, a communication apparatus is provided, which includes a processor and an interface circuit. The interface circuit is configured to receive a signal from another communication apparatus outside the communication apparatus and transmit the signal to the processor, or send a signal from the processor to another communication apparatus outside the communication apparatus. The processor is configured to implement the method in the second aspect and any possible design by means of a logic circuit or by executing code instructions.

[0088] In the seventh aspect, a computer readable storage medium is provided, which stores a computer program or instructions. When the computer program or instructions are executed by a processor, the method in the first aspect or the second aspect and any possible design is implemented.

[0089] In the eighth aspect, a computer program product is provided, which stores instructions. When the instructions are executed by a processor, the method in the first aspect or the second aspect and any possible design is implemented.

[0090] In a ninth aspect, a chip system is provided, which includes a processor and can further include a memory for implementing the method in the first aspect or the second aspect and any possible design. The chip system can be composed of a chip or can include a chip and other discrete devices.

[0091] In a tenth aspect, a communication system is provided, which includes the apparatus (e.g., a network device) in the first aspect and the apparatus (e.g., a terminal device) in the second aspect.

[0092] The technical effects that can be achieved by the technical solutions in any of the third aspect to the tenth aspect can be described with reference to the technical effects that can be achieved by the technical solutions in the first aspect, and the repeated parts will not be described herein. BRIEF DESCRIPTION OF DRAWINGS

[0093] Figure 1 An architecture diagram of a communication system according to an embodiment of the present application;

[0094] Figure 2 A polar encoding diagram according to an embodiment of the present application;

[0095] Figure 3 A flow diagram of a communication method according to an embodiment of the present application;

[0096] Figure 4 An information bit diagram according to an embodiment of the present application;

[0097] Figure 5 An encoding flow diagram according to an embodiment of the present application;

[0098] Figure 6 A sub-block interleaving diagram according to an embodiment of the present application;

[0099] Figure 7 A sub-block interleaving diagram according to an embodiment of the present application;

[0100] Figure 8 A structure diagram of a communication apparatus according to an embodiment of the present application;

[0101] Figure 9 A structure diagram of a communication apparatus according to an embodiment of the present application. DETAILED DESCRIPTION

[0102] The embodiments of the present application can be applied to various fields using polar coding, such as data storage field, optical network communication field, and wireless communication field, and the like. The foregoing wireless communication field can include, but is not limited to, 5G communication system, future communication system (such as 6G communication system), satellite communication system, device-to-device (D2D) communication system, machine to machine (M2M) communication system, internet of things (IoT), unmanned aerial vehicle communication system, narrow band-internet of things (NB-IoT) system, long term evolution (LTE) system, and three application scenarios of 5G mobile communication system, eMBB, ultra reliable low latency communication (URLLC), and massive machine-type communications (mMTC).

[0103] The communication system to which the data transmission method provided by the embodiments of the present application is applicable will be introduced below in combination with Figure 1 Figure 1 The communication system 100 includes a sending end 101 and a receiving end 102. The sending end 101 can be a network device or a terminal device, and the receiving end 102 can be a network device or a terminal device. Optionally, when the sending end 101 is a network device, the receiving end 102 can be a terminal device; when the receiving end 102 is a network device, the sending end 101 can be a terminal device.

[0104] The sending end 101 can include an encoder, and the sending end 101 can perform polar coding on the to-be-coded bits through the encoder and output the coded codewords. The coded codewords can be transmitted to the receiving end 102 through rate matching, interleaving, and modulation on the channel. The receiving end 102 can include a decoder, and the receiving end 102 can receive and demodulate the signal from the sending end 101, and the receiving end 102 can perform decoding on the received signal through the decoder.

[0105] ​The terminal device to which the present application relates includes a device that provides voice and / or data connectivity to a user, and specifically includes a device that provides voice connectivity to a user, or a device that provides data connectivity to a user, or a device that provides both voice and data connectivity to a user. For example, the terminal device can include a handheld device having wireless connection capability, or a processing device connected to a wireless modem. The terminal device can include a user equipment (UE), a wireless terminal device, a mobile terminal device, a device-to-device (D2D) terminal device, a vehicle-to-everything (V2X) terminal device, a machine-to-machine / Machine-Type Communications (M2M / MTC) terminal device, an Internet of Things (IoT) terminal device, a subscriber unit, a subscriber station, a mobile station, a remote station, an access point (AP), a remote terminal, an access terminal, a user terminal, a user agent, or a user device, a satellite, a drone, a balloon, an airplane, etc. For example, the terminal device can include a mobile telephone (also known as a "cellular" telephone), a computer with mobile termination, a portable, pocket, hand-held, computer-included mobile device, etc. For example, the terminal device can include a personal communication service (PCS) telephone, a cordless telephone, a session initiation protocol (SIP) telephone, a wireless local loop (WLL) station, a personal digital assistant (PDA), etc. The terminal device can also include a limited device, such as a low power device, or a limited storage device, or a limited computing device, etc. For example, the terminal device can include a bar code, a radio frequency identification (RFID), a sensor, a global positioning system (GPS), a laser scanner, etc. As an example and not by way of limitation, the terminal device can also be a wearable device in embodiments of the present application.The wearable device can also be referred to as a smart wearable device or a smart wearable device, etc., which is a general term for devices that are designed and developed by applying wearable technology to daily wear. The various terminal devices introduced above can be considered as vehicle-mounted terminal devices if they are located on a vehicle (e.g., placed inside or installed inside a vehicle), and the vehicle-mounted terminal device is also referred to as an on-board unit (OBU), for example.

[0106] The network device involved in the present application, for example, includes an access network (AN) device, such as a base station (e.g., an access point), which can refer to a device in an access network that communicates with a wireless terminal device through one or more cells over the air interface, or for example, a network device in a vehicle-to-everything (V2X) technology is a road side unit (RSU). The network device can include an evolved base station (NodeB or eNB or e-NodeB, evolutional Node B) in a long term evolution (LTE) system or long term evolution-advanced (LTE-A), or can also include a next generation node B (gNB) in an evolved packet core (EPC), a 5th generation (5G), a new radio (NR) system (also referred to as an NR system), or can also include a centralized unit (CU) and a distributed unit (DU) in a cloud radio access network (Cloud RAN) system, satellites, drones, balloons, and aircraft, etc., and the embodiments of the present application are not limited.

[0107] At present, since the polar coding can be strictly proved to reach the channel capacity of the channel coding scheme, it has high performance, low complexity, flexible matching mode, etc. At present, it has been determined by the third generation partnership project (3 rd generation partnership project, 3GPP) to be the control channel coding scheme for the 5G control channel enhanced mobile broadband (eMBB) scenario.

[0108] Referring to Figure 2 , a polar coding schematic diagram is shown.Figure 2 Corresponding to the encoding code length of 8, each circle in each row represents a summation between the bit of the row where the circle is located and the row where the circle reaches, and the bit on the right side of the circle is the summation result. For example, the first circle in the row where the first frozen bit is located means that the summation between the frozen bit 0 of the first row where the circle is located and the bit 0 of the second row where the circle reaches is 0.

[0109] wherein u0 to u7 are to-be-encoded bits, and the to-be-encoded bits are divided into two categories of fixed bits (frozen) and information bits (data) according to the reliability of the corresponding bit subchannels. The bit subchannels with lower reliability are set as fixed bit subchannels, and the bit values are usually 0. The bit subchannels with higher reliability are set as information bit subchannels, and are used to carry information bits. As shown in Figure 2 u7, u6, u5, and u3 are four bit subchannels with higher reliability, and are set as information bits, and u4, u2, u1, and u0 are four bits with lower reliability, and are set as fixed bits (frozen).

[0110] It should be noted that during data transmission, the receiving end and the transceiving end of the fixed bit subchannel are known. It can be understood that the bit subchannel can also be referred to as a subchannel in this paper. Similarly, the bit subchannel set can also be referred to as a subchannel set.

[0111] At present, polar encoding can be applied to a physical downlink control channel (PDCCH). The PDCCH is introduced below.

[0112] The PDCCH is used to carry downlink control information (DCI). The scheduling unit of the PDCCH is a control channel element (CCE). A CCE can carry a coded bit sequence of 108 bits. At present, the aggregation level (AL) that can be supported by the PDCCH is 1 / 2 / 4 / 8 / 16, that is, the PDCCH can include 1 / 2 / 4 / 8 / 16 CCEs, and therefore, the length E of the coded bit sequence of the PDCCH is 108 bits, 216 bits, 432 bits, 864 bits, and 1728 bits. At present, the maximum mother code length N of the PDCCH coding and decoding is 512 bits, and therefore, for the PDCCH with AL of 8\16, a sequence of 512 bits can be obtained through polar encoding, and then bits are repeatedly selected in the sequence of 512 bits to obtain coded bit sequences of 864 bits and 1728 bits.

[0113] For example, when AL = 8\16 of PDCCH, a coded bit sequence d0, d1, d2, …, d N-1 , of length 512 can be obtained by Polar code encoding. Then sub-block interleaving is performed, and the interleaved coded bit sequence can be denoted as y0, y1, y2, …, y N-1 . Then bit selection can be performed in y0, y1, y2, …, y N-1 according to the following pseudo code to obtain a coded bit sequence of length 864 / 1728:

[0114] for k = 0 to E-1

[0115] ek= y mod(k,N) ;

[0116] end for

[0117] According to the above pseudo code, when AL = 8\16, the starting point e0 of bit selection is from the first bit y0.

[0118] When AL = 4 of PDCCH, a coded bit sequence of length 512 can be obtained by Polar code encoding. Then sub-block interleaving is performed, and the interleaved coded bit sequence can be denoted as y0, y1, y2, …, y N-1 . Then bit selection can be performed in y0, y1, y2, …, y N-1 according to the following pseudo code to obtain a coded bit sequence of length 432:

[0119] for k = 0 to E-1

[0120] e k = y k+N-E ;

[0121] end for

[0122] According to the above pseudo code, when AL = 4, the first 80 bits are skipped in bit selection, and the starting point e0 of bit selection is from the 81st bit y 80 .

[0123] Currently, the terminal device needs to decode all the PDCCH before stopping decoding after receiving the PDCCH, even if the terminal device has obtained the data sent by the network device through the PDCCH when decoding part of the code blocks of the PDCCH, the terminal device still needs to stop decoding after decoding all the PDCCH. For example, the network device sends a PDCCH with AL=8 to the terminal device, if the communication environment of the terminal device is good, the data can be obtained through 4 CCE, but the terminal device still needs to decode all the 8 CCE of the PDCCH according to the decoding mode corresponding to AL=8, which leads to high complexity of PDCCH blind detection.

[0124] Therefore, the embodiment of the present application provides a communication method and device, which, in the case that the PDCCH supports self-decoding (i.e., the length of the information bit sequence is less than a threshold value), makes the encoding construction (i.e., information bit / frozen bit) of the PDCCH with a higher aggregation level (e.g., AL=4 / 8 / 16, etc.) include the encoding construction (i.e., information bit / frozen bit) of the PDCCH with a lower aggregation level (e.g., AL=2 / 4 / 8, etc.), so that even if the aggregation level of the PDCCH is high, the receiving end can decode a small number of CCE to obtain data, without continuing to decode other CCE, thereby realizing early stopping of blind detection and reducing the complexity of the receiver. The method and the device are based on the same concept, and since the principles of the method and the device for solving the problem are similar, the implementation of the device and the method can be mutually referred to, and the repeated parts will not be described herein.

[0125] In the embodiments of the present application, "when", "if" and "whether" all refer to the case that the device will make corresponding processing under certain objective circumstances, and are not limited by time, and do not require the device to have a judgment action when implemented, and also do not mean that there are other limitations. Unless otherwise specified, "if" and "whether" can be replaced, and "when" and "in the case of" can be replaced. "When" and "if" / "whether" can be replaced.

[0126] In the embodiments of the present application, "at least one" means one or more, and "multiple" means two or more. "And / or" describes the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, A and / or B, which can represent the following cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or the like means any combination of these items, including single item or any combination of multiple items. For example, at least one of a, b, or c, can represent a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, and c can be single or multiple.

[0127] And, unless there is a contrary indication, the application embodiments refer to the ordinal numbers such as "first", "second" and the like are used to distinguish a plurality of objects, and are not used to limit the size, content, order, timing, priority or importance of the plurality of objects, and the like. For example, the first encoding bit sequence and the second encoding bit sequence are only used to distinguish different encoding bit sequences, and do not represent the difference in length, priority or importance of the two encoding bit sequences.

[0128] The network architecture and service scenarios described in the application embodiments are used to more clearly illustrate the technical solutions of the application embodiments, and do not constitute a limitation on the technical solutions provided by the application embodiments. Those skilled in the art can know that, with the evolution of network architecture and the appearance of new service scenarios, the technical solutions provided by the application embodiments are also applicable to similar technical problems.

[0129] In the application, the encoding structure can be understood as the position of the information bit / frozen bit. The same encoding structure can be understood as the same information bit. The same information bit also means the same frozen bit. The information bit and the frozen bit can be derived from each other.

[0130] Referring to Figure 3 , a flowchart of a communication method provided by the application is shown. The method comprises:

[0131] S301, the network device determines the information bit corresponding to the first encoding bit sequence according to the length of the information bit sequence.

[0132] Wherein, if the length of the information bit sequence is less than a threshold value Th, the information bit corresponding to the first encoding bit sequence includes the information bit corresponding to the second encoding bit sequence, the aggregation level of the first encoding bit sequence is higher than the aggregation level of the second encoding bit sequence, and the first encoding bit sequence is carried on the PDCCH.

[0133] For example, the length of the information bit sequence can be the length K of the payload, or the length of the information bit sequence can also be the sum of the length of the payload and the CRC bit, that is, K+L.

[0134] For example, the information bit corresponding to the first encoding bit sequence can include a first information bit set, a second information bit set and a third information bit set. The encoding structure of the first encoding bit sequence can be called the first encoding structure. As Figure 4 shown.

[0135] Wherein, the first information bit set is composed of E sub-channels according to the same sub-channel corresponding bit in the H sub-channels with high reliability and the H sub-channels with high reliability in the E / 2 sub-channels. For example, the above-mentioned E / 2 sub-channels can be the last E / 2 sub-channels in the E sub-channels.

[0136] For the convenience of description, the bit set corresponding to the H sub-channels with high reliability in the E sub-channels is referred to as a fourth information bit set, and the bit set corresponding to the H sub-channels with high reliability in the E / 2 sub-channels is referred to as a fifth information bit set. E is the length of the first encoded bit sequence, and H is an integer greater than 0, for example, H is equal to the length K of the payload, or H is equal to the sum of the length of the payload and the length of the cyclic redundancy check (CRC) bit, that is, K+L, and the like.

[0137] In an exemplary description, the H sub-channels with high reliability can be understood as the first H sub-channels in the order of reliability from high to low.

[0138] The second information bit set is composed of information bits in the fourth information bit set that are different from the fifth information bit set.

[0139] The third information bit set is composed of information bits in the fifth information bit set that are different from the fourth information bit set.

[0140] In the above information bits, the second information bit set and the third information bit set are used to carry the same first information bits. The information bits in the second information bit set and the third information bit set can be one-to-one corresponding (or associated), and the information bits with the corresponding relationship or the association relationship carry the same information bits. The first information bit set is used to carry information bits in the information bit sequence except the first information bits. That is, the first information bit set and the second information bit set jointly carry all bits of the information bit sequence, and the first information bit set and the third information bit set jointly carry all bits of the information bit sequence. It should be understood that the first information bits can include one or more information bits.

[0141] In the above manner, the fourth information bit set can be the union of the first information bit set and the second information bit set, and the fifth information bit set can be the union of the first information bit set and the third information bit set.

[0142] Since the information bits corresponding to the second encoded bit sequence can include the bit set corresponding to the H sub-channels with high reliability in the E / 2 sub-channels, that is, the above-mentioned fifth information bit set, that is, the union of the first information bit set and the third information bit set. It can be seen that the information bits corresponding to the first encoded bit sequence include the information bits corresponding to the second encoded bit sequence.

[0143] If the length of the information bit sequence is greater than the threshold value Th, the first coded bit sequence corresponds to the information bits including the bits of the H sub-channels with high reliability in the E sub-channels, i.e., the fourth information bit set described above, E is the length of the first coded bit sequence, and H is an integer greater than 0. The coding construction of the first coded bit sequence can be referred to as a second coding construction.

[0144] When the length of the information bit sequence is equal to the threshold value Th, the coding construction of the first coded bit sequence can be the first coding construction, i.e., including the first information bit set, the second information bit set, and the third information bit set. Alternatively, the coding construction of the first coded bit sequence can also be the second coding construction, i.e., including the fourth information bit set.

[0145] The threshold value will be introduced below in combination with two cases of the length of the information bit sequence.

[0146] Case one, the length of the information bit sequence can be the length K of the payload, and the threshold value can be any one of the following examples one to three.

[0147] Example one, if the aggregation level of the first coded bit sequence is 1 or 2, Th is a numerical value 1, for example, the numerical value 1 is 0. If the aggregation level of the first coded bit sequence is 4, Th is a numerical value 2, for example, the numerical value 2 is 70. If the aggregation level of the first coded bit sequence is greater than or equal to 8, Th is a numerical value 3, for example, the numerical value 3 is 140.

[0148] It can be understood that if the aggregation level of the first coded bit sequence is 1 or 2, the coding construction of the first coded bit sequence is the second coding construction. If the aggregation level of the first coded bit sequence is 4 or 8, or a higher aggregation level, and the aggregation level of the first coded bit sequence is greater than 8, when the length K of the information bit sequence is less than Th, the coding construction of the first coded bit sequence is the first coding construction, and when the length K of the information bit sequence is less than Th, the coding construction of the first coded bit sequence is the second coding construction.

[0149] Example two, Th is related to at least one of the following: the aggregation level of the first coded bit sequence, the size (or length) of the CCE in the PDCCH, the switching threshold of the rate matching mode (or described as the switching code rate R), and the length of the CRC bit sequence of the first coded bit sequence. The switching threshold of the rate matching mode can be understood as a threshold value for determining the rate matching mode. For example, assuming that the determination method of the rate matching mode is that if E>N, the rate matching mode adopts repetition; if E≤N, when R=K / E≤7 / 16, the puncturing is adopted, and when R=K / E>7 / 16, the truncation is adopted. The switching threshold of the rate matching mode can be 7 / 16.

[0150] Example three, Th can satisfy the following formula:

[0151] Th = floor (AL / 2 x CCE size x R-CRC size ) ;

[0152] Or, Th = ceil (AL / 2 x CCE size x R-CRC size ) ;

[0153] Or, Th = round (AL / 2 x CCE size x R-CRC size ) ;

[0154] Wherein, Th is a threshold value, AL is the aggregation level of the first coded bit sequence, CCE size is the size (or length) of CCE in PDCCH, CRC size is the length of CRC bit sequence of the first coded bit sequence, R is the switching threshold of rate matching mode, floor () is the down rounding.

[0155] Case two, the length of information bit sequence is the sum of load and the length of CRC bit, that is K+L, the threshold value can be any one of the following examples four to six.

[0156] Example four, if the aggregation level of the first coded bit sequence is 1 or 2, Th is the value 2, for example, the value 1 is 24. If the aggregation level of the first coded bit sequence is 4, Th is the value 2, for example, the value 2 is 94. If the aggregation level of the first coded bit sequence is greater than or equal to 8, Th is the value 3, for example, the value 3 is 164.

[0157] It can be understood that if the aggregation level of the first coded bit sequence is 1 or 2, the coding construction of the first coded bit sequence is the second coding construction. If the aggregation level of the first coded bit sequence is 4 or 8, or higher aggregation level, the aggregation level of the first coded bit sequence is greater than 8, when the length of information bit sequence is less than Th, the coding construction of the first coded bit sequence is the first coding construction, when the length of information bit sequence is less than Th, the coding construction of the first coded bit sequence is the second coding construction.

[0158] In Example 5, Th is related to at least one of the following: the aggregation level of the first coded bit sequence, the size (or length) of the CCE in the PDCCH, and the switching threshold of the rate matching manner (or described as the switching rate R). The switching threshold of the rate matching manner can be understood as a threshold value for determining the rate matching manner. For example, assuming that the determination manner of the rate matching manner is that if E > N, the rate matching manner adopts repetition; if E ≤ N, when R = K / E ≤ 7 / 16, puncturing is adopted, and when R = K / E > 7 / 16, truncation is adopted. The switching threshold of the rate matching manner can be 7 / 16.

[0159] In Example 6, Th can satisfy the following formula:

[0160] Th = floor (AL / 2 × CCE size × R) ;

[0161] or Th = ceil (AL / 2 × CCE size × R) ;

[0162] or Th = round (AL / 2 × CCE size × R) ;

[0163] wherein Th is a threshold value, AL is the aggregation level of the first coded bit sequence, CCE size is the size (or length) of the CCE in the PDCCH, R is the switching threshold of the rate matching manner, floor() is the floor function, ceil() is the ceiling function, and round() is the rounding function.

[0164] In S302, the network device maps the information bit sequence to the information bits corresponding to the first coded bit sequence.

[0165] In S303, the network device generates the first coded bit sequence according to the bit sequence in which the information bit sequence is mapped.

[0166] In S304, the network device transmits the first coded bit sequence. Correspondingly, the terminal device receives the first symbol sequence.

[0167] It should be understood that the first symbol sequence can be a signal received through a spatial channel after the first coded bit sequence is subjected to modulation, frequency conversion, and the like.

[0168] In S305, the terminal device determines the information bits corresponding to the first symbol sequence according to the length of the information bit sequence.

[0169] If the length of the information bit sequence is less than the threshold value, the information bits corresponding to the first symbol sequence include the information bits corresponding to the second symbol sequence, and the aggregation level of the first symbol sequence is higher than the aggregation level of the second symbol sequence.

[0170] S306, the terminal device decodes the first symbol sequence according to the information bits.

[0171] The specific decoding process will be described below in combination with the encoding process of the first encoded bit sequence.

[0172] The present application supports self-decoding in PDCCH, so that the encoding construction (i.e. information bits / frozen bits) of part of bits in PDCCH with a higher aggregation level (e.g. AL=4 / 8 / 16, etc.) is the same as that of PDCCH with a lower aggregation level (e.g. AL=2 / 4 / 8, etc.), so that even if the aggregation level of PDCCH is high, the receiving end can decode a small number of CCEs to obtain data without continuing to decode other CCEs, thereby realizing early stopping of blind detection and reducing the complexity of the receiver.

[0173] In a possible embodiment, part of the CCEs to which the bits in the first encoded bit sequence are mapped are the same as the CCEs to which the bits in the second encoded bit sequence are mapped. For example, taking the aggregation level of the first encoded bit sequence as 8 and the aggregation level of the second encoded bit sequence as 4 as an example, assuming that the first encoded bit sequence is mapped on CCEs #0-#7 and the second encoded bit sequence is mapped on CCEs #0-#3, in the present application, part of the bits in the first encoded bit sequence that have the same encoding construction (i.e. the same information bits) as the second encoded bit sequence can be mapped on CCEs #0-#3. Two implementation manners of this embodiment will be described below in combination with the generation process of the first encoded bit sequence.

[0174] First, the generation / encoding process of the first encoded bit sequence will be described.

[0175] As shown in Figure 5 , the generation process of the first encoded bit sequence can include:

[0176] S501, determining the mother code length N of the PDCCH.

[0177] In an implementation manner, the parameter n can be determined according to the following pseudo code first, and then the mother code length N of the PDCCH can be obtained according to N=2 n

[0178]

[0179] According to the above pseudo code, in an example, the mother code length N of the PDCCH is n max a positive integer, for example, n max =9, etc. In another implementation manner, the parameter n1 can be determined according to the length E of the first encoded bit sequence first, and then the mother code length N of the PDCCH can be obtained according to N=2 n ​, the mother code length N of the PDCCH is obtained:

[0180]

[0181] R min = 1 / 8;

[0182]

[0183] n = max{min{n1, n2, n max}, n min};

[0184] Compared with the previous implementation mode, the implementation mode improves the performance stability of the Polar code construction.

[0185] S502, determining a rate matching mode of the first coded bit sequence.

[0186] In a possible implementation mode, if E>N, the rate matching mode adopts repetition; if E≤N, when K / E≤7 / 16, puncturing is adopted, and when K / E>7 / 16, shortening is adopted.

[0187] For example, the rate matching mode of the first coded bit sequence can be repetition or puncturing.

[0188] S503, determining information bits / frozen bits.

[0189] For details, refer to the related description of S301.

[0190] S504, mapping the information bit sequence to the information bits, and performing Polar code encoding to obtain an N-long coded bit vector d0, d1, d2, …, d N-1 .

[0191] S505, performing sub-block interleaving on d0, d1, d2, …, d N-1 to obtain an N-long coded bit vector y0, y1, y2, …, y N-1 .

[0192] It should be noted that S505 is an optional step.

[0193] S506, performing bit selection on the N-long coded bit vector (which can be d0, d1, d2, …, d N-1 , or y0, y1, y2, …, y N-1 ), and obtaining the first coded bit sequence according to the bit sequence after the bit selection.

[0194] Optionally, the starting point of the bit selection corresponding to the first encoded bit sequence is related to the aggregation level, code rate, rate matching manner, etc.

[0195] The starting point of the bit selection corresponding to the first encoded bit sequence can refer to the position of the first bit selected in the N-length encoded bit vector, or can be understood as the position of the first bit of the first encoded bit sequence in the N-length encoded bit vector.

[0196] In a possible implementation, to make the part of the CCEs mapped by the first encoded bit sequence and the CCEs mapped by the second encoded bit sequence same in the encoding construction, the starting point of the bit selection corresponding to the first encoded bit sequence can be modified, for example, the starting point of the bit selection corresponding to the first encoded bit sequence can be related to the aggregation level, code rate, rate matching manner, etc.

[0197] For example, the first encoded bit sequence can satisfy the following formula, or the first encoded bit sequence can be determined by the following formula:

[0198]

[0199] wherein, e k is the kth bit in the first encoded bit sequence, wherein e0 is the first bit of the first encoded bit sequence, that is, the starting point of the bit selection corresponding to the first encoded bit sequence. For example, the length of the first bit sequence is determined based on the length of the first encoded bit sequence; or the length of the first bit sequence is 432 / 216 / 108; or the length of the first bit sequence is the length of the second encoded bit sequence.

[0200] Optionally, if the length of the information bit sequence is greater than a threshold value, the first encoded bit sequence can satisfy the following formula:

[0201] e k = d k+N-E .

[0202] The above method can be implemented by the following pseudo code:

[0203] Bit selection part:

[0204]

[0205] In another possible implementation, in order to make the part of the first coded bit sequence which is mapped to the same CCE as the second coded bit sequence after the encoding construction of the second coded bit sequence, interleaving can be performed after the bit selection in the above S506. For example, assuming that the coded bit sequence 1 is obtained after the bit selection in the above S506, the first coded bit sequence is obtained after the interleaving of the coded bit sequence 1.

[0206] In this way, the bit selection can be implemented by the following pseudo code:

[0207]

[0208] For example, the first M bits in the first coded bit sequence are the same as the last M bits in the coded bit sequence 1, where M is the length of the second coded bit sequence.

[0209] In one specific implementation, the coded bit sequence 1 can be cyclically shifted forward according to the starting point of the PDCCH (or coded bit sequence) when AL=2, so that the first M bits in the first coded bit sequence are the same as the bit sequence of the PDCCH when AL=2.

[0210] For example, the coded bit sequence 1 can be divided into several sub-blocks according to the length of the PDCCH (or coded bit sequence) when AL=4. For example, if the AL of the coded bit sequence 1 is 8, the coded bit sequence 1 can be divided into 2 sub-blocks. If the AL of the coded bit sequence 1 is 16, the coded bit sequence 1 can be divided into 4 sub-blocks. When the coded bit sequence 1 is sub-block interleaved, the last sub-block can be interleaved first. For example, assuming that the AL of the coded bit sequence 1 is 8, the coded bit sequence 1 can be divided into 2 sub-blocks, i.e., sub-block 0 and sub-block 1, and after the sub-block interleaving, the sub-block 1 is located before the sub-block 0, as shown in FIG. 6. Figure 6 For example, assuming that the AL of the coded bit sequence 1 is 16, the coded bit sequence 1 can be divided into 4 sub-blocks, i.e., sub-block 0 to sub-block 3, and after the sub-block interleaving, the sub-block 3 is located before the sub-block 0, sub-block 1 and sub-block 2, as shown in FIG. 7. Figure 7

[0211] For another example, the coded bit sequence 1 can be interleaved in reverse order. For example, the coded bit sequence 1 can be divided into R sub-blocks, i.e., sub-block 0 to sub-block R-1, and after the interleaving, the order of the sub-blocks is sub-block R-1, sub-block R-2, …, sub-block 0.

[0212] The above describes the generation process of the first coded bit sequence, and the decoding process of the first symbol sequence is described below in combination with the generation process of the first coded bit sequence.

[0213] The decoding process of the first symbol sequence can include:​

[0214] A1, determine the information bits / frozen bits.

[0215] The terminal device determines the information bits and the frozen bits in the same manner as the network device, and specific manners can be referred to the related description of S301, which will not be repeated here.

[0216] A2, perform the inverse process of S506 on the symbol sequence of E length to obtain a third symbol sequence of N length.

[0217] For example, the symbol sequence of E length is actually a bit sequence after bit selection, and thus the bit sequence before bit selection can be derived from the symbol sequence of E length in the reverse direction according to the bit selection method in S506. For another example, the symbol sequence of E length is actually a bit sequence after interleaving, and thus the bit sequence before sub-block interleaving can be derived from the symbol sequence of E length in the reverse direction according to the sub-block interleaving method in S506.

[0218] A3, decode the third symbol sequence according to the information bits and the frozen bits to obtain the original bit sequence.

[0219] For example, the log likelihood ratio (LLR) of each bit in the third symbol sequence is calculated. For an information bit, if the LLR>0, the bit is determined to be 0, and if the LLR<0, the bit is determined to be 1. For a frozen bit, the bit can be set to 0 regardless of the LLR.

[0220] A4, obtain the information bit sequence from the information bits.

[0221] In the case that the PDCCH supports self-decoding (i.e., the length of the information bit sequence is less than a threshold value), the application makes the encoding construction (i.e., the information bits / frozen bits) of the PDCCH with a higher aggregation level (e.g., AL=4 / 8 / 16, etc.) include the encoding construction (i.e., the information bits / frozen bits) of the PDCCH with a lower aggregation level (e.g., AL=2 / 4 / 8, etc.), so that even if the aggregation level of the PDCCH is high, the receiving end can decode a small number of CCEs to obtain data without continuing to decode other CCEs, thereby achieving early stopping of blind detection and reducing the complexity of the receiver.

[0222] In addition, by modifying the starting point of bit selection corresponding to the first encoding bit sequence or performing interleaving after bit selection, the CCEs to which the part of the first encoding bit sequence that is mapped in the same manner as the second encoding bit sequence are mapped can be the same as the CCEs to which the second encoding bit sequence is mapped, so that the receiving end can decode a small number of CCEs to obtain data, thereby further facilitating early stopping of blind detection and reducing the complexity of the receiver.

[0223] Based on the same inventive concept as the method embodiments, the embodiments of the present application provide a communication device, the structure of which can be as shown in the figure Figure 8 , which comprises a communication unit 801 and a processing unit 802.

[0224] In an embodiment, the communication device can be specifically used to implement the method performed by the network device in the embodiment of Figure 3 , and the device can be the network device itself, or a chip or chip set or part of a chip in the network device for performing the related method functions. The processing unit 802 is configured to determine information bits corresponding to a first coded bit sequence according to a length of an information bit sequence, wherein if the length of the information bit sequence is less than or equal to a threshold value, the information bits corresponding to the first coded bit sequence include information bits corresponding to a second coded bit sequence, an aggregation level of the first coded bit sequence is higher than an aggregation level of the second coded bit sequence, and the first coded bit sequence is carried on a PDCCH; map the information bit sequence to the information bits corresponding to the first coded bit sequence; and generate the first coded bit sequence according to a bit sequence in which the information bit sequence is mapped. The communication unit 801 is configured to transmit the first coded bit sequence.

[0225] Optionally, the processing unit 802 is configured to, when generating the first coded bit sequence according to the bit sequence in which the information bit is mapped, perform bit selection on the bit sequence in which the information bit is mapped; and generate the first coded bit sequence according to the bit sequence obtained after the bit selection.

[0226] In an embodiment, the communication device can be specifically used to implement the method performed by the terminal device in the embodiment of Figure 3 , and the device can be the terminal device itself, or a chip or chip set or part of a chip in the terminal device for performing the related method functions. The communication unit 801 is configured to receive a first symbol sequence, wherein the first symbol sequence is carried on a PDCCH. The processing unit 802 is configured to determine information bits corresponding to the first symbol sequence according to a length of an information bit sequence, wherein if the length of the information bit sequence is less than or equal to a threshold value, the information bits corresponding to the first symbol sequence include information bits corresponding to a second symbol sequence, and an aggregation level of the first symbol sequence is higher than an aggregation level of the second symbol sequence; and decode the first symbol sequence according to the information bits.

[0227] Optionally, the processing unit 802 is specifically configured to: recover the first symbol sequence according to a bit selection method corresponding to the first symbol sequence to obtain a third symbol sequence; decode the third symbol sequence according to the information bits; and obtain the information bit sequence from the decoded bit sequence.

[0228] The division of the modules in the embodiments of the present application is illustrative, and is merely a logical function division. In actual implementation, another division manner can be used. In addition, each function module in each embodiment of the present application can be integrated in one processor, or can be physically separated, or two or more modules can be integrated in one module. The integrated module can be implemented in the form of hardware or in the form of a software function module. It can be understood that the functions or implementation of each module in the embodiments of the present application can be further referred to the related description of the method embodiments.

[0229] In one possible manner, the communication device can be as shown in Figure 9 The device can be a communication device or a chip in a communication device. The communication device can be the terminal device in the above embodiments or the network device in the above embodiments. The device includes a processor 901 and a communication interface 902, and can further include a memory 903. The processing unit 802 can be the processor 901. The communication unit 801 can be the communication interface 902. Optionally, the processor 901 and the memory 903 can be integrated together.

[0230] The processor 901 can be a CPU or a digital processing unit, etc. The communication interface 902 can be a transceiver, an interface circuit such as a transceiver circuit, a transceiver chip, etc. The device further includes a memory 903 for storing programs executed by the processor 901. The memory 903 can be a non-volatile memory such as a hard disk drive (HDD) or a solid-state drive (SSD), etc., and can also be a volatile memory such as a random-access memory (RAM). The memory 903 can be any other medium capable of carrying or storing desired program codes in the form of instructions or data structures and capable of being accessed by a computer, but is not limited to this.

[0231] The processor 901 is configured to execute the program codes stored in the memory 903, and is specifically configured to execute the actions of the processing unit 802 described above, which will not be repeated here. The communication interface 902 is specifically configured to execute the actions of the communication unit 801 described above, which will not be repeated here.

[0232] The specific connection medium between the communication interface 902, the processor 901 and the memory 903 is not limited in the embodiments of the present application. In the embodiments of the present application, the memory 903, the processor 901 and the communication interface 902 are connected through a bus 904, and the bus is Figure 9 represented by a thick line in the embodiments of the present application, the connection mode between other components is only schematically illustrated, and is not limited. The bus can be divided into an address bus, a data bus, a control bus and the like. For convenience of representation, only one thick line is used to represent the bus in the embodiments of the present application, but it does not mean that there is only one bus or only one type of bus. Figure 9 Figure 9

[0233] The embodiments of the present application also provide a computer readable storage medium for storing computer software instructions required for the processor to execute, which contains programs required for the processor to execute.

[0234] The embodiments of the present application also provide a communication system, which comprises a communication device for realizing the function of the terminal device in the embodiments of the present application and a communication device for realizing the function of the network device in the embodiments of the present application. Figure 3 Figure 3

[0235] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system or a computer program product. Therefore, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage and the like) containing computer-usable program code.

[0236] The present application is described with reference to flowcharts and / or block diagrams of the method, device (system) and computer program product according to the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of the flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing apparatus to produce a machine, so that the instructions executed by the computer or other programmable data processing apparatus produce a device that implements the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one flow or multiple flows and / or blocks Figure 1 The functions specified in one flow or multiple flows and / or blocks

[0237] ​​​​These computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture including instructions which implement the flow Figure 1 The flow or flows and / or blocks Figure 1 The flow or flows and / or blocks

[0238] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions that execute on the computer or other programmable apparatus provide steps for implementing the flow Figure 1 The flow or flows and / or blocks Figure 1 The flow or flows and / or blocks

Claims

1. A communication method characterized by comprising: The method comprises: determining information bits corresponding to a first coded bit sequence according to a length of an information bit sequence, wherein if the length of the information bit sequence is less than or equal to a threshold value, the information bits corresponding to the first coded bit sequence comprise information bits corresponding to a second coded bit sequence, an aggregation level of the first coded bit sequence is higher than an aggregation level of the second coded bit sequence, and the first coded bit sequence is carried on a physical downlink control channel (PDCCH); mapping the information bit sequence to the information bits corresponding to the first coded bit sequence; generating the first coded bit sequence according to a bit sequence in which the information bit sequence is mapped; and transmitting the first coded bit sequence.

2. The method of claim 1, wherein, The information bits corresponding to the first coded bit sequence comprise: a first information bit set, a second information bit set, and a third information bit set; the first information bit set is composed of information bits that are the same in a fourth information bit set and a fifth information bit set; the second information bit set is composed of information bits that are different in the fourth information bit set and the fifth information bit set; the third information bit set is composed of information bits that are different in the fourth information bit set and the fifth information bit set; the fourth information bit set is composed of bit positions corresponding to H sub-channels with high reliability in E sub-channels, and the fifth information bit set is composed of bit positions corresponding to H sub-channels with high reliability in E / 2 sub-channels; the second information bit set and the third information bit set are used to carry the same first information bit, and the first information bit set is used to carry information bits other than the first information bit in the information bit sequence; E is a length of the first coded bit sequence, and H is an integer greater than 0.

3. The method of claim 2, wherein, The information bits corresponding to the second coded bit sequence are composed of the first information bit set and the third information bit set.

4. The method according to any one of claims 1 to 3, characterized in that, If the length of the information bit sequence is greater than the threshold value, the information bits corresponding to the first coded bit sequence comprise bit positions corresponding to H sub-channels with high reliability in E sub-channels, E is a length of the first coded bit sequence, and H is an integer greater than 0.

5. The method according to any one of claims 1 to 4, characterized in that, If the aggregation level of the first coded bit sequence is 4, the threshold value is 70. Or, if the aggregation level of the first coded bit sequence is greater than or equal to 8, the threshold value is 140.

6. The method according to any one of claims 1 to 4, wherein The threshold value is related to at least one of the following: the aggregation level of the first coded bit sequence, the size of a CCE in the PDCCH, a switching threshold of a rate matching mode, and the length of a CRC bit sequence of the first coded bit sequence.

7. The method according to any one of claims 1 to 4, wherein The threshold value satisfies the following formula: Th = floor(AL / 2 x CCE size x R - CRC size ); wherein Th is the threshold value, AL is the aggregation level of the first coded bit sequence, CCE size is the size of CCEs in the PDCCH, CRC size is the CRC size of the first coded bit sequence, R is a switching threshold of a rate matching manner, and floor() is a floor function.

8. The method according to any one of claims 1 to 7, wherein, part of the bits in the first coded bit sequence are mapped to the same CCE as the second coded bit sequence, and the information bits corresponding to the part of the bits are the same as the information bits corresponding to the second coded bit sequence.

9. The method of claim 8, wherein, The starting point of bit selection corresponding to the first coded bit sequence is related to at least one of the following parameters: an aggregation level of the first coded bit sequence, a code rate of the first coded bit sequence, and a rate matching manner of the first coded bit sequence.

10. The method of any one of claims 1-9, wherein, The first coded bit sequence satisfies the following formula: wherein e k is the bit numbered k in the first coded bit sequence, E is the length of the first coded bit sequence, N is the mother code length of the PDCCH, d n is the bit numbered n in the third coded bit sequence, the third coded bit sequence being the bit sequence obtained after encoding the information bit sequence.

11. The method of claim 8, wherein, The first coded bit sequence is obtained after interleaving a fourth coded bit sequence, and the fourth coded bit sequence is obtained after coding and bit selection on an information bit sequence.

12. The method of claim 11, wherein, The first M bits in the first coded bit sequence are the same as the last M bits in the fourth coded bit sequence, where M is the length of the second coded bit sequence.

13. The method of any one of claims 1-12, wherein, The rate matching manner of the first coded bit sequence is repetition or puncturing.

14. The method of any one of claims 1-13, wherein, The first coded bit sequence is generated according to a bit sequence mapped with the information bit sequence, including: coding the bit sequence mapped with the information bit sequence to obtain a coded bit sequence; performing bit selection on the coded bit sequence; generating the first coded bit sequence according to the bit sequence obtained after bit selection.

15. The method according to any one of claims 1 to 14, wherein: The aggregation level of the second coded bit sequence is 4 or 2.

16. A method of communication, comprising: The method comprises: receiving a first symbol sequence, the first symbol sequence being carried on a physical downlink control channel (PDCCH); determining information bits corresponding to the first symbol sequence according to the length of an information bit sequence, wherein if the length of the information bit sequence is less than or equal to a threshold value, the information bits corresponding to the first symbol sequence include information bits corresponding to a second symbol sequence, and the aggregation level of the first symbol sequence is higher than that of the second symbol sequence; decoding the first symbol sequence according to the information bits.

17. The method of claim 16, wherein, The information bits corresponding to the first symbol sequence include: a first information bit set, a second information bit set, and a third information bit set; wherein the first information bit set is composed of information bits that are the same in a fourth information bit set and a fifth information bit set; the second information bit set is composed of information bits that are different in the fourth information bit set and the fifth information bit set; the third information bit set is composed of information bits that are different in the fourth information bit set and the fifth information bit set; wherein the fourth information bit set is composed of bit positions corresponding to H subchannels with high reliability ranking in E subchannels, and the fifth information bit set is composed of bit positions corresponding to H subchannels with high reliability ranking in E / 2 subchannels; the second information bit set and the third information bit set are used to carry the same first information bit, and the first information bit set is used to carry information bits other than the first information bit in the information bit sequence; E is the length of the first coded bit sequence, and H is an integer greater than 0.

18. The method of claim 17, wherein, The information bits corresponding to the second symbol sequence are composed of the first information bit set and the third information bit set.

19. The method of any one of claims 16-18, wherein, If the length of the information bit sequence is greater than the threshold value, the information bits corresponding to the first symbol sequence include bit positions corresponding to the first H sub-channels in the E sub-channels sorted according to reliability, where E is the length of the first encoded bit sequence, and H is an integer greater than 0.

20. The method of any one of claims 16-19, wherein, If the aggregation level of the first symbol sequence is 4, the threshold value is 70. Or, if the aggregation level of the first symbol sequence is greater than or equal to 8, the threshold value is 140.

21. The method of any one of claims 16-20, wherein, The threshold value is related to at least one of the following: the aggregation level of the first symbol sequence, the size of the CCE in the PDCCH, the switching threshold of the rate matching mode, and the length of the CRC bit sequence of the first symbol sequence.

22. The method of any one of claims 16-20, wherein, The threshold value satisfies the following formula: Th = floor(AL / 2 x CCE size x R - CRC size ); wherein Th is the threshold value, AL is the aggregation level of the first symbol sequence, CCE size is the size of CCEs in the PDCCH, CRC size is the length of the CRC bit sequence of the first symbol sequence, R is a switching threshold of a rate matching manner, and floor() is a down rounding.

23. The method of any one of claims 16-22, wherein, The CCEs to which part of the bits in the first symbol sequence are mapped are the same as the CCEs to which the second symbol sequence is mapped, and the information bits corresponding to the part of the bits are the same as the information bits corresponding to the second symbol sequence.

24. The method of claim 23, wherein, The starting point of the bit selection corresponding to the first symbol sequence is related to at least one of the following parameters: the aggregation level of the first symbol sequence, the code rate of the first symbol sequence, and the rate matching mode of the first symbol sequence.

25. The method of any one of claims 16-24, wherein, The encoded bit sequence corresponding to the first symbol sequence satisfies the following formula: wherein e k is the kth bit in the encoded bit sequence corresponding to the first symbol sequence, E is the length of the first symbol sequence, N is the mother code length of the PDCCH, d n is the nth bit in the third encoded bit sequence, the third encoded bit sequence being a bit sequence obtained by encoding the information bit sequence.

26. The method of claim 25, wherein, The encoded bit sequence corresponding to the first symbol sequence is obtained by interleaving a fourth encoded bit sequence, and the fourth encoded bit sequence is obtained by encoding an information bit sequence and performing bit selection.

27. The method of claim 26, wherein, The first M bits in the encoded bit sequence corresponding to the first symbol sequence are the same as the last M bits in the fourth encoded bit sequence, where M is the length of the second symbol sequence.

28. The method of any one of claims 16-27, wherein, The rate matching mode of the first symbol sequence is repetition or puncturing.

29. The method of any one of claims 16-28, wherein, The decoding of the first symbol sequence according to the information bits includes: recovering the first symbol sequence according to the bit selection method corresponding to the first symbol sequence to obtain a third symbol sequence; decoding the third symbol sequence according to the information bits; obtaining an information bit sequence from the decoded bit sequence.

30. The method of any one of claims 16-29, wherein, The aggregation level of the second encoded bit sequence is 4 or 2.

31. A communications device, characterized by The apparatus includes a processor and a memory storing program instructions that, when executed by the processor, cause the method of any one of claims 1-15 to be performed, or the method of any one of claims 16-30 to be performed.

32. A computer-readable storage medium, comprising: The computer storage medium stores computer-readable instructions that, when executed on a communication device, cause the method of any one of claims 1-15 to be performed, or the method of any one of claims 16-30 to be performed.

33. A computer program product, characterised in that, The computer program product, when executed on a device, causes the device to perform the method of any one of claims 1-15 or the method of any one of claims 16-30.

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