FlexRay communication system based on on-chip shared storage

Abstract

The invention provides a FlexRay communication system based on an on-chip shared memory, which relates to the technical field of vehicle-mounted network communication and comprises a processor, a system bus, an external memory and a FlexRay controller, the processor is connected with a host interface of the system bus; a host interface of the FlexRay controller is connected with a host interface of the system bus, and a slave interface of the FlexRay controller is connected with a slave interface of the system bus; and the external memory is connected with the slave interface of the system bus. The communication data in the FlexRay controller is stored in the external memory outside the FlexRay controller, and the FlexRay controller is configured through the processor, so that the FlexRay controller autonomously accesses the external memory, and the processor is supported to directly read and write the communication data in the external memory, thereby not only improving the storage capacity and expansibility, but also improving the reliability of the FlexRay controller. And the system flexibility and the data access efficiency are enhanced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of vehicle network communication, in particular to a FlexRay communication system based on on-chip shared storage. BACKGROUND

[0002] FlexRay bus, as a high real-time and high reliability vehicle communication protocol, is widely used in automotive powertrain, chassis control and advanced driver assistance system (ADAS). The traditional FlexRay communication controller usually stores key information such as communication cycle configuration, message frame descriptor and transmission data buffer in the special registers or memories inside the controller.

[0003] However, with the increasing complexity of vehicle electronic systems, the amount of communication data has increased significantly, and the traditional internal storage method has the following problems: Limited storage resources: the on-chip storage capacity is limited, which is difficult to support the storage of large-scale data frames or complex scheduling tables; Poor configuration flexibility: configuration information is fixed in the internal, which is difficult to update dynamically, and is not conducive to system reconstruction and online debugging; Inconvenient resource sharing: if the processor needs to access communication data (such as for diagnosis or monitoring), it must be indirectly read through the controller, which is inefficient; Insufficient scalability: in the multi-node collaboration or software-defined communication scenario, it is difficult to realize centralized management of configuration and data.

[0004] Therefore, a new FlexRay communication architecture is needed to improve the traditional internal storage method and support efficient access by the host processor to improve system flexibility, scalability and resource sharing capability. SUMMARY

[0005] The purpose of the present application is to provide a FlexRay communication system based on on-chip shared storage to improve the above problems. In order to achieve the above purpose, the technical solutions adopted by the present application are as follows: The present application provides a FlexRay communication system based on on-chip shared storage, which comprises a processor, a system bus, an external memory and a FlexRay controller; The processor is connected to the host interface of the system bus; The host interface of the FlexRay controller is connected to the host interface of the system bus, and the slave interface is connected to the slave interface of the system bus; The external memory is connected to the slave interface of the system bus; The processor is configured to access the system bus and configure the FlexRay controller based on the system bus and access the external memory based on the system bus; The external memory is configured to store communication data of the FlexRay controller; The FlexRay controller is configured to access the system bus and read and write the communication data in a preset area of the external memory based on the system bus.

[0006] As a preferred scheme of the present application, the preset area includes a synchronization frame table storage area, a data message buffer storage area, a first channel header field buffer storage area, a second channel header field buffer storage area and a header field message buffer storage area; The synchronization frame table area is configured to store information of a synchronization frame of the FlexRay controller; The data message buffer is configured to buffer related information of a first frame, the first frame being a frame received or sent by the FlexRay controller; The first channel header field buffer storage area, the second channel header field buffer storage area and the header field message buffer storage area are all configured to store header information of a message received by the FlexRay controller; The first channel header field buffer storage area and the second channel header field buffer storage area both manage the header information based on a first-in-first-out mode; The header field message buffer storage area manages the header information based on a preset fast access mechanism.

[0007] As a preferred scheme of the present application, when the FlexRay controller receives a first data frame, header information of the first data frame is copied to a first area, the first area being the first channel header field buffer storage area, the second channel header field buffer storage area or the header field message buffer storage area.

[0008] As a preferred scheme of the present application, the configuration of the FlexRay controller includes: When configuring the sending or receiving data, the processor configures a first parameter of the FlexRay controller, the first parameter being a parameter defined in a FlexRay protocol; After the processor completes the configuration of the first parameter, the processor configures a control register of a message buffer inside the FlexRay controller.

[0009] As a preferred scheme of the present application, the FlexRay controller is further provided with an address mapping and access control module, which is used to map hardware resources to system address space and control the access order and authority of the processor and the FlexRay controller to shared memory.

[0010] As a preferred scheme of the present application, the FlexRay controller is further provided with a message buffer index register. The message buffer index register indexes the message buffer control register and the physical message buffer through a preset index field, and obtains an index value of each message buffer control register and physical message buffer, one index value corresponding to one physical message buffer and one message buffer control register. The message buffer control register controls the physical message buffer based on the index value.

[0011] As a preferred scheme of the present application, the control of the physical message buffer based on the index value comprises: identifying the data field of each physical message buffer based on a data field offset; A first message buffer control register controls a first physical message buffer based on a first offset, the index value of the first message buffer control register and the first physical message buffer being the same, the first offset being the offset of a first data field relative to a first base address, the first base address being the base address of a first region of the external memory corresponding to the first data field, and the first data field being the data field of the first physical message buffer in the first message buffer control register.

[0012] As a preferred scheme of the present application, a FlexRay communication system based on on-chip shared storage further comprises: In the system initialization stage, the processor writes the communication information of the FlexRay controller into the FlexRay controller; the FlexRay controller writes the communication information into a preset region of the external memory according to its corresponding data structure, the communication information including communication cycle, static segment length and message ID mapping table; The FlexRay controller obtains the physical address of the configuration information by reading a first register inside the FlexRay controller, obtains the configuration information based on the physical address, and stores the configuration information in the FlexRay controller according to its corresponding data structure.

[0013] As a preferred scheme of the present application, a FlexRay communication system based on on-chip shared storage further comprises: In the communication process, the FlexRay controller reads the message buffer data from the external memory according to the internal communication schedule table, and sends the message buffer data to the FlexRay bus based on the physical layer interface of the FlexRay controller. When the FlexRay controller receives the data frame, the FlexRay controller writes the received data frame into the message buffer of the external memory.

[0014] As a preferred scheme of the application, the host interface of the system bus supports AHB, APB, AXI and PCIe bus protocols; and the external memory is a system shared memory and supports DMA or memory-mapped I / O access.

[0015] The application has the following beneficial effects: The application stores the communication data in the FlexRay controller in the external memory outside the FlexRay controller, and configures the FlexRay controller through the processor, so that the FlexRay controller autonomously accesses the external memory, and the processor directly communicates with the external memory to read and write the communication data, which not only improves the storage capacity and expandability, but also enhances the system flexibility and data access efficiency.

[0016] Other features and advantages of the application will be described in the following description, and some will become apparent from the description, or will be understood through implementation of the embodiments of the application. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments, and it should be understood that the following drawings only show some of the embodiments of the application, and therefore should not be regarded as a limitation on the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0018] Figure 1 A structure schematic diagram of a FlexRay communication system based on on-chip shared storage according to an embodiment of the application; Figure 2 Another structure schematic diagram of a FlexRay communication system based on on-chip shared storage according to an embodiment of the application; Figure 3 A region division schematic diagram of a FlexRay controller of a FlexRay communication system based on on-chip shared storage according to an embodiment of the application; Figure 4A control architecture diagram of a physical message buffer of a FlexRay communication system based on on-chip shared storage according to an embodiment of the present application. DETAILED DESCRIPTION

[0019] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will be combined with the accompanying drawings of the embodiments of the present application to make a clear and complete description of the technical solutions in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. The components of the embodiments of the present application described and shown in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0020] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. Meanwhile, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0021] Embodiment 1 The embodiment provides a FlexRay communication system based on on-chip shared storage.

[0022] It should be noted that the FlexRay communication system based on on-chip shared storage of the embodiment can be widely applied to vehicle-mounted domain controllers, intelligent driving systems and other scenes with high requirements for communication flexibility and data throughput.

[0023] Referring to Figure 1 , a FlexRay communication system based on on-chip shared storage includes a processor, a system bus, an external memory and a FlexRay controller; The host interface of the processor is connected to the host interface of the system bus; The host interface of the FlexRay controller is connected to the host interface of the system bus, and the slave interface is connected to the slave interface of the system bus; The external memory is connected to the slave interface of the system bus; The processor is configured to access the system bus, access the external memory based on the system bus and configure the FlexRay controller; The external memory is configured to store communication data of the FlexRay controller; The FlexRay controller is used to access the system bus and read and write the preset region of the external memory based on the system bus for the communication data.

[0024] It can be understood that, as shown in FIG. 1 and Figure 2 The processor CPU is connected with the FlexRay communication controller through the host interface of the AXI bus, configures the FlexRay communication controller, and determines the space used by the FlexRay in the external memory. The FlexRay controller establishes a communication link with the external memory SRAM through its host interface unit, and performs relevant read and write operations on the region of the external memory SRAM divided by the CPU. The external memory is the system SRAM, which shares the address space with the host processor.

[0025] The communication data is migrated from the FlexRay controller to the external memory, while the control information is reserved in the dedicated register in the FlexRay controller. The configuration information includes the configuration information related to the FlexRay module and the configuration information related to the message buffer, and the communication data content includes the data transmitted and received by the FlexRay module and the frame header related information. This design enables the FlexRay controller to flexibly access the message buffer content in the external memory, while maintaining efficient management of the message buffer control parameters.

[0026] The FlexRay controller is both a slave of the bus configured by the processor for its register and a host of the data bus directly accessing the memory and configuring the message buffer. The processor is the main control core, which is responsible for configuring the FlexRay related transmission mode and transmission parameters. The FlexRay controller, through its module internal host interface, works together with the processor as the host of the whole system, and shares the bus access right to access the external memory and perform operations. Meanwhile, the slave module in the FlexRay controller is connected to the slave port of the bus, which is used for the processor to configure the FlexRay controller.

[0027] As a preferred scheme of the embodiment, the preset region includes a synchronization frame table storage region, a data message buffer storage region, a first channel header field buffer storage region, a second channel header field buffer storage region, and a header field message buffer storage region. The synchronization frame table region is used to store the information of the synchronization frame of the FlexRay controller. The data message buffer is used to buffer the related information of the first frame, and the first frame is the frame received or transmitted by the FlexRay controller. The first channel header field buffer storage area, the second channel header field buffer storage area, and the header field message buffer storage area are all used to store message header information received by the FlexRay controller; The first channel header field buffer storage area and the second channel header field buffer storage area both manage the message header information based on a first-in-first-out method; The header field message buffer storage area manages the message header information based on a preset fast access mechanism.

[0028] It is understandable that if Figure 2 As shown, the FlexRay controller reads and writes to a preset area of ​​the external SRAM memory through the host interface. The FlexRay controller divides the preset area into a synchronization frame table storage area, a data message buffer storage area, a receive FIFO A-channel header buffer storage area, a receive FIFO B-channel header buffer storage area, and a header message buffer storage area. The receive FIFO A-channel header buffer storage area, the receive FIFO B-channel header buffer storage area, and the header message buffer storage area are all header message buffer storage areas. The synchronization frame table storage area is used to store information related to synchronization frames. The data message buffer storage area is used to cache information related to received or transmitted frames, including frame format and data. The receive FIFO message buffer header storage area is used to store received message header information and is managed using a first-in-first-out (FIFO) method. The header message buffer storage area is used to store received message header information and provides a fast access mechanism.

[0029] like Figure 3 As shown, the synchronization frame table area, data message buffer area, and header field message buffer area were originally placed inside the FlexRay controller for storing communication data. Now these areas need to be migrated to the external memory, so it is necessary to divide the preset area in the external memory into multiple storage areas, so as to migrate these areas inside the FlexRay controller to the corresponding storage areas of the external memory, maintain consistency before and after the migration, so that the reading and writing of these areas by the FlexRay controller are not affected, and the processor or the user can more conveniently read the contents stored in these areas in the external memory.

[0030] By allocating dedicated buffers for different data types (such as synchronization frames, data messages, header fields, etc.), the FlexRay module can process data more efficiently, thereby effectively avoiding access conflicts between different types of data and improving the working efficiency of the FlexRay module.

[0031] After the storage area is clearly divided, the CPU can more easily find the corresponding storage location according to the data type, simplifying the access logic. For example, when the synchronization frame information needs to be accessed, the CPU can directly access the synchronization frame table area without searching in a large amount of data.

[0032] Placing these key areas (including the synchronization frame table area, the message buffer data area, the message buffer header field area of the receiving FIFO, and the header field message buffer) in the external memory instead of inside the FlexRay module can enhance the scalability and flexibility of the FlexRay communication system. The external memory is usually more abundant than the storage resources inside the FlexRay module and can support larger message buffer sizes and quantities, thereby adapting to application requirements of different scales and complexities.

[0033] On the other hand, resource sharing and efficient utilization can be achieved. As a shared resource, the external memory can be accessed by multiple subsystems (including the FlexRay controller), improving overall resource utilization and reducing the occupation of duplicate resources.

[0034] Moreover, according to real-time requirements, the communication system of the embodiment can more flexibly allocate external memory resources among different tasks, improving the overall performance and response speed of the system, thereby optimizing resource allocation.

[0035] In addition, many modern processors support direct memory access (DMA), allowing peripherals (such as the FlexRay controller) to directly exchange data with the external memory, reducing the CPU burden and improving data transmission efficiency.

[0036] The FlexRay communication system of the embodiment also improves system integration and interoperability. The use of a standard external memory interface makes it easier for the FlexRay module to integrate with other system components, promoting compatibility and interoperability between different suppliers.

[0037] As a preferred scheme of the embodiment, when the FlexRay controller receives a first data frame, the header information of the first data frame is copied to a first area, which is the first channel header field buffer storage area, the second channel header field buffer storage area, or the header field message buffer storage area.

[0038] It can be understood that for the header field message buffer, this part of the area is specially used to store the header information of the received data frame, so as to facilitate the host processor to access and process quickly. It provides an independent buffer for each received message, even if the message itself is invalid or incomplete, its header information will be recorded. Each data frame contains a frame header segment, which contains various key attributes of the frame, such as frame ID, payload length, cycle count, etc. These information is crucial for parsing frame content, maintaining network synchronization, and ensuring the accuracy and reliability of data transmission. When the FlexRay controller receives a data frame, it will first copy the header information of the frame to the header field message buffer area, that is, the A channel header field buffer storage area and the B channel header field buffer storage area of the receive FIFO, and the header field message buffer storage area. In this way, by pre-storing the frame header information, the host processor can quickly obtain and process these information without directly accessing the original data frame, improving the response speed and efficiency of the system. At the same time, even if some frames cannot be normally received due to errors or other reasons, their header information will still be recorded, which is helpful for subsequent fault diagnosis and analysis.

[0039] As a preferred scheme of the embodiment, the configuring the FlexRay controller comprises: When configuring the sending or receiving data, the processor configures the first parameter of the FlexRay controller, the first parameter being a parameter defined in the FlexRay protocol; After the processor completes the configuration of the first parameter, the processor configures the control register of the message buffer inside the FlexRay controller.

[0040] It can be understood that when configuring the sending or receiving data, the CPU first configures the general parameters of the FlexRay controller, the general parameters being parameters defined in the FlexRay protocol, to determine the cycle time and synchronization frame ID of data sending, etc.; and then configures the frame ID, data, etc. used for sending data by configuring the control register of the message buffer inside the FlexRay controller.

[0041] As a preferred scheme of the embodiment, the FlexRay controller is further provided with an address mapping and memory access control module, which is used to map the hardware resources to the system address space and control the access order and permission of the shared memory between the processor and the FlexRay controller.

[0042] It can be understood that, since the communication data related storage area originally located in the FlexRay controller is migrated to the preset area of the external memory, the FlexRay controller needs to use the external memory through the system bus if it wants to continue using the storage area, and the FlexRay controller ensures the coordinated access to the shared storage area with the host processor through address mapping and access control module, which is a key interface management unit in the FlexRay controller. It maps the hardware resources to the system address space and coordinates the access sequence and permission of the shared memory of the CPU and the controller, so as to avoid data conflict, guarantee communication real-time and reliability, and avoid data conflict and access delay.

[0043] As a preferred scheme of the embodiment, the FlexRay controller is further provided with a message buffer index register; The message buffer index register indexes the message buffer control register and the physical message buffer through a preset index field, and obtains an index value of each message buffer control register and the physical message buffer, one index value corresponding to one physical message buffer and one message buffer control register; The message buffer control register controls the physical message buffer based on the index value.

[0044] The control of the physical message buffer based on the index value includes: identifying the data field of each physical message buffer based on a data field offset; The first message buffer control register controls the first physical message buffer based on a first offset, the index value of the first message buffer control register and the first physical message buffer being the same, the first offset being the offset of the first data field relative to the first base address, the first base address being the base address of the first region of the external memory corresponding to the first data field, and the first data field being the data field of the first physical message buffer in the first message buffer control register.

[0045] As you can understand, a FlexRay controller uses a data structure called a message buffer to store frame data, configuration information, control information, and status information. Each message buffer consists of two parts: message buffer control data and a physical message buffer. This embodiment retains the message buffer control data in dedicated registers within the FlexRay controller, while migrating the physical message buffer to external memory. Through the FlexRay controller's host interface unit (CHI), the host processor can directly read and write the contents of the message buffer in external memory, enabling real-time monitoring and dynamic adjustment of communication data.

[0046] All received FlexRay frame data and frame header information are stored in a data structure called a physical message buffer. These physical message buffers are located in an external memory area. The buffer consists of two fields: a message buffer header field and a message buffer data field. The message buffer header field contains the frame header and slot status information, while the data field stores the frame data.

[0047] Since there are too many physical message buffers and the configuration methods are basically the same, there is no need to set up a separate configuration register for each physical message buffer to avoid wasting storage space. Here, the message buffer index register is used to index and control the message buffer control register through its built-in index field. The message buffer control register then controls the message buffer to save storage space. The data field of each physical message buffer is identified by the data field offset. Figure 4 As shown, Figure 4 The diagram shows an architecture of 32 physical message buffers. For each physical message buffer with an index value of i, the i-th corresponding register contains the offset of the message buffer data field relative to the base address of the external memory area used.

[0048] As a preferred solution of this embodiment, a FlexRay communication system based on on-chip shared storage further includes: During the system initialization phase, the processor writes the communication information of the FlexRay controller into the FlexRay controller; the FlexRay controller writes the communication information into a preset area of ​​the external memory according to its corresponding data structure, wherein the communication information includes a communication period, a static segment length, and a message ID mapping table; The FlexRay controller obtains the physical address of the configuration information by reading the first register therein, obtains the configuration information based on the physical address, and stores the configuration information in the FlexRay controller according to its corresponding data structure.

[0049] As a preferred scheme of the embodiment, the FlexRay communication system based on the on-chip shared storage further comprises: In the communication process, the FlexRay controller reads the message buffer data from the external storage according to the internal communication schedule table, and sends the message buffer data to the FlexRay bus based on the physical layer interface of the FlexRay controller. When the FlexRay controller receives a data frame, the FlexRay controller writes the received data frame into the message buffer of the external storage.

[0050] It can be understood that, in the system initialization stage, the CPU writes the FlexRay communication information (such as the communication cycle, the static segment length, the message ID mapping table, etc.) into the FlexRay controller, and the FlexRay controller writes the communication information according to the corresponding data structure into the preset area of the external storage, that is, the corresponding storage area in the external storage. The FlexRay controller obtains the physical address of the configuration information by reading the configuration-related registers in the FlexRay controller, and saves the configuration information in the storage according to the corresponding data format, so as to achieve the effect of automatically reading the to-be-sent data from the external storage and sending the data at the beginning of the communication cycle.

[0051] In the communication process, the controller reads the message buffer data from the external storage according to the communication schedule table, and sends the message buffer data to the FlexRay bus via the physical layer interface; when the FlexRay controller receives a data frame, the FlexRay controller writes the received data frame into the message buffer of the external storage, that is, the data message buffer storage area and the header field message buffer storage area.

[0052] The CPU can read the received data at any time through the host interface unit for diagnostic analysis, or modify the content of the sending buffer to realize instruction injection. The address mapping module ensures the access timing coordination to avoid bus conflict.

[0053] As a preferred scheme of the embodiment, the host interface of the system bus supports AHB, APB, AXI and PCIe bus protocols; and the external storage is a system shared storage and supports DMA or memory-mapped I / O access.

[0054] It can be understood that, the host interface unit of the system bus of the embodiment supports AHB, APB, AXI and PCIe bus protocols, etc., so as to realize the high-speed interconnection between the system bus and the host processor. The external storage is a system shared storage, and shares the same storage space with the host processor, and supports DMA or memory-mapped I / O access. The host processor can dynamically modify the communication configuration information through the host interface unit, so as to realize the online reconstruction of the communication parameters.

[0055] The above merely illustrates the specific embodiments of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application.

Claims

1. A FlexRay communication system based on shared memory on chip, characterized in that, The FlexRay communication system comprises a processor, a system bus, an external memory and a FlexRay controller; The processor is connected to the host interface of the system bus; The host interface of the FlexRay controller is connected to the host interface of the system bus, and the slave interface is connected to the slave interface of the system bus; The external memory is connected to the slave interface of the system bus; The processor is used for accessing the system bus and configuring the FlexRay controller based on the system bus and accessing the external memory based on the system bus; The external memory is used for storing communication data of the FlexRay controller; The FlexRay controller is used for accessing the system bus and reading and writing the communication data in a preset area of the external memory based on the system bus.

2. The FlexRay communication system based on shared memory on chip according to claim 1, characterized in that, The preset area comprises a synchronization frame table storage area, a data message buffer storage area, a first channel header field buffer storage area, a second channel header field buffer storage area and a header field message buffer storage area; The synchronization frame table area is used for storing information of a synchronization frame of the FlexRay controller; The data message buffer is used for buffering related information of a first frame, wherein the first frame is a frame received or sent by the FlexRay controller; The first channel header field buffer storage area, the second channel header field buffer storage area and the header field message buffer storage area are all used for storing header information of a message received by the FlexRay controller; The first channel header field buffer storage area and the second channel header field buffer storage area both manage the header information based on a first-in-first-out mode; The header field message buffer storage area manages the header information based on a preset fast access mechanism.

3. The FlexRay communication system based on shared memory on chip according to claim 2, characterized in that When the FlexRay controller receives a first data frame, the header information of the first data frame is copied to a first area, wherein the first area is the first channel header field buffer storage area, the second channel header field buffer storage area or the header field message buffer storage area.

4. The FlexRay communication system based on shared memory on chip according to claim 1, characterized in that The configuration of the FlexRay controller comprises: When configuring the sending or receiving data, the processor configures a first parameter of the FlexRay controller, wherein the first parameter is a parameter defined in a FlexRay protocol; After the processor completes the configuration of the first parameter, the processor configures a control register of a message buffer in the FlexRay controller.

5. The FlexRay communication system based on shared memory on chip according to claim 1, characterized in that The FlexRay controller is further provided with an address mapping and memory access control module, which is used for mapping hardware resources to a system address space and controlling the access order and permission of the processor and the FlexRay controller to the shared memory.

6. The FlexRay communication system based on shared memory on chip according to claim 1, characterized in that The FlexRay controller is further provided with a message buffer index register. The message buffer index register indexes the message buffer control register and the physical message buffer by using a preset index field to obtain an index value of each of the message buffer control register and the physical message buffer, wherein one index value corresponds to one physical message buffer and one message buffer control register; The message buffer control register controls the physical message buffer based on the index value.

7. The FlexRay communication system based on shared memory on chip according to claim 6, characterized in that The controlling of the physical message buffer based on the index value includes: Identifying the data field of each physical message buffer based on the data field offset; The first message buffer control register controls the first physical message buffer based on a first offset, the index value of the first message buffer control register and the first physical message buffer are the same, the first offset is the offset of the first data field relative to the first base address, the first base address is the base address of the first area of ​​the external memory corresponding to the first data field, and the first data field is the data field of the first physical message buffer in the first message buffer control register.

8. The FlexRay communication system based on shared memory on chip according to claim 1, characterized in that , also includes: During the system initialization phase, the processor writes the communication information of the FlexRay controller into the FlexRay controller; the FlexRay controller writes the communication information into a preset area of ​​the external memory according to its corresponding data structure, wherein the communication information includes a communication period, a static segment length, and a message ID mapping table; The FlexRay controller obtains the physical address of the configuration information by reading the first register therein, obtains the configuration information based on the physical address, and stores the configuration information in the FlexRay controller according to its corresponding data structure.

9. The FlexRay communication system based on shared memory on chip of claim 1, wherein , also includes: During the communication process, the FlexRay controller reads the message buffer data from the external memory according to its internal communication scheduling table, and sends the message buffer data to the FlexRay bus based on the physical layer interface of the FlexRay controller; When the FlexRay controller receives a data frame, the FlexRay controller writes the received data frame into the message buffer of the external memory.

10. The FlexRay communication system based on shared memory on chip of claim 1, wherein The host interface of the system bus supports AHB, APB, AXI and PCIe bus protocols; the external memory is system shared memory and supports DMA or memory mapped I / O access.

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