A FlexRay communication system based on on-chip shared memory

Abstract

The application provides a FlexRay communication system based on on-chip shared storage, relates to the technical field of vehicle-mounted network communication, and comprises a processor, a system bus, an external memory and a FlexRay controller; the host interface of the processor is connected with the host interface of the system bus; the host interface of the FlexRay controller is connected with the host interface of the system bus, the slave interface is connected with the slave interface of the system bus; and the external memory is connected with the slave interface of the system bus. The application stores the communication data in the FlexRay controller in the external memory outside the FlexRay controller, configures the FlexRay controller through the processor, realizes that the FlexRay controller autonomously accesses the external memory, and also supports the processor to directly read and write the communication data of the external memory, so that the storage capacity and the expansibility are improved, and the system flexibility and the data access efficiency are enhanced.

Description

Technical Field

[0001] This invention relates to the field of vehicle network communication technology, and more specifically, to a FlexRay communication system based on on-chip shared storage. Background Technology

[0002] FlexRay bus, as a high-real-time and high-reliability automotive communication protocol, is widely used in automotive powertrains, chassis control, and advanced driver assistance systems (ADAS). Traditional FlexRay communication controllers typically store critical information such as communication cycle configuration, message frame descriptors, and data transmission buffers in dedicated registers or memory within the controller.

[0003] However, with the increasing complexity of in-vehicle electronic systems and the significant increase in communication data, traditional internal storage methods have revealed the following problems:

[0004] Limited storage resources: On-chip storage capacity is limited, making it difficult to support the storage of large-scale data frames or complex scheduling tables;

[0005] Poor configuration flexibility: Configuration information is fixed internally, making dynamic updates difficult and hindering system reconstruction and online debugging;

[0006] Resource sharing is inconvenient: If the processor needs to access communication data (such as for diagnostics or monitoring), it must read it indirectly through the controller, which is inefficient;

[0007] Insufficient scalability: In multi-node collaboration or software-defined communication scenarios, it is difficult to achieve centralized management of configuration and data.

[0008] Therefore, there is an urgent need for a new FlexRay communication architecture to improve the traditional internal storage method and support efficient access by the host processor, so as to enhance the system's flexibility, scalability and resource sharing capabilities. Summary of the Invention

[0009] The purpose of this invention is to provide a FlexRay communication system based on on-chip shared memory to improve the aforementioned problems. To achieve this purpose, the technical solution adopted by this invention is as follows:

[0010] This application provides a FlexRay communication system based on on-chip shared memory, the FlexRay communication system including a processor, a system bus, external memory and a FlexRay controller;

[0011] The processor is connected to the host interface of the system bus;

[0012] The host interface of the FlexRay controller is connected to the host interface of the system bus, and the slave interface is connected to the slave interface of the system bus.

[0013] The external memory is connected to the slave interface of the system bus;

[0014] The processor is used to access the system bus, and based on the system bus, access the external memory and configure the FlexRay controller;

[0015] The external memory is used to store the communication data of the FlexRay controller;

[0016] The FlexRay controller is used to access the system bus and read and write communication data to a preset area of ​​the external memory based on the system bus.

[0017] As a preferred embodiment of the present invention, the preset area includes a synchronization frame table storage area, a data message buffer storage area, a first channel header field buffer storage area, a second channel header field buffer storage area, and a header field message buffer storage area;

[0018] The synchronization frame table area is used to store information about the synchronization frames of the FlexRay controller;

[0019] The data message buffer is used to cache relevant information of the first frame, which is a frame received or sent by the FlexRay controller;

[0020] The first channel header field buffer storage area, the second channel header field buffer storage area, and the header field message buffer storage area are all used to store the message header information received by the FlexRay controller;

[0021] Both the first channel header field buffer storage area and the second channel header field buffer storage area manage the message header information based on a first-in-first-out (FIFO) method.

[0022] The header field message buffer storage area manages the message header information based on a preset fast access mechanism.

[0023] As a preferred embodiment of the present invention, when the FlexRay controller receives the first data frame, it copies the header information of the first data frame to a first region, wherein the first region is the storage region of the first channel header field buffer, the storage region of the second channel header field buffer, or the storage region of the header field message buffer.

[0024] As a preferred embodiment of the present invention, configuring the FlexRay controller includes:

[0025] When configuring sending or receiving data, the processor configures the first parameter of the FlexRay controller, which is a parameter specified in the FlexRay protocol;

[0026] After the processor completes the configuration of the first parameter, the processor configures the control register of the message buffer inside the FlexRay controller.

[0027] As a preferred embodiment of the present invention, the FlexRay controller is further provided with an address mapping and memory access control module, which is used to map hardware resources to the system address space and control the access order and permissions of the processor and the FlexRay controller to shared memory.

[0028] As a preferred embodiment of the present invention, the FlexRay controller is further provided with a message buffer index register;

[0029] The message buffer index register indexes the message buffer control register and the physical message buffer through a preset index field to obtain the index value of each message buffer control register and the physical message buffer. Each index value corresponds to one physical message buffer and one message buffer control register.

[0030] The message buffer control register controls the physical message buffer based on the index value.

[0031] As a preferred embodiment of the present invention, controlling the physical message buffer based on the index value includes:

[0032] The data fields of each physical message buffer are identified based on the data field offset;

[0033] The first message buffer control register controls the first physical message buffer based on a first offset. The index values ​​of the first message buffer control register and the first physical message buffer are the same. The first offset is the offset of the first data field relative to the first base address. The first base address is the base address of the first region of the external memory corresponding to the first data field. The first data field is the data field of the first physical message buffer within the first message buffer control register.

[0034] As a preferred embodiment of the present invention, a FlexRay communication system based on on-chip shared memory further includes:

[0035] During the system initialization phase, the processor writes the communication information of the FlexRay controller into the FlexRay controller; the FlexRay controller writes the communication information into a preset area of ​​the external memory according to its corresponding data structure, and the communication information includes the communication cycle, static segment length and message ID mapping table;

[0036] The FlexRay controller obtains the physical address of the configuration information by reading its internal first register, retrieves the configuration information based on the physical address, and stores the configuration information in the FlexRay controller according to its corresponding data structure.

[0037] As a preferred embodiment of the present invention, a FlexRay communication system based on on-chip shared memory further includes:

[0038] During communication, the FlexRay controller reads message buffer data from the external memory according to its internal communication scheduling table, and sends the message buffer data to the FlexRay bus based on the physical layer interface of the FlexRay controller.

[0039] When the FlexRay controller receives a data frame, it writes the received data frame into the message buffer of the external memory.

[0040] As a preferred embodiment of the present invention, the host interface of the system bus supports AHB, APB, AXI and PCIe bus protocols; the external memory is a system shared memory and supports DMA or memory-mapped I / O access.

[0041] The beneficial effects of this invention are as follows:

[0042] This invention stores the communication data within the FlexRay controller in an external memory outside the FlexRay controller, and configures the FlexRay controller through a processor. This enables the FlexRay controller to access the external memory autonomously, while also supporting the processor to directly read and write communication data to the external memory. This not only improves storage capacity and scalability, but also enhances system flexibility and data access efficiency.

[0043] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing embodiments of the invention. Attached Figure Description

[0044] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a schematic diagram of a FlexRay communication system based on on-chip shared memory, as described in an embodiment of the present invention.

[0046] Figure 2 This is a schematic diagram of another structure of a FlexRay communication system based on on-chip shared memory as described in an embodiment of the present invention;

[0047] Figure 3 This is a schematic diagram showing the area division for storing communication data inside the FlexRay controller of a FlexRay communication system based on on-chip shared memory, as described in an embodiment of the present invention.

[0048] Figure 4 This is a schematic diagram of the control architecture of the physical message buffer of a FlexRay communication system based on on-chip shared storage, as described in an embodiment of the present invention. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0050] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0051] Example 1:

[0052] This embodiment provides a FlexRay communication system based on on-chip shared memory.

[0053] It should be noted that the FlexRay communication system based on on-chip shared storage in this embodiment can be widely used in scenarios with high requirements for communication flexibility and data throughput, such as vehicle domain controllers and intelligent driving systems.

[0054] See Figure 1 The figure shows a FlexRay communication system based on on-chip shared memory, including a processor, system bus, external memory, and FlexRay controller.

[0055] The processor is connected to the host interface of the system bus;

[0056] The host interface of the FlexRay controller is connected to the host interface of the system bus, and the slave interface is connected to the slave interface of the system bus.

[0057] The external memory is connected to the slave interface of the system bus;

[0058] The processor is used to access the system bus, and based on the system bus, access the external memory and configure the FlexRay controller;

[0059] The external memory is used to store the communication data of the FlexRay controller;

[0060] The FlexRay controller is used to access the system bus and read and write communication data to a preset area of ​​the external memory based on the system bus.

[0061] Understandably, as shown in Figure 1 and Figure 2 As shown, the CPU connects to the FlexRay communication controller via the host interface of the AXI bus, configures the FlexRay communication controller, and determines the space used by FlexRay in external memory. The FlexRay controller establishes a communication link with the external SRAM through its host interface unit and performs related read and write operations on the areas allocated by the CPU in the external SRAM. The external memory is the system SRAM, which shares the address space with the host processor.

[0062] The communication data is migrated from the FlexRay controller's internal memory to external storage, while control information is retained in dedicated registers within the FlexRay controller. This configuration information includes FlexRay module-related configuration details and message buffer-related configuration information, while the communication data includes data sent and received by the FlexRay module, as well as frame header information. This design allows the FlexRay controller to flexibly access the message buffer contents in external storage while maintaining efficient management of message buffer control parameters.

[0063] The FlexRay controller functions as both a slave device on the bus (configured by the processor to its registers) and a master device on the data bus (directly accessing memory and configuring the message buffer). The processor, as the primary control core, is responsible for configuring FlexRay-related transmission modes and parameters. The FlexRay controller, through its internal master interface, works alongside the processor as the system's master, sharing bus access rights to access and operate external memory. Simultaneously, the slave modules within the FlexRay controller are connected to the corresponding slave ports on the bus, allowing the processor to configure the FlexRay controller.

[0064] As a preferred embodiment, the preset area includes a synchronization frame table storage area, a data message buffer storage area, a first channel header field buffer storage area, a second channel header field buffer storage area, and a header field message buffer storage area.

[0065] The synchronization frame table area is used to store information about the synchronization frames of the FlexRay controller;

[0066] The data message buffer is used to cache relevant information of the first frame, which is a frame received or sent by the FlexRay controller;

[0067] The first channel header field buffer storage area, the second channel header field buffer storage area, and the header field message buffer storage area are all used to store the message header information received by the FlexRay controller;

[0068] Both the first channel header field buffer storage area and the second channel header field buffer storage area manage the message header information based on a first-in-first-out (FIFO) method.

[0069] The header field message buffer storage area manages the message header information based on a preset fast access mechanism.

[0070] It is understandable that, such as Figure 2As shown, the FlexRay controller performs read and write operations on a preset area of ​​external SRAM through the host interface. The FlexRay controller divides this preset area into a synchronization frame table storage area, a data message buffer storage area, a receive FIFO A channel header field buffer storage area, a receive FIFO B channel header field buffer storage area, and a header field message buffer storage area. Specifically, the receive FIFO A channel header field buffer storage area, the receive FIFO B channel header field buffer storage area, and the header field message buffer storage area are all header field message buffer storage areas. The synchronization frame table storage area stores information related to synchronization frames. The data message buffer storage area buffers information related to received or transmitted frames, including frame format and data. The receive FIFO message buffer header field storage area stores the received message header information and manages it using a first-in, first-out (FIFO) method. The header field message buffer storage area stores the received message header information and provides a fast access mechanism.

[0071] like Figure 3 As shown, the synchronization frame table area, data message buffer, and header field message buffer area were originally located inside the FlexRay controller to store communication data. Now, these areas need to be migrated to external memory. Therefore, the preset areas in the external memory need to be divided into multiple storage areas. This allows these areas inside the FlexRay controller to be migrated to the corresponding storage areas in the external memory, maintaining consistency before and after the migration. This ensures that the FlexRay controller's reading and writing of these areas is not affected, while also making it easier for the processor or user to read the contents stored in these areas of the external memory.

[0072] By allocating dedicated buffers for different data types (such as synchronization frames, data messages, header fields, etc.), the FlexRay module can process data more efficiently, thereby effectively avoiding access conflicts between different types of data and improving the working efficiency of the FlexRay module.

[0073] By clearly dividing the storage areas, the CPU can more easily find the corresponding storage location based on the data type, simplifying the access logic. For example, when accessing synchronization frame information, the CPU can directly access the synchronization frame table area without having to search through a large amount of data.

[0074] Placing these critical areas of the FlexRay communication system (including the synchronization frame table area, message buffer data area, receive FIFO message buffer header field area, and header field message buffer) in external memory instead of inside the FlexRay module enhances the scalability and flexibility of the FlexRay communication system. External memory typically has richer storage resources than the internal storage of the FlexRay module, supporting larger message buffer sizes and numbers to adapt to application needs of varying scales and complexities.

[0075] On the other hand, it enables resource sharing and efficient utilization. As a shared resource, external storage can be accessed by multiple subsystems (including the FlexRay controller), improving overall resource utilization and reducing the occupation of duplicate resources.

[0076] Furthermore, based on real-time requirements, the communication system in this embodiment can more flexibly allocate external memory resources among different tasks, improving the overall performance and response speed of the system, thereby optimizing resource allocation.

[0077] In addition, many modern processors support Direct Memory Access (DMA), which allows peripherals (such as FlexRay controllers) to exchange data directly with external memory, reducing the CPU load and improving data transfer efficiency.

[0078] The FlexRay communication system in this embodiment also improves system integration and interoperability by using a standard external memory interface, making it easier to integrate the FlexRay module with other system components and promoting compatibility and interoperability between different vendors.

[0079] As a preferred embodiment, when the FlexRay controller receives the first data frame, it copies the header information of the first data frame to a first region, which is the storage region of the first channel header field buffer, the storage region of the second channel header field buffer, or the storage region of the header field message buffer.

[0080] Understandably, the header field message buffer is specifically designed to store the header information of received data frames, enabling the host processor to quickly access and process it. It provides an independent buffer for each received message, recording its header information even if the message itself is invalid or incomplete. Each data frame contains a frame header segment, which includes various key attributes about the frame, such as frame ID, payload length, and cycle count. This information is crucial for parsing frame content, maintaining network synchronization, and ensuring the accuracy and reliability of data transmission. When the FlexRay controller receives a data frame, it first copies the frame's header information to the header field message buffer area, specifically the header field buffer areas for channel A and channel B of the receive FIFO, as well as the header field message buffer area. By pre-storing the frame header information, the host processor can quickly obtain and process this information without directly accessing the original data frame, improving system response speed and efficiency. Furthermore, even if some frames cannot be received normally due to errors or other reasons, their header information is still recorded, aiding in subsequent fault diagnosis and analysis.

[0081] As a preferred embodiment, configuring the FlexRay controller includes:

[0082] When configuring sending or receiving data, the processor configures the first parameter of the FlexRay controller, which is a parameter specified in the FlexRay protocol;

[0083] After the processor completes the configuration of the first parameter, the processor configures the control register of the message buffer inside the FlexRay controller.

[0084] Understandably, when configuring data transmission or reception, the CPU first configures the general parameters of the FlexRay controller, which are the parameters specified in the FlexRay protocol, to determine the data transmission period and synchronization frame ID, etc.; then, by configuring the message buffer control register inside the FlexRay controller, the frame ID, data, etc. used for data transmission are configured.

[0085] As a preferred embodiment, the FlexRay controller is further provided with an address mapping and memory access control module, which is used to map hardware resources to the system address space and control the access order and permissions of the processor and the FlexRay controller to shared memory.

[0086] Understandably, since the communication data-related storage area, originally located inside the FlexRay controller, has been moved to a pre-defined area of ​​external memory, the FlexRay controller needs to access the external memory via the system bus if it wants to continue using this storage area. The FlexRay controller ensures coordinated access to the shared memory area with the host processor through the address mapping and memory access control module. The address mapping and memory access control module is a key interface management unit in the FlexRay controller. It maps hardware resources to the system address space and coordinates the access order and permissions of the CPU and controller to the shared memory, thereby avoiding data conflicts, ensuring real-time and reliable communication, and preventing data conflicts and access delays.

[0087] As a preferred embodiment, the FlexRay controller is further provided with a message buffer index register;

[0088] The message buffer index register indexes the message buffer control register and the physical message buffer through a preset index field to obtain the index value of each message buffer control register and the physical message buffer. Each index value corresponds to one physical message buffer and one message buffer control register.

[0089] The message buffer control register controls the physical message buffer based on the index value.

[0090] The control of the physical message buffer based on the index value includes:

[0091] The data fields of each physical message buffer are identified based on the data field offset;

[0092] The first message buffer control register controls the first physical message buffer based on a first offset. The index values ​​of the first message buffer control register and the first physical message buffer are the same. The first offset is the offset of the first data field relative to the first base address. The first base address is the base address of the first region of the external memory corresponding to the first data field. The first data field is the data field of the first physical message buffer within the first message buffer control register.

[0093] Understandably, the FlexRay controller uses a data structure called a message buffer to store frame data, configuration information, control information, and status information. Each message buffer consists of two parts: the message buffer's control data and the physical message buffer. In this embodiment, the message buffer control data is still stored in a dedicated register within the FlexRay controller, while the physical message buffer is moved to external memory. Through the FlexRay controller's Host Interface Unit (CHI), the host processor can directly read and write the contents of the message buffer in external memory, enabling real-time monitoring and dynamic adjustment of communication data.

[0094] All frame data and frame header information received by FlexRay are stored in a data structure called a physical message buffer. These physical message buffers are located in external memory. Each buffer contains two fields: a message buffer header field and a message buffer data field. The message buffer header field contains the frame header and timeslot status information, while the data field stores the frame data.

[0095] Because there are a large number of physical message buffers and their configuration methods are basically the same, it is unnecessary to set a separate configuration register for each physical message buffer to avoid wasting storage space. Instead, a message buffer index register is used, with its built-in index field to index and control the message buffer control register. The message buffer control register then controls the message buffers, thus saving storage space. The data field of each physical message buffer is identified by a data field offset. For example... Figure 4 As shown, Figure 4 The diagram shows the architecture of 32 physical message buffers. For each physical message buffer with an index value of i, the i-th corresponding register contains the offset of the message buffer's data field relative to the base address of the external memory region used.

[0096] As a preferred embodiment, a FlexRay communication system based on on-chip shared memory further includes:

[0097] During the system initialization phase, the processor writes the communication information of the FlexRay controller into the FlexRay controller; the FlexRay controller writes the communication information into a preset area of ​​the external memory according to its corresponding data structure, and the communication information includes the communication cycle, static segment length and message ID mapping table;

[0098] The FlexRay controller obtains the physical address of the configuration information by reading its internal first register, retrieves the configuration information based on the physical address, and stores the configuration information in the FlexRay controller according to its corresponding data structure.

[0099] As a preferred embodiment, a FlexRay communication system based on on-chip shared memory further includes:

[0100] During communication, the FlexRay controller reads message buffer data from the external memory according to its internal communication scheduling table, and sends the message buffer data to the FlexRay bus based on the physical layer interface of the FlexRay controller.

[0101] When the FlexRay controller receives a data frame, it writes the received data frame into the message buffer of the external memory.

[0102] Understandably, during system initialization, the CPU writes FlexRay communication information (such as communication cycle, static segment length, message ID mapping table, etc.) into the FlexRay controller. The FlexRay controller then writes the communication information into a preset area of ​​external memory according to the corresponding data structure, i.e., the corresponding storage area in external memory. The FlexRay controller obtains the physical address of the configuration information by reading its internal configuration-related registers and saves it in storage according to the corresponding data format, so as to automatically read the data to be sent from external memory and send it at the beginning of the communication cycle.

[0103] During communication, the controller reads message buffer data from external memory according to the communication schedule table and sends it to the FlexRay bus via the physical layer interface. When the FlexRay controller receives a data frame, it writes the received data frame into the message buffer of the external memory, namely the data message buffer storage area and the header field message buffer storage area.

[0104] The CPU can read received data at any time through the host interface unit for diagnostic analysis, or modify the contents of the transmit buffer to achieve instruction injection. The address mapping module ensures access timing coordination and avoids bus conflicts.

[0105] As a preferred embodiment, the host interface of the system bus supports AHB, APB, AXI and PCIe bus protocols; the external memory is a system shared memory and supports DMA or memory-mapped I / O access.

[0106] It is understood that the host interface unit of the system bus in this embodiment supports AHB, APB, AXI, and PCIe bus protocols, thereby enabling high-speed interconnection between the system bus and the host processor. The external memory is a system shared memory, sharing the same storage space with the host processor, and supports DMA or memory-mapped I / O access. The host processor can dynamically modify communication configuration information through the host interface unit, enabling online reconfiguration of communication parameters.

[0107] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A FlexRay communication system based on on-chip shared memory, characterized in that, The FlexRay communication system includes a processor, a system bus, external memory, and a FlexRay controller; The processor is connected to the host interface of the system bus; The host interface of the FlexRay controller is connected to the host interface of the system bus, and the slave interface is connected to the slave interface of the system bus. The external memory is connected to the slave interface of the system bus; The processor is used to access the system bus, and based on the system bus, access the external memory and configure the FlexRay controller; The external memory is used to store the communication data of the FlexRay controller; The FlexRay controller is used to access the system bus and read and write communication data to a preset area of ​​the external memory based on the system bus; The preset area includes a synchronization frame table storage area, a data message buffer storage area, a first channel header field buffer storage area, a second channel header field buffer storage area, and a header field message buffer storage area. The synchronization frame table area is used to store information about the synchronization frames of the FlexRay controller; The data message buffer is used to cache relevant information of the first frame, which is a frame received or sent by the FlexRay controller; The first channel header field buffer storage area, the second channel header field buffer storage area, and the header field message buffer storage area are all used to store the message header information received by the FlexRay controller; Both the first channel header field buffer storage area and the second channel header field buffer storage area manage the message header information based on a first-in-first-out (FIFO) method. The header field message buffer storage area manages the message header information based on a preset fast access mechanism; When the FlexRay controller receives the first data frame, it copies the header information of the first data frame to a first region, which is the storage area for the first channel header field buffer, the storage area for the second channel header field buffer, or the storage area for the header field message buffer.

2. The FlexRay communication system based on on-chip shared memory according to claim 1, characterized in that... The configuration of the FlexRay controller includes: When configuring sending or receiving data, the processor configures the first parameter of the FlexRay controller, which is a parameter specified in the FlexRay protocol; After the processor completes the configuration of the first parameter, the processor configures the control register of the message buffer inside the FlexRay controller.

3. The FlexRay communication system based on on-chip shared memory according to claim 1, characterized in that... The FlexRay controller is also equipped with an address mapping and memory access control module, which is used to map hardware resources to the system address space and control the access order and permissions of the processor and the FlexRay controller to shared memory.

4. The FlexRay communication system based on on-chip shared memory according to claim 1, characterized in that... The FlexRay controller also includes a message buffer index register. The message buffer index register indexes the message buffer control register and the physical message buffer through a preset index field to obtain the index value of each message buffer control register and the physical message buffer. Each index value corresponds to one physical message buffer and one message buffer control register. The message buffer control register controls the physical message buffer based on the index value.

5. A FlexRay communication system based on on-chip shared memory according to claim 4, characterized in that... The control of the physical message buffer based on the index value includes: The data fields of each physical message buffer are identified based on the data field offset; The first message buffer control register controls the first physical message buffer based on a first offset. The index values ​​of the first message buffer control register and the first physical message buffer are the same. The first offset is the offset of the first data field relative to the first base address. The first base address is the base address of the first region of the external memory corresponding to the first data field. The first data field is the data field of the first physical message buffer within the first message buffer control register.

6. A FlexRay communication system based on on-chip shared memory according to claim 1, characterized in that... It also includes: During the system initialization phase, the processor writes the communication information of the FlexRay controller into the FlexRay controller; the FlexRay controller writes the communication information into a preset area of ​​the external memory according to its corresponding data structure, and the communication information includes the communication cycle, static segment length and message ID mapping table; The FlexRay controller obtains the physical address of the configuration information by reading its internal first register, retrieves the configuration information based on the physical address, and stores the configuration information in the FlexRay controller according to its corresponding data structure.

7. A FlexRay communication system based on on-chip shared memory according to claim 1, characterized in that... It also includes: During communication, the FlexRay controller reads message buffer data from the external memory according to its internal communication scheduling table, and sends the message buffer data to the FlexRay bus based on the physical layer interface of the FlexRay controller. When the FlexRay controller receives a data frame, it writes the received data frame into the message buffer of the external memory.

8. A FlexRay communication system based on on-chip shared memory according to claim 1, characterized in that... The host interface of the system bus supports AHB, APB, AXI and PCIe bus protocols; the external memory is a system shared memory and supports DMA or memory-mapped I / O access.

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