Image sensor

Abstract

The embodiment of the invention discloses an image sensor. The image sensor with the four-pixel structure is provided with a four-pixel circuit, and the four-pixel circuit comprises four photoelectric detector pixel circuits and a bridge circuit. The bridge circuit selectively couples floating diffusion nodes corresponding to the four photodetector pixels and allows the four photodetector pixel circuits to selectively operate in a four-pixel mode, a dual-pixel mode, or a single-pixel mode. Each photodetector pixel circuit may include a multi-conversion gain circuit to provide a wide dynamic range.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to image sensors. BACKGROUND

[0002] Many modern electronic devices, such as digital cameras, optical imaging devices, etc., include image sensors. Image sensors include an array of photosensitive structures that convert light into electrical charges. Examples of image sensors include charge-coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors. CMOS image sensors are favored over CCD image sensors due to low power consumption, small size, fast data processing, direct data output, and low manufacturing cost. SUMMARY

[0003] According to one aspect of embodiments of the present application, an image sensor is provided, comprising: photodiodes in a first array within a first semiconductor substrate; a four-pixel circuit, wherein the four-pixel circuit includes four photodiodes in a two-by-two sub-array, further includes four transfer gates, four floating diffusion regions, and four source followers; and a bridge circuit selectively coupling the four floating diffusion regions.

[0004] According to another aspect of embodiments of the present application, an image sensor is provided, comprising: a semiconductor substrate; a first photodetector including a first photodiode, a first transfer gate, and a first floating diffusion node in the semiconductor substrate; a second photodetector including a second photodiode, a second transfer gate, and a second floating diffusion node in the semiconductor substrate; a third photodetector including a third photodiode, a third transfer gate, and a third floating diffusion node in the semiconductor substrate; a fourth photodetector including a fourth photodiode, a fourth transfer gate, and a fourth floating diffusion node in the semiconductor substrate; a first transistor having a pair of source / drain regions electrically coupled to the first floating diffusion node and the second floating diffusion node, respectively; a second transistor having a pair of source / drain regions electrically coupled to the third floating diffusion node and the fourth floating diffusion node, respectively; and a third transistor having a pair of source / drain regions electrically coupled to the first floating diffusion node and the third floating diffusion node, respectively.

[0005] According to yet another aspect of embodiments of the present application, an image sensor is provided, comprising: a first chip including a first semiconductor substrate; four photodetector pixel circuits, each of the photodetector pixel circuits including a photodiode, a transfer gate, a floating diffusion node, a source follower, a multiple conversion gain transistor, and a lateral overflow integration capacitor (LOFIC), wherein the photodiode is in the first semiconductor substrate; a color filter, wherein the photodiodes of the four photodetector pixel circuits are under the color filter; and a bridge circuit selectively coupling the four floating diffusion nodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. In accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components in the various figures may be arbitrarily increased or decreased relative to each other for ease of illustration or to provide emphasis.

[0007] Figures 1A-1B Circuit diagrams of four-pixel circuits for image sensors according to various embodiments of the present disclosure are provided.

[0008] Figures 2-4 Circuit diagrams of four-pixel circuits for image sensors according to various embodiments of the present disclosure are provided.

[0009] Figure 5 is a graph illustrating the operation of a triple conversion gain circuit according to some embodiments.

[0010] Figures 6A-6B Circuit diagrams of multiple conversion gain circuits according to various embodiments are provided.

[0011] Figure 7 A cross-sectional view of an image sensor is shown in accordance with some embodiments.

[0012] Figure 8 Data mapping to form an image from an image sensor is shown in accordance with some embodiments.

[0013] Figures 9-14 Circuit diagrams are provided that illustrate the distribution of image sensor components among device layers according to various embodiments.

[0014] Figure 15 A plan view of a four-pixel group according to an embodiment is shown.

[0015] Figures 16-22 A series of cross-sectional views are provided illustrating an embodiment of a manufacturing process according to the present disclosure.

[0016] Figure 23 A flow chart of a manufacturing process according to some embodiments of the present disclosure is provided.

[0017] Figure 24 A flow chart illustrating one embodiment of a method of operating a quad is provided.

[0018] Figure 25 A flow chart illustrating a reset operation of an image sensor according to some embodiments is provided.

[0019] Figures 26-27 A flow chart of an image sensor read operation according to some embodiments is provided. DETAILED DESCRIPTION

[0020] The following disclosure provides a number of different embodiments or examples for implementing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the disclosure in any way. For example, in the following description, the formation of a first component over or on a second component can comprise embodiments where the first component and second component are in direct contact, and can also comprise embodiments where additional components can be formed between the first component and the second component such that the first component and second component can not be in direct contact. Furthermore, the present disclosure can refer to reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not indicate a relationship between the different embodiments and / or configurations discussed.

[0021] Spatially relative terms such as "beneath", "below", "lower", "above", "upper" and the like can be used herein for ease of description to describe one element or component's or portion's relationship to another element, component or portion as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. The terms "first", "second", "third", "fourth" etc. are used herein only for identification of one of a plurality of elements or components, and are not intended to denote a physical or logical relationship between the elements or components. For example, although one element (e.g. an opening) can be referred to as a "first" element in some embodiments, the element can be referred to as a "second" element in other embodiments.

[0022] One type of CMOS image sensor has an array of photodetectors, each comprising a photosensitive region within a semiconductor substrate, a transfer gate, a floating diffusion node, a source follower, a row select transistor, and a reset transistor. When the reset transistor is off, the floating diffusion node attains a reference voltage. The photosensitive region is part of a photodiode or other photodetector structure that converts light into charge. Illumination causes charge to accumulate in the photodiode or other photodetector structure until the transfer gate is closed, at which point the charge flows to the floating diffusion node. The charge changes the floating diffusion node voltage. The floating diffusion node voltage is applied to the gate electrode of the source follower. When the corresponding row select transistor is closed, current flows through the source follower at a rate dependent on the floating diffusion node voltage. The current is detected and used to infer the amount of charge transferred to the floating diffusion node, which in turn reflects the amount of radiation incident on the photosensitive region during the sampling interval.

[0023] Conversion gain is an important parameter for CMOS image sensors of the type described above. Conversion gain is related to the capacitance of the floating diffusion node. If the conversion gain is too high, the photodetector pixel circuit can saturate and be unable to distinguish between light intensity levels. If the conversion gain is too low, there will be too much noise compared to the signal and light intensity variations at lower light intensity levels will be lost. At high light levels, low conversion gain is generally desirable. For low light levels, high conversion gain is generally desirable. The effective range of a CMOS image sensor between the lowest and highest light levels is its dynamic range. The dynamic range depends on the floating diffusion node capacitance.

[0024] The dynamic range can be increased by adding a dual conversion gain circuit in the photodetector pixel circuit. The dual conversion gain circuit allows adaptation to higher light intensity levels by selectively adding capacitance to the floating diffusion node. The source of the capacitance can be a lateral overflow integration capacitor (LOFIC). In high conversion gain mode, the dual conversion gain circuit adds extra capacitance to the floating diffusion node and reduces the conversion gain. In low conversion gain mode, the dual conversion gain circuit isolates the extra capacitance from the floating diffusion node. Dual conversion gain is primarily used to adapt to higher light intensity levels. The concept of dual conversion gain can be extended to include other multi-conversion gain circuits, such as a triple conversion gain circuit that allows selection between three possible levels of capacitance.

[0025] One method of extending the dynamic range to adapt to lower light intensity levels is to use a four-pixel structure. In a four-pixel structure, a two-by-two subarray of adjacent photodetector pixels is disposed under each color filter in a color filter / micro-lens array. When the light intensity level is high, the four photodetector pixels operate independently to provide a high resolution image. When the light intensity level is low, the four photodetector pixels are combined into one pixel to provide a quarter resolution image with relatively lower noise.

[0026] One method of implementing data combination from four adjacent photodetector pixels is to have them share a floating diffusion node. Four different transfer gates selectively transfer charge from their respective photodiodes to the floating diffusion node. In high resolution mode, the photodetector pixels are read serially and the floating diffusion node is reset between each read operation. In low resolution mode, the charge from all four photodiodes is transferred to the floating diffusion node at each read operation. A disadvantage of this method is that the reset time becomes a limiting factor, particularly in high resolution mode where the pixels are read serially and in low conversion gain mode where the LOFIC adds extra capacitance to the photodetector pixel circuit.

[0027] Another method of combining data from four adjacent photodetector pixels is to combine their readouts. The photodetector pixels are read by column decoders and the signals from these column decoders are combined during signal processing. A disadvantage of this method is that noise is introduced with each read operation. When the outputs of four read operations are combined, there are four read noise contributions to the resulting data point. The contribution of four read noises is counterproductive to the expected benefit of combining four signals to reduce noise. Another disadvantage of combining signals is that four separate read operations are performed to provide each data point, which extends the read time.

[0028] According to the present disclosure, the above-described problems are addressed by a bridge circuit that selectively couples floating diffusion nodes corresponding to photodetector pixels in a four-pixel circuit. The four-pixel circuit includes four photodetector pixel circuits, each of which can include a multiple conversion gain circuit. The bridge circuit allows the four photodetector pixel circuits to be selectively operated in a four-pixel mode, a two-pixel mode, or a single-pixel mode.

[0029] In the single-pixel mode, the bridge circuit isolates the four floating diffusion nodes of the four photodetector pixel circuits from each other so that each photodetector pixel circuit can operate independently of the other circuits. The multiple conversion gain circuit can be operated to vary the capacitance of the floating diffusion node so that each photodetector pixel can be in a high conversion gain mode, a low conversion gain mode, or some intermediate conversion gain mode. In some embodiments, the multiple conversion gain circuit is a dual conversion gain circuit. In some embodiments, the multiple conversion gain circuit is a triple conversion gain circuit that is operable to selectively add a first additional capacitance or first and second additional capacitances in a floating diffusion mode to provide a high, medium, or low conversion gain mode. The single-pixel mode provides a high resolution image that is suitable for high and low light levels at an acceptable low sampling rate.

[0030] In dual-pixel mode, the bridge circuit connects the four floating diffusion nodes of the four photodetector pixel circuits as two pairs, causing the four photodetector pixel circuits to operate as two photodetector pixel circuits. The transfer gates are operated so that the charge accumulated by the photodiodes of the paired photodetector pixels is mixed in the combined floating diffusion nodes. The voltage on the combined floating diffusion nodes can be read by either or both of the source followers associated with the connected photodetector pixel circuits. In either case, a single read operation provides data from a pair of photodiodes, which produces lower noise than adding the outputs of two separate read operations. Dual-pixel mode provides medium resolution. Dual-pixel mode can be combined with high, medium, or low conversion gain mode. The multiple conversion gain circuits can all utilize the same conversion gain switching signal. In some embodiments, some of the multiple conversion gain circuits have independent mode switching signals, so that extra capacitance from zero, one, or two of the multiple conversion gain circuits can be selectively added to each combined floating diffusion node to provide a wide range of conversion gain modes.

[0031] In quad-pixel mode, the bridge circuit connects the four floating diffusion nodes of the four photodetector pixel circuits, causing the four photodetector pixel circuits to operate as one combined photodetector pixel circuit. The transfer gates are operated so that the charge accumulated by the four adjacent photodiodes is mixed in one combined floating diffusion node. The voltage on the combined floating diffusion node can be read by one or more of the four source followers associated with the four photodetector pixel circuits in the quad-pixel circuit. A single read operation can provide data from four photodiodes, which produces lower noise than adding the outputs of four separate read operations. Quad-pixel mode can be combined with high, medium, or low conversion gain mode. Optionally, the multiple conversion gain circuits have independent mode switching signals, so that extra capacitance from zero, one, two, three, or all of the multiple conversion gain circuits can be selectively added to the combined floating diffusion node to reduce conversion gain in quad-pixel mode. Quad-pixel mode provides 1 / 4 the resolution of single-pixel mode. A low resolution image can be more accurate and take up less memory than an equivalent full resolution image under the same lighting conditions.

[0032] The bridge circuit can include transistors or other switching structures. In some embodiments, the bridge circuit includes three transistors: two transistors to connect the floating diffusion nodes of two pairs of adjacent photodetector pixels, and a third transistor to connect the two pairs of adjacent pixels. In some embodiments, the bridge circuit includes a fourth transistor to maintain equivalence between the photodetector pixels and to simplify the manufacturing process. The transistors can be NMOS transistors, PMOS transistors, or other types of transistors.

[0033] Another important performance parameter for CMOS image sensors is resolution. High resolution is achieved by high pixel density. The area occupied by the transistors in the photodetector pixel circuit limits the pixel density. One way to overcome this limitation is to use two to three device layers. The first portion of the photodetector pixel circuit, including the photodiode and the transfer gate, is located in the first device layer. The second portion of the photodetector pixel circuit is located in the second device layer. Application specific integrated circuits (ASICs) can be provided in the peripheral region of the second device layer or in a third device layer.

[0034] The photodetector pixel circuit components on the second device layer can include one or more of a row select transistor, a reset transistor, a multiple conversion gain circuit (which can include a reset transistor), and a source follower. In some embodiments, the bridge circuit is located on the second device layer. In some other embodiments, the bridge circuit is located on the first device layer. Having the bridge circuit on the first device layer can reduce the capacitance of the floating diffusion node and increase the conversion gain. In some embodiments, the source follower is located on the first device layer with the bridge circuit, while some other components of the four-pixel circuit are located on the second device layer. This latter structure can provide a high conversion gain mode in which the floating diffusion node does not include any contribution to the wiring pair capacitance from the first device layer to the second device layer.

[0035] Unlike the prior art, which has one shared floating diffusion node for the four-pixel structure, the four-pixel structure according to the present disclosure allows each photodetector pixel circuit to have independent multiple conversion gain circuits and independent LOFICs. As the pixel density gets higher, it can be difficult to package so many LOFICs. In some embodiments, this problem is solved by locating the LOFICs in the first device layer with the photodiodes and transfer gates, while locating other components of the photodetector pixel circuit in the second device layer. In some embodiments, this problem is solved by locating the LOFICs in the third device layer with the ASICs.

[0036] Figure 1A is a circuit diagram 100 of a portion of an image sensor including a four-pixel circuit 105. The four-pixel circuit 105 includes four photodetector pixel circuits 101A-101D and a bridge circuit 107. Each photodetector pixel circuit 101A-101D includes a photodiode PD, a floating diffusion node FD, a transfer gate TX, a source follower SF, and a row select transistor RSL. The photodetector pixel circuit 101A-101D circuit can also include a reset transistor or a dual conversion gain circuit (not shown).

[0037] Bridge circuit 107 is connected to the four floating diffusion nodes FD and contains circuitry for selectively coupling and decoupling the four floating diffusion nodes FD to implement various modes. These modes can include: a 1C mode in which the four floating diffusion nodes FD are decoupled; a 2C mode in which the floating diffusion nodes FD of photodetector pixel circuits 101A and 101C are coupled and the floating diffusion nodes FD of photodetector pixel circuits 101B and 101D are coupled; and a 4C mode in which all four floating diffusion nodes FD are coupled.

[0038] Row select transistors RSL of photodetector pixel circuits 101A and 101C are coupled to column wire 103A. Row select transistors RSL of photodetector pixel circuits 101B and 101B are coupled to column wire 103B. Column wires 103A and 103B are wire structures connected to column decoders (not shown). There can be one column decoder for each column in the photodetector array.

[0039] Transmission gate TX is selectively enabled by transmission gate signal V TX-A -V TX-D . Transmission gate signal V TX-A -V TX-D can be independent. Source follower SF is selectively enabled by row select signals V RS-A and V RS-B . Each of row select signals V RS-A and V RS-B is provided by a different row driver (not shown). In 1C mode, row select signals V RS-A and V RS-B are serial operations for each read operation. In 2C and 4C modes, only one of row select signals V RS-A and V RS-B is used for read operation.

[0040] Figure 1B is a circuit diagram 110 of a portion on the image sensor including four-pixel circuit 105A. Four-pixel circuit 105A is similar to four-pixel circuit 105 of Figure 1A except that all four row select transistors RSL are coupled to column wire 103A. This configuration allows the use of fewer column wires and can improve conversion gain by reducing parasitic capacitance, at the cost of Figure 1B the configuration of four-pixel circuit 105A requiring the use of four independent row select signals V RS_A -V RS_D . Compared to the structure of Figure 1B , the structure of Figure 1A has the advantage of allowing half the row driver operations to be performed in sequence to acquire an image.

[0041] Figure 2is a circuit diagram 200 showing the four-pixel circuit 105 in the case where the bridge circuit 107 is implemented by a bridge circuit 107A. The bridge circuit 107A includes four switching transistors 201A-201D, which can be operated by two control signals V SW1 and V SW2 . When both control signals V SW1 and V SW2 are set to low, all four switching transistors 201A-201D are turned off and the 1C mode is implemented. When control signal V SW1 is set to low and control signal V SW2 is set to high, switching transistors 201B and 201C are turned on while switching transistors 201A and 201D remain off, which implements the 2C mode. When both control signals V SW1 and V SW2 are set to high, all four switching transistors 201A-201D are turned on and the 4C mode is implemented.

[0042] Figure 3 is a circuit diagram 300 showing the four-pixel circuit 105 in the case where the bridge circuit 107 is implemented by a bridge circuit 107B. The bridge circuit 107B is similar to the bridge circuit 107A of Figure 2 , except that it lacks switching transistor 201D. Removing switching transistor 201D simplifies the circuit and can allow for a reduction in the capacitance of the floating diffusion node FD. Retaining switching transistor 201D simplifies the manufacturing process and simplifies the process of maintaining equal capacitance between the four floating diffusion nodes FD in the four-pixel circuit 105.

[0043] Figure 4 is a circuit diagram 400 of a four-pixel circuit 405. The four-pixel circuit 405 is similar to the four-pixel circuit 105 of Figure 1A , except that the four-pixel circuit 405 has photodetector pixel circuits 401A-401D in place of photodetector pixel circuits 101A-101D. The photodetector pixel circuits 401A-401D have the components of the photodetector pixel circuits 101A-101D, but also include a three-transimpedance gain circuit 409A-409D, respectively.

[0044] The three-transimpedance gain circuits 409A-409D can each include a first transimpedance gain transistor CG1, a second transimpedance gain transistor CG2, a reset transistor RST, a capacitor control transistor CC, a LOFIC. The reset transistor RST is operated by a reset control signal V RT_A -V RT_D . The capacitor control transistor CC can be operated by a capacitor control signal V CC_A -V CC_Doperation. The first conversion gain transistor CG1 and the second conversion gain transistor CG2 are turned on by the conversion gain control signals V CG1_A -V CG1_D and V CG2_A -V CG2_D operation to achieve a low, medium, or high conversion gain mode.

[0045] Figure 5 is a chart 500 showing the operation of the three conversion gain circuit 409A. The three conversion gain circuits 409B-409D can operate in a similar manner. For a reset operation, the reset control signal V RT_A and the conversion gain control signals V CG1_A and V CG2_A are all set to high, such that the first conversion gain transistor CG1, the second conversion gain transistor CG2, and the reset transistor RST are all closed. This results in the floating diffusion node FD being set to VDD, and the LOFIC being set to discharge.

[0046] To enter the low conversion gain mode, the reset control signal V RT_A is set to low, while the conversion gain control signals V CG1_A and V CG2_A remain high. This results in the floating diffusion node FD floating, and including the capacitance of the first and second conversion gain transistors CG1 and CG2, and the LOFIC. This state can be maintained until the next read operation involving the floating diffusion node FD, after which the reset operation can be repeated.

[0047] To enter the medium conversion gain mode, the reset control signal V RT_A and the conversion gain control signals V CG2_A are set to low, while the conversion gain control signal V CG1_A remains high. This results in the floating diffusion node FD including the capacitance of the source / drain region 411 (see Figure 4 ) and other capacitances associated with the first conversion gain transistor CG1, but not including the capacitance of the LOFIC. The source / drain region 411 can be larger or have a heavier doping than any source / drain region that is always coupled to the floating diffusion node FD, such as the drain region of the pass gate TX (also referred to as the floating diffusion region), the source region of the first conversion gain transistor CG1, and source / drain regions associated with the bridge circuit 107 (see Figure 4). These other source / drain regions can remain small and lightly doped so as to keep the capacitance of the floating diffusion node FD low in the high conversion gain mode. On the other hand, the capacitance of the source / drain region 411 can be made as large as or larger than all of these other source / drain regions so as to provide a significant increase in the capacitance of the floating diffusion node FD when transitioning from the high conversion gain mode to the medium conversion gain mode. In some embodiments, the addition of the source / drain region 411 to the floating diffusion node FD at least doubles the capacitance of the floating diffusion node FD.

[0048] To enter the high conversion gain mode, the conversion gain control signal V CG1_A and V CG2_A are set low along with the reset control signal V RT_A . This causes the floating diffusion node FD to float and isolate from the capacitance of the source / drain region 411 and the LOFIC. This state can be maintained until the next read operation, after which the reset operation can be repeated again.

[0049] The low, medium, and high conversion gain modes can be used in conjunction with a 1C mode, 2C mode, or 4C mode. In the 4C mode, the reset operation of the four photodetector pixel circuits 401A-401D can be performed simultaneously. In the 1C mode, the reset operation of the four photodetector pixel circuits 401A-401D can be performed asynchronously. In the 4C mode, the transfer gates TX can be turned on simultaneously to initiate the read operation. The synchronous operation improves the read operation speed. In the 1C mode, the transfer gates TX can be turned off asynchronously. The asynchronous operation allows the sharing of the column wires 403A and 403B (see Figure 4 ) between the photodiodes PD in the four-pixel circuit 405.

[0050] Figures 6A-6B Circuit diagrams 600A-600B of multi-conversion gain circuits 409E-409F according to various other embodiments are provided. The multi-conversion gain circuit 409E is Figure 4 one of the alternatives to the three-conversion gain circuits 409A-409D in the example. In the multi-conversion gain circuit 409E Figure 6A , the capacitor control transistor CC (see Figure 4 ) has been replaced with a direct connection to V dd . In the three-conversion gain circuit 409F Figure 6B , the LOFIC is connected to ground instead of V ref1 . In the three-conversion gain circuit 409F Figure 6B , the first conversion gain transistor CG1 has been removed, thereby simplifying the circuit shown to a dual-conversion gain circuit that only provides a low conversion gain mode and a high conversion gain mode. In some embodiments, V ref1 is V DDIn some embodiments, V ref1 In some embodiments, V ref1 is a negative voltage bias (polarity similar to V DD In some embodiments, V ref1 is an indeterminate floating voltage. Each of these options provides slightly different behavior for the corresponding multi-conversion gain circuit, and any of these options may provide optimal performance for a particular application. When a capacitor-controlled transistor CC is provided, the capacitor-controlled transistor CC can be manipulated to further tune the behavior of these multi-conversion gain circuits.

[0051] Figure 7 A cross-sectional view of an image sensor 700 according to some embodiments is shown. Image sensor 700 is an integrated circuit (IC) device and may be a 3D-IC including a first chip 783, a second chip 779, and a third chip 775 stacked, bonded, and interconnected. First chip 783 includes a first semiconductor substrate 739 and a first metal interconnect structure 743. Second chip 779 includes a second semiconductor substrate 751 and a second metal interconnect structure 747. Third chip 775 includes a third semiconductor substrate 763 and a third metal interconnect structure 759.

[0052] The photodiodes 711 in the first array 723 are disposed within the first semiconductor substrate 739. A deep trench isolation (DTI) structure 715 provides electrical isolation between adjacent photodiodes 711. The microlenses 701 and color filters 709 are located in a second array 719 above the first array 723. The backside metal grid 705 provides optical isolation between adjacent color filters 709. The number density of the second array 719 is one-fourth that of the first array 723, so there are four photodiodes 711 under each color filter 709. The four photodiodes 711 under each color filter 709 form a two-by-two subarray and are located in a four-pixel circuit. The four-pixel circuit may correspond to Figure 1A The four-pixel circuit 105 or any other four-pixel circuit provided by the present disclosure.

[0053] Figure 8 Shows something like Figure 7 The process of forming an image in the 1C and 4C modes by the four-pixel structure of the image sensor 700. Figure 8 As shown, color filters 709 may be green (G), red (R), and blue (B) arranged in a Bayer pattern. In 4C mode, image data from photodiode 711 is mapped according to the color filter layout. In 1C mode, image data from photodiode 711 may be mapped to a Bayer pattern image format corresponding to a higher resolution. Interpolation may be used to map pixel positions in the image that are offset from actual pixel positions of the same color.

[0054] Figure 9 A circuit diagram 900 is provided showing a photodetector pixel circuit 401A (see FIG. Figure 4 ) components, components of the bridge circuit 107 (represented by the switching transistor 201A) and the application-specific integrated circuit (ASIC) are distributed among the first chip 783, the second chip 779 and the third chip 775 (see Figure 7 ) in 3D-IC. Figure 9 As shown, the photodiode PD and the transmission gate TX can be provided on the first chip 783. The photodetector pixel circuit 401A (see Figure 4 ) including the source follower SF, the row select transistor RSL and the triple conversion gain circuit 409A, can be provided on the second chip 779, which leaves more area for the photodiode PD on the first chip 783. Figure 4 ) components, such as bridge circuit 107A (see Figure 2 ) switching transistor 201A may also be provided on the second chip 779. The floating diffusion node FD includes some components on the first chip 783, such as the drain region of the transmission gate TX (which may be called a floating diffusion region), some components on the second chip 779, such as the source region of the first conversion gain transistor CG1, and wiring between the first chip 783 and the second chip 779. The ASIC may be provided on the third chip 775.

[0055] Figure 10 A circuit diagram 1000 is provided illustrating component distribution among a first chip 783 , a second chip 779 , and a third chip 775 according to another embodiment. Figure 10 The components of the circuit diagram 1000 are shown in FIG. Figure 9 The component distribution shown in the circuit diagram 900 is different because the LOFIC is located on the third chip 775. This configuration facilitates providing one LOFIC for each photodiode PD. The capacitor control transistor CC (if included) can be kept on the same chip as the LOFIC to reduce wiring.

[0056] Figure 11 A circuit diagram 1100 is provided illustrating component distribution among the first chip 783 , the second chip 779 , and the third chip 775 according to another embodiment. Figure 11 The components of the circuit diagram 1100 are arranged with Figure 9 The component distribution shown in the circuit diagram 900 is different because the LOFIC is located on the first chip 783. This configuration also facilitates providing a LOFIC for each photodiode PD. The LOFIC is located in the first metal interconnect structure 743 (see FIG. Figure 7), so the available area of ​​the photodiode PD will not be reduced.

[0057] Figure 12 A circuit diagram 1200 is provided showing the distribution of components between the first chip 783, the second chip 779, and the third chip 775 according to another embodiment. Figure 12 In the embodiment of FIG. 1 , the first conversion gain transistor CG1 (or only the reset transistor in the case of no multi-conversion gain circuit), the source follower SF and the switching transistor 201A are located on the first chip 783, while the photodetector pixel circuit 401A (see FIG. 1 ) is located on the first chip 783. Figure 4 ) are located on the second chip 779. In this embodiment, all components that are part of the floating diffusion node FD in the high conversion gain mode are on the first chip 783. An advantage of this configuration is that when in the high conversion gain mode, the floating diffusion node FD has no capacitance associated with the wiring extending between the first chip 783 and the second chip 779.

[0058] Figure 13 A circuit diagram 1300 is provided showing the component distribution between the first chip 783 and the second chip 779 according to an embodiment suitable for a dual device layer 3DIC. Figure 13 In the embodiment of the photodetector pixel circuit 401A (see Figure 4 ) and all components of the bridge circuit 107 (represented by the switching transistor 201A) are on the first chip 783. The ASIC can be provided on the second chip 779.

[0059] Figure 14 A circuit diagram 1400 is provided showing component distribution between a first chip 783 and a second chip 779 according to another embodiment suitable for a dual device layer 3DIC. Figure 14 An embodiment similar to Figure 13 , except that the LOFIC is located on a second chip 779 together with the ASIC.

[0060] Figure 15 A plan view 1500 is provided showing the Figure 13 The circuit diagram 1300 and Figure 14 A possible layout of four pixel circuit transistors on first chip 783, consistent with circuit diagram 1400 , is shown in plan view 1500 . Four pixel regions, pixel regions 1501A-1501D, are shown. Photodiode PD and source / drain regions have n-type doping. P-doped region 1527 provides isolation. Heavily p-doped region 1511 can be used as a contact to maintain heavily p-doped region 1511 at ground or some other fixed bias voltage.

[0061] The wiring structure 1503A connects the source / drain region of the switching transistor 201A to the floating diffusion region 1505B in the pixel region 1501B. The wiring structure 1503A also connects the floating diffusion region 1505B to the gate electrode of the source follower SF in the pixel region 1501B.

[0062] The wiring structure 1503B connects the source / drain region of the switching transistor 201B to the floating diffusion region 1505D in the pixel region 1501D. The wiring structure 1503B also connects the floating diffusion region 1505D to the gate electrode of the source follower SF in the pixel region 1501D.

[0063] The wiring structure 1503C connects the source / drain region of the switching transistor 201D to the floating diffusion region 1505C in the pixel region 1501C. The wiring structure 1503C also connects the floating diffusion region 1505C to the gate electrode of the source follower SF in the pixel region 1501C.

[0064] The wiring structure 1503D connects the source / drain region of the switching transistor 201C to the floating diffusion region 1505A in the pixel region 1501A. The wiring structure 1503D also connects the floating diffusion region 1505A to the gate electrode of the source follower SF in the pixel region 1501A.

[0065] Figures 16-22 A series of cross-sectional views of components of an image sensor at different stages of fabrication according to the processes of the present disclosure are shown. Although Figures 16-22 are described in terms of a series of actions, it is understood that the order of the actions can change, and that the series of actions is applicable to structures other than the structures shown. In some embodiments, some of the actions can be omitted entirely or partially. Furthermore, although Figures 16-22 are described in terms of a series of actions, it is understood that, Figures 16-22 the structures shown in are not limited to the method of fabrication, but can exist independently as structures separate from the method.

[0066] The method can start with front-end-of-line (FEOL) and back-end-of-line (BEOL) processing of each of the first chip 783, the second chip 779, and the third chip 775. Although these are referred to as chips, at this stage of processing, they can be wafers. Figure 16 The first chip 783, the second chip 779, and the third chip 775 at the end of the FEOL and BEOL processing are shown. The three device layers can be processed separately so far, or in any order.

[0067] The first chip 783 includes a photodiode 711 formed in a first semiconductor substrate 739. The semiconductor substrate can be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. At least an upper portion of the semiconductor substrate is semiconductor. The semiconductor can be, for example, silicon (Si), a III-V semiconductor, or some other binary semiconductor, ternary semiconductor (e.g., AlGaAs), higher order semiconductor, etc. In some embodiments, the semiconductor is or includes silicon (Si), etc. The photodiode 711 can be formed by ion implantation into the first semiconductor substrate 739 during FEOL processing. Additional structures formed during FEOL processing can include, for example, pass gates 731, floating diffusion regions 727, and isolation structures 733.

[0068] A first metal interconnect structure 743 including wiring 745 surrounded by interlayer dielectric 749 is formed during BEOL processing. The wiring 745 is arranged in multiple metallization layers. Vias (not shown) connect the wiring 745 between adjacent metallization layers. The wires and vias in the metal interconnect structure can be or include copper (Cu), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), zirconium (Zi), titanium (Ti), tantalum (Ta), aluminum (Al), conductive carbides, oxides, alloys of these metals, etc., or any other suitable conductive material. The wires and vias can also include diffusion barrier layers, such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), etc. The interlayer dielectric can include one or more layers of silicon dioxide (SiO2), low-k dielectric, or ultra-low-k dielectric. Low-k refers to a dielectric constant less than that of silicon dioxide (SiO2). Examples of low-k dielectrics include organosilicate glass (OSG), such as carbon-doped silicon dioxide, fluorine-doped silicon dioxide (also known as fluorinated quartz glass (FSG)), organic polymer low-k dielectrics, and porous silicate glass. The metal interconnect structure can also include an etch stop layer. The etch stop layer can be aluminum oxide (AlO x ), silicon nitride (SiN), silicon carbide (SiC), silicon carbon nitride (SiCN), silicon carbon oxide (SiOC), silicon carbon oxide nitride (SiOCN), combinations thereof, etc.

[0069] The uppermost layer of the first metal interconnect structure 743 is a bonding layer. The bonding layer includes a contact pad 753 and a dielectric 757. The contact pad 753 can be one of the metals described above as suitable for wires. In some embodiments, the contact pad 753 is a metal suitable for metal-to-metal bonding. In some embodiments, the dielectric 757 is silicon dioxide (SiO2), silicon oxynitride (SiON), etc., or some other dielectric suitable for dielectric-to-dielectric bonding.

[0070] FEOL processing of the second chip 779 provides transistor 771. BEOL processing provides a second metal interconnect structure 747, which includes wiring 758 and interlayer dielectric 760. The uppermost layer of the second metal interconnect structure 747 is a bonding layer. The bonding layer may include contact pads 754 and bonding dielectric 756.

[0071] FEOL processing of the third chip 775 provides transistors 767 and other components of the ASIC (not shown). BEOL processing provides a third metal interconnect structure 759, which includes wiring 768 and an interlayer dielectric 770. The topmost layer of the third metal interconnect structure 759 is a bonding layer. The bonding layer may include contact pads 764 and a bonding dielectric 766.

[0072] The LOFIC (not shown) can be formed during BEOL processing and can be located in the first metal interconnect structure 743, the second metal interconnect structure 747, or the third metal interconnect structure 759. In some embodiments, the LOFIC is a metal-insulator-metal capacitor. In some embodiments, the LOFIC is a trench capacitor. In some embodiments, the LOFIC is a metal-oxide-metal capacitor. In some embodiments, the LOFIC includes interdigitated metal plates. In some embodiments, the LOFIC is disposed in the topmost metallization layer of the metal interconnect structure.

[0073] like Figure 17 As shown in cross-sectional view 1700 of FIG, the process can continue by bonding second chip 779 to first chip 783. The bond can be a dielectric-to-dielectric bond between bonding dielectric 756 and bonding dielectric 757, a metal-to-metal bond between contact pad 754 and contact pad 753, or a bond that includes both dielectric-to-dielectric and metal-to-metal. In either case, an electrical connection is formed between contact pad 754 and contact pad 753.

[0074] like Figure 18 As shown in the cross-sectional view 1800 of , the second semiconductor substrate 751 can be thinned from the back side. The second semiconductor substrate 751 can be thinned by etching, mechanical grinding, CMP, etc., or some other suitable process. In some embodiments, thinning reduces the second semiconductor substrate 751 to a thickness in the range of about 1 μm to about 10 μm. In some embodiments, thinning reduces the second semiconductor substrate 751 to a thickness of about 5 μm or less. In some embodiments, thinning reduces the second semiconductor substrate 751 to a thickness of about 3 μm or less. If the second semiconductor substrate 751 is too thick, it may be impractical to form TSV (through substrate via). If the second semiconductor substrate 751 is too thin, its structure may be unstable.

[0075] like Figure 19As shown in the cross-sectional view 1900 of FIG, TSV 755 can be formed through the second semiconductor substrate 751. The process can include forming an isolation structure on the back side 1901, etching a hole that falls on the wire 758 in the second metal interconnect structure 747, lining the hole with a dielectric, performing a breakthrough etch to expose the wiring, filling the hole with a conductive material, and planarization. The conductive material can be doped polysilicon, a metal, or some other suitable conductor. If the conductive material is a metal, the metal can be or include, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), indium (In), nickel (Ni), etc.

[0076] like Figure 20 As shown in the cross-sectional view 2000 of , a bonding structure may be formed on the back side 1901. Figure 21 As shown in the cross-sectional view 2100 of FIG, the second chip 779 with the first chip 783 attached thereto may be bonded to the third chip 775. The bonding may be dielectric-to-dielectric bonding, metal-to-metal bonding, or a combination of dielectric-to-dielectric and metal-to-metal bonding.

[0077] like Figure 22 As shown in the cross-sectional view 2200 of , the first semiconductor substrate 739 can then be thinned from the back side 2201. The first semiconductor substrate 739 can be thinned by etching, mechanical grinding, CMP, etc. or some other suitable process. In some embodiments, the thinning reduces the second semiconductor substrate 751 to a thickness in the range of about 1 μm to about 10 μm. In some embodiments, the thinning reduces the first semiconductor substrate 739 to a thickness of about 5 μm or less. In some embodiments, the thinning reduces the second semiconductor substrate 751 to a thickness of about 3 μm or less. If the first semiconductor substrate 739 is too thick, light may not be able to effectively penetrate to the photodiode 711. If the first semiconductor substrate 739 is too thin, the photodiode 711 may not be able to effectively capture light. Further processing can provide a DTI structure 715, a backside metal grid 705, a color filter 709, a microlens 701, a contact pad 735, thereby producing a structure such as Figure 7 The structure shown.

[0078] Figure 23 A flow chart of a process 2300 for forming an image sensor of the present disclosure is provided. Although process 2300 is shown and described below as a series of actions or events, it should be understood that the order in which these actions or events are shown should not be construed as limiting. For example, some actions may occur in a different order and / or concurrently with other actions or events than those shown and / or described herein. Furthermore, not all of the actions shown are required to implement one or more aspects or embodiments described herein. Furthermore, one or more actions described herein may be performed in one or more separate actions and / or stages.

[0079] Process 2300 begins at action 2301 with FEOL and BEOL processing of first, second, and third device layers. Figure 16 Cross-sectional diagram 1600 provides an example of these device layers after initial processing. At this stage of processing, each device layer can be a separate wafer. The wafers can later be diced to form chips. The FEOL processing forms wells, transistors, diodes, isolation structures, etc. in the substrates. The BEOL processing forms metal interconnect structures, capacitors, and bonding structures. The first device layer can contain photodiode arrays or other photodetector structures, transfer gates, etc. The second device layer can include some photodetector pixel circuit components. The first device layer or the second device layer can contain row drivers and column decoders for the photodiode arrays. The third device layer can include an ASIC.

[0080] Action 2303 is to align the first and second device layers and bond them together through their respective bonding layers. Figure 17 Cross-sectional diagram 1700 provides an example.

[0081] Action 2305 is to thin the semiconductor substrate of the second device layer from the backside. Figure 18 Cross-sectional diagram 1800 provides an example.

[0082] Action 2307 is to form TSVs through the semiconductor substrate of the second device layer from the backside. Figure 19 Cross-sectional diagram 1900 provides an example.

[0083] Action 2311 is to form contact pads and bonding structures at the backside of the second device layer. Figure 20 Cross-sectional diagram 2000 provides an example.

[0084] Action 2313 is to align the second and third device layers and bond them together so that the TSVs are coupled to the third device. Figure 21 Cross-sectional diagram 2100 provides an example.

[0085] Action 2317 is to thin the semiconductor substrate of the first device layer from the backside. Figure 22 Cross-sectional diagram 2200 provides an example.

[0086] Action 2319 is to form DTI structures from the backside of the semiconductor substrate of the first device layer. Action 2321 is additional processing to form backside metal grids, color filters, and microlenses on the backside of the semiconductor substrate of the first device layer. Action 2323 is to form contact pads on the backside of the semiconductor substrate of the first device layer. Figure 7 Cross-sectional diagram 2300 provides an example of the final structure.

[0087] Figure 24is a flowchart of a method 2400 for operating an image sensor having a four-pixel structure according to the present disclosure. The method starts with act 2401, selecting between 1C, 2C, and 4C modes. Act 2403 is determining whether the 1C mode has been selected. If the 1C mode has been selected, act 2405 operates the bridging circuit to isolate the floating diffusion node in each four-pixel array. If the 1C mode has not been selected, act 2407 determines whether the 2C mode has been selected. If the 2C mode has been selected, act 2409 operates the bridging circuit so that the paired floating diffusion nodes in each four-pixel array are coupled. If the 2C mode has not been selected, act 2411 operates the bridging circuit so that all four floating diffusion nodes in each four-pixel array are electrically coupled.

[0088] Figure 25 is a flowchart of a method 2500 for operating an image sensor having a three- conversion gain circuit and a four-pixel structure according to the present disclosure. The method 2500 is compatible with the method 2400 in Figure 24 . The method 2500 starts with act 2501, selecting a low, medium, or high conversion gain mode. Act 2503 is performing a reset operation, which can include turning off all of the reset and conversion gain transistors in the three-conversion gain circuit. Act 2505 determines whether the low conversion gain mode has been selected. If the low conversion gain mode has been selected, act 2507 turns off the reset transistor while leaving the conversion gain transistors closed. If the low conversion gain mode has not been selected, act 2509 determines whether the medium conversion gain mode has been selected. If the medium conversion gain mode has been selected, act 2511 turns off the reset transistor and the second conversion gain transistor, but closes the first conversion gain transistor. If the 2C mode has not been selected, act 2513 turns off all of the reset transistors and all of the conversion gain transistors.

[0089] Figure 26 is a flowchart of a method 2600 for performing a read operation on an image sensor having a four-pixel structure according to embodiments of the present disclosure. Act 2601 decides to initiate a read operation. The determination can be made based on a clock. Act 2603 is determining whether the 1C mode has been selected. If the 1C mode has been selected, act 2605 sequentially operates each row driver of the photodetector array. If the 1C mode has not been selected, act 2607 sequentially operates each other row driver of the photodetector array. In either case, the method continues with act 2609. Act 2609 determines whether the 4C mode has been selected. If the 4C mode has not been selected, act 2613 operates each column decoder of the photodetector array. If the 4C mode has been selected, act 2611 operates only each other column decoder of the photodetector array.

[0090] Figure 27is a flowchart of a method 2700 for performing a read operation on an image sensor having a four-pixel configuration according to another embodiment of the disclosure. The method 2700 includes many of the same steps as the method 2600. Figure 26 But in the method 2700, the action 2613 of operating each column decoder is performed in each case, and the action 2609 of determining whether the 4C mode is selected can be performed after the action 2613. In the method 2700, if the 4C mode is not selected, the action 2703 outputs data from each column decoder in a conventional manner. If the 4C mode is selected, the action 2701 outputs an average of the values produced by each pair of column decoders.

[0091] Some aspects of the disclosure relate to an image sensor comprising photodiodes in a first array within a first semiconductor substrate, a four-pixel circuit, and a bridge circuit. The four-pixel circuit comprises four photodiodes in a two-by-two subarray, further comprising four pass transistors, four floating diffusion regions, and four source followers. The bridge circuit selectively couples the four floating diffusion regions. In some embodiments, the four-pixel circuit further comprises four multi- conversion gain circuits. In some embodiments, the four multi-conversion gain circuits each comprise a respective LOFIC. In some embodiments, each of the four multi-conversion gain circuits comprises two transistors connected in series between a respective LOFIC and a respective floating diffusion region. In some embodiments, the image sensor further comprises an integrated circuit that generates control signals that selectively operate the two transistors in series to independently determine a low, medium, or high conversion gain mode. In some embodiments, the image sensor further comprises an integrated circuit, wherein the integrated circuit generates a first control signal that operates the bridge circuit to connect a group that selectively includes one, two, or four of the four floating diffusion regions, and a second control signal that selectively operates the four multi-conversion gain circuits to independently determine a conversion gain mode.

[0092] In some embodiments, the image sensor further comprises an integrated circuit that generates control signals that operate the bridge circuit to connect a group that selectively includes one, two, or four of the four floating diffusion regions. In some embodiments, the image sensor further comprises two column decoders, two wiring structures, and an integrated circuit. Each wiring structure connects two of the four source followers to one of the two column decoders. When the bridge circuit couples the four floating diffusion regions, the outputs of the two column decoders are averaged.

[0093] In some embodiments, the image sensor further comprises two column decoders, two wiring structures, and an integrated circuit. Each wiring structure connects two of the four source followers to one of the two column decoders. When the bridge circuit couples the four floating diffusion regions, the integrated circuit disables one of the two column decoders.

[0094] In some embodiments, the four source followers and the bridge circuit are located on the first semiconductor substrate. In some embodiments, the four source followers and the bridge circuit are located on the second semiconductor substrate, and the second semiconductor substrate is attached to the first semiconductor substrate. In some embodiments, the image sensor further includes a row driver and a column decoder located on the second semiconductor substrate. In some embodiments, the image sensor further includes a through-substrate via in the second semiconductor substrate and a third semiconductor substrate, wherein the third semiconductor substrate includes an integrated circuit. The through-substrate via connects the integrated circuit to the column decoder. In some embodiments, the image sensor further includes color filters located in a second array, wherein the second array has a quarter of the number density of the first array, such that each color filter has four photodiodes. In some embodiments, the four-pixel circuit further includes four double conversion gain circuits.

[0095] Some aspects of the present disclosure relate to an image sensor including a semiconductor substrate, first, second, third, and fourth photodetectors, and first, second, and third switching transistors. The first through fourth photodetectors include first through fourth photodiodes, first through fourth transfer gates, and first through fourth floating diffusion nodes, respectively. The first transistor has a pair of source / drain regions electrically coupled to the first and second floating diffusion nodes, respectively. The second transistor has a pair of source / drain regions electrically coupled to the third and fourth floating diffusion nodes, respectively. The third transistor has a pair of source / drain regions electrically coupled to the first and third floating diffusion nodes, respectively. In some embodiments, the image sensor further includes a fourth transistor having a pair of source / drain regions electrically coupled to the second and fourth floating diffusion nodes, respectively. In some embodiments, the image sensor further includes first through fourth source followers having first through fourth gate electrodes, respectively, wherein the first through fourth floating diffusion nodes are coupled to the first through fourth gate electrodes, respectively. The image sensor further includes a column decoder. A wiring structure connects source regions of the first through fourth source followers to the column decoder.

[0096] Some aspects of the present disclosure relate to an image sensor comprising a first chip, four photodetector pixel circuits, the first chip comprising a first semiconductor substrate, each photodetector pixel circuit comprising a photodiode, a transfer gate, a floating diffusion node, a source follower, a multiple conversion gain transistor, and a lateral overflow integration capacitor (LOFIC). The photodiode is located in the first semiconductor substrate. The photodiodes of the four photodetector pixel circuits are located under a color filter. The image sensor further comprises a bridge circuit selectively coupling the four floating diffusion nodes. In some embodiments, the image sensor further comprises a second chip attached to the first chip, wherein the second chip comprises a second semiconductor substrate, the LOFIC is located in the second chip, and the source follower is located in the first chip.

[0097] In some embodiments, the image sensor further comprises a second chip and a third chip, the second chip comprising a second semiconductor substrate, the third chip comprising a third semiconductor substrate. The second chip is attached to the first chip, and the third chip is attached to the second chip. The source follower is located in the second chip. In some embodiments, the LOFIC is located in the third chip. In some embodiments, the LOFIC is located in the first chip.

[0098] The foregoing summarizes features of several embodiments in order that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily apply the present disclosure as a basis for the design or modification of other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments set forth herein. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. An image sensor comprising: a photodiode in a first array within a first semiconductor substrate; a quad pixel circuit, wherein the quad pixel circuit includes four of the photodiodes in a two-by-two subarray, further includes four pass gates, four floating diffusion regions, and four source followers; and a bridge circuit selectively coupling the four floating diffusion regions.

2. The image sensor of claim 1, wherein, the quad pixel circuit further includes four multiple conversion gain circuits.

3. The image sensor of claim 2, wherein, the four multiple conversion gain circuits each include a four lateral overflow integration capacitor.

4. The image sensor of claim 3, wherein, each of the four multiple conversion gain circuits includes two transistors connected in series between a respective one of the lateral overflow integration capacitors and a respective one of the floating diffusion regions.

5. The image sensor of claim 3, further comprising an integrated circuit, wherein, the integrated circuit generates a first control signal that operates the bridge circuit to connect a group that selectively includes one, two, or four of the four floating diffusion regions, and a second control signal that selectively operates the four multiple conversion gain circuits to independently determine a conversion gain mode.

6. The image sensor of claim 1, further comprising: two column decoders; two wiring structures, wherein each of the wiring structures connects two of the four source followers to one of the two column decoders; and an integrated circuit that averages outputs of the two column decoders when the bridge circuit couples the four floating diffusion regions.

7. The image sensor of claim 1, further comprising: two column decoders; two wiring structures, wherein each of the wiring structures connects two of the four source followers to one of the two column decoders; and an integrated circuit that disables one of the two column decoders when the bridge circuit couples the four floating diffusion regions.

8. An image sensor comprising: a semiconductor substrate; a first photodetector including a first photodiode, a first pass gate, and a first floating diffusion node in the semiconductor substrate; a second photodetector including a second photodiode, a second pass gate, and a second floating diffusion node in the semiconductor substrate; a third photodetector including a third photodiode, a third pass gate, and a third floating diffusion node in the semiconductor substrate; a fourth photodetector including a fourth photodiode, a fourth pass gate, and a fourth floating diffusion node in the semiconductor substrate; a first transistor having a pair of source / drain regions electrically coupled to the first and second floating diffusion nodes, respectively; a second transistor having a pair of source / drain regions electrically coupled to the third and fourth floating diffusion nodes, respectively; and a third transistor having a pair of source / drain regions electrically coupled to the first and third floating diffusion nodes, respectively.

9. The image sensor of claim 8, further comprising: a first source follower having a first gate electrode, wherein the first floating diffusion node is coupled to the first gate electrode; and a second source follower having a second gate electrode, wherein the second floating diffusion node is coupled to the second gate electrode. ​ ​ a second source follower having a second gate electrode, wherein the second floating diffusion node is coupled to the second gate electrode; a third source follower having a third gate electrode, wherein the third floating diffusion node is coupled to the third gate electrode; a fourth source follower having a fourth gate electrode, wherein the fourth floating diffusion node is coupled to the fourth gate electrode; and a column decoder, wherein a wiring structure connects source regions of the first source follower, the second source follower, the third source follower, and the fourth source follower to the column decoder.

10. An image sensor, comprising: a first chip comprising a first semiconductor substrate; four photodetector pixel circuits, each of the photodetector pixel circuits comprising a photodiode, a transfer gate, a floating diffusion node, a source follower, a multiple conversion gain transistor, and a lateral overflow integration capacitor, wherein the photodiode is located in the first semiconductor substrate; a color filter, wherein the photodiodes of the four photodetector pixel circuits are located under the color filter; and a bridge circuit selectively coupling the four floating diffusion nodes.

Images