Semiconductor structure, manufacturing method thereof and memory system

Abstract

The embodiment of the invention discloses a semiconductor structure, a manufacturing method thereof and a memory system. The semiconductor structure comprises an active column, wherein the active column comprises a first part and a second part which are arranged along a first direction; the gate structure extends along the second direction and covers at least one side wall of the first part; wherein the second direction is perpendicular to the first direction; the bit line structure extends in the third direction and covers at least one first sub-side wall, opposite to the second part in the third direction, of the second part; wherein the first sub-side wall is spaced from the side wall of the first part; the third direction intersects with the second direction and is perpendicular to the first direction.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and relate to, but are not limited to, a semiconductor structure and a manufacturing method thereof, and a memory system. BACKGROUND

[0002] In recent years, the semiconductor integrated circuit industry has experienced rapid growth, and the feature size of semiconductor devices continues to shrink, and the integration density of memories is also increasing, and the performance is also becoming more and more powerful. For example, dynamic random access memory (DRAM), static random access memory (SRAM) and NAND memory, etc. are commonly used semiconductor memory devices in computers.

[0003] Through improving the circuit design and manufacturing process, the planar storage unit is scaled to a smaller size. However, as the feature size of the storage unit approaches the lower limit, the planar process and manufacturing technology become challenging and costly. Therefore, how to further simplify the manufacturing process of the semiconductor structure in the memory and improve the electrical performance of the semiconductor structure has become a problem to be solved in the industry. SUMMARY

[0004] The present disclosure provides a semiconductor structure and a manufacturing method thereof, and a memory system.

[0005] In a first aspect, the present disclosure provides a semiconductor structure, comprising:

[0006] an active pillar, the active pillar comprising a first portion and a second portion arranged along a first direction;

[0007] a gate structure, the gate structure extending along a second direction and covering at least one sidewall of the first portion; wherein the second direction is perpendicular to the first direction;

[0008] a bit line structure, the bit line structure extending along a third direction and covering at least one first sub-sidewall of the second portion opposite along the third direction; wherein the first sub-sidewall is spaced apart from the sidewall of the first portion; the third direction intersects the second direction, and the third direction is perpendicular to the first direction.

[0009] In some embodiments, the bit line structure comprises:

[0010] a bit line contact, the bit line contact covering a surface of the second portion opposite to the first portion and at least one first sub-sidewall of the second portion opposite along the third direction;

[0011] a bit line, the bit line extending along the third direction and covering the bit line contact; wherein the bit line comprises a protrusion towards the active pillar, the protrusion covering at least the bit line contact on the first sub-sidewall.

[0012] In some embodiments, the bit line contact covers one of the first sub-sidewalls of the second portion opposite along the third direction; wherein the first sub-sidewall covered by the bit line contact is opposite along the third direction to the sidewall covered by the gate structure.

[0013] In some embodiments, the semiconductor structure comprises:

[0014] a plurality of the active pillars, the plurality of the active pillars arrayed along the second direction and the third direction;

[0015] a plurality of the bit line structures, the plurality of the bit line structures spaced along the second direction;

[0016] a first isolation structure, the first isolation structure comprising first isolation portions and second isolation portions alternately arranged along the third direction; the first isolation portions being between two active pillars adjacent along the second direction; the second isolation portions being between two protrusions adjacent along the second direction; wherein a dimension of the first isolation portion along the first direction is greater than a dimension of the second isolation portion along the first direction.

[0017] In some embodiments, the dimension of the first isolation portion along the first direction is equal to a sum of a dimension of the active pillar along the first direction and a dimension of the bit line structure covering a surface of the second portion opposite to the first portion along the first direction.

[0018] the dimension of the second isolation portion along the first direction is equal to a dimension of the bit line structure between two active pillars adjacent along the third direction along the first direction.

[0019] In some embodiments, the semiconductor structure further comprises:

[0020] a second isolation structure, the second isolation structure extending along the second direction and between the bit line structure and the gate structure; wherein the second isolation structure covers at least one second sub-sidewall of the second portion opposite along the third direction; the second sub-sidewall being between the first sub-sidewall and a sidewall of the first portion.

[0021] In some embodiments, the gate structure covers two sidewalls of the first portion opposite along the third direction; the second isolation structure covers two second sub-sidewalls of the second portion opposite along the third direction.

[0022] In some embodiments, the gate structure covers one of two sidewalls of the first portion opposite along the third direction, and the second isolation structure covers the second sub-sidewall of the second portion opposite close to the gate structure; the semiconductor structure further comprises:

[0023] a third isolation structure extending along the second direction and covering the other of the two sidewalls of the first portion opposite along the third direction and covering the second sub-sidewall of the second portion opposite away from the gate structure.

[0024] In some embodiments, the semiconductor structure further comprises: a capacitor structure located at a side of the first portion opposite away from the second portion.

[0025] In a second aspect, the present disclosure provides a manufacturing method of a semiconductor structure, the manufacturing method comprising:

[0026] forming an active pillar comprising a first portion and a second portion arranged along a first direction;

[0027] forming a gate structure extending along a second direction and covering at least one sidewall of the first portion; wherein the second direction is perpendicular to the first direction;

[0028] forming a bit line structure extending along a third direction and covering at least one first sub-sidewall of the second portion opposite along the third direction; wherein the first sub-sidewall is spaced apart from the sidewall of the first portion; the third direction intersects the second direction, and the third direction is perpendicular to the first direction.

[0029] In some embodiments, the forming a bit line structure extending along a third direction and covering at least one first sub-sidewall of the second portion opposite along the third direction comprises:

[0030] forming a bit line contact covering a surface of the second portion opposite away from the first portion and at least one of the first sub-sidewalls of the second portion opposite along the third direction;

[0031] forming a bit line extending along the third direction and covering the bit line contact; wherein the bit line comprises a protrusion towards the active pillar, the protrusion covering at least the bit line contact on the first sub-sidewall.

[0032] In some embodiments, the manufacturing method further comprises:

[0033] providing a substrate;

[0034] etching the substrate to form a plurality of first trenches spaced along the second direction, the first trenches extending along the third direction; wherein a dimension of the first trenches in the first direction is less than a dimension of the substrate in the first direction;

[0035] filling the plurality of first trenches to form a plurality of initial first isolation structures, respectively;

[0036] etching the substrate and the plurality of initial first isolation structures to form a plurality of second trenches spaced along the third direction, the plurality of first trenches and the plurality of second trenches dividing the substrate into a plurality of the active pillars arranged in an array along the second direction and the third direction; wherein the second trenches comprise first sub-trenches and second sub-trenches alternately arranged along the second direction; the first sub-trenchs are located between two adjacent active pillars along the third direction, a depth of the first sub-trenchs is equal to a depth of the first trenches and greater than a depth of the second sub-trenchs; the remaining initial first isolation structures constitute first isolation structures;

[0037] forming a sacrificial structure in the first sub-trenchs; a height of the sacrificial structure is less than or equal to a difference between the depth of the first sub-trenchs and the second sub-trenchs;

[0038] the forming the gate structure extending along the second direction and covering at least one sidewall of the first portion comprises:

[0039] forming the gate structure in the second trench with the sacrificial structure.

[0040] In some embodiments, the etching the substrate and the plurality of initial first isolation structures to form a plurality of second trenches spaced along the third direction comprises:

[0041] etching the substrate and the plurality of initial first isolation structures to form initial second trenches extending along the second direction; a depth of the initial second trenches is less than the depth of the first sub-trenchs;

[0042] etching the substrate exposed at a bottom of the initial second trenches to form the second trenches; wherein a depth of the substrate etched is equal to a difference between the depth of the first sub-trenchs and the initial second trenches.

[0043] In some embodiments, the manufacturing method further comprises:

[0044] removing the sacrificial structure to form a recess, the recess exposing the first sub-sidewall of the second portion;

[0045] forming a bit line structure extending along a third direction and covering at least one first sub-side wall of the second portion opposite along the third direction, comprises:

[0046] forming a bit line structure filling the recess and covering a surface of the second portion opposite away from the first portion.

[0047] In some embodiments, the manufacturing method further comprises:

[0048] thinning the substrate from a surface of the substrate opposite away from the first isolation structure until the sacrificial structure and the first isolation structure are exposed;

[0049] the removing the sacrificial structure, comprises:

[0050] removing the exposed sacrificial structure.

[0051] In some embodiments, the forming a bit line structure filling the recess and covering a surface of the second portion opposite away from the first portion, comprises:

[0052] etching the active pillar such that the surface of the second portion opposite away from the first portion is lower than a surface of the exposed first isolation structure and higher than a bottom surface of the recess;

[0053] forming a bit line material layer covering the recess, the first isolation structure and the active pillar;

[0054] removing part of the bit line material layer until the first isolation structure is exposed, the bit line material layer between two adjacent first isolation structures constituting the bit line structure.

[0055] In some embodiments, the method further comprises:

[0056] forming a second isolation structure extending along the second direction in the second trench formed with the sacrificial structure; wherein the second isolation structure covers at least one second sub-side wall of the second portion opposite along the third direction; the second sub-side wall is between the first sub-side wall and a sidewall of the first portion;

[0057] the forming a gate structure in the second trench formed with the sacrificial structure, comprises:

[0058] forming the gate structure in the second trench formed with the second isolation structure.

[0059] In some embodiments, the forming a second isolation structure extending along the second direction in the second trench formed with the sacrificial structure, comprises:

[0060] forming the second isolation structure in the second trench in which the second isolation structure is formed, comprises:

[0061] forming the second isolation structure in the second trench in which the second isolation structure is formed, comprises:

[0062] forming the second isolation structure in the second trench in which the second isolation structure is formed, comprises:

[0063] In some embodiments, forming the second isolation structure in the second trench in which the second isolation structure is formed, comprises:

[0064] forming the second isolation structure in one of the second trenches among the two adjacent second trenches; the second isolation structure covers one of the second sub-sides of the second portion of the active pillar between the two adjacent second trenches;

[0065] forming the second isolation structure in the second trench in which the second isolation structure is formed, comprises:

[0066] forming the second isolation structure in the second trench in which the second isolation structure is formed, comprises:

[0067] The manufacturing method further comprises:

[0068] forming a third isolation structure in another of the second trenches among the two adjacent second trenches; the third isolation structure covers another side of the first portion that is opposite to the side of the first portion that is close to the second isolation structure along the third direction, and covers another of the second sub-sides of the second portion that is opposite to the side of the second portion that is close to the second isolation structure along the third direction.

[0069] In a third aspect, the present disclosure provides a memory system, comprising: a memory, the memory comprising the semiconductor structure according to any one of the above embodiments; and a controller coupled to the memory; the controller is configured to control the memory.

[0070] In a third aspect, the present disclosure provides a memory system, comprising: a memory, the memory comprising the semiconductor structure according to any one of the above embodiments; and a controller coupled to the memory; the controller is configured to control the memory.

[0071] In the embodiments of the present disclosure, the active pillar includes a first portion and a second portion arranged along a first direction, the gate structure covers at least one sidewall of the first portion, and the bit line structure covers at least one first sub-sidewall of the second portion opposite along a third direction, and the first sub-sidewall is spaced from the sidewall of the first portion. That is, the bit line structure can cover at least one first sub-sidewall of the active pillar, thereby increasing the contact area of the bit line structure and the active pillar, reducing the contact resistance, and being beneficial to improving the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0072] Figures la to Id A process flow diagram of a semiconductor structure provided by the embodiments of the present disclosure is provided.

[0073] Figure 2 A schematic diagram of a semiconductor structure provided by the embodiments of the present disclosure is provided.

[0074] Figure 3 A schematic diagram of a bit line structure in a semiconductor structure provided by the embodiments of the present disclosure is provided.

[0075] Figure 4 A schematic diagram of another bit line structure in a semiconductor structure provided by the embodiments of the present disclosure is provided.

[0076] Figure 5 A schematic diagram of another semiconductor structure provided by the embodiments of the present disclosure is provided.

[0077] Figure 6 A schematic diagram of a gate structure and a second isolation structure in another semiconductor structure provided by the embodiments of the present disclosure is provided.

[0078] Figure 7 A schematic diagram of a gate structure, a second isolation structure and a third isolation structure in another semiconductor structure provided by the embodiments of the present disclosure is provided.

[0079] Figure 8 A step flow diagram of a manufacturing method of a semiconductor structure provided by the embodiments of the present disclosure is provided.

[0080] Figures 9a to 9k A structure schematic diagram of each step in a manufacturing method of a semiconductor structure provided by the embodiments of the present disclosure is provided.

[0081] Figure 10 A schematic diagram of forming a second isolation structure and a gate structure provided by the embodiments of the present disclosure is provided.

[0082] Figure 11 A schematic diagram of another forming a second isolation structure and a gate structure provided by the embodiments of the present disclosure is provided.

[0083] Figure 12A schematic diagram of forming a second isolation structure, a third isolation structure, and a gate structure is provided for embodiments of the present disclosure.

[0084] Figure 13 A schematic diagram of a memory system is provided for embodiments of the present disclosure. DETAILED DESCRIPTION

[0085] For the purpose of promoting an understanding of the principles of the present disclosure, reference will now be made to the embodiments illustrated in the drawings, which are described below. It will be appreciated that the present disclosure can be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided as examples of implementing the present disclosure so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0086] In the following description, numerous specific details are given to provide a thorough understanding of the present disclosure. However, it will be apparent that the present disclosure can be practiced without one or more of these specific details. In some embodiments, well-known structures and functions are not described in detail in order to avoid obscuring the concepts of the present disclosure.

[0087] Generally, the terminology can be understood at least in part from usage of the singular throughout the present disclosure. For example, as used herein, the terms "one or more" can describe any feature, structure, or characteristic in the singular or can describe combinations of features, structures, or characteristics, in the plural, depending at least in part on the context in which such terms are used. Similarly, as used herein, the terminology "a," "an," or "the" can be understood to convey a singular usage or to convey a plural usage, depending at least in part on the context in which such terms are used. Additionally, as used herein, the terminology "based on" can be understood as not necessarily being confined to only those factors that are explicitly enumerated, and can instead be understood to allow other factors to exist that are not explicitly enumerated, which can depend at least in part on the context in which the terminology is used.

[0088] Unless otherwise defined, the terms used herein are intended to be interpreted in their broadest, ordinary sense. The terms "a," "an," and "the" used herein are intended to be interpreted to include both singular and plural forms, unless otherwise indicated by the context. It will be further understood that the terms "comprises", "comprising", "includes", "including", "has", "having", "contains" and / or "containing", when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0089] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description in order to explain the technical solutions of the present disclosure. The preferred embodiments of the present disclosure are described in detail as follows, however, in addition to these detailed descriptions, the present disclosure can also have other implementations.

[0090] In some embodiments, the memory can include a memory cell array, and the memory cell array includes a plurality of arrayed memory cells, each of which can be composed of one memory node and one transistor. The memory in the present disclosure includes but is not limited to dynamic random access memory, static random access memory, ferroelectric random access memory (FRAM), magnetoresistive random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), nano random access memory (NRAM), etc. In the following, dynamic random access memory is taken as an example for illustration, and the memory node in the dynamic random access memory can be a capacitor, so that one transistor and one capacitor in the memory cell form a 1T1C (1 Transistor 1 Capacitor) structure.

[0091] Here and hereinafter, the first direction can be a direction perpendicular to the substrate surface, and the second direction and the third direction can be two directions parallel to the substrate surface. In some embodiments, the second direction intersects with the third direction, and the included angle between the two ranges from 0 to 90 degrees. In some embodiments, the second direction can be perpendicular to the third direction. In order to clearly describe the present disclosure, the following embodiments take the first direction as the Z direction in the drawing, the second direction as the X direction in the drawing, and the third direction as the Y direction in the drawing for example for illustration. However, it should be noted that the description of the direction in the following embodiments is only used to illustrate the present disclosure, and does not limit the scope of the present disclosure.

[0092] As shown in FIG. 1, a semiconductor structure 10 provided by the present disclosure includes a substrate 100, a first dielectric layer 200, a second dielectric layer 300, and a memory cell array 400. Figures la to Id As shown in FIG. 2, a manufacturing method of a semiconductor structure 10 provided by the present disclosure includes the following steps. Figures la to Id The manufacturing method at least includes the following steps:

[0093] As shown in FIG. 2, a manufacturing method of a semiconductor structure 10 provided by the present disclosure includes the following steps. Figure laAs shown, a plurality of first isolation structures 111 spaced apart and arranged along the X direction are formed from the first surface 100a of the substrate 100 (the first isolation structures may extend along the Y direction), and a plurality of word line structures 120 and a plurality of second isolation structures 122 alternately arranged along the Y direction are formed from the first surface 100a of the substrate 100. The word line structures 120 and the second isolation structures 122 extend along the X direction. The word line structures 120, the second isolation structures 122, and the first isolation structures 111 divide the substrate 100 into a plurality of active pillars 101 arrayed along the X and Y directions. The depths of the word line structures 120 and the second isolation structures 122 are both less than the depth of the first isolation structures 111. The word line structures 120 include at least a gate structure 121 that covers two opposite sidewalls of two adjacent active pillars 101 along the Y direction, and the gate structure 121 may extend along the X direction. Finally, a gate structure 121 is formed from the second surface 100a of the substrate 100. Figure la The substrate 100 is thinned (not shown because it has been removed) until the first isolation structure 111 is exposed. It should be noted that a capacitor structure 103, a capacitor contact 104, etc. may also be formed on the first surface 100a. The gate structure 121 may include a gate dielectric layer and a gate. The gates on the sidewalls of multiple active pillars 101 arranged along the X direction may be interconnected to form a word line (WL).

[0094] like Figure lb As shown, the substrate 100 located between the first isolation structures 111 is etched to form a plurality of bit line trenches 130, and the bit line trenches 130 and the first isolation structures 111 are arranged alternately along the X direction. The bit line trenches 130 can be used to form a bit line (BitLine, BL) structure. It should be noted that the bottom of the bit line trench 130 formed by etching needs to be as close to the active pillar 101 as possible to reduce the resistance between the subsequently formed bit line structure and the active pillar 101, thereby improving the electrical performance of the semiconductor structure. Therefore, the depth of the bit line trench 130 is large, and the amount of etching of the substrate 100 required to form the bit line trench 130 is large. In order to minimize the amount of etching of the substrate 100 during the formation of the bit line trench 130, the amount of etching of the substrate 100 can be increased. Figure la The etching depth of the word line structure 120 and the second isolation structure 122 formed in the steps shown increases the size of the active pillar 101 in the Z direction.

[0095] like Figure lc As shown, a bit line contact layer 132 is formed in the bit line trench 130. The bit line contact layer 132 can be formed by deposition, metal silicide treatment, etc. The bit line contact layer 132 can effectively reduce the contact resistance between the active pillar 101 and the subsequently formed bit line.

[0096] like Figure IdAs shown, the bit line 133 is formed in the bit line trench 130 with the bit line contact layer 132, and the bit line 133 and the bit line contact layer 132 together form a bit line structure 131. It can be understood that, since Figure lb In the step of forming the bit line trench 130, a large amount of etching of the substrate 100 is required, and the word line structure 120 and the second isolation structure 122 have a large depth, so the etching process is more demanding, increasing the difficulty of manufacturing the semiconductor structure. In addition, since the bit line structure 131 only covers one end surface of the active pillar 101 in the Z direction, the contact area between the bit line structure 131 and the active pillar 101 is small, and the resistance between them is large.

[0097] As shown, Figure 2 The present disclosure provides a semiconductor structure 20, comprising: an active pillar 201, the active pillar 201 comprising a first part 201a and a second part 201b arranged along a first direction; a gate structure 221, the gate structure 221 extending along a second direction and covering at least one sidewall of the first part 201a; wherein the second direction is perpendicular to the first direction; a bit line structure 231, the bit line structure 231 extending along a third direction and covering at least one first sub-sidewall sw1 of the second part 201b opposite along the third direction; wherein the first sub-sidewall sw1 is spaced apart from the sidewall of the first part 201a; the third direction intersects the second direction, and the third direction is perpendicular to the first direction.

[0098] In the embodiments of the present disclosure, the semiconductor structure 20 comprises at least one active pillar 201, which can be used to form a transistor in a 1T1C memory cell structure. The material of the active pillar 201 can include elemental semiconductor materials such as silicon (Si), germanium (Ge), etc., or compound semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc. The active pillar 201 can further comprise a doped region at both ends in the first direction (i.e., the Z direction), which can be formed by diffusion, ion implantation, etc. The active pillar 201 comprises a first part 201a and a second part 201b arranged along the first direction, wherein the first part 201a can be in contact with the gate structure 221, and the second part 201b can be in contact with the bit line structure 231. In some embodiments, the active pillar 201 can further connect to a capacitor structure 203 at an end away from the bit line structure 231 in the Z direction.

[0099] The gate structure 221 can extend along a second direction (i.e., the X direction), and the gate structure 221 covers at least one sidewall of the first portion 201a. The gate structure 221 can include a gate dielectric layer and a gate electrode. The gate electrodes on the sidewalls of the plurality of active pillars 201 arranged along the X direction can be connected to each other, thereby forming a word line. The gate dielectric layer includes, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), high-k material, etc. The gate electrode includes, but is not limited to, copper (Cu), tungsten (W), titanium nitride (TiN), etc.

[0100] The bit line structure 231 extends along a third direction (i.e., the Y direction), and the bit line structure 231 covers at least one first sub-sidewall sw1 of the second portion 201b along the Y direction. The first sub-sidewall sw1 is spaced apart from the sidewall of the first portion 201a, that is, the part of the bit line structure 231 covering the first sub-sidewall sw1 is spaced apart from the gate structure 221, thereby preventing leakage between the bit line structure 231 and the gate structure 221. Exemplarily, the sidewall of the second portion 201b can include the first sub-sidewall sw1 and a second sub-sidewall sw2. The second sub-sidewall sw2 is continuous with the first sub-sidewall sw1, and the second sub-sidewall sw2 is located between the first sub-sidewall sw1 and the sidewall of the first portion 201a. The bit line structure 231 only covers the first sub-sidewall sw1 and does not cover the second sub-sidewall sw2. The space between the bit line structure 231 and the gate structure 221 can be filled with an isolation material, which includes, but is not limited to, silicon oxide, spin-on dielectric, silicon nitride, silicon oxynitride, etc.

[0101] In this way, the bit line structure 231 can cover at least one first sub-sidewall sw1 of the active pillar 201, thereby increasing the contact area between the bit line structure 231 and the active pillar 201, reducing the contact resistance, and being beneficial to improving the electrical performance of the semiconductor structure. It should be noted that, Figure 2 Exemplarily, only the case where the bit line structure 231 covers two first sub-sidewalls sw1 of the active pillar 201 is shown, and the bit line structure 231 can cover one first sub-sidewall sw1 of the active pillar 201 in an actual product. In some embodiments, the bit line structure 231 can not cover the top surface of the active pillar 201 in the Z direction.

[0102] In some embodiments, as Figure 3As shown, the bit line structure 231 includes: a bit line contact 232 covering a surface of the second portion 201b opposite to the first portion 201a and at least one first sub-side wall sw1 of the second portion 201b opposite in the third direction; and a bit line 233 extending in the third direction and covering the bit line contact 232; wherein the bit line 233 includes a protrusion 234 towards the active pillar 201, and the protrusion 234 covers at least the bit line contact 232 on the first sub-side wall sw1.

[0103] In the embodiments of the present disclosure, the bit line structure 231 includes the bit line contact 232 and the bit line 233. The bit line contact 232 can be formed by deposition, metal silicidation process, etc., and can effectively reduce the contact resistance between the active pillar 201 and the bit line 233. The bit line 233 can be formed by depositing a conductive material, which includes but is not limited to copper, tungsten, titanium nitride, etc. The bit line contact 232 can cover a surface of the second portion 201b opposite to the first portion 201a, i.e., the bit line contact 232 covers the top surface of the active pillar 201 in the Z direction, and the bit line contact 232 can also cover at least one first sub-side wall sw1 of the second portion 201b opposite in the Y direction, thereby increasing the contact area of the bit line structure 231 and the active pillar 201, reducing the contact resistance, and improving the electrical performance of the semiconductor structure 20. It should be noted that Figure 3 In the embodiments of the present disclosure, the bit line contact 232 covers two first sub-side walls sw1 of the active pillar 201, but in actual products, the bit line contact 232 can cover one first sub-side wall sw1 of the active pillar 201 (for example, the bit line contact 232 covers the first sub-side wall sw1 on the left side of the active pillar 201 in the Y direction, and the bit line contact 232 does not cover the first sub-side wall sw1 on the right side of the active pillar 201 in the Y direction). Figure 4 )。

[0104] The bit line 233 includes a protrusion 234 towards the active pillar 201, and the protrusion 234 can cover the bit line contact 232. The protrusion 234 and the part of the bit line 233 extending in the Y direction can be one whole and formed by the same conductive material. It can be understood that if the bit line contact 232 covers one first sub-side wall sw1 of the active pillar 201, the protrusion 234 is located on one side of the active pillar 201 in the Y direction (the side where the bit line contact 232 is located); if the bit line contact 232 covers two first sub-side walls sw1 of the active pillar 201, the protrusion 234 is located on both sides of the active pillar 201 in the Y direction. In this way, the protrusion 234 and the bit line contact 232 can effectively increase the contact area of the bit line structure 231 and the active pillar 201, thereby reducing the contact resistance.

[0105] In some embodiments, as Figure 4As shown, the bit line contact 232 covers one of the two first sub-sidewalls sw1 of the second portion 201b opposite in the third direction; wherein the first sub-sidewall sw1 covered by the bit line contact 232 is opposite to the sidewall covered by the gate structure 221 in the third direction.

[0106] In the embodiments of the present disclosure, if the bit line contact 232 only covers one of the two first sub-sidewalls sw1 of the second portion 201b of the active pillar 201 opposite in the Y direction, the first sub-sidewall sw1 covered by the bit line contact 232 is opposite to the sidewall covered by the gate structure 221 in the Y direction. In this way, the protrusion 234 covering the bit line contact 232 and the gate structure 221 are respectively located on the two sides of the active pillar 201 in the Y direction, which can effectively reduce the occurrence of the leakage problem compared to the protrusion 234 and the gate structure 221 being located on the same side of the active pillar 201 in the Y direction.

[0107] In some embodiments, as shown in Figure 5 The semiconductor structure 20 includes: a plurality of active pillars 201 arranged in the second direction and the third direction; a plurality of bit line structures 231 arranged in the second direction; a first isolation structure 211 including first isolation portions 211a and second isolation portions 211b arranged alternately in the third direction; the first isolation portion 211a is located between two active pillars 201 adjacent in the second direction; the second isolation portion 211b is located between two protrusions 234 adjacent in the second direction; wherein the size of the first isolation portion 211a in the first direction is greater than the size of the second isolation portion 211b in the first direction.

[0108] In the embodiments of the present disclosure, referring to Figure 5 The semiconductor structure 20 can include a plurality of active pillars 201 arranged in the X direction and the Y direction. Exemplarily, a plurality of initial first isolation structures arranged in the X direction can be formed in the substrate first, the initial first isolation structures extend in the Y direction; then the substrate and the initial first isolation structures are etched to form a plurality of gate trenches arranged in the Y direction, the gate trenches extend in the X direction, the depth of the gate trenches is less than the depth of the initial first isolation structures, the plurality of gate trenches and the plurality of initial first isolation structures divide the substrate into a plurality of active pillars 201; finally, the gate structures and other isolation structures are formed in the gate trenches.

[0109] Specifically, the first isolation structure 211 can include first isolation portions 211a and second isolation portions 211b arranged alternately along the Y direction. This is because the bottom of the gate trench can have a morphology with alternating depths along the X direction, and the protrusions 234 of the bit line structure 231 can be formed in the portion of the gate trench with a greater depth. The finally formed first isolation portion 211a is located between two active pillars 201 adjacent along the X direction, that is, the initial first isolation structure at the location of the first isolation portion 211a is not removed by etching; the second isolation portion 211b is located between two protrusions 234 adjacent along the X direction, that is, the portion of the initial first isolation structure at the location of the second isolation portion 211b is removed by etching to form the portion of the gate trench with a smaller depth. Therefore, the size of the first isolation portion 211a in the Z direction is greater than the size of the second isolation portion 211b in the Z direction. The second isolation portion 211b can be used to isolate two protrusions 234 adjacent along the X direction to prevent leakage and other problems of two bit lines adjacent along the X direction.

[0110] In some embodiments, the size of the first isolation portion 211a in the first direction is equal to the sum of the size of the active pillar 201 in the first direction and the size of the bit line structure 231 in the first direction covering the surface of the second portion away from the first portion; the size of the second isolation portion 211b in the first direction is equal to the size of the bit line structure 231 in the first direction between two active pillars 201 adjacent along the third direction.

[0111] In the embodiments of the present disclosure, with reference to Figure 5 The size h1 of the first isolation portion 211a in the Z direction can be equal to the size h2 of the active pillar 201 in the Z direction and the size h3 of the portion of the bit line structure 231 covering the top surface of the active pillar 201 in the Z direction, that is, the initial first isolation structure at the location of the first isolation portion 211a is not removed by etching in the process of etching the gate trench. The size h4 of the second isolation portion 211b in the Z direction is equal to the size h5 of the bit line structure 231 in the Z direction between two active pillars 201 adjacent along the Y direction, that is, the size h4 of the second isolation portion 211b in the Z direction is equal to the size h5 of the bit line structure 231 in the Z direction at the location of the protrusion 234, so that the second isolation portion 211b can effectively isolate two protrusions 234 adjacent along the X direction to prevent leakage and other problems of two bit lines adjacent along the X direction.

[0112] In some embodiments, as Figure 3As shown, the semiconductor structure 20 further includes: a second isolation structure 240 extending along the second direction and located between the bit line structure 231 and the gate structure 221; wherein the second isolation structure 240 covers at least one second sub-side wall sw2 opposite to the second portion 201b along the third direction; and the second sub-side wall sw2 is located between the first sub-side wall sw1 and the side wall of the first portion 201a.

[0113] In the embodiments of the present disclosure, in order to prevent the phenomenon of electric leakage between the protrusion 234 of the bit line structure 231 and the gate structure 221 located on the same side of the active pillar 201, the second isolation structure 240 can be arranged between the protrusion 234 and the gate structure 221, the second isolation structure 240 extends along the X direction, and the material of the second isolation structure 240 includes but is not limited to silicon oxide, spin-on dielectric, silicon nitride, silicon oxynitride, etc.

[0114] The second isolation structure 240 can cover at least one second sub-side wall sw2 opposite to the second portion 201b along the Y direction, the second sub-side wall sw2 is continuous with the first sub-side wall sw1, and the second sub-side wall sw2 is located between the first sub-side wall sw1 and the side wall of the first portion 201a, that is, the second isolation structure 240 is located between the protrusion 234 and the gate structure 221.

[0115] In some embodiments, as shown in FIG. 2B, the gate structure 221 covers two side walls opposite to the first portion 201a along the third direction; and the second isolation structure 240 covers two second sub-side walls sw2 opposite to the second portion 201b along the third direction. Figure 6

[0116] In the embodiments of the present disclosure, the gate structure 221 can cover two side walls opposite to the first portion 201a of the active pillar 201 along the Y direction, that is, one gate structure 221 is respectively covered on two side walls of the active pillar 201 (Double Gate structure). In this way, the second isolation structure 240 can cover two second sub-side walls sw2 opposite to the second portion 201b along the Y direction, thereby preventing the phenomenon of electric leakage between the two gate structures 221 respectively located on the two side walls of the active pillar 201 and the bit line structure 231 (the protrusion 234).

[0117] In some embodiments, as shown in FIG. 2B, the gate structure 221 covers two side walls opposite to the first portion 201a along the third direction; and the second isolation structure 240 covers two second sub-side walls sw2 opposite to the second portion 201b along the third direction. Figure 7 ​As shown, the gate structure 221 covers one of the two sidewalls of the first portion 201a opposite along the third direction, and the second isolation structure 240 covers the second sub-sidewall sw2 of the second portion 201b opposite close to the gate structure 221. The semiconductor structure 20 further comprises a third isolation structure 250 extending along the second direction and covering the other of the two sidewalls of the first portion 201a opposite along the third direction and covering the second sub-sidewall sw2 of the second portion 201b opposite away from the gate structure 221.

[0118] In the embodiments of the present disclosure, the gate structure 221 can cover one of the two sidewalls of the first portion 201a of the active pillar 201 opposite along the Y direction (single gate structure), and thus the second isolation structure 240 can cover the second sub-sidewall sw2 of the second portion 201b opposite close to the gate structure 221, i.e., the second isolation structure 240 is located between the gate structure 221 and the protrusion 234, preventing the phenomenon of current leakage between the gate structure 221 and the bit line structure 231.

[0119] The semiconductor structure 20 can further comprise a third isolation structure 250 extending along the X direction and covering the other of the two sidewalls of the first portion 201a opposite along the Y direction and covering the second sub-sidewall sw2 of the second portion 201b opposite away from the gate structure 221. Thus, the third isolation structure 250 can prevent the phenomenon of current leakage between the gate structure 221 covering one active pillar 201 and the adjacent other active pillar 201'. The material of the third isolation structure 250 includes but is not limited to silicon oxide, spin-on dielectric, silicon nitride, silicon oxynitride, etc., and the third isolation structure 250 can comprise an air gap.

[0120] In some embodiments, as Figure 2 As shown, the semiconductor structure 20 further comprises a capacitor structure 203 located on the side of the first portion 201a opposite away from the second portion 201b.

[0121] In the embodiments of the present disclosure, the semiconductor structure 20 can further comprise a capacitor structure 203, so as to form a storage unit together with the transistor composed of the active pillar 201 and the gate structure 221. That is, the capacitor structure 203 is located at one end of the active pillar 201 close to the first portion 201a in the Z direction, and the bit line structure 231 is located at the other end of the active pillar 201 close to the second portion 201b in the Z direction. Exemplarily, the capacitor structure 203 can be connected to the active pillar 201 through a capacitor contact 204. The capacitor structure 203 can comprise two electrodes and an insulating layer located between the two electrodes.

[0122] As shown in Figure 8 , the present disclosure provides a method for manufacturing a semiconductor structure, Figures 9a to 9k which is a schematic diagram of a structure corresponding to a process of the method for manufacturing a semiconductor structure 30, the method comprising the following steps:

[0123] Step S10, forming an active pillar comprising a first portion and a second portion arranged along a first direction;

[0124] Step S20, forming a gate structure extending along a second direction and covering at least one sidewall of the first portion; wherein the second direction is perpendicular to the first direction;

[0125] Step S30, forming a bit line structure extending along a third direction and covering at least one first sub-sidewall of the second portion opposite along the third direction; wherein the first sub-sidewall is spaced from the sidewall of the first portion; the third direction intersects the second direction, and the third direction is perpendicular to the first direction.

[0126] It should be understood that Figure 8 the steps shown in the above description are not exclusive, and other steps can be performed before, after or between any of the steps shown in the above description; Figure 8 each step shown in the above description can be adjusted in sequence according to actual needs.

[0127] In the embodiments of the present disclosure, referring to Figure 9c , an active pillar 301 can be formed in the substrate 300 by etching or other processes, and the active pillar 301 can include a first portion 301a and a second portion 301b arranged along the Z direction. The active pillar 301 can be used to form a transistor in a 1T1C structure of a memory cell. The material of the active pillar 301 can include elemental semiconductor materials such as silicon, germanium, etc., or compound semiconductor materials such as gallium nitride, gallium arsenide or indium phosphide, etc. The active pillar 301 can also include a doped region at both ends in the first direction (i.e. the Z direction), which can be formed by diffusion, ion implantation or other processes.

[0128] Referring to Figure 9e , a gate structure 321 extending along the X direction and covering at least one sidewall of the first portion 301a can be formed by deposition, etching or other processes. The gate structure 321 can include a gate dielectric layer and a gate electrode formed in sequence, the gate electrode can be a word line, and the gate dielectric layer can include but is not limited to silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant materials, etc., and the gate electrode can include but is not limited to copper, tungsten, titanium nitride, etc. For example, the gate dielectric layer covers at least one sidewall of the first portion 301a, which can be formed by deposition, thermal oxidation or other processes, and the gate electrode covers the gate dielectric layer.

[0129] Referring to 9k, the bit line structure 331 covering at least one first sub-side wall sw1 opposite to the second portion 301b in the Y direction can be formed by deposition, etching, chemical mechanical polishing (CMP), and the like. The first sub-side wall sw1 and the sidewall of the first portion 301a are spaced, that is, the part of the bit line structure 331 covering the first sub-side wall sw1 is spaced from the gate structure 321, thereby preventing leakage between the bit line structure 331 and the gate structure 321. Exemplarily, the space between the bit line structure 331 and the gate structure 321 can be filled with an isolation material, which includes but is not limited to silicon oxide, spin-on dielectric, silicon nitride, silicon oxynitride, and the like.

[0130] In this way, the bit line structure 331 can cover at least one first sub-side wall sw1 of the active pillar 301, thereby increasing the contact area between the bit line structure 331 and the active pillar 301, reducing the contact resistance, and being beneficial to improve the electrical performance of the semiconductor structure 30.

[0131] In some embodiments, the forming the bit line structure 331 covering at least one first sub-side wall sw1 opposite to the second portion 301b in the third direction includes: forming a bit line contact 332 covering the surface of the second portion 301b away from the first portion 301a and at least one first sub-side wall sw1 opposite to the second portion 301b in the third direction; and forming a bit line 333 extending in the third direction and covering the bit line contact 332; wherein the bit line 333 includes a protrusion 334 toward the active pillar 301, and the protrusion 334 covers at least the bit line contact 332 on the first sub-side wall sw1.

[0132] In the embodiments of the present disclosure, referring to Figure 9i The bit line contact 332 can be formed on at least one first sub-side wall sw1 opposite to the second portion 301b in the Y direction and the top surface of the second portion 301b by a metal silicidation process, deposition, and the like. The bit line contact 332 can effectively reduce the contact resistance between the active pillar 301 and the bit line. In some embodiments, an independent bit line contact 332 can be formed on each active pillar 301 in the plurality of active pillars. In other embodiments, one bit line contact 332 connected to the plurality of active pillars 301 can also be formed, that is, the bit line contact 332 can extend in the Y direction and be connected to the plurality of active pillars 301 in the Y direction.

[0133] Referring to Figure 9kA bit line 333 extending along the Y direction and covering the bit line contact 332 can be formed by deposition, etching, chemical mechanical polishing, etc. The bit line 333 includes a protrusion 334 facing the active pillar 301, and the protrusion 334 can cover the bit line contact 332. The protrusion 334 and the part of the bit line 333 extending along the Y direction can be formed integrally and synchronously by the same conductive material. It can be understood that if the bit line contact 332 covers a first sub-side wall sw1 of the active pillar 301, the protrusion 334 is located on one side of the active pillar 301 in the Y direction (the side where the bit line contact 332 is located); if the bit line contact 332 covers two first sub-side walls sw1 of the active pillar 301, the protrusion 334 is located on both sides of the active pillar 301 in the Y direction. In this way, the protrusion 334 and the bit line contact 332 can effectively increase the contact area of the bit line structure 331 and the active pillar 301, thereby reducing the contact resistance.

[0134] In some embodiments, referring to Figures 9a to 9e , the manufacturing method further includes:

[0135] providing a substrate;

[0136] etching the substrate to form a plurality of first trenches arranged at intervals along the second direction, the first trenches extending along the third direction; wherein the size of the first trenches in the first direction is smaller than the size of the substrate in the first direction;

[0137] filling the plurality of first trenches to form a plurality of initial first isolation structures, respectively;

[0138] etching the substrate and the plurality of initial first isolation structures to form a plurality of second trenches arranged at intervals along the third direction, the plurality of first trenches and the plurality of second trenches dividing the substrate into a plurality of active pillars arranged in an array along the second direction and the third direction; wherein the second trenches include first sub-trenches and second sub-trenches arranged alternately along the second direction; the first sub-trenches are located between two active pillars adjacent along the third direction, and the depth of the first sub-trenches is equal to the depth of the first trenches and greater than the depth of the second sub-trenches; the remaining initial first isolation structures constitute first isolation structures;

[0139] forming a sacrificial structure in the first sub-trench; the height of the sacrificial structure is less than or equal to the depth difference between the first sub-trench and the second sub-trench;

[0140] the forming of the gate structure extending along the second direction and covering at least one sidewall of the first part includes: forming the gate structure in the second trench with the sacrificial structure.

[0141] In the embodiments of the present disclosure, referring toFigure 9a A substrate 300 can be provided first, which can include elemental semiconductor materials such as silicon, germanium, etc., or compound semiconductor materials such as gallium nitride, gallium arsenide, or indium phosphide, etc. The substrate 300 can be used to form a plurality of active pillars.

[0142] With reference to the foregoing Figure 9a A plurality of first trenches 310t can be formed first on the first surface 300a of the substrate 300 by using photolithography and etching processes, which are spaced along the X direction and extend along the Y direction and are used to form first isolation structures, and the depth of the first trenches 310t in the Z direction is less than the thickness of the substrate 300 in the Z direction. Then, the first trenches 310t are filled with insulating materials by using deposition processes, etc., so as to form a plurality of initial first isolation structures 310, respectively. The insulating materials include but are not limited to silicon oxide, spin-on dielectric, silicon nitride, silicon oxynitride, etc.

[0143] With reference to the foregoing Figure 9c The substrate 300 and the initial first isolation structures 310 can be etched by using etching processes, so as to form a plurality of second trenches 320t which are spaced along the Y direction and extend along the X direction, and the plurality of first trenches 310t and the plurality of second trenches 320t divide the substrate 300 into a plurality of active pillars 301 which are arranged in an array along the X direction and the Y direction. The second trenches 320t include first sub-trenches 322t and second sub-trenches 323t which are alternately arranged along the X direction, the first sub-trenches 322t are located between two adjacent active pillars 301 along the Y direction, the depth of the first sub-trenches 322t is equal to the depth of the first trenches 310t and is greater than the depth of the second sub-trenches 323t, and the remaining initial first isolation structures 310 constitute first isolation structures 311. Illustratively, the second trenches 320t having a deep-shallow alternating profile along the X direction, i.e., the deeper first sub-trenches 322t and the shallower second sub-trenches 323t which are alternately arranged along the X direction, can be formed by means of step-by-step etching and by respectively controlling the etching rates of the substrate 300 and the initial first isolation structures 310, etc. The deeper first sub-trenches 322t can be used to form sacrificial structures subsequently, and the sacrificial structures can be used to form protruding portions of bit line structures, so as to increase the contact area of the bit line structures with the active pillars and reduce the resistance.

[0144] With reference to the foregoing Figure 9d The sacrificial structures 324 can be formed in the plurality of first sub-trenches 322t by using deposition processes, etc., and the height of the sacrificial structures 324 is less than or equal to the depth difference between the first sub-trenches 322t and the second sub-trenches 323t, that is, the top surface of the sacrificial structures 324 is lower than or flush with the bottom surface of the second sub-trenches 323t. The material of the sacrificial structures 324 includes but is not limited to carbon, silicon nitride, etc., and preferably, the material of the sacrificial structures 324 is silicon nitride.

[0145] Reference Figure 9e The gate structure 321 can be formed in the second trench 320t with the sacrificial structure 324 by deposition, thermal oxidation and etching processes, and the gate structure 321 covers at least one sidewall of the second trench 320t, that is, the gate structure 321 can be connected to multiple active pillars 301 in the X direction. In some embodiments, the gate structure 321 can cover one sidewall of the second trench 320t, that is, a single gate structure. In other embodiments, the gate structure 321 can cover two sidewalls of the second trench 320t, that is, a double gate structure. In other embodiments, the gate structure 321 can also surround all sidewalls of the first part 301a of the active pillar 301, that is, a gate all around (GAA) structure.

[0146] In some embodiments, referring to Figure 9b and Figure 9c The etching the substrate and the plurality of initial first isolation structures to form a plurality of second trenches spaced along the third direction comprises: etching the substrate and the plurality of initial first isolation structures to form an initial second trench extending along the second direction; the depth of the initial second trench is less than the depth of the first sub-trench; and etching the substrate exposed at the bottom of the initial second trench to form the second trench; wherein the etching depth of the exposed substrate is equal to the depth difference between the first sub-trench and the initial second trench.

[0147] In the embodiments of the present disclosure, referring to Figure 9b The second trench corresponding mask can be formed on the surface of the substrate 300 and the initial first isolation structure 310 first, and then the first etching process is used to etch the substrate 300 and the initial first isolation structure 310 synchronously to form the initial second trench 321t extending along the X direction, and the depth of the initial second trench 321t is less than the designed depth of the first sub-trench. It should be noted that the etching rate of the substrate 300 and the initial first isolation structure 310 in the first etching process is the same, so the bottom of the initial second trench 321t is flat. It can be understood that the second sub-trench 323t and the first isolation structure 311 can be formed in this step, and the second sub-trench 323t is located in the first isolation structure 311. The first sub-trench needs to continue to etch the substrate 300.

[0148] Reference Figure 9cThe second etching process continues to etch the substrate 300 exposed by the initial second trench 321t to form a second trench 320t, and the depth of the substrate 300 etched by the second etching process is equal to the depth difference between the first sub-trench 322t and the initial second trench 321t. Exemplarily, by controlling the etching selectivity ratio of different materials, the second etching process can only etch the substrate 300, and the etching of the initial first isolation structure 310 is negligible.

[0149] In some embodiments, referring to Figures 9e to 9g The manufacturing method further includes: thinning the substrate 300 from the surface of the substrate 300 opposite to the first isolation structure 311 until the sacrificial structure 324 and the first isolation structure 311 are exposed; and removing the sacrificial structure 324 includes: removing the exposed sacrificial structure 324.

[0150] In the embodiments of the present disclosure, referring to Figure 9e The substrate 300 can be thinned from the second surface 300b of the substrate 300 until the sacrificial structure 324 and the first isolation structure 311 are exposed by using wafer grinding, chemical mechanical polishing, or the like, and the second surface 300b can be a surface opposite to the first surface 300a of the substrate 300. Figure 9f A schematic view of the semiconductor structure after the substrate 300 is thinned from the second surface and the sacrificial structure 324 is removed (the second surface is not shown in Figure 9f It can be understood that the second surface here is another surface of the substrate 300 that is not etched to form the first isolation structure 311 and the gate structure 321, i.e., the surface opposite to the first isolation structure 311. It should be noted that Figure 9f The substrate 300 in Figure 9e The substrate 300 in Figure 9f The first surface 300a of the substrate 300 in faces downward. In some embodiments, the first surface 300a can also be bonded to another substrate (wafer), such as another substrate where the peripheral circuit is located.

[0151] Referring to Figure 9g The exposed sacrificial structure 324 after the substrate 300 is thinned can be removed by using etching or the like to form a recess 325, and the recess 325 can be used to form a protrusion of a bit line structure.

[0152] In some embodiments, referring to Figures 9g to 9k, the manufacturing method further comprises: removing the sacrificial structure 324 to form a recess 325, the recess 325 exposes the first sub-sidewall sw1 of the second part 301b; and the forming the bit line structure 331 extending along a third direction and covering at least one first sub-sidewall sw1 of the second part 301b opposite to the second part 301b along the third direction comprises: forming the bit line structure 331 filling the recess 325 and covering the surface of the second part 301b opposite to the first part 301a.

[0153] In the embodiments of the present disclosure, referring to Figure 9g The exposed sacrificial structure 324 after the thinning of the substrate 300 can be removed by etching or other processes to form a recess 325, which can be used to form a protrusion of the bit line structure. The recess 325 exposes at least one first sub-sidewall sw1 of the second part 301b of the active pillar 301 opposite along the Y direction.

[0154] Referring to Figure 9k The bit line structure 331 can be formed in the recess 325 and on the top surface of the second part 301b by using a metal silicide process, deposition or other processes. In this way, the bit line structure 331 fills the recess 325, i.e., the bit line structure 331 covers at least one first sub-sidewall sw1 of the second part 301b, and the bit line structure 331 covers the top surface of the second part 301b, thereby increasing the contact area between the bit line structure 331 and the active pillar 301, reducing the contact resistance therebetween, and facilitating the improvement of the electrical performance of the semiconductor structure.

[0155] In some embodiments, referring to Figures 9h to 9k The forming the bit line structure filling the recess and covering the surface of the second part opposite to the first part comprises: etching the active pillar so that the surface of the second part opposite to the first part is lower than the surface of the exposed first isolation structure and higher than the bottom surface of the recess; forming a bit line material layer covering the recess, the first isolation structure and the active pillar; and removing part of the bit line material layer until the first isolation structure is exposed, and the bit line material layer between two adjacent first isolation structures constitutes the bit line structure.

[0156] In the embodiments of the present disclosure, referring to Figure 9h After the sacrificial structure 324 is removed and the recess 325 is formed, the active pillar 301 can be etched so that the top surface of the second part 301b is lower than the top surface of the exposed first isolation structure 311 and higher than the bottom surface of the recess 325. In this way, a third trench 330t can be formed between any two adjacent first isolation structures 311, and the bit line structure subsequently formed in the third trench 330t can be self-aligned, thereby reducing the difficulty of the manufacturing process.

[0157] Reference is made to Figure 9i The bit line contact 332 can be formed on at least one of the first sub- side walls swl opposite to each other along the Y direction of the second portion 301b and the top surface of the second portion 301b by a metal silicidation process, deposition or the like. It is to be noted that the bit line contact 332 can be formed on one of the first sub-side walls swl opposite to each other along the Y direction of the second portion 301b or on both of the first sub-side walls swl opposite to each other along the Y direction of the second portion 301b. Exemplarily, reference is made to Figure 3 a schematic view of a semiconductor structure with the bit line contact formed on both of the first sub-side walls opposite to each other along the Y direction of the second portion; and Figure 4 a schematic view of a semiconductor structure with the bit line contact formed on one of the first sub-side walls opposite to each other along the Y direction of the second portion.

[0158] Reference is made to Figure 9j The conductive material layer 335 can be formed above the third trench 330t with the bit line contact 332 formed therein by deposition or the like. The conductive material layer 335 can include one or more layers, thereby forming a one or more layer structure of the bit line. Preferably, the conductive material layer 335 can include a titanium nitride layer covering the bit line contact 332 and a tungsten layer covering the titanium nitride layer. The conductive material layer 335 covers the recess 325, the first isolation structure 311 and the top surface of the second portion 301b of the active pillar 301. The conductive material layer 335 and the bit line contact 332 together constitute a bit line material layer.

[0159] Reference is made to Figure 9k The conductive material layer 335 can be removed by chemical mechanical polishing or the like until the top surface of the first isolation structure 311 is re-exposed. The conductive material layer 335 between two adjacent first isolation structures 311 constitutes a bit line 333. The bit line 333 and the bit line contact 332 together constitute a bit line structure 331, i.e. the self-alignment of the bit line structure 331 is achieved.

[0160] It can be understood that Figures 9a to 9k In the formation of the semiconductor structure 30, the substrate 300 is thinned from the second surface thereof and the sacrificial structure 324 is exposed (the sacrificial structure 324 can serve as a thinning stop layer or a CMP stop layer), so that a relatively large thickness of the substrate material can be removed in a relatively simple thinning process. Thus, the etching amount of the substrate 300 in the etching of the active pillar 301 to form the third trench 330t can be reduced, and the depth of the second trench 320t for forming the gate structure 321 can also be small, greatly reducing the difficulty of the etching process.

[0161] In some embodiments, reference is made toFigure 10 The method further includes: forming a second isolation structure 340 extending along the second direction in the second trench 320t in which the sacrificial structure 324 is formed; wherein the second isolation structure 340 covers at least one second sub-side wall sw2 of the second portion 301b opposite along the third direction; the second sub-side wall sw2 is between the first sub-side wall sw1 and a side wall of the first portion 301a; and the forming the gate structure 321 in the second trench 320t in which the sacrificial structure 324 is formed includes: forming the gate structure 321 in the second trench 320t in which the second isolation structure 340 is formed.

[0162] In the embodiments of the present disclosure, referring to Figure 10 After the sacrificial structure 324 is formed, the top surface of the sacrificial structure 324 can be flush with the top surface of the first isolation structure in the second trench 320t, so that the second isolation structure 340 extending along the X direction can be formed above the sacrificial structure 324 and the first isolation structure, and the second isolation structure 340 can cover at least one second sub-side wall sw2 of the second portion 301b opposite along the Y direction, the second sub-side wall sw2 is between the first sub-side wall sw1 and the side wall of the first portion 301a, that is, the second isolation structure 340 can be located between the sacrificial structure 324 (the protrusion for forming the bit line structure) and the subsequently formed gate structure. The material of the second isolation structure 340 includes but is not limited to silicon oxide, spin-on dielectric, silicon nitride, silicon oxynitride, etc.

[0163] Continuing to refer to Figure 10 The gate structure 321 can be formed in the second trench 320t in which the second isolation structure 340 is formed by using deposition, etching and other processes. It can be understood that the second isolation structure 340 can prevent the problem of electric leakage between the gate structure 321 and the protrusion for subsequently forming the bit line structure. It should be noted that Figure 10 Each gate structure 321 in the embodiment of the present disclosure only contacts one active pillar 301. One gate structure 321 (covering the side wall of one active pillar 301) can be formed in each second trench 320t, or two gate structures 321 (covering two side walls opposite to each other of two adjacent active pillars 301) can be formed.

[0164] In some embodiments, referring to Figure 11, the forming the second isolation structure 340 extending along the second direction in the second trench 320t formed with the sacrifice structure 324 includes: forming the second isolation structure 340 covering two second sub-side walls sw2 opposite to the second portion 301b along the third direction in two adjacent second trenches 320t; and the forming the gate structure 321 in the second trench 320t formed with the second isolation structure 340 includes: forming the gate structure 321 covering two side walls opposite to the first portion 301a along the third direction in two adjacent second trenches 320t.

[0165] In the embodiments of the present disclosure, referring to Figure 11 , the second isolation structure 340 covering two second sub-side walls sw2 opposite to the second portion 301b along the Y direction can be formed in two adjacent second trenches 320t by using a deposition process. Then the gate structure 321 covering two side walls opposite to the first portion 301a along the Y direction is formed in two adjacent second trenches 320t, that is, a double gate structure is formed. In this way, the second isolation structure 340 can cover two second sub-side walls sw2 opposite to the second portion 301b along the Y direction, thereby preventing the phenomenon of electric leakage between two gate structures 321 respectively located on two side walls of the active pillar 301 and the bit line structure (the bump).

[0166] In some embodiments, referring to Figure 12 , the forming the second isolation structure 340 extending along the second direction in the second trench 320t formed with the sacrifice structure 324 includes: forming the second isolation structure 340 in one of the two adjacent second trenches 320t; the second isolation structure 340 covers one of the second sub-side walls sw2 of the second portion 301b of the active pillar 301 between the two adjacent second trenches 320t; the forming the gate structure 321 in the second trench 320t formed with the second isolation structure 340 includes: forming the gate structure 321 on the second isolation structure 340; the gate structure 321 covers one side wall of the first portion 301a opposite to the second isolation structure 340; and the manufacturing method further includes: forming a third isolation structure 350 extending along the second direction in the other of the two adjacent second trenches 320t; the third isolation structure 350 covers another side wall of the first portion 301a opposite to the gate structure 321 along the third direction and covers another second sub-side wall sw2 of the second portion 301b opposite to the second isolation structure 340 along the third direction.

[0167] In embodiments of the present disclosure, referring to Figure 12 A second isolation structure 340 covering a second sub-sidewall sw2 of the second portion 301b can be formed in a second trench 320t, and a gate structure 321, i.e., a single gate structure, can be formed above the second isolation structure 340. In addition, a third isolation structure 350 can also be formed in the second trench 320t, and the third isolation structure 350 can be used to isolate the gate structure 321 from another active pillar 301'. The material of the third isolation structure 350 includes but is not limited to silicon oxide, spin-on dielectric, silicon nitride, silicon oxynitride, etc., and the third isolation structure 350 can include an air gap. It can be understood that the second isolation structure 340 is located between the gate structure 321 and the sacrificial structure 324 (a bump for forming a bit line structure later), preventing the phenomenon of leakage between the gate structure 321 and the bit line structure. The third isolation structure 350 can prevent the phenomenon of leakage between the gate structure 321 covering an active pillar 301 and an adjacent another active pillar 301'.

[0168] As shown in Figure 13 The present disclosure provides a memory system 400, including: a memory 401 including the semiconductor structure according to any one of the above embodiments; a controller 402 coupled to the memory 401; the controller 402 is configured to control the memory 401.

[0169] In embodiments of the present disclosure, the controller 402 is coupled to the memory 401 and is configured to control the memory 401 to perform read, write, etc. The memory 401 can include the semiconductor structure according to any one of the above embodiments, and the controller 402 can include a processor, a microcontroller, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.

[0170] It can be understood that in the semiconductor structure and memory system provided by the present disclosure, the bit line structure can cover at least one first sub-side wall of the active column, thereby increasing the contact area between the bit line structure and the active column, reducing the contact resistance, and being beneficial to improving the electrical performance of the semiconductor structure. In the manufacturing method of the semiconductor structure provided by the present disclosure, since thinning is performed from the second surface of the substrate and the sacrificial structure is exposed (the sacrificial structure can be used as a thinning stop layer or a CMP stop layer), a large thickness of substrate material can be removed during the thinning process with a relatively simple process. In this way, the amount of etching of the substrate during the process of etching the active column to form the third groove can be reduced, and the depth of the second groove used to form the gate structure can also be smaller, which greatly reduces the difficulty of the etching process.

[0171] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0172] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0173] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0174] The above description is merely an embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A semiconductor structure, characterized by, Comprising: an active pillar comprising a first portion and a second portion arranged along a first direction; a gate structure extending along a second direction and covering at least one sidewall of the first portion; wherein the second direction is perpendicular to the first direction; a bit line structure extending along a third direction and covering at least one first sub-sidewall of the second portion opposite along the third direction; wherein the first sub-sidewall is spaced from the sidewall of the first portion; the third direction intersects the second direction, and the third direction is perpendicular to the first direction.

2. The semiconductor structure of claim 1, wherein, The bit line structure comprises: a bit line contact covering a surface of the second portion opposite from the first portion and at least one first sub-sidewall of the second portion opposite along the third direction; a bit line extending along the third direction and covering the bit line contact; wherein the bit line comprises a protrusion towards the active pillar, the protrusion covering at least the bit line contact on the first sub-sidewall.

3. The semiconductor structure of claim 2, wherein, The bit line contact covers one of the first sub-sidewalls of the two first sub-sidewalls of the second portion opposite along the third direction; wherein the first sub-sidewall covered by the bit line contact is opposite from the sidewall covered by the gate structure along the third direction.

4. The semiconductor structure of claim 2, wherein, The semiconductor structure comprises: a plurality of the active pillars arranged in an array along the second direction and the third direction; a plurality of the bit line structures arranged in an array along the second direction; a first isolation structure comprising first isolation portions and second isolation portions arranged alternately along the third direction; the first isolation portions are between two active pillars adjacent along the second direction; the second isolation portions are between two protrusions adjacent along the second direction; wherein a dimension of the first isolation portion along the first direction is greater than a dimension of the second isolation portion along the first direction.

5. The semiconductor structure of claim 4, wherein: the dimension of the first isolation portion along the first direction is equal to a sum of a dimension of the active pillar along the first direction and a dimension of the bit line structure covering the surface of the second portion opposite from the first portion along the first direction; the dimension of the second isolation portion along the first direction is equal to a dimension of the bit line structure between two active pillars adjacent along the third direction along the first direction.

6. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a second isolation structure extending along the second direction and between the bit line structure and the gate structure; wherein the second isolation structure covers at least one second sub-sidewall of the second portion opposite along the third direction; the second sub-sidewall is between the first sub-sidewall and the sidewall of the first portion.

7. The semiconductor structure of claim 6, wherein, the gate structure covers two sidewalls of the first portion opposite along the third direction; the second isolation structure covers two second sub-sidewalls of the second portion opposite along the third direction.

8. The semiconductor structure of claim 6, wherein, The gate structure covers one of two sidewalls of the first portion opposite along the third direction, and the second isolation structure covers the second sub-sidewall of the second portion opposite close to the gate structure; The semiconductor structure further comprises: A third isolation structure extending along the second direction and covering the other of the two sidewalls of the first portion opposite along the third direction and covering the second sub-sidewall of the second portion opposite away from the gate structure.

9. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a capacitor structure located at the side of the first portion opposite away from the second portion.

10. A method of manufacturing a semiconductor structure, characterized by, The manufacturing method comprises: forming an active pillar comprising a first portion and a second portion arranged along a first direction; forming a gate structure extending along a second direction and covering at least one sidewall of the first portion; wherein the second direction is perpendicular to the first direction; forming a bit line structure extending along a third direction and covering at least one first sub-sidewall of the second portion opposite along the third direction; wherein the first sub-sidewall is spaced from the sidewall of the first portion; the third direction intersects the second direction, and the third direction is perpendicular to the first direction.

11. The manufacturing method according to claim 10, wherein The forming of the bit line structure extending along the third direction and covering at least one first sub-sidewall of the second portion opposite along the third direction comprises: forming a bit line contact covering a surface of the second portion opposite away from the first portion and at least one of the first sub-sidewalls of the second portion opposite along the third direction; forming a bit line extending along the third direction and covering the bit line contact; wherein the bit line comprises a protrusion towards the active pillar, and the protrusion covers at least the bit line contact on the first sub-sidewall.

12. The manufacturing method according to claim 10, wherein The manufacturing method further comprises: providing a substrate; etching the substrate to form a plurality of first grooves spaced along the second direction, the first grooves extending along the third direction; wherein a dimension of the first grooves in the first direction is smaller than a dimension of the substrate in the first direction; filling the plurality of first grooves to form a plurality of initial first isolation structures respectively; etching the substrate and the plurality of initial first isolation structures to form a plurality of second grooves spaced along the third direction, and the plurality of first grooves and the plurality of second grooves divide the substrate into a plurality of active pillars arranged in an array along the second direction and the third direction; wherein the second grooves comprise first sub-grooves and second sub-grooves alternately arranged along the second direction; the first sub-grooves are located between two adjacent active pillars along the third direction, and a depth of the first sub-grooves is equal to a depth of the first grooves and greater than a depth of the second sub-grooves; the remaining initial first isolation structures constitute first isolation structures; forming a sacrificial structure in the first sub-grooves; a height of the sacrificial structure is less than or equal to a difference between the depth of the first sub-grooves and the depth of the second sub-grooves; The forming of the gate structure extending along the second direction and covering at least one sidewall of the first portion comprises: forming the gate structure in the second trench formed with the sacrificial structure.

13. The manufacturing method according to claim 12, wherein The etching the substrate and the plurality of initial first isolation structures to form a plurality of second trenches spaced along the third direction comprises: etching the substrate and a plurality of the initial first isolation structures to form initial second trenches extending along the second direction; the initial second trenches have a depth less than a depth of the first sub-trenches; etching the substrate exposed at a bottom of the initial second trenches to form the second trenches; wherein the exposed substrate is etched to a depth equal to a difference between the depth of the first sub-trenches and the initial second trenches.

14. The manufacturing method according to claim 12, wherein The manufacturing method further comprises: removing the sacrificial structure to form a recess exposing the first sub-side wall of the second portion; The forming the bit line structure extending along the third direction and covering at least one first sub-side wall of the second portion opposite along the third direction comprises: forming a bit line structure filling the recess and covering a surface of the second portion opposite away from the first portion.

15. The manufacturing method according to claim 14, wherein The manufacturing method further comprises: thinning the substrate from a surface of the substrate opposite away from the first isolation structure until the sacrificial structure and the first isolation structure are exposed; The removing the sacrificial structure comprises: removing the exposed sacrificial structure.

16. The manufacturing method according to claim 15, wherein The forming the bit line structure filling the recess and covering a surface of the second portion opposite away from the first portion comprises: etching the active pillar such that the surface of the second portion opposite away from the first portion is lower than a surface of the exposed first isolation structure and higher than a bottom surface of the recess; forming a bit line material layer covering the recess, the first isolation structure, and the active pillar; removing part of the bit line material layer until the first isolation structure is exposed, the bit line material layer between two adjacent first isolation structures constituting the bit line structure.

17. The manufacturing method of claim 12, wherein, The method further comprises: forming a second isolation structure extending along the second direction in the second trench formed with the sacrificial structure; wherein the second isolation structure covers at least one second sub-side wall of the second portion opposite along the third direction; the second sub-side wall is between the first sub-side wall and a side wall of the first portion; The forming the gate structure in the second trench formed with the sacrificial structure comprises: forming the gate structure in the second trench formed with the second isolation structure.

18. The manufacturing method according to claim 17, wherein The forming the second isolation structure extending along the second direction in the second trench formed with the sacrificial structure comprises: forming the second isolation structure covering two second sub-side walls of the second portion opposite along the third direction in two adjacent second trenches; The forming the gate structure in the second trench formed with the second isolation structure comprises: forming the gate structure covering two side walls of the first portion opposite along the third direction in two adjacent second trenches.

19. The manufacturing method according to claim 17, wherein The forming the second isolation structure extending along the second direction in the second trench formed with the sacrificial structure comprises: forming the second isolation structure in one of the second trenches of the two adjacent second trenches; the second isolation structure covering one of the second sub-sidewalls of the second portion of the active pillar between the two adjacent second trenches; the forming the gate structure in the second trench with the second isolation structure formed therein comprises: forming the gate structure on the second isolation structure; the gate structure covering one sidewall of the first portion on a side relatively close to the second isolation structure; the manufacturing method further comprises: forming a third isolation structure extending along the second direction in the other of the second trenches of the two adjacent second trenches; the third isolation structure covering another sidewall of the first portion on a side relatively far away from the gate structure along the third direction and covering another of the second sub-sidewalls of the second portion on a side relatively far away from the second isolation structure along the third direction.

20. A memory system, comprising: comprises: a memory comprising the semiconductor structure according to any one of claims 1 to 9; a controller coupled to the memory; the controller is configured to control the memory.

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