Semiconductor device and preparation method thereof, three-dimensional memory and storage system

Abstract

The invention discloses a semiconductor device and a preparation method thereof, a three-dimensional memory and a storage system. The semiconductor device includes: a plurality of semiconductor pillars each extending in a first direction; the first dielectric layers are located between the adjacent semiconductor columns; the bit line is positioned on one side of the semiconductor column along the first direction; the second dielectric layer at least covers the surface, far away from the semiconductor column, of the bit line; the cover layer covers the second dielectric layer; and the first connecting structure penetrates through the cover layer and the second dielectric layer along the first direction and is connected with the bit line.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor technology, and particularly relate to a semiconductor device and a manufacturing method thereof, a three-dimensional memory and a storage system. BACKGROUND

[0002] Memory is a memory device used for saving information in modern information technology, and its main function is to store programs and various data, and can complete the access of programs or data automatically at high speed during the operation of a computer. Taking a semiconductor device DRAM (Dynamic Random Access Memory) as an example, the DRAM usually includes a plurality of memory cells, each memory cell including a transistor and a capacitor, the source of the transistor being connected with the capacitor, the drain of the transistor being connected with a bit line, and the bit line being led out through a connection structure.

[0003] At present, how to further reduce the process difficulty and increase the process window in the process of manufacturing a semiconductor device is one of the technical problems to be solved by those skilled in the art. SUMMARY

[0004] The semiconductor device and the manufacturing method thereof, the three-dimensional memory and the storage system provided by the embodiments of the present application can solve or partially solve the above-mentioned deficiencies in the prior art or other deficiencies in the prior art.

[0005] According to the semiconductor device provided by the first aspect of the present application, the semiconductor device comprises:

[0006] a plurality of semiconductor pillars, each extending along a first direction;

[0007] a first dielectric layer located between adjacent semiconductor pillars;

[0008] a bit line located on one side of the semiconductor pillars along the first direction;

[0009] a second dielectric layer covering at least a surface of the bit line away from the semiconductor pillars;

[0010] a cap layer covering the second dielectric layer; and

[0011] a first connection structure penetrating the cap layer and the second dielectric layer along the first direction and connected with the bit line.

[0012] According to the manufacturing method of the semiconductor device provided by the second aspect of the present application, the manufacturing method comprises:

[0013] forming an initial semiconductor structure including a first dielectric layer, a bit line and a plurality of initial semiconductor pillars extending along a first direction, the first dielectric layer being located between adjacent initial semiconductor pillars, the bit line being located at a side of the initial semiconductor pillars along the first direction;

[0014] forming a second dielectric layer at a side of the bit line away from the initial semiconductor pillars;

[0015] forming a cap layer covering a surface of the second dielectric layer;

[0016] forming a first connection hole penetrating through the cap layer along the first direction and stopping at the second dielectric layer;

[0017] removing part of the second dielectric layer through the first connection hole to expose the bit line; and

[0018] forming a first connection structure in the first connection hole.

[0019] According to the third aspect of the present application, a three-dimensional memory is provided, comprising a peripheral circuit and the semiconductor device according to the first aspect of the present application, and the semiconductor device is bonded to the peripheral circuit.

[0020] According to the fourth aspect of the present application, a storage system is provided, comprising a controller and the semiconductor device according to the first aspect of the present application, the controller is coupled to the semiconductor device and used to control the semiconductor device to store data.

[0021] The semiconductor device and the preparation method thereof, the three-dimensional memory and the storage system provided by the embodiments of the present application can form a second dielectric layer at a side of a bit line away from an initial semiconductor pillar, so that the second dielectric layer can be used as a stop layer, and a first connection hole is formed step by step with the second dielectric layer as a boundary, the first connection hole is first formed to penetrate through a cap layer and stop at the second dielectric layer, and then part of the second dielectric layer is removed through the first connection hole to further deepen the first connection hole to expose the bit line, so that the problem of over-etching or under-etching in the process of etching the first connection hole can be avoided, the process window is increased, and the process difficulty is reduced.

[0022] It should be understood that the content described in this section is not intended to identify key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent through the following description. BRIEF DESCRIPTION OF DRAWINGS

[0023] Other features, objects, and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments, read in conjunction with the accompanying drawings. The drawings are intended to be more of a schematic nature than a limiting nature. In the drawings:

[0024] Figures 1 to 28 is a process schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0025] Figure 29 is a flow schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present application; and

[0026] Figure 30 is a block diagram of a system with a semiconductor device according to an embodiment of the present application.

[0027] Reference signs:

[0028] 100, first dielectric layer; 101, first dielectric trench; 102, second dielectric trench;

[0029] 103, bit line dielectric trench; 110, first sub-dielectric layer; 120, second sub-dielectric layer;

[0030] 130, first sacrificial layer; 140, second sacrificial layer; 150, dielectric sacrificial layer;

[0031] 200, wafer; 201, first trench; 202, second trench; 203, third trench;

[0032] 204, first surface; 205, second surface; 210, semiconductor pillar;

[0033] 211, preliminary semiconductor pillar; 211-1, initial semiconductor pillar; 212, drain;

[0034] 213, channel; 214, source; 300, bit line; 310, metal layer;

[0035] 400, second dielectric layer; 410, first covering part; 420, second covering part;

[0036] 500, cap layer; 510, first part; 520, second part; 610, gate structure;

[0037] 611, gate layer; 611-1, first gate part; 611-2, second gate part;

[0038] 612, gate dielectric layer; 613, gate adhesive layer; 620, gate isolation layer;

[0039] 630, initial gate structure; 700, isolation structure; 710, isolation dielectric layer;

[0040] 720, isolation conductive layer; 810, first connection structure; 811, first connection hole;

[0041] 812, first connection dielectric layer; 813, first connection conductive layer;

[0042] 820, second connection structure; 821, second connection dielectric layer;

[0043] 822, second connection conductive layer; 830, gate cut structure; 840, mask layer;

[0044] 900, system; 901, memory system; 902, semiconductor device;

[0045] 903, memory controller; 904, host. DETAILED DESCRIPTION

[0046] For a better understanding of the present application, various aspects of the present application will be described in greater detail below with reference to the drawings. It is to be noted that these detailed descriptions are merely descriptive of exemplary embodiments of the present application and are not intended in any way to limit the scope of the present application. Throughout the specification, like drawing reference numerals refer to like elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0047] It should be noted that in this specification, the expressions first, second, third and the like are used to distinguish one feature from another feature only, and do not indicate any limitation on the features, especially do not indicate any sequential order.

[0048] In the drawings, the thickness, size, and shape of components have been slightly adjusted for ease of explanation. The drawings are merely examples and are not strictly drawn to scale. As used in this document, the terms "substantially", "approximately", and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in a measuring or computing process that would be recognized by those of ordinary skill in the art.

[0049] It should also be understood that expressions such as "include", "including", "have", "has", "contain" and / or "containing" and the like, are open-ended expressions that are used to specify the presence of stated features, elements, and / or components, but do not preclude the presence or addition of one or more other features, elements, components, and / or combinations of them. In addition, when expressions such as "at least one of" appear after a list of two or more items, it is meant that any of the listed items can be present, individually or in combination with one or more of the other listed items. Furthermore, when describing embodiments of the present application, the use of "may" means "one or more embodiments of the present application". Also, the term "exemplary" is intended to mean an example or an illustration.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0051] It should be noted that the embodiments and features of the embodiments in the present application can be combined with each other without conflict. In addition, unless explicitly limited or clearly contradicted by context, specific steps in the methods described herein can be performed in any order or simultaneously, unless explicitly limited or clearly contradicted by context. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0052] In addition, in the present application, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over the entirety of an underlying or overlying structure, or can have an area less than the area of the underlying or overlying structure. Further, a layer can be a region of a continuous structure that has a thickness less than the thickness of the continuous structure. The layer can extend horizontally, vertically, and / or along an inclined surface. A layer can include a plurality of sub-layers. In addition, where "connected" or "coupled" is used herein to refer to a relationship between or among multiple devices, it is meant that there is some level of contact between or among the devices, unless specifically stated otherwise or otherwise clear from the context.

[0053] Taking a semiconductor device DRAM as an example, a transistor of the DRAM usually includes a gate, a source, a drain and a channel. The source of the transistor is electrically connected with one of the electrode plates of a capacitor, the other electrode plate of the capacitor can be grounded or connected with a reference voltage, the drain of the transistor is electrically connected with a bit line (BL), and the gate of the transistor is electrically connected with a word line (WL). The word line is used to apply a voltage to control the conduction or cutoff of the transistor, the bit line is used to perform a read or write operation on the capacitor when the transistor is turned on, and the amount of charge stored in the capacitor represents whether a binary bit is 1 or 0. Among them, the bit line is led out through a first connecting structure, and the gate is led out through a second connecting structure. For a vertical transistor, the bit line is located on one side of the gate along a first direction, and the size of the first connecting structure along the first direction is smaller than the size of the second connecting structure along the first direction. In the process of forming the first connecting structure and the second connecting structure, if the first connecting hole corresponding to the first connecting structure and the second connecting hole corresponding to the second connecting structure are etched synchronously, then too much etching liquid is easy to cause over-etching of the first connecting hole and to etch through the bit line, and on the contrary, too little etching liquid is likely to cause insufficient etching of the second connecting hole and to fail to expose the gate, so that the second connecting structure formed in the second connecting hole in the subsequent process cannot be in contact with the gate. If the first connecting hole and the second connecting hole are etched separately, when the first connecting hole is etched, it is still difficult to control the etching amount and there is a risk of etching through the bit line.

[0054] Based on this, in order to solve at least part of the above problems, the embodiments of the present application provide a preparation method of a semiconductor device. Figure 29 The flowchart of the preparation method of the semiconductor device of one embodiment of the present application is shown; as Figure 29 shown, the preparation method 1000 includes:

[0055] S100, forming an initial semiconductor structure. In combination Figures 15 to 21 shown, the initial semiconductor structure includes a first dielectric layer 100, a bit line 300 and a plurality of initial semiconductor columns 211-1 extending along a first direction (z direction), the first dielectric layer 100 is located between adjacent initial semiconductor columns 211-1, and the bit line 300 is located on one side of the initial semiconductor column 211-1 along the first direction (z direction);

[0056] S200, forming a second dielectric layer 400 on the side of the bit line 300 away from the initial semiconductor column 211-1 (see Figure 22 );

[0057] S300, forming a cap layer 500 covering the surface of the second dielectric layer 400 (see Figure 23 );

[0058] S400, forming a first connection hole 811 (see Figure 24 ) through the cap layer 500 in the first direction (z direction) and stopping at the second dielectric layer 400;

[0059] S500, removing part of the second dielectric layer 400 through the first connection hole 811 to expose the bit line 300;

[0060] S600, forming a first connection structure 810 in the first connection hole 811 (see Figure 25 and Figure 26 ).

[0061] As can be seen from the above, by forming the second dielectric layer 400 on the side of the bit line 300 away from the initial semiconductor pillar 211-1, the second dielectric layer 400 can be used as a stop layer, and the first connection hole 811 is formed in steps with the second dielectric layer 400 as the boundary, first connection hole 811 is formed through the cap layer 500 and stops at the second dielectric layer 400, and then part of the second dielectric layer 400 is removed through the first connection hole 811 to further deepen the first connection hole 811 to expose the bit line 300, thereby avoiding the problem of over-etching or under-etching in the process of etching the first connection hole 811, increasing the process window and reducing the process difficulty.

[0062] The steps in the semiconductor device preparation method of the embodiments of the present application will be described in detail below.

[0063] Step S100

[0064] As shown in Figures 1 to 21 , in step S100, an initial semiconductor structure is formed, which includes a first dielectric layer 100, a bit line 300 and a plurality of initial semiconductor pillars 211-1 extending in the first direction, the first dielectric layer 100 is located between adjacent initial semiconductor pillars 211-1, and the bit line 300 is located on one side of the initial semiconductor pillar 211-1 in the first direction (z direction). Wherein, the initial semiconductor pillar 211-1 can include a drain 212.

[0065] In some embodiments, the initial semiconductor structure can be formed based on a wafer 200, and the material of the wafer 200 can be any suitable semiconductor material, for example, it can be a single-element semiconductor material such as silicon (Si) or germanium (Ge), or a composite semiconductor material such as silicon germanium (SiGe), silicon on insulator (SOI) or germanium on insulator (GeOI). As an example, the wafer 200 has a first surface 204 and a second surface 205 arranged back to back in the first direction (z direction).

[0066] Figure 1 is a top view schematic diagram of a wafer with a first sub-dielectric layer formed in the embodiments of the present application,Figure 2 In the implementation mode of this application Figure 1 The cross-sectional view at AA, Figure 3 : is a schematic top view of a wafer having a second trench and a third trench formed thereon in an embodiment of the present application. Figure 4 In the embodiment of this application Figure 3 The cross-sectional view at AA, Figure 5 : is a schematic top view of a wafer having initial semiconductor columns formed thereon in an embodiment of the present application. Figure 6 In the embodiment of this application Figure 5 The cross-sectional view at AA, Figure 9 : is a schematic top view of a wafer having a gate structure and an isolation structure formed thereon in an embodiment of the present application. Figure 10 In the embodiment of this application Figure 9 Schematic cross-sectional view at AA.

[0067] The initial semiconductor structure can be formed by: Figure 1 and Figure 2 As shown, a plurality of first trenches 201 are formed in the wafer 200 from the first surface 204 thereof, spaced apart along the third direction (x direction) and extending along the second direction (y direction); a first dielectric material is filled in the first trenches 201 to form a first sub-dielectric layer 110; wherein the first dielectric layer 100 includes the first sub-dielectric layer 110, and the first dielectric material may include, but is not limited to, silicon nitride, silicon oxynitride, silicon carbide, or silicon dioxide. Figure 3 and Figure 4 As shown, a plurality of second grooves 202 and third grooves 203 are formed in the wafer 200 from the first surface 204 of the wafer 200, which are alternately distributed along the second direction (y direction) and extend along the third direction (x direction), so as to divide part of the wafer 200 into a plurality of prepared semiconductor pillars 211. The first groove 201, the second groove 202 and the third groove 203 can all be formed in the wafer 200 by an etching process, and the etching depth of the first groove 201, the second groove 202 and the third groove 203 along the first direction (z direction) can be less than the thickness of the wafer 200. The above-mentioned etching process includes but is not limited to a wet etching process, a dry etching process such as a plasma etching process or a reactive ion etching process, or a combination of any of the above processes. The projection shape of the prepared semiconductor pillar 211 on the plane perpendicular to the first direction (z direction) can be, but is not limited to, a semicircular, circular, rectangular, triangular or any other shape. As shown in FIG. Figure 9 and Figure 10 As shown, a gate structure 610 is formed in the second trench 202; an isolation structure 700 is formed in the third trench 203, and the gate structure 610 and the isolation structure 700 are spaced apart along the second direction (y direction); Figure 5 andFigure 6 As shown, an initial semiconductor pillar 211-1 is formed based on the preliminary semiconductor pillar 211, the initial semiconductor pillar 211-1 includes the drain 212; as shown, a bit line 300 is formed based on the drain 212. In the foregoing, the first direction, the second direction and the third direction are perpendicular to each other. As an example, the first direction can be the thickness direction of the wafer 200, the first direction, the second direction and the third direction are perpendicular to each other. Figure 21

[0068] In some embodiments, the gate structure 610 can be formed in the second trench 202 by forming an initial gate structure 630 covering the inner wall of the second trench 202 in the second trench 202, for example, the initial gate structure 630 includes the gate dielectric layer 612 and the gate layer 611. When forming the initial gate structure 630, the gate dielectric layer 612 can be formed first on the inner wall of the second trench 202, which can be formed by in-situ oxidation of the inner wall of the second trench 202, or by a thin film deposition process. Among them, the material of the gate dielectric layer 612 can include but is not limited to silicon oxide, silicon oxynitride, silicon nitride or high-K materials such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide; then the gate layer 611 is formed on the surface of the gate dielectric layer 612, the material of the gate layer 611 can include but is not limited to polysilicon, conductive metal or conductive alloy, for example, the material of the gate layer 611 can include polysilicon, tungsten, aluminum, titanium, copper, cobalt, tungsten nitride or a combination of any of the above. In addition, in order to improve the adhesion between the gate layer 611 and the gate dielectric layer 612, a gate adhesion layer 613 can also be formed on the surface of the gate dielectric layer 612 before forming the gate layer 611, in other words, the gate adhesion layer 613 is located between the gate layer 611 and the gate dielectric layer 612. Among them, the material of the gate adhesion layer 613 can include but is not limited to at least one of titanium nitride, tantalum nitride, tungsten carbide. As shown, Figure 13 Figure 16 As shown, the initial gate structure 630 is divided into two gate structures 610 arranged opposite to each other along the second direction (y direction). In the foregoing, the gate adhesion layer 613 and the gate layer 611 can be formed by a thin film deposition process. Among them, the thin film deposition process can be but not limited to a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process or a combination of any of the above processes.

[0069] ​​In some embodiments, the initial gate structure 630 can be divided as follows: After forming the initial gate structure 630, the portion of the initial gate structure 630 covering the bottom surface of the second trench 202 can be removed by punching. The remaining initial gate structure 630 covers the sidewalls of the second trench 202 extending along the first direction (z-direction) and has a circular shape. Gate cutout structures 830 are formed at both ends of the initial gate structure 630 along the third direction (x-direction). The gate cutout structures 830 penetrate the initial gate structure 630 along the first direction (z-direction). As a result, the initial gate structure 630 is divided by the two gate cutout structures 830 into two gate structures 610 disposed opposite each other along the second direction (y-direction). Subsequently, a gate isolation layer 620 can be formed in the remaining space of the second trench 202. The gate isolation layer 620 is located between the two gate structures 610 along the second direction (y-direction).

[0070] In other embodiments, Figure 9 and Figure 10 As shown, the gate isolation layer 620 may be formed before the initial gate structure 630 is divided. In other words, the gate isolation layer 620 is formed in the gap formed by the initial gate structure 630 before the initial gate structure 630 is divided. Figure 11 : is a schematic top view of a wafer having a first dielectric groove formed therein in an embodiment of the present application. Figure 12 In the embodiment of this application Figure 11 The cross-sectional view at AA, Figure 14 : is a schematic top view of a wafer having a second sub-dielectric layer formed thereon in an embodiment of the present application, Figure 15 In the embodiment of this application Figure 14 The cross-sectional view at AA, Figure 16 In the embodiment of this application Figure 14 Schematic cross-sectional view at BB. As an example, the depth of the first trench 201 along the first direction (z direction) is greater than the depth of the second trench 202 and the third trench 203 along the first direction (z direction). In this case, the initial gate structure 630 can also be divided into two gate structures 610 in the following manner: thinning the wafer 200 from the second surface 205 to expose the first sub-dielectric layer 110; Figure 11 and Figure 12 As shown, a portion of the first sub-dielectric layer 110 is removed to form a first dielectric trench 101 exposing a portion of the initial gate structure 630. Figure 7 As shown, the first sub-dielectric layer 110 is formed in the first trench 201, and a plurality of first trenches 201 are spaced apart along the third direction (x direction) and extend along the second direction (y direction). Figure 11 and Figure 12As shown, the first dielectric trenches 101 formed after removing the portion of the first sub-dielectric layer 110 in the first trenches 201 also extend along the second direction (y direction), and the plurality of first dielectric trenches 101 are spaced apart along the third direction (x direction), so that a plurality of different portions of the initial gate structure 630 are exposed in the plurality of first dielectric trenches 101 distributed along the third direction (x direction). As shown, Figure 13 As shown, the second dielectric trenches 102 extending along the third direction (x direction) are formed by removing the exposed portion of the initial gate structure 630 through the first dielectric trenches 101. As shown, Figures 14 to 16 As shown, the second dielectric material is filled in the second dielectric trenches 102 and the portion of the first dielectric trenches 101 to form the second sub-dielectric layer 120. The first dielectric layer 100 includes the first sub-dielectric layer 110 and the second sub-dielectric layer 120, and the materials of the first sub-dielectric layer 110 and the second sub-dielectric layer 120 can be the same or different, which is not limited in the present application. The gate cut structure 830 is formed at both ends of the initial gate structure 630 along the third direction (x direction), and the gate cut structure 830 penetrates the initial gate structure 630 along the first direction (z direction). Thus, the initial gate structure 630 is divided into two gate structures 610 arranged opposite to each other along the second direction (y direction) by the two gate cut structures 830.

[0071] In some embodiments, the wafer 200 includes a first region (not shown) and a second region (not shown) located at least one side of the first region along the third direction (x direction). As shown, Figure 17 As shown, the mask layer 840 can be formed on the side of the wafer 200 away from the first surface 204 when forming the first dielectric trenches 101, and the mask layer 840 defines a plurality of patterns of the first dielectric trenches 101, which correspond one-to-one to the plurality of first trenches 201 located in the first region. Thus, the portion of the first dielectric layer 100 located in the first region can be removed by using the patterned mask layer 840, while the portion of the first dielectric layer 100 located in the second region is not removed. Since the first dielectric trenches 101 are not formed in the second region, when the exposed initial gate structure 630 is removed through the first dielectric trenches 101 subsequently, the second dielectric trenches 102 formed do not extend to the second region along the third direction (x direction) or only extend to a part of the second region. Thus, as shown, Figure 17 As shown, the thickness of the gate layer 611 of the gate structure 610 divided along the third direction (x direction) in the first direction (z direction) is different, and the thickness of the portion of the gate layer 611 located in the first region in the first direction (z direction) is less than the thickness of at least a portion of the gate layer 611 located in the second region in the first direction (z direction). For example, as shown, Figure 17As shown, the gate layer 611 of the gate structure 610 includes a first gate portion 611-1 and a second gate portion 611-2 located at least one side of the first gate portion 611-1 along the third direction (x direction), and the thickness of the first gate portion 611-1 along the first direction (z direction) is less than the thickness of the second gate portion 611-2 along the first direction (z direction). Since the thickness of the second gate portion 611-2 along the first direction (z direction) is greater than the thickness of the first gate portion 611-1 along the first direction (z direction), the size of the second connection structure 820 along the first direction (z direction) is smaller when the second connection structure 820 is connected to the second gate portion 611-2 than when the second connection structure 820 is connected to the first gate portion 611-1, so that the depth of the second connection hole required for etching when forming the second connection structure 820 is smaller, and the process difficulty is also reduced.

[0072] In some embodiments, the isolation structure 700 includes an isolation layer (not shown), and the isolation structure 700 can be formed by: filling the second trench 202 and the third trench 203 with a sacrificial material; removing the sacrificial material in the third trench 203; depositing an isolation material in the third trench 203 to form the isolation layer with an air gap; and removing the sacrificial material in the second trench 202 to facilitate subsequent formation of the initial gate structure 630 in the second trench 202. Specifically, the isolation material can be deposited in the third trench 203 using two different deposition rates, in other words, a first deposition rate can be used to form a portion of the isolation layer on the inner wall of the third trench 203, and a second deposition rate greater than the first deposition rate can be used to form another portion of the isolation layer at the opening of the third trench 203. Since the second deposition rate is greater than the first deposition rate, when depositing the two portions simultaneously, the isolation material at the opening of the third trench 203 quickly seals the opening, while due to the slower first deposition rate, there is still some space in the third trench 203 that is not filled with the isolation material after the sealing, thereby forming an air gap. Since the air gap has a lower dielectric constant, which is close to that of a vacuum, the presence of the air gap can reduce the dielectric constant of the entire isolation layer, thereby reducing the parasitic capacitance and the electrical interference between adjacent two semiconductor pillars. The size and position of the air gap can be adjusted by controlling the first deposition rate and the second deposition rate during the formation of the air gap, and the greater the ratio between the second deposition rate and the first deposition rate, the larger the air gap formed in the isolation layer, and the better the effect of reducing the parasitic capacitance. For example, the ratio a between the second deposition rate and the first deposition rate can be in the range of 1≤a≤3. As an example, the ratio a can be in the range of 1.5≤a≤2. In addition, those skilled in the art should understand that the structure, composition and generation process of the isolation layer with the air gap can be changed without departing from the technical solutions claimed in the present application, to obtain the various results and advantages described in the present specification.

[0073] It should be noted that, as shown in Figure 8 In addition to improving the isolation effect through the air gap, the isolation structure 700 can also improve the isolation effect by setting the isolation conductive layer 720, and subsequently grounding or connecting the negative pressure of the isolation conductive layer 720 can improve the coupling effect between the two adjacent semiconductor pillars 210. As an example, in order to further improve the isolation effect of the isolation structure 700 and reduce the electrical interference between the two adjacent semiconductor pillars 210, the isolation structure 700 can include the isolation dielectric layer 710 and the isolation conductive layer 720. In this case, the isolation structure 700 can be formed by: filling a sacrificial material in the second trench 202 and the third trench 203; removing the sacrificial material in the third trench 203; forming the isolation dielectric layer 710 on the inner wall of the third trench 203, wherein the material of the isolation dielectric layer 710 can include but is not limited to silicon oxide, silicon oxynitride, or silicon nitride. The isolation conductive layer 720 is formed in the gap formed by the isolation dielectric layer 710, wherein the material of the isolation conductive layer 720 can include but is not limited to at least one of tungsten, titanium nitride, copper, and silver. The sacrificial material in the second trench 202 is removed to facilitate the subsequent formation of the initial gate structure 630 in the second trench 202. It should be noted that if the materials of the gate dielectric layer 612 and the isolation dielectric layer 710 are the same, the same process can be used to form the gate dielectric layer 612 and the isolation dielectric layer 710 on the inner walls of the second trench 202 and the third trench 203, respectively, and then fill the sacrificial material in the remaining space of the second trench 202 and the third trench 203.

[0074] In some embodiments, as shown in Figure 5 and Figure 6 Before forming the initial gate structure 630 and the isolation structure 700 in the second trench 202 and the third trench 203, respectively, the portion of the preliminary semiconductor pillar 211 away from the first surface 204 can be doped through the second trench 202 and the third trench 203 to form the drain 212. In addition, as shown in Figure 26 and Figure 27 After forming the initial gate structure 630 and the isolation structure 700, the end of the initial semiconductor pillar 211-1 away from the drain 212 can also be doped to form the source 214, forming the semiconductor pillar 210, and the remaining part of the semiconductor pillar 210 constitutes the channel 213. The semiconductor pillar 210 includes the source 214, the drain 212, and the channel 213 between the source 214 and the drain 212 in the first direction (z direction). The drain 212 and the source 214 can be doped with P-type dopants, or can be doped with N-type dopants. The dopants of the drain 212 and the source 214 can be the same or different. For example, the above-mentioned dopants can include but are not limited to boron (B), aluminum (Al), gallium (Ga), phosphorus (P), arsenic (As), or antimony (Sb).

[0075] In some embodiments, the bit line 300 can be formed as follows: Figures 17 to 19 As shown, a dielectric sacrificial layer 150 is formed in the remaining space of the first dielectric groove 101; Figure 20 As shown, a metal layer 310 is formed to cover the drain 212 and the dielectric sacrificial layer 150, wherein the material of the metal layer 310 may include, but is not limited to, at least one of titanium (Ti), cobalt (Ni), and nickel (Ni). Figure 21 As shown, the metal layer 310 is annealed to form the bit line 300. Taking the drain 212 as P-type polysilicon and the metal layer 310 as an example, a Ni film is formed to cover the drain 212 and the surface of the dielectric sacrificial layer 150; a Ni3N2 film is deposited on the side of the Ni film away from the drain 212 to prevent Ni from flowing during the subsequent rapid thermal annealing process; the Ni film is subjected to a rapid thermal annealing process. During this process, Ni does not react with the dielectric sacrificial layer 150, but only reacts with the drain 212 to form a high-resistance metal silicide. In other words, the growth of the high-resistance metal silicide during the annealing process consumes the drain 212. For every x-thickness growth of the metal silicide, a y-thickness of the drain 212 is consumed; the high-resistance metal silicide is subjected to a rapid thermal annealing process to convert the high-resistance metal silicide into a low-resistance metal silicide Ni2Si. The low-resistance metal silicide Ni2Si serves as the bit line 300. After forming the bit line 300, the remaining metal layer 310 is removed, for example, by removing the Ni3N2 film and the unreacted Ni film through a selective wet etching process; Figure 21 As shown, the dielectric sacrificial layer 150 is removed to form the bit line dielectric trench 103 .

[0076] like Figure 19 As shown, in order to simplify the process and reduce the difficulty of removing the dielectric sacrificial layer 150, the dielectric sacrificial layer 150 may include a first sacrificial layer 130 and a second sacrificial layer 140, and the material of the second sacrificial layer 140 includes a metal element. Figure 17 and Figure 18As shown, a first sacrificial layer 130 can be formed on the inner wall of the remaining space of the first dielectric groove 101; and a second sacrificial layer 140 can be formed in the gap formed by the first sacrificial layer 130. The second sacrificial layer 140 can have an air gap. The first sacrificial layer 130 and the second sacrificial layer 140 can both be formed by a thin film deposition process, and the thin film deposition process can be but is not limited to a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process or a combination of any of the above processes. Since the first sacrificial layer 130 and the second sacrificial layer 140 will cover the surface of the drain 212 during the actual deposition process, as shown in FIG. Figure 19 After the deposition process is completed, a chemical mechanical polishing (CMP) process can be used to remove the first sacrificial layer 130 and the second sacrificial layer 140 covering the surface of the drain electrode 212 to expose the surface of the drain electrode 212. As an example, the material of the first sacrificial layer 130 is silicon nitride, the material of the second sacrificial layer 140 is titanium nitride, and the material of the metal layer 310 is nickel. Compared to silicon nitride, titanium nitride is not only easier to remove, but also contains the metallic element titanium, which can be removed simultaneously with the metal layer 310 remaining after annealing using the same etchant.

[0077] Step S200

[0078] like Figure 21 and Figure 22 As shown, in step S200, a second dielectric layer 400 is formed on a side of the bit line 300 away from the drain 212. The second dielectric layer 400 can be formed on a surface of the bit line 300 away from the drain 212 by a thin film deposition process, and the material of the second dielectric layer 400 can include, but is not limited to, topology structure silicon nitride (TS SIN).

[0079] like Figure 21 As shown, multiple bit lines 300 extend along the second direction (y direction) and are spaced apart along the third direction (x direction). Each bit line 300 is connected to multiple initial semiconductor pillars 211-1 distributed along the second direction (y direction). A bit line dielectric trench 103 extending along the second direction (y direction) is formed between two adjacent bit lines 300 along the third direction (x direction). Figure 22As shown, the second dielectric layer 400 covers the inner wall of the bitline dielectric trench 103 and the surface of the bitline 300 away from the drain 212. The thickness of the portion of the second dielectric layer 400 covering the surface of the bitline 300 is greater than the thickness of the portion of the second dielectric layer 400 covering the inner wall of the bitline dielectric trench 103. This not only enables the portion of the second dielectric layer 400 covering the surface of the bitline 300 to act as a stop layer when etching the first connection hole 811, but also prevents the portion of the second dielectric layer 400 covering the inner wall of the bitline dielectric trench 103 from occupying too much space in the bitline dielectric trench 103. This ensures that a large amount of remaining space remains in the bitline dielectric trench 103 after the second dielectric layer 400 is formed, so that the dielectric material subsequently filled in this remaining space can effectively isolate two adjacent bitlines 300. Taking the second dielectric layer 400 as an example, the material of the topological silicon nitride is topological silicon nitride. The inherent characteristics of the topological silicon nitride make it possible for the deposition thickness of the topological silicon nitride on the horizontal surface to be greater than the deposition thickness on the vertical or inclined surface when the topological silicon nitride is deposited. Therefore, when the topological silicon nitride is deposited from the side of the bit line 300 away from the drain 212, the topological silicon nitride will cover the surface of the bit line 300 and the inner wall of the bit line dielectric groove 103, and the thickness of the portion of the topological silicon nitride covering the surface of the bit line 300 will be greater than the thickness of the portion of the topological silicon nitride covering the inner wall of the bit line dielectric groove 103.

[0080] Step S300

[0081] like Figure 23 As shown, in step S300, a cap layer 500 is formed to cover the surface of the second dielectric layer 400. The cap layer 500 may be a single-layer structure or a multi-layer structure. The material of the cap layer 500 may include, but is not limited to, silicon oxide, silicon oxynitride, or silicon nitride. The cap layer 500 may be formed by a thin film deposition process, which may include, but is not limited to, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a combination of any of the above processes.

[0082] like Figure 22 As shown, the second dielectric layer 400 covers the inner wall of the bit line dielectric trench 103 and the surface of the bit line 300 away from the drain 212, and the bit line dielectric trench 103 is not filled with the second dielectric layer 400. Figure 23After the cap layer 500 is formed, a portion of the cap layer 500, namely the first portion 510, is located on a side of the second dielectric layer 400 away from the bit lines 300 along the first direction (z-direction). Another portion of the cap layer 500, namely the plurality of second portions 520, is located within the remaining space of each bit line dielectric trench 103. Specifically, the second portions 520 are located between two adjacent bit lines 300 along the third direction (x-direction). Thus, the second portions 520 of the cap layer 500 can isolate the two adjacent bit lines 300 and reduce electrical interference between the two adjacent bit lines 300. Furthermore, to enhance the isolation effect of the second portions 520, the second portions 520 may include air gaps.

[0083] Step S400

[0084] like Figure 24 As shown, in step S400, a first connection hole 811 is formed that penetrates the cap layer 500 along the first direction (z direction) and stops at the second dielectric layer 400. The first connection hole 811 can be formed in the cap layer 500 by an etching process, wherein the etching process includes but is not limited to a wet etching process, a dry etching process such as a plasma etching process or a reactive ion etching process, or a combination of any of the above processes. The cap layer 500 and the second dielectric layer 400 are made of different materials, and the cap layer 500 and the second dielectric layer 400 have different etching selectivities for the same etchant. The projection shape of the first connection hole 811 on a plane perpendicular to the first direction (z direction) can be, but is not limited to, a semicircular, circular, rectangular, triangular, or any other arbitrary shape. In addition, based on the characteristics of the etching process, the size of the first connection hole 811 in the second direction (y direction) gradually decreases along the first direction (z direction) toward the second dielectric layer 400.

[0085] Step S500

[0086] In step S500, a portion of the second dielectric layer 400 is removed through the first connection hole 811 to expose the bit line 300. For example, a punching process can be used to remove the second dielectric layer 400 exposed through the first connection hole 811, thereby exposing the bit line 300. It can be seen that in the embodiment of the present application, the first connection hole 811 is formed in steps with the second dielectric layer 400 as the boundary. The first connection hole 811 is first made to penetrate the cap layer 500 and stop at the second dielectric layer 400. Then, a portion of the second dielectric layer 400 is removed through the first connection hole 811, thereby deepening the first connection hole 811 to expose the bit line 300. Compared to directly etching the first connection hole 811 in one step, the embodiment of the present application uses a two-step etching + punching process to form the first connection hole 811. This can avoid the problem of over-etching or under-etching during the etching of the first connection hole 811, thereby increasing the process window and reducing the process difficulty.

[0087] Step S600

[0088] like Figure 26 As shown, in step S600 , a first connection structure 810 is formed in the first connection hole 811 . Figure 25 Schematic diagram of a top view of a semiconductor device in an embodiment of the present application, Figure 26 In the implementation mode of this application Figure 25 Schematic cross-sectional view at BB, Figure 27 In the implementation mode of this application Figure 26 A schematic cross-sectional view at AA; Figure 28 In the implementation mode of this application Figure 26 A cross-sectional view at CC. Figure 24 and Figure 26 As shown, the first connection structure 810 may include a first connection dielectric layer 812 and a first connection conductive layer 813. Both the first connection dielectric layer 812 and the first connection conductive layer 813 may be formed in the first connection hole 811 through a thin film deposition process. Specifically, the first connection dielectric layer 812 may be formed on the sidewalls of the first connection hole 811 extending along the first direction (z-direction); and the first connection conductive layer 813 may be formed within the gap enclosed by the first connection dielectric layer 812. The material of the first connection dielectric layer 812 may include, but is not limited to, silicon oxide, silicon oxynitride, or silicon nitride. The material of the first connection conductive layer 813 may include, but is not limited to, polysilicon, tungsten, aluminum, titanium, copper, cobalt, tungsten nitride, or any combination thereof.

[0089] In some embodiments, the preparation method may further include: forming a second connection hole (not shown) that penetrates the cap layer 500 and the second dielectric layer 400 along the first direction (z direction) and extends to the gate layer 611; Figure 28 As shown, a second connection structure 820 connected to the gate layer 611 is formed in the second connection hole. The second connection structure 820 may include a second connection dielectric layer 821 and a second connection conductive layer 822. Both the second connection dielectric layer 821 and the second connection conductive layer 822 may be formed in the second connection hole through a thin film deposition process. Specifically, the second connection dielectric layer 821 may be formed on the sidewalls of the second connection hole extending along the first direction (z-direction); and the second connection conductive layer 822 may be formed within the gap formed by the second connection dielectric layer 821. The material of the second connection dielectric layer 821 may include, but is not limited to, silicon oxide, silicon oxynitride, or silicon nitride. The material of the second connection conductive layer 822 may include, but is not limited to, polysilicon, tungsten, aluminum, titanium, copper, cobalt, tungsten nitride, or any combination thereof.

[0090] According to the above, if Figure 23In some embodiments, the gate layer 611 of the gate structure 610 can include a first gate portion 611-1 and a second gate portion 611-2 located on at least one side of the first gate portion 611-1 along the third direction (x direction), and the thickness of the first gate portion 611-1 along the first direction (z direction) is less than the thickness of the second gate portion 611-2 along the first direction (z direction). Thus, in order to reduce the depth of the second connection hole along the first direction (z direction) and reduce the process difficulty of forming the second connection hole, the second connection hole can be formed directly above the second gate portion 611-2, that is, the second connection hole can expose the second gate portion 611-2. Thus, the second connection structure 820 formed in the second connection hole subsequently can facilitate the contact of the second gate portion 611-2. Compared with the scheme that the second connection structure 820 contacts the first gate portion 611-1, the depth of the second connection hole along the first direction (z direction) is smaller in the scheme that the second connection structure 820 contacts the second gate portion 611-2, and thus the etching process difficulty of the second connection hole is lower.

[0091] In addition, in combination with Figures 25 to 28 In some embodiments, the semiconductor device further includes a first dielectric layer 100, a second dielectric layer 400, a bit line 300, a cap layer 500, a first connection structure 810, and a plurality of semiconductor pillars 210. The plurality of semiconductor pillars 210 each extend along the first direction (z direction), the first dielectric layer 100 is located between adjacent semiconductor pillars 210, the bit line 300 is located on one side of the semiconductor pillars 210 along the first direction (z direction), the second dielectric layer 400 covers at least the surface of the bit line 300 away from the semiconductor pillars 210, the cap layer 500 covers the second dielectric layer 400, and the first connection structure 810 penetrates the cap layer 500 and the second dielectric layer 400 along the first direction (z direction) and is connected to the bit line 300.

[0092] In some embodiments, the semiconductor device further includes a first dielectric layer 100, a second dielectric layer 400, a bit line 300, a cap layer 500, a first connection structure 810, and a plurality of semiconductor pillars 210. The plurality of semiconductor pillars 210 each extend along the first direction (z direction), the first dielectric layer 100 is located between adjacent semiconductor pillars 210, the bit line 300 is located on one side of the semiconductor pillars 210 along the first direction (z direction), the second dielectric layer 400 covers at least the surface of the bit line 300 away from the semiconductor pillars 210, the cap layer 500 covers the second dielectric layer 400, and the first connection structure 810 penetrates the cap layer 500 and the second dielectric layer 400 along the first direction (z direction) and is connected to the bit line 300.

[0093] In some embodiments, the plurality of bit lines 300 each extends along a second direction (y direction) and is spaced apart along a third direction (x direction), and the bit line 300 is connected with a plurality of semiconductor pillars 210 distributed along the second direction (y direction). The semiconductor pillar 210 includes a source 214, a channel 213, and a drain 212 distributed along a first direction (z direction), the drain 212 is connected with the bit line 300, and the source 214 is located on a side of the drain 212 away from the bit line 300. A second dielectric layer 400 covers at least a surface of the bit line 300 away from the semiconductor pillar 210, and a cap layer 500 covers the second dielectric layer 400. As an example, as shown in Figure 27 The cap layer 500 includes a first portion 510 and a plurality of second portions 520. The first portion 510 is located on a side of the second dielectric layer 400 away from the bit line 300 along the first direction (z direction), and the plurality of second portions 520 are spaced apart along the third direction (x direction). The second portion 520 extends along the second direction (y direction) and protrudes into a space between two adjacent bit lines 300 along the third direction (x direction) away from the first portion 510 along the first direction (z direction). The first direction, the second direction, and the third direction are perpendicular to each other. In addition, in order to improve the isolation effect of the second portion 520 and reduce the electrical interference between the two adjacent bit lines 300 along the third direction (x direction), the second portion 520 of the cap layer 500 has an air gap.

[0094] As shown in Figure 27 The second dielectric layer 400 includes a plurality of first covering portions 410 and a plurality of second covering portions 420. The plurality of first covering portions 410 respectively covers a surface of the plurality of bit lines 300 away from the semiconductor pillar 210 along the first direction (z direction), and the second covering portion 420 is located between two adjacent bit lines 300 along the third direction (x direction). The second covering portion 420 covers at least a sidewall of the bit line 300 extending along the first direction (z direction) and a surface of the first dielectric layer 100 between the two adjacent bit lines 300. The thickness of the first covering portion 410 is greater than the thickness of the second covering portion 420. As an example, the material of the second dielectric layer 400 can include, but is not limited to, Topology Structure Silicon Nitride (TS SIN). Compared with other dielectric materials, the Topology Structure Silicon Nitride has a characteristic that when the Topology Structure Silicon Nitride is deposited, the deposition thickness of the Topology Structure Silicon Nitride on a horizontal surface is greater than the deposition thickness of the Topology Structure Silicon Nitride on a vertical or inclined surface. Therefore, the thickness of the portion of the Topology Structure Silicon Nitride covering the surface of the bit line 300 is greater than the thickness of the portion of the Topology Structure Silicon Nitride covering the sidewall of the bit line 300.

[0095] In some embodiments, as Figure 15As shown, the first dielectric layer 100 can include a first sub-dielectric layer 110 and a second sub-dielectric layer 120, the second sub-dielectric layer 120 is located on a side of the first sub-dielectric layer 110 along the first direction (z direction) towards the second dielectric layer 400. The materials of the first sub-dielectric layer 110 and the second sub-dielectric layer 120 can be the same or different.

[0096] In some embodiments, the semiconductor device can further include isolation structures 700 and gate structures 610 spaced apart along a second direction (y direction), the isolation structures 700 and the gate structures 610 are both located in the first dielectric layer 100 and extend along a third direction (x direction), the isolation structures 700 and the gate structures 610 have a plurality of semiconductor pillars 210 spaced apart along the third direction (x direction) therebetween, the first direction, the second direction and the third direction are all perpendicular to each other. As an example, the gate structures 610 are located on the sidewalls of the semiconductor pillars 210 extending along the first direction (z direction). As shown, Figure 14 As shown, the gate structure 610 includes a gate dielectric layer 612 and a gate layer 611, the gate dielectric layer 612 extends along the third direction (x direction), the gate layer 611 is located on a side of the gate dielectric layer 612 away from the semiconductor pillar 210. The material of the gate dielectric layer 612 can include, but is not limited to, silicon oxide, silicon oxynitride, silicon nitride, or high-K materials such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, etc., and the material of the gate layer 611 can include, but is not limited to, polysilicon, conductive metal or conductive alloy. In order to improve the adhesion between the gate layer 611 and the gate dielectric layer 612, the gate structure 610 can further include a gate adhesion layer 613 located between the gate dielectric layer 612 and the gate layer 611. The material of the gate adhesion layer 613 can include, but is not limited to, at least one of titanium nitride, tantalum nitride, tungsten carbide.

[0097] In some embodiments, as shown, Figure 28 The semiconductor device can further include a second connection structure 820 connected with the gate structure 610, the second connection structure 820 penetrates the cap layer 500 and the second dielectric layer 400 along the first direction (z direction) and is connected with the gate layer 611 of the gate structure 610. In order to reduce the process difficulty of forming the second connection structure 820 and reduce the etching depth of the second connection hole along the first direction (z direction), the gate layer 611 of the gate structure 610 has different thicknesses along the first direction (z direction) along the third direction (x direction). For example, as shown, Figure 21As shown, the gate layer 611 includes a first gate portion 611-1 and a second gate portion 611-2 located at least one side of the first gate portion 611-1 along the third direction (x direction), a thickness of the first gate portion 611-1 along the first direction (z direction) is less than a thickness of the second gate portion 611-2 along the first direction (z direction), and the second connection structure 820 is connected with the second gate portion 611-2.

[0098] Further, the application also provides a three-dimensional memory including a peripheral circuit and the semiconductor device, and the peripheral circuit is bonded to the semiconductor device. The peripheral circuit can include, but is not limited to, at least one of a high-voltage device, a low-voltage device, and an ultra-low-voltage device. The high-voltage device can include, but is not limited to, at least one of a row decoder, a column decoder, a word line driver, and a bit line driver. The low-voltage device can include, but is not limited to, a page buffer or a logic device. The ultra-low-voltage device can include, but is not limited to, an I / O circuit.

[0099] In addition, the application also provides a storage system including a controller and the semiconductor device, and the controller is coupled to the semiconductor device and used to control the semiconductor device to store data.

[0100] Figure 30 A block diagram of a system having a semiconductor device is shown. The system 900 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle-mounted computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device located therein. As shown in FIG. 9, the system 900 can include a host 904 and a memory system 901 having one or more semiconductor devices 902 and a memory controller 903. The host 904 can be a processor of an electronic device, such as a central processing unit (CPU), or can be a system on chip (SoC), such as an application processor (AP). The host 904 can be configured to send or receive data to or from the semiconductor device 902. Figure 30 As shown in FIG. 9, the system 900 can include a host 904 and a memory system 901 having one or more semiconductor devices 902 and a memory controller 903. The host 904 can be a processor of an electronic device, such as a central processing unit (CPU), or can be a system on chip (SoC), such as an application processor (AP). The host 904 can be configured to send or receive data to or from the semiconductor device 902.

[0101] The semiconductor device 902 can be any semiconductor device disclosed in the present application, such as Figures 25 to 28 The semiconductor device is shown. According to some embodiments, the memory controller 903 is coupled to the semiconductor device 902 and the host 904, and is configured to control the semiconductor device 902. The memory controller 903 can manage data stored in the semiconductor device 902, and communicate with the host 904.

[0102] In some embodiments, the memory controller 903 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, compact flash (CF) card, universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile telephones, etc. In some embodiments, the memory controller 903 is designed to operate in a high duty cycle environment, such as an SSD or embedded multimedia card (eMMC), which is used as a data storage device for mobile devices such as smartphones, tablets, laptops, etc. as well as enterprise storage arrays. The memory controller 903 can be configured to control operations of the semiconductor device 902, such as read, erase, and program operations. The memory controller 903 can also be configured to manage various functions related to data stored in or to be stored into the semiconductor device 902, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 903 is further configured to process error correction codes (ECC) related to data read from or written to the semiconductor device 902. Any other suitable functions can also be performed by the memory controller 903, for example, formatting the semiconductor device 902. The memory controller 903 can communicate with external devices (e.g., the host 904) according to a particular communication protocol. For example, the memory controller 903 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a firewire protocol, etc.

[0103] It should be understood that the various forms of flow illustrated above can be reordered, steps added or removed. As an example, the steps recited in the present disclosure can be performed in parallel, in series, in different orders, without limitation herein, so long as the desired results of the technology disclosed herein are achieved.

[0104] The specific embodiments discussed above do not constrain the scope of the present application. Those skilled in the art will readily understand that various modifications, combinations, sub-combinations, and alternatives of the specific embodiments discussed above can be made in light of design requirements and other factors. Any modifications, changes, and improvements made to the specific embodiments discussed above should be considered within the scope of the present application.

Claims

1. A semiconductor device, characterized by, include: A plurality of semiconductor pillars, each extending along a first direction; a first dielectric layer, located between adjacent semiconductor pillars; a bit line located on one side of the semiconductor column along the first direction; a second dielectric layer, covering at least a surface of the bit line away from the semiconductor pillar; a cover layer, covering the second dielectric layer; as well as A first connecting structure penetrates the cap layer and the second dielectric layer along the first direction and is connected to the bit line.

2. The semiconductor device of claim 1, wherein, The plurality of bit lines extend along the second direction and are spaced apart along the third direction, and the bit lines are connected to the plurality of semiconductor pillars distributed along the second direction; Wherein, the cover layer comprises: a first portion located on a side of the second dielectric layer away from the bit line along the first direction; a plurality of second portions, each extending along the second direction and spaced apart along the third direction, wherein the second portion extends along the first direction away from the first portion and into between two adjacent bit lines along the third direction; The first direction, the second direction and the third direction intersect with each other.

3. The semiconductor device of claim 2, wherein, The second portion has an air gap.

4. The semiconductor device of claim 2, wherein, The second dielectric layer includes: a plurality of first covering portions, respectively covering surfaces of the plurality of bit lines away from the semiconductor pillars along the first direction; and A plurality of second covering portions at least cover sidewalls of the bit lines extending along the first direction and a surface of the first dielectric layer located between two adjacent bit lines.

5. The semiconductor device of claim 4, wherein, The thickness of the first covering portion is greater than the thickness of the second covering portion.

6. The semiconductor device according to any one of claims 1 to 5, wherein The material of the second dielectric layer includes topological silicon nitride.

7. The semiconductor device according to any one of claims 1 to 5, wherein The first dielectric layer includes: a first sub-dielectric layer; The second sub-dielectric layer is located on a side of the first sub-dielectric layer facing the second dielectric layer along the first direction.

8. The semiconductor device according to any one of claims 1 to 5, wherein The semiconductor device further includes: Isolation structure; a gate structure, spaced apart from the isolation structure along the second direction; The isolation structure and the gate structure are both located in the first dielectric layer and extend along the third direction. There are a plurality of semiconductor pillars spaced apart along the third direction between the isolation structure and the gate structure. The first direction, the second direction and the third direction intersect with each other.

9. The semiconductor device of claim 8, wherein, The semiconductor device further includes: A second connecting structure penetrates the cap layer and the second dielectric layer along the first direction and is connected to the gate structure.

10. The semiconductor device of claim 9, wherein, The gate structure includes a gate layer extending along the third direction, the gate layer includes a first gate portion and a second gate portion located on at least one side of the first gate portion along the third direction, the thickness of the first gate portion along the first direction is less than the thickness of the second gate portion along the first direction, and the second connecting structure is connected to the second gate portion.

11. A method of manufacturing a semiconductor device, characterized by, include: forming an initial semiconductor structure, the initial semiconductor structure comprising a first dielectric layer, a bit line, and a plurality of initial semiconductor pillars extending along a first direction, wherein the first dielectric layer is located between adjacent initial semiconductor pillars, and the bit line is located on one side of the initial semiconductor pillars along the first direction; forming a second dielectric layer on a side of the bit line away from the initial semiconductor column; forming a cap layer covering a surface of the second dielectric layer; forming a first connection hole penetrating through the cap layer along the first direction and stopping at the second dielectric layer; removing part of the second dielectric layer through the first connection hole to expose the bit line; and forming a first connection structure in the first connection hole.

12. The method of producing a semiconductor device according to Claim 11, wherein The plurality of bit lines each extend along a second direction and are spaced apart along a third direction, and the bit lines are connected with a plurality of the initial semiconductor pillars distributed along the second direction; wherein forming a second dielectric layer on a side of the bit line away from the initial semiconductor pillar comprises: forming a bit line dielectric groove extending along the second direction between two adjacent bit lines along the third direction; and forming the second dielectric layer covering the inner wall of the bit line dielectric groove and the surface of the bit line; wherein the thickness of the part of the second dielectric layer covering the surface of the bit line is greater than the thickness of the part of the second dielectric layer covering the inner wall of the bit line dielectric groove, and the first direction, the second direction and the third direction intersect with each other.

13. The method of producing a semiconductor device according to Claim 11, wherein The initial semiconductor structure further comprises a gate structure extending along a third direction and located on the side wall of the initial semiconductor pillar extending along the first direction; wherein the preparation method further comprises: forming a second connection structure penetrating through the cap layer and the second dielectric layer along the first direction and connected with the gate structure; wherein the first direction and the third direction intersect.

14. The method of producing a semiconductor device according to any one of claims 11 to 13, wherein The first dielectric layer comprises a first sub-dielectric layer; wherein forming an initial semiconductor structure comprises: forming a plurality of first grooves spaced apart along a third direction and each extending along a second direction in the wafer from a first surface of the wafer; filling a first dielectric material in the first grooves to form the first sub-dielectric layer; forming a plurality of second grooves and third grooves alternately distributed along the second direction and each extending along the third direction in the wafer from the first surface of the wafer, so that part of the wafer is divided into a plurality of preliminary semiconductor pillars; forming a gate structure in the second grooves and an isolation structure in the third grooves; forming the initial semiconductor pillar based on the preliminary semiconductor pillar, the initial semiconductor pillar comprising a drain; and forming the bit line based on the drain; wherein the first direction, the second direction and the third direction intersect with each other.

15. The method of producing a semiconductor device according to Claim 14, wherein forming a gate structure in the second grooves comprises: forming an initial gate structure covering the inner wall of the second groove in the second groove; and dividing the initial gate structure into two gate structures oppositely arranged along the second direction.

16. The method of producing a semiconductor device according to Claim 15, wherein Before dividing the initial gate structure into two gate structures, the preparation method further comprises: forming a gate isolation layer in the gap formed by the initial gate structure.

17. The method of producing a semiconductor device according to Claim 16, wherein The wafer further comprises a second surface oppositely arranged with the first surface, and the first dielectric layer further comprises a second sub-dielectric layer, and the depth of the first grooves along the first direction is greater than the depth of the second grooves and the third grooves along the first direction; wherein dividing the initial gate structure into two gate structures comprises: thinning the wafer from the second surface to expose the first sub-dielectric layer; removing part of the first sub-dielectric layer to form a first dielectric slot exposing part of the initial gate structure, the first dielectric slot extending along the second direction; removing part of the initial gate structure exposed through the first dielectric slot to form a second dielectric slot extending along the third direction; filling a second dielectric material in the second dielectric slot and part of the first dielectric slot to form the second sub-dielectric layer; and forming two gate cut structures along the first direction through the initial gate structure at two ends of the initial gate structure along the third direction to divide the initial gate structure into two gate structures.

18. The method of producing a semiconductor device according to Claim 17, wherein forming the bit line based on the drain includes: forming a dielectric sacrificial layer in the remaining space of the first dielectric slot; forming a metal layer covering the drain and the dielectric sacrificial layer; annealing the metal layer to form the bit line; and removing the dielectric sacrificial layer and the remaining metal layer to form a bit line dielectric slot.

19. The method of producing a semiconductor device according to Claim 18, wherein forming the dielectric sacrificial layer in the remaining space of the first dielectric slot includes: forming a first sacrificial layer on the inner wall of the remaining space of the first dielectric slot; and forming a second sacrificial layer in the gap surrounded by the first sacrificial layer, the material of the second sacrificial layer including a metal element.

20. The method of fabricating a semiconductor device according to Claim 14, wherein, forming the initial semiconductor pillar based on the preliminary semiconductor pillar includes: doping part of the preliminary semiconductor pillar away from the first surface through the second trench and the third trench to form the drain.

21. A three-dimensional memory, comprising: The semiconductor device includes a peripheral circuit and any one of claims 1-10, the peripheral circuit is bonded to the semiconductor device.

22. A storage system, comprising: The storage system includes a controller and any one of claims 1-10, the controller is coupled to the semiconductor device and is configured to control the semiconductor device to store data.

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