Semiconductor structure and preparation method thereof, three-dimensional memory and storage system

Abstract

The invention provides a semiconductor structure and a preparation method thereof, a three-dimensional memory and a memory system, relates to the technical field of semiconductor chips, and aims to solve the problem that adjacent bit lines are easy to couple. A semiconductor structure includes a plurality of semiconductor pillars and a plurality of bit lines. Wherein the semiconductor columns extend along a first direction, and the plurality of semiconductor columns are arranged at intervals along a second direction. The bit lines extend in the first direction, the multiple bit lines are arranged at intervals in the second direction, and one bit line and one semiconductor column are arranged in a stacked mode in the third direction. In the bit lines and the semiconductor columns which are arranged in the stacked mode, in the second direction, the size of the semiconductor columns is larger than that of the bit lines; the first direction intersects the second direction, and the third direction is perpendicular to the first direction and the second direction. Through the arrangement, under the condition that the density of the semiconductor columns is not changed, the distance between the bit lines is increased, the problem that adjacent bit lines are easy to couple is solved, and the storage stability of the semiconductor structure is improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor chip, and particularly relates to a semiconductor structure and a preparation method thereof, a three-dimensional memory and a storage system. BACKGROUND

[0002] A dynamic random access memory (DRAM) is composed of a plurality of memory cells, each of which is composed of a memory capacitor controlled by a transistor, that is, the DRAM is a memory cell of a 1 transistor to 1 memory capacitor structure (1T1C).

[0003] Among them, the conduction and cutoff of the transistor determine whether to allow or prohibit the reading and rewriting of the information stored in the memory capacitor structure. The memory capacitor structure represents 1 and 0 in logic through more and less of the charge stored therein, or the high and low of the voltage difference between the two ends of the capacitor. SUMMARY

[0004] Embodiments of the present disclosure provide a semiconductor structure and a preparation method thereof, a three-dimensional memory and a storage system.

[0005] Embodiments of the present disclosure adopt the following technical solutions:

[0006] In one aspect, a semiconductor structure is provided. The semiconductor structure includes: a plurality of semiconductor pillars and a plurality of bit lines. The semiconductor pillars extend along a first direction, and the plurality of semiconductor pillars are spaced apart along a second direction. The plurality of bit lines extend along the first direction, and the plurality of bit lines are spaced apart along the second direction. One of the bit lines and one of the semiconductor pillars are stacked in a third direction. In the stacked bit lines and semiconductor pillars: in the second direction, the size of the semiconductor pillar is greater than the size of the bit line; the first direction intersects the second direction, and the third direction is perpendicular to the first direction and the second direction.

[0007] In some embodiments, the bit lines extend along the first direction, and the plurality of bit lines are spaced apart along the second direction. In the stacked bit lines and semiconductor pillars: in the second direction, the edges on both sides of the bit line are located within the edges of the semiconductor pillar.

[0008] In some embodiments, the stacked bit lines and semiconductor pillars constitute a semiconductor assembly. In the semiconductor assembly: in the second direction, the first side wall of the bit line and the second side wall of the semiconductor pillar are located on the same side of the semiconductor assembly, and the distance between the first side wall of the bit line and the second side wall of the semiconductor pillar ranges from 1 nm to 3 nm.

[0009] In some embodiments, the semiconductor structure further comprises: a transistor and a capacitor structure, the transistor is connected to the semiconductor pillar away from the bit line, and the capacitor structure is connected to the transistor.

[0010] In some embodiments, the distance between adjacent bit lines in the second direction ranges from 12 nm to 21 nm.

[0011] In some embodiments, the semiconductor structure further comprises: a dielectric layer, the dielectric layer comprises a first part and a second part, the first part is located between adjacent semiconductor pillars, and the second part is located on a side of the bit line away from the semiconductor pillar, the dielectric layer, the bit line and the semiconductor pillar collectively enclose an air gap.

[0012] In some embodiments, the bit line comprises a conductive layer and a barrier layer, the barrier layer is located between the conductive layer and the semiconductor pillar.

[0013] In some embodiments, the semiconductor structure further comprises: a transistor and a capacitor structure, the transistor is connected to the semiconductor pillar away from the bit line, and the capacitor structure is connected to the transistor.

[0014] In another aspect, a method for manufacturing a semiconductor structure, comprising: forming a plurality of semiconductor pillars in a dielectric layer, the plurality of semiconductor pillars extend along a first direction, and the plurality of semiconductor pillars are spaced apart along a second direction; forming a plurality of bit lines on the semiconductor pillars, the plurality of bit lines extend along the first direction, and the plurality of bit lines are spaced apart along the second direction, one bit line and one semiconductor pillar are stacked in a third direction; in the stacked bit line and semiconductor pillar: in the second direction, the size of the semiconductor pillar is greater than the size of the bit line; wherein the first direction intersects the second direction, and the third direction is perpendicular to the first direction and the second direction.

[0015] In some embodiments, the forming a bit line on the semiconductor pillar comprises: removing part of the semiconductor pillar, so that the dielectric layer exceeds the semiconductor pillar in the third direction; depositing a dielectric material on the semiconductor pillar; removing part of the dielectric material to form a first via hole penetrating the semiconductor pillar; sequentially forming a barrier layer and a conductive layer in the first via hole, the barrier layer and the conductive layer collectively constitute a bit line, and the distance between adjacent bit lines in the second direction ranges from 12 nm to 21 nm.

[0016] In some embodiments, after forming the bit line on the semiconductor pillar, further comprising: removing part of the dielectric layer along the third direction to expose the bit line and part of the semiconductor pillar close to the bit line, the bit line and the semiconductor pillar arranged in a stack form a semiconductor component, in the semiconductor component: in the second direction, a first sidewall of the bit line and a second sidewall of the semiconductor pillar are located on the same side of the semiconductor component, and a distance between the first sidewall of the bit line and the second sidewall of the semiconductor pillar ranges from 1 nm to 3 nm; forming a dielectric layer on the bit line, the dielectric layer, the bit line and the semiconductor pillar enclosing an air gap.

[0017] In some embodiments, the removing part of the dielectric layer along the third direction comprises: forming a first mask layer on the bit line; removing the dielectric layer on both sides of the bit line and part of the dielectric layer on both sides of the semiconductor pillar to form a second via; forming a second mask layer covering the bottom wall and the sidewall of the second via; removing the second mask layer on the bottom wall of the second via; and removing part of the dielectric layer at the bottom of the second via to deepen the second via.

[0018] In another aspect, a three-dimensional memory is provided, comprising: the semiconductor structure and the peripheral device as described above, and the peripheral device is connected to the semiconductor structure.

[0019] In another aspect, a storage system is provided, comprising: the three-dimensional memory and the controller as described above, and the controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

[0020] In another aspect, an electronic device is provided, comprising: a mainboard and the storage system as described above, and the mainboard is electrically connected to the storage system. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings described in the following description are only the drawings of some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings described in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0022] Figure 1 is a block diagram of an electronic device according to some embodiments;

[0023] Figure 2 is a block diagram of a storage system according to some embodiments;

[0024] Figure 3 is a block diagram of a storage system according to some other embodiments;

[0025] Figure 4 is a three-dimensional structural diagram of a memory according to some embodiments;

[0026] Figure 5 is a cross-sectional view of a memory according to some embodiments;

[0027] Figure 6 for Figure 4 A schematic diagram of the structure of a storage unit;

[0028] Figure 7 for Figure 6 The equivalent circuit diagram of the memory cell shown;

[0029] Figure 8 is a schematic structural diagram of a semiconductor structure according to some embodiments;

[0030] Figure 9 for Figure 8 A magnified view of the structure in the middle A frame;

[0031] Figure 10 for Figure 9 A cross-sectional view of the dielectric layer on the supplementary bit line in the middle BB section;

[0032] Figure 11 A flowchart of a method for preparing a semiconductor structure according to some embodiments;

[0033] Figure 12 is a schematic structural diagram after a plurality of semiconductor pillars are formed in a dielectric layer according to some embodiments;

[0034] Figure 13 A flowchart of a method for preparing a semiconductor structure according to some other embodiments;

[0035] Figure 14 is a schematic diagram of a structure after a portion of a semiconductor column is removed according to some embodiments;

[0036] Figure 15 is a schematic diagram of a structure after a dielectric material is deposited on a semiconductor pillar according to some embodiments;

[0037] Figure 16 is a schematic diagram of a structure after forming a first through hole penetrating the semiconductor pillar according to some embodiments;

[0038] Figure 17 is a schematic structural diagram after a barrier layer and a conductive layer are sequentially formed in the first through hole according to some embodiments;

[0039] Figure 18 A structure after chemical mechanical polishing of the barrier layer and the conductive layer according to some embodiments;

[0040] Figure 19 A flowchart of the preparation method after forming the bit line on the semiconductor pillar according to some embodiments;

[0041] Figure 20 A flowchart of the preparation method of removing part of the dielectric layer along the third direction according to some embodiments;

[0042] Figure 21 A structure after removing part of the bit line according to some embodiments;

[0043] Figure 22 A structure after forming the first mask layer according to some embodiments;

[0044] Figure 23 A structure after chemical mechanical polishing of the surface of the first mask layer according to some embodiments;

[0045] Figure 24 A structure after forming the second via according to some embodiments;

[0046] Figure 25 A structure after forming the second mask layer according to some embodiments;

[0047] Figure 26 A structure after removing the second mask layer on the bottom wall of the second via according to some embodiments;

[0048] Figure 27 A structure after removing part of the dielectric layer at the bottom of the second via according to some embodiments;

[0049] Figure 28 A structure after removing the second mask layer according to some embodiments;

[0050] Figure 29 A structure after forming the dielectric layer on the bit line according to some embodiments.

[0051] Reference signs: 18, semiconductor structure; 19, semiconductor pillar; BL, bit line; 20, semiconductor component; 21, first sidewall; 22, second sidewall; 23, dielectric layer; 231, first part; 232, second part; 24, air gap; 25, conductive layer; 26, barrier layer; 27, dielectric material; 28, first via; 29, first mask layer; 30, second via; 31, second mask layer. DETAILED DESCRIPTION

[0052] In the following, the technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0053] In the description of the present disclosure, it should be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only intended to facilitate the description of the present disclosure and simplify the description, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0054] Unless the context clearly requires otherwise, throughout the description and the claims, the term "comprise", "comprising", and the like are to be construed in an open, inclusive and a non-exclusive sense, that is as "comprising, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "exemplary embodiments" or "some examples" are intended to mean that a particular feature, structure, material, or characteristic included in the embodiment or example is included in at least one embodiment or example of the present disclosure. The illustrative representation of the above terms does not necessarily mean the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any one or more embodiments or examples in any appropriate manner.

[0055] In the following, the terms "first", "second" are only used for description purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0056] In describing some embodiments, "coupled" and "connected", and their derivatives, can be used. For example, the term "connected" can be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. For another example, the term "coupled" can be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. However, the term "coupled" can also mean that two or more components have no direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited by the content herein.

[0057] “A, B, and C at least one of” is used herein to mean at least one of A, B, or C; furthermore, A, B, and C individually and the plurality of these meanings combinations are also intended.

[0058] “A and / or B” means A and B individually and the following three combinations: A only, B only, and A and B.

[0059] Use of “adapted to” or “configured to,” as used herein, means open and inclusive language that does not exclude additional devices or steps not explicitly described.

[0060] Additionally, use of “based on” means open and inclusive, as the process, step, calculation, or other action based on a stated condition or value can in fact be based on additional condition or values beyond those stated.

[0061] As used herein, “about,” “substantially,” or “approximately” means an acceptable range of error for a given value as determined by one of ordinary skill in the art to which the disclosure pertains, which will vary from implementation to implementation, but that is not outside the scope of the claims.

[0062] In the disclosure, the meaning of “on,” “over,” and “above” should be construed in the broadest sense consistent with the context, such that “on” means not only “directly on” but also “on” with an intervening feature or layer therebetween, and “over” or “above” means not only “over” or “above” but also “over” or “above” with no intervening feature or layer therebetween (i.e., directly on).

[0063] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples. In the interest of clarity, not all of the circular features depicted throughout the figures can have been shown. In the drawings and description, identical reference numerals indicate similar, but not necessarily identical, elements. Additionally, it is to be understood that changes and modifications can be effected time to time by one skilled in the art with the disclosure herein. Accordingly, numerous specific embodiments disclosed herein are to be considered in all respects as illustrative only. Various modifications in form and detail can be made without departing from the spirit and scope of the disclosure. Therefore, the disclosure is not to be limited to the specific embodiments set forth herein and can include practices or constructs within the scope of the claims and their equivalents.

[0064] As used herein, the term "substrate" refers to a material on which subsequent layers of material can be added. The substrate itself can be patterned. The material added on the substrate can be patterned or can remain unpatterned. In addition, the substrate can comprise a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0065] Some embodiments of the present disclosure provide an electronic device. Figure 1 Fig. 1 is a block diagram of an electronic device according to some embodiments. As shown in the figure, the electronic device 1 comprises a storage system 2 and a circuit board 3. Among them, the storage system 2 is electrically connected with the circuit board 3. In addition to this, the electronic device 1 can also comprise at least one of a central processing unit (CPU) and a cache, etc. Figure 1

[0066] Exemplarily, the electronic device 1 can be any one of a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0067] Some embodiments of the present disclosure also provide a storage system 2. The storage system 2 can be applied to the above-mentioned electronic device 1, of course, the storage system 2 can also be applied to other electronic devices 1, and the present disclosure does not limit this.

[0068] Figure 2 Fig. 2 is a block diagram of a storage system according to some embodiments. As shown in the figure, the storage system 2 comprises a controller 4 and a memory 5. Among them, the controller 4 is coupled with the memory 5, and is configured to control the memory 5 to store data. Figure 2

[0069] ​​The storage system 2 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 2 can be applied to and packaged into different types of electronic products, for example, a mobile phone (e.g., a cell phone), a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a game console, a printer, a positioning device, a wearable device, a smart sensor, a mobile power supply, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device 1 having a storage.

[0070] In some embodiments, as shown in FIG. 1A, the storage system 2 includes a controller 4 and one memory 5, and the storage system 2 can be integrated into a memory card. Figure 2

[0071] The memory card includes any one of a PC card (PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD) card, or a UFS.

[0072] In other embodiments, as shown in FIG. 1B, the storage system 2 includes a controller 4 and a plurality of memories 5, and the storage system 2 is integrated into a Solid State Drive (SSD). Figure 3

[0073] In the storage system 2, in some embodiments, the controller 4 is configured to operate in a low duty cycle environment, for example, an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices 2 for personal computers, digital cameras, mobile phones, etc.

[0074] In other embodiments, the controller 4 is configured to operate in a high duty cycle environment, for example, an SSD or an eMMC used for data storage of mobile devices such as smart phones, tablet computers, notebook computers, etc., and enterprise storage arrays.

[0075] ​​In some embodiments, the controller 4 can be configured to manage data stored in the memory 5 and communicate with an external device (e.g., a host). In some embodiments, the controller 4 can also be configured to control operations of the memory 5, such as read, erase, and program operations. In some embodiments, the controller 4 can also be configured to manage various functions related to data stored or to be stored in the memory 5, including at least one of bad block management, garbage collection, logical to physical address translation, and wear leveling. In some embodiments, the controller 4 is also configured to process error correction codes for data read from or written to the memory 5.

[0076] Of course, the controller 4 may also perform any other suitable functions, such as formatting the memory 5 ; for example, the controller 4 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0077] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Mini Interface (SCSI) protocol, Enhanced Minidisk Interface (ESDI) protocol, Integrated Drive Electronics 2 (IDE) protocol, and Firewire protocol.

[0078] The controller 4 may be, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof.

[0079] Some embodiments of the present disclosure provide a memory 5. The memory 5 can be applied to the above-mentioned storage system 2. Of course, the memory 5 can be applied to other storage systems 2, and the present disclosure does not limit this.

[0080] Figure 4 is a three-dimensional structural diagram of a memory according to some embodiments, Figure 5 is a cross-sectional view of a memory according to some embodiments, Figure 6 for Figure 4 The structural diagram of a storage unit in Figure 7 for Figure 6An equivalent circuit diagram of the storage unit shown.

[0081] It should be noted that, in Figure 4 and Figure 5 , a memory 5 provided by embodiments of the present disclosure is in a three-dimensional coordinate system of X-Y-Z, the memory 5 extends in the X-Y plane, and the first direction X and the second direction Y are, for example, two orthogonal directions in the plane (for example, the plane of the source layer SL) where the memory 5 is located: the first direction X is, for example, the extension direction of the bit line BL, and the second direction Y is, for example, the extension direction of the word line WL. The third direction Z is perpendicular to the X-Y plane.

[0082] As used herein, “parallel”, “perpendicular”, “equal” include the stated case and the approximately similar case to the stated case, the range of the approximately similar case is within an acceptable deviation range, wherein the acceptable deviation range is determined by the person of ordinary skill in the art considering the measurement being discussed and the error related to the measurement of the specific quantity (i.e., the limitation of the measurement system). For example, “parallel” includes absolute parallel and approximately parallel, wherein the acceptable deviation range of approximately parallel can be, for example, within 5° deviation; “perpendicular” includes absolute perpendicular and approximately perpendicular, wherein the acceptable deviation range of approximately perpendicular can also be, for example, within 5° deviation. “Equal” includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two is less than or equal to 5% of either.

[0083] Referring to Figure 4 and Figure 5 , some embodiments of the present disclosure provide a memory 5 including a semiconductor device 6 and a peripheral device 7. The peripheral device 7 can be disposed on one side of the semiconductor device 6.

[0084] As shown in Figure 5 , the semiconductor device 6 can include a storage unit array 8 and a source layer SL. The peripheral device 7 can be disposed, for example, on the side of the storage unit array 8 away from the source layer SL.

[0085] As used in the present disclosure, whether a component (e.g., a layer, structure, or device) is “on”, “above”, or “below” another component (e.g., a layer, structure, or device) is determined in the third direction Z relative to the peripheral device 7 of the memory 5 when the peripheral device 7 is located in the lowest plane of the memory 5 in the third direction Z. Throughout the present disclosure, the same concept is applied to describe the spatial relationship.

[0086] Referring to Figure 5 and Figure 6The source layer SL can be connected to a first reference voltage, which can be a ground voltage or other voltage. The source layer SL can include a semiconductor material, such as monocrystalline silicon, monocrystalline germanium, a III-V compound semiconductor material, a II-VI compound semiconductor material, and other suitable semiconductor materials. The source layer SL can be partially or entirely doped. Illustratively, the source layer SL can include a doped region doped with a p-type dopant. The source layer SL can also include an undoped region.

[0087] Referring to Figure 4 and Figure 5 , the memory cell array 8 includes a plurality of memory cells 81 arranged in a first direction X and a second direction Y.

[0088] As shown in Figure 5 , Figure 6 and Figure 7 , the memory cell 81 includes a transistor structure T and a capacitor structure C. The transistor structure T can include a channel structure formed by the semiconductor pillar 19 and a gate layer 11 adjacent to the channel structure. A gate dielectric layer 12 is disposed between the semiconductor pillar 19 and the corresponding gate layer 11. The semiconductor pillar 19 has a source and a drain, which are respectively located at two ends of the semiconductor pillar 19. The material of the channel structure includes a semiconductor material, and the material of the source and the drain can include a semiconductor material doped with a p-type dopant or an n-type dopant.

[0089] It should be noted that the semiconductor material is, for example, monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, a III-V compound semiconductor material, a II-VI compound semiconductor material, and other suitable semiconductor materials. The p-type dopant includes boron or gallium. The n-type dopant includes phosphorus or arsenic.

[0090] The drain of the transistor structure T is connected to the bit line BL, and the source of the transistor structure T is connected to one plate of the capacitor structure C. That is, the transistor structure T is connected to the end of the semiconductor pillar 19 away from the bit line BL, the capacitor structure C is connected to the transistor structure T, and the other plate of the capacitor structure C can be connected to the source layer SL. The capacitor structure C represents logical 1 and 0 by more or less of the electric charge stored therein, or in other words, by higher or lower voltage difference between the two plates of the capacitor structure C. The gate layer 11 of the transistor structure T is connected to the word line WL. In this way, the transistor structure T can be controlled to be turned on or turned off by applying a voltage to the word line WL, and the bit line BL performs a read or write operation on the transistor structure T when the transistor structure T is turned on.

[0091] In some embodiments, referring to Figure 4 and Figure 5 , the semiconductor device 6 can further include an array interconnection layer 13. The array interconnection layer 13 can be coupled to the memory cell 81.

[0092] The array interconnect layer 13 can include word lines WL and bit lines BL. The word lines WL can be coupled to the gate layers 11 of the transistor structures T in the at least one memory cell 81. The bit lines BL can be coupled to the drain of the transistor structures T in the at least one memory cell 81. The gate layers 11 of the plurality of transistor structures T spaced apart along the second direction Y can be coupled to the same word line WL.

[0093] In the above embodiments, as shown in FIG. 1, the peripheral device 7 coupled to the semiconductor device 6 can include a substrate 15 and a peripheral circuit 14 disposed on the substrate 15. The substrate 15 can be made of monocrystalline silicon or other suitable materials, such as silicon germanium, germanium, or a silicon-on-insulator film. The peripheral circuit 14 is configured to control and sense the array device. The peripheral circuit 14 can be any suitable digital, analog, and / or mixed-signal control and sensing circuitry for supporting the operation of the array device, including but not limited to a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driving circuit (e.g., a word line driver), a charge pump, a current or voltage reference, or any active or passive components (e.g., a transistor, a diode, a resistor, or a capacitor structure C) of the circuit. The peripheral circuit 14 can also include any other circuit compatible with advanced logic processes, including logic circuits (e.g., a processor and a programmable logic device (PLD)) or memory circuits (e.g., a static random-access memory (SRAM)). Figure 5 The peripheral circuit 14 can be coupled to the array interconnect layer 13, so that the semiconductor device 6 and the peripheral device 7 can be coupled. Specifically, since the peripheral circuit 14 is coupled to the array interconnect layer 13, the peripheral circuit 14 in the peripheral device 7 can be coupled to the transistor structure T in the semiconductor device 6 to realize the transmission of electrical signals between the peripheral circuit 14 and the transistor structure T. In some possible implementations, a bonding interface can be disposed between the peripheral circuit 14 and the array interconnect layer 13, so that the peripheral circuit 14 and the array interconnect layer 13 can be bonded and coupled to each other through the bonding interface.

[0094]

[0095] ​In the above embodiment, a first connection portion 16 located on the array interconnect layer 13 may be provided on a side of the semiconductor device 6 near the peripheral circuit 14. The first connection portion 16 is used to connect to the transistor structure T inside the semiconductor device 6. The peripheral circuit 14 may include a second connection portion 17 and a transistor disposed on a substrate 15. The second connection portion 17 is connected to the transistor disposed on the substrate 15 and is located on a side of the transistor near the semiconductor device 6. The transistor disposed on the substrate 15 may include a complementary metal oxide semiconductor (CMOS). In the above embodiment, the first connection portion 16 and the second connection portion 17 are bonded to each other. The bonding between the first connection portion 16 and the second connection portion 17 enables a connection between the transistor structure T and the transistor disposed on the substrate 15, thereby enabling a connection between the semiconductor device 6 and the peripheral circuit 14.

[0096] Some embodiments of the present disclosure further provide a semiconductor structure, as shown below. Figures 8 to 10 , the semiconductor structures provided in some embodiments of the present disclosure are illustrated.

[0097] Figure 8 is a schematic structural diagram of a semiconductor structure according to some embodiments. Figure 9 for Figure 8 A magnified view of the structure in frame A. Figure 10 for Figure 9 Cross-sectional view of the dielectric layer on the supplementary bit line in the BB section. Figure 4 、 Figure 5 、 Figure 8 、 Figure 9 and Figure 10 Some embodiments of the present disclosure provide a semiconductor structure 18, which may be a memory 5. For example, the semiconductor structure 18 includes a semiconductor device 6 and a peripheral device 7. Alternatively, the semiconductor structure 18 may be a portion of the memory 5. For example, the semiconductor structure 18 may be the semiconductor device 6 in the memory 5. This is not specifically limited in the embodiments of the present disclosure.

[0098] like Figure 9 and Figure 10 As shown, the present disclosure provides a semiconductor structure 18 comprising: a plurality of semiconductor pillars 19 and a plurality of bit lines BL. The semiconductor pillars 19 extend along a first direction X, and the plurality of semiconductor pillars 19 are spaced apart along a second direction Y. The bit lines BL extend along the first direction X, and the plurality of bit lines BL are spaced apart along the second direction Y. One bit line BL and one semiconductor pillar 19 are stacked in a third direction Z. In the stacked bit lines BL and semiconductor pillars 19, in the second direction Y, the semiconductor pillars 19 are larger than the bit lines BL.

[0099] It should be noted that "the size of the semiconductor pillar 19 is larger than the size of the bit line BL in the second direction Y" can be understood as the width of the semiconductor pillar 19 is larger than the width of the bit line BL in the second direction Y. Therefore, in the stacked bit line BL and semiconductor pillar 19, the edge of the semiconductor pillar 19 can extend beyond the edge of the bit line BL in the second direction Y.

[0100] In some examples, in the stacked bit line BL and semiconductor pillar 19, edges on both sides of the bit line BL may be located within the edge of the semiconductor pillar 19 in the second direction Y. In other examples, in the stacked bit line BL and semiconductor pillar 19, edges on one side of the bit line BL may be aligned with edges of the semiconductor pillar 19 in the second direction Y, and edges on the other side of the bit line BL may be located within the edge of the semiconductor pillar 19.

[0101] In other embodiments, in the second direction Y, since the size of the semiconductor pillar 19 is the same as the size of the bit line BL, that is, the edge of the semiconductor pillar 19 is flush with the edge of the bit line BL, and since the density between the semiconductor pillars 19 is high, the spacing between adjacent bit lines BL is small, which can easily lead to coupling problems between adjacent bit lines BL, affecting the storage performance of the semiconductor structure 18.

[0102] As described above, in the semiconductor structure 18 provided in some embodiments of the present disclosure, in the second direction Y, the size of the semiconductor pillar 19 is larger than the size of the bit line BL, and the edge of the bit line BL is within the edge of the semiconductor pillar 19. When the density of the semiconductor pillar 19 remains unchanged, the spacing between adjacent bit lines BL in the second direction Y increases, which is beneficial to reduce the occurrence of capacitive coupling, thereby improving the storage stability of the semiconductor structure 18.

[0103] In some embodiments, as Figure 9 and Figure 10 As shown, the bit lines BL extend along a first direction X, and a plurality of bit lines BL are spaced apart along a second direction Y. In a stacked set of bit lines BL and semiconductor pillars 19, edges on both sides of the bit lines BL are located within the edges of the semiconductor pillars 19 in the second direction Y. This increases the spacing between adjacent bit lines BL in the second direction Y, thereby reducing capacitive coupling and improving the storage stability of the semiconductor structure 18.

[0104] Moreover, in some embodiments described above, in the second direction Y, the edge of one side of the bit line BL is flush with the edge of one side of the semiconductor pillar 19, and the edge of the other side of the bit line BL is within the edge of the other side of the semiconductor pillar 19. In comparison, in the present embodiment, in the second direction Y, the edges of both sides of the bit line BL are within the edge of the semiconductor pillar 19, further increasing the spacing between two adjacent bit lines BL in the second direction Y, improving the capacitive coupling problem caused by the close spacing between adjacent bit lines BL, and helping to further improve the storage stability of the semiconductor structure 18.

[0105] In some embodiments, as Figure 10 As shown, the stacked bit line BL and semiconductor pillar 19 form a semiconductor component 20. In semiconductor component 20, in the second direction Y, the edges of both sides of the bit line BL are located within the edge of the semiconductor pillar 19. The first sidewall 21 of the bit line BL and the second sidewall 22 of the semiconductor pillar 19 are located on the same side of the semiconductor component 20. The distance between the first sidewall 21 of the bit line BL and the second sidewall 22 of the semiconductor pillar 19 ranges from 1 nm to 3 nm. Here, the distance between the first sidewall 21 of the bit line BL and the second sidewall 22 of the semiconductor pillar 19 refers to the vertical distance between the plane containing the first sidewall 21 of the bit line BL and the plane containing the second sidewall 22 of the semiconductor pillar 19.

[0106] For example, in the second direction Y, the distance between the first sidewall 21 of the bit line BL and the second sidewall 22 of the semiconductor pillar 19 can be 1 nm, 2 nm, or 3 nm. In the second direction Y, when the distance between the first sidewall 21 of the bit line BL and the second sidewall 22 of the semiconductor pillar 19 approaches 1 nm, while ensuring good conductivity of the bit line BL, the spacing between adjacent bit lines BL can be increased, the problem of bit line BL coupling can be improved, and the storage stability of the semiconductor structure 18 can be enhanced. In the second direction Y, when the distance between the first sidewall 21 of the bit line BL and the second sidewall 22 of the semiconductor pillar 19 approaches 3 nm, the spacing between adjacent bit lines BL is significantly increased, and the effect of improving capacitive coupling is better.

[0107] In some embodiments, as Figure 9 and Figure 10As shown, the stacked bit lines BL and semiconductor pillars 19 constitute a semiconductor assembly 20. In two adjacent semiconductor assemblies 20, the distance d1 between the two bit lines BL in the second direction Y is greater than the distance d2 between the two semiconductor pillars 19. Through this arrangement, while the arrangement density of the semiconductor pillars 19 remains unchanged, the spacing between adjacent bit lines BL along the second direction Y is increased, which helps reduce the occurrence of bit line BL coupling and improves the storage stability of the semiconductor structure 18. Alternatively, while maintaining the spacing between adjacent bit lines BL in the second direction Y, the density of semiconductor pillars 19 can be further increased, which helps increase the storage capacity of the semiconductor structure 18.

[0108] In some embodiments, as Figure 9 and Figure 10 As shown, in the second direction Y, the distance d1 between adjacent bit lines BL ranges from 12 nm to 21 nm. Here, the distance d1 between adjacent bit lines BL refers to the minimum distance between adjacent bit lines BL. For example, in the second direction Y, the distance d1 between adjacent bit lines BL can be 12 nm, 16 nm, or 21 nm. When the distance d1 between adjacent bit lines BL in the second direction Y approaches 12 nm, the occurrence of bit line BL coupling can be reduced when the arrangement density of multiple bit lines BL is high, thereby improving the storage stability of the semiconductor structure 18. When the distance d1 between adjacent bit lines BL in the second direction Y approaches 21 nm, the occurrence of bit line BL coupling can be further reduced, thereby improving the storage stability of the semiconductor structure 18.

[0109] In some embodiments, as Figure 9 and Figure 10 As shown, the semiconductor structure 18 further includes a dielectric layer 23. The dielectric layer 23 includes a first portion 231 and a second portion 232. The first portion 231 is located between adjacent semiconductor pillars 19, and the second portion 232 is located on the side of the bit line BL away from the semiconductor pillar 19. The dielectric layer 23, the bit line BL, and the semiconductor pillar 19 together enclose an air gap 24. Please refer to Figure 9 and Figure 10 The first portion 231 is located between adjacent semiconductor pillars 19, but the first portion 231 does not completely fill the space between adjacent semiconductor pillars 19. The end of the semiconductor pillar 19 close to the bit line BL is exposed in the air gap 24. Please continue to refer to Figure 10 Since the material used in the dielectric layer 23 has a poor hole-filling ability, the first portion 231 and the second portion 232 located between adjacent semiconductor pillars 19 can be spaced apart in the third direction Z, so that the dielectric layer 23, the bit lines BL and the semiconductor pillars 19 jointly enclose an air gap 24. Using air as a dielectric, the bit lines BL are prevented from contacting each other and causing coupling of the bit lines BL, which is beneficial to improving the storage stability of the semiconductor structure 18.

[0110] Exemplarily, the material of the medium layer 23 can include one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, carbon, boron-doped silicon oxide, phosphorus-doped silicon oxide, boron nitride, germanium silicon, polysilicon, amorphous silicon, amorphous carbon, or a combination of multiple of the above materials.

[0111] With reference to the above description of the semiconductor structure 18, Figure 10 In the embodiment, the first part 231 near the end of the bit line BL can extend along the sidewall of the semiconductor pillar 19 towards the bit line BL, for example Figure 10 In the embodiment, the first part 231 near the end of the bit line BL extends along the sidewall of the semiconductor pillar 19 upwards by a portion, and in the second direction Y, the upwardly extending portion is thin, covers the sidewall of the semiconductor pillar 19, is beneficial to isolate adjacent semiconductor pillars 19, reduce the leakage current, and improve the stability of the semiconductor structure 18.

[0112] In some embodiments, as shown in Figure 10 The bit line BL includes a conductive layer 25 and a barrier layer 26 between the conductive layer 25 and the semiconductor pillar 19. The conductive layer 25 has a conductive function and can control the conduction of a row of semiconductor pillar 19 structures by applying a voltage to the bit line BL. The barrier layer 26 is located between the conductive layer 25 and the semiconductor pillar 19, which can prevent the constituent materials of the conductive layer 25 and the constituent materials of the semiconductor pillar 19 from diffusing with each other. Exemplarily, in the plane of the second direction Y and the third direction Z, the shape of the barrier layer 26 can be a "concave" shape, the barrier layer 26 can be located on both sides of the conductive layer 25 in the second direction Y, and the barrier layer 26 can be located on the side of the conductive layer 25 close to the semiconductor pillar 19.

[0113] Exemplarily, the material of the conductive layer 25 can include one of W, Al, Cu, Ag, Au, Co, Pt, Ni, Ti, Ta, TiN, TaN, TaC, TaSiN, NiSi, CoSi, TiAl, WSi, or a combination of multiple of the above materials. The material of the conductive layer 25 in the embodiment can be one of the above materials or a combination of multiple of the above materials, or can also be other suitable conductive materials.

[0114] Exemplarily, the material of the barrier layer 26 can be TiN. TiN as the barrier layer 26 is beneficial to prevent the material of the conductive layer 25 and the material of the semiconductor pillar 19 from diffusing with each other, and TiN has good adhesion, which is beneficial to improve the stability of the semiconductor structure 18.

[0115] Figure 11 The flowchart of the method for manufacturing the semiconductor structure according to some embodiments, Figure 12A schematic diagram of a structure after forming a plurality of semiconductor pillars in a dielectric layer according to some embodiments. Some embodiments of the present disclosure also disclose a method for manufacturing a semiconductor structure 18, as shown in Figure 11 comprises S1-S2.

[0116] S1, forming a plurality of semiconductor pillars in a dielectric layer, the plurality of semiconductor pillars extending along a first direction, the plurality of semiconductor pillars being spaced apart along a second direction.

[0117] In this step, as shown in Figure 12 a plurality of semiconductor pillars 19 are formed in the dielectric layer 23, the plurality of semiconductor pillars 19 extending along a first direction X, the plurality of semiconductor pillars 19 being spaced apart along a second direction Y. The first direction intersects the second direction, and a third direction is perpendicular to the first direction and the second direction. After forming the plurality of semiconductor pillars 19 in the dielectric layer 23, the surface of the semiconductor pillars 19 can be subjected to chemical mechanical polishing (CMP) so that the upper surface of the semiconductor pillars 19 is flush with the upper surface of the dielectric layer 23.

[0118] S2, forming a plurality of bit lines on the semiconductor pillars, the plurality of bit lines extending along the first direction, the plurality of bit lines being spaced apart along the second direction, and one bit line and one semiconductor pillar being stacked in the third direction; in the stacked bit line and semiconductor pillar: in the second direction, the size of the semiconductor pillar is greater than the size of the bit line.

[0119] Figure 13 A flowchart of a method for manufacturing a semiconductor structure according to some embodiments. In this step, as shown in Figure 13 comprises S21-S24.

[0120] S21, removing part of the semiconductor pillars so that the dielectric layer protrudes beyond the semiconductor pillars in the third direction.

[0121] In this step, as shown in Figure 14 An etching process can be used to remove part of the semiconductor pillars 19 so that the dielectric layer 23 protrudes beyond the semiconductor pillars 19 in the third direction Z.

[0122] S22, depositing a dielectric material on the semiconductor pillars.

[0123] In this step, as shown in Figure 15 A dielectric material 27 can be deposited on the semiconductor pillars 19 to Figure 15Taking the position of the semiconductor pillar 19 shown as an example, the dielectric material 27 can cover the upper surface of the semiconductor pillar 19. The dielectric material 27 deposited on the semiconductor pillar 19 can fill the gaps between the dielectric layers 23. The dielectric material 27 deposited on the semiconductor pillar 19 can also fill the gaps between the dielectric layers 23 and then cover the dielectric layer 23. The dielectric material 27 and the dielectric layer 23 can be made of the same material. Here, the deposited dielectric material 27 can be formed by, for example, a thin film deposition process. The thin film deposition process includes any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0124] S23 , removing a portion of the dielectric material to form a first through hole penetrating to the semiconductor pillar.

[0125] In this step, if Figure 16 As shown, a portion of the dielectric material 27 above the semiconductor pillar 19 can be removed by an etching process, exposing the semiconductor pillar 19 in the third direction Z to form a first through hole 28 that penetrates the semiconductor pillar 19. In the second direction Y, the first through hole 28 is located within the edge of the semiconductor pillar 19.

[0126] S24 , sequentially forming a barrier layer and a conductive layer in the first through hole, wherein the barrier layer and the conductive layer together constitute a bit line, and in the second direction, a distance between adjacent bit lines ranges from 12 nm to 21 nm.

[0127] In this step, if Figure 17 and Figure 18As shown, a barrier layer 26 can be first formed in the first through hole 28. After the barrier layer 26 is formed, a conductive layer 25 can be formed on the barrier layer 26. The material of the barrier layer 26 can be TiN. TiN as the barrier layer 26 is beneficial for preventing the material of the conductive layer 25 from interdiffusion with the material of the semiconductor pillar 19. In addition, TiN has good adhesion, which is beneficial for improving the stability of the semiconductor structure 18. The material of the conductive layer 25 can include one or a combination of multiple materials selected from W, Al, Cu, Ag, Au, Co, Pt, Ni, Ti, Ta, TiN, TaN, TaC, TaSiN, NiSi, CoSi, TiAl, and WSi. Here, the barrier layer 26 and the conductive layer 25 can be formed, for example, by a thin film deposition process. The thin film deposition process includes any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0128] Continue to refer Figure 17 and Figure 18 After the barrier layer 26 and the conductive layer 25 are sequentially formed in the first through hole 28, chemical mechanical polishing (CMP) can be performed on the barrier layer 26 and the conductive layer 25 to make the barrier layer 26 and the conductive layer 25 flush with the dielectric layer 23 in the third direction Z. The barrier layer 26 and the conductive layer 25 together constitute the bit line BL, and in the second direction Y, the distance d1 between adjacent bit lines BL ranges from 12 nm to 21 nm.

[0129] The bit lines BL formed through the above steps extend along a first direction X. Multiple bit lines BL are spaced apart along a second direction Y. One bit line BL and one semiconductor pillar 19 are stacked in a third direction Z. In the stacked bit lines BL and semiconductor pillars 19, the semiconductor pillars 19 are larger than the bit lines BL in the second direction Y. While maintaining the density of semiconductor pillars 19, the increased spacing between adjacent bit lines BL in the second direction Y helps reduce capacitive coupling, thereby improving the storage stability of the semiconductor structure 18.

[0130] In addition, the preparation method in this embodiment uses a mature and simple preparation process, eliminating the need for additional new process development. Furthermore, since no carbon material is used as a sacrificial layer during the preparation process, no polluting gases such as carbon dioxide are generated, thereby reducing the risk of contamination.

[0131] In some embodiments, as Figure 19As shown, after the bit line BL is formed on the semiconductor pillar 19 , the following steps are further included: S3 - S4 .

[0132] S3. Remove part of the dielectric layer along the third direction to expose the bit line and part of the semiconductor pillar close to the bit line. The stacked bit line and semiconductor pillar constitute a semiconductor component. In the semiconductor component: in the second direction, the first side wall of the bit line and the second side wall of the semiconductor pillar are located on the same side of the semiconductor component, and the distance between the first side wall of the bit line and the second side wall of the semiconductor pillar is in the range of 1 nm to 3 nm.

[0133] In this step, if Figure 20 As shown, removing part of the dielectric layer 23 along the third direction includes: S31 to S35.

[0134] S31 , forming a first mask layer on the bit line BL.

[0135] In this step, if Figure 21 As shown in FIG, a portion of the bit line BL is removed so that the bit line BL is lower than the semiconductor pillar 19 in the third direction Z. Figure 21 and Figure 22 After removing part of the bit line BL, a first mask layer 29 (such as a patterned photoresist layer) is formed. The first mask layer 29 is located on the bit line BL and the semiconductor. Here, the first mask layer 29 can be formed by, for example, a coating process, an exposure process, and a development process in sequence. Figure 22 and Figure 23 After forming the first mask layer 29, the first mask layer 29 on the semiconductor pillar 19 can be removed by performing chemical mechanical polishing (CMP) on the surface of the first mask layer 29. The first mask layer 29 is beneficial for protecting the bit line BL from being removed in the subsequent etching process.

[0136] S32 , removing the dielectric layer on both sides of the bit line and a portion of the dielectric layer on both sides of the semiconductor pillar to form a second through hole.

[0137] In this step, if Figure 24 As shown, an etching process can be used to remove the dielectric layer 23 on both sides of the bit line BL and a portion of the dielectric layer 23 on both sides of the semiconductor pillar 19 to form a second through hole 30. A first mask layer 29 is located on the bit line BL to protect the bit line BL from being etched. After forming the second through hole 30, the first mask layer 29 can be removed by CMP or retained.

[0138] S33 , forming a second mask layer, where the second mask layer covers the bottom wall and side walls of the second through hole.

[0139] In this step, if Figure 25As shown, after the second via hole 30 is formed, a thin film deposition process can be used to form a second mask layer 31, which covers the bottom wall and the sidewall of the second via hole 30 and the first mask layer 29. The second mask layer 31 on the first mask layer 29 can be removed by CMP.

[0140] S34, remove the second mask layer on the bottom wall of the second via hole.

[0141] In this step, as shown, Figure 26 the second mask layer 31 on the bottom wall of the second via hole 30 is removed, and the remaining second mask layer 31 is located on the sidewall of the bit line BL and the sidewall of the semiconductor column 19 exposed in the second via hole 30, which is beneficial to protect the bit line BL and the semiconductor column 19 from being removed in the subsequent etching process.

[0142] S35, remove part of the medium layer at the bottom of the second via hole to deepen the second via hole.

[0143] In this step, as shown, Figure 27 an etching process can be used to remove part of the medium layer 23 at the bottom of the second via hole 30 to deepen the second via hole 30. In the deepened second via hole 30, part of the medium covered by the second mask layer 31 in the third direction Z is retained on the sidewall of the semiconductor column 19, which is beneficial to isolate adjacent semiconductor columns 19. As shown, Figure 28 after the second via hole 30 is deepened, the second mask layer 31 can be removed.

[0144] Through the above steps, part of the medium layer 23 can be removed in the third direction Z to expose the bit line BL and part of the semiconductor column 19 close to the bit line BL. The bit line BL and the semiconductor column 19 arranged in layers constitute a semiconductor assembly 20, in which: in the second direction Y, the first sidewall 21 of the bit line BL and the second sidewall 22 of the semiconductor column 19 are located on the same side of the semiconductor assembly 20, and the distance d1 between the first sidewall 21 of the bit line BL and the second sidewall 22 of the semiconductor column 19 is in the range of 1nm-3nm. The semiconductor structure 18 formed by the above steps can increase the distance between adjacent bit lines BL while ensuring good conductivity of the bit line BL, improve the coupling problem of the bit line BL, and improve the storage stability of the semiconductor structure 18.

[0145] S4, form a medium layer on the bit line, and the medium layer, the bit line and the semiconductor column surround an air gap.

[0146] In this step, as shown, Figure 28 and Figure 29As shown, after deepening the second via hole 30, a dielectric layer 23 can be formed on the bit line BL by a deposition process. The dielectric layer 23 formed in this step is an integral layer structure covering the bit line BL and the second via hole 30. Further, the dielectric layer 23, the bit line BL and the semiconductor pillar 19 enclose the air gap 24, which is beneficial for isolating adjacent bit lines BL and adjacent semiconductor pillars 19.

[0147] The above merely provides the specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a plurality of semiconductor pillars extending along a first direction, a plurality of the semiconductor pillars being spaced apart along a second direction; a plurality of bit lines extending along the first direction, a plurality of the bit lines being spaced apart along the second direction, one of the bit lines being stacked with one of the semiconductor pillars along a third direction; in the stacked bit lines and semiconductor pillars: in the second direction, a dimension of the semiconductor pillars is greater than a dimension of the bit lines; the first direction intersects the second direction, and the third direction is perpendicular to the first direction and the second direction.

2. The semiconductor structure of claim 1, wherein, The bit lines extend along the first direction, a plurality of the bit lines being spaced apart along the second direction; in the stacked bit lines and semiconductor pillars: in the second direction, edges on both sides of the bit lines are located within edges of the semiconductor pillars.

3. The semiconductor structure of claim 2, wherein, The stacked bit lines and semiconductor pillars form a semiconductor assembly, in the semiconductor assembly: in the second direction, a first sidewall of the bit lines and a second sidewall of the semiconductor pillars are located on the same side of the semiconductor assembly, and a distance between the first sidewall of the bit lines and the second sidewall of the semiconductor pillars ranges from 1 nm to 3 nm.

4. The semiconductor structure according to any of claims 1-3, characterized in that, The stacked bit lines and semiconductor pillars form a semiconductor assembly, in two adjacent semiconductor assemblies: in the second direction, a distance between two of the bit lines is greater than a distance between two of the semiconductor pillars.

5. The semiconductor structure of claim 4, wherein, In the second direction, a distance between adjacent bit lines ranges from 12 nm to 21 nm.

6. The semiconductor structure of any of claims 1-3, wherein, The semiconductor structure further comprises: a dielectric layer comprising a first portion and a second portion, the first portion being located between adjacent semiconductor pillars; the second portion being located on a side of the bit lines away from the semiconductor pillars, the dielectric layer, the bit lines, and the semiconductor pillars collectively defining an air gap.

7. The semiconductor structure of any of claims 1-3, wherein, The bit lines comprise a conductive layer and a barrier layer, the barrier layer being located between the conductive layer and the semiconductor pillars.

8. The semiconductor structure of any of claims 1-3, wherein, The semiconductor structure further comprises: a transistor connected to an end of the semiconductor pillars away from the bit lines, and a capacitor structure connected to the transistor.

9. A method of fabricating a semiconductor structure, characterized by, The semiconductor structure comprises: forming a plurality of semiconductor pillars in a dielectric layer, the plurality of semiconductor pillars extending along a first direction, a plurality of the semiconductor pillars being spaced apart along a second direction; forming a plurality of bit lines on the semiconductor pillars, the bit lines extending along the first direction, a plurality of the bit lines being spaced apart along the second direction, one of the bit lines being stacked with one of the semiconductor pillars along a third direction; in the stacked bit lines and semiconductor pillars: in the second direction, a dimension of the semiconductor pillars is greater than a dimension of the bit lines; wherein the first direction intersects the second direction, and the third direction is perpendicular to the first direction and the second direction.

10. The method of claim 9, wherein the semiconductor structure is prepared by a method comprising: The forming of the bit lines on the semiconductor pillars comprises: removing part of the semiconductor pillars, so that the dielectric layer exceeds the semiconductor pillars along the third direction; depositing a dielectric material on the semiconductor pillars; removing part of the dielectric material to form a first via hole penetrating to the semiconductor pillars; A barrier layer and a conductive layer are sequentially formed in the first via, and the barrier layer and the conductive layer together constitute a bit line, wherein in the second direction, the distance between adjacent bit lines ranges from 12 nm to 21 nm.

11. The method of claim 9, wherein the semiconductor structure is prepared by a method comprising: After forming the bit line on the semiconductor pillar, further comprising: Part of the dielectric layer is removed along the third direction to expose the bit line and part of the semiconductor pillar close to the bit line, and the bit line and the semiconductor pillar are stacked to constitute a semiconductor component, wherein in the second direction, the first sidewall of the bit line and the second sidewall of the semiconductor pillar are located on the same side of the semiconductor component, and the distance between the first sidewall of the bit line and the second sidewall of the semiconductor pillar ranges from 1 nm to 3 nm. A dielectric layer is formed on the bit line, and the dielectric layer, the bit line and the semiconductor pillar surround an air gap.

12. The method of claim 11, wherein the semiconductor structure is prepared by a method comprising: The removing part of the dielectric layer along the third direction comprises: A first mask layer is formed on the bit line; The dielectric layer on both sides of the bit line and part of the dielectric layer on both sides of the semiconductor pillar are removed to form a second via; A second mask layer is formed, which covers the bottom wall and sidewall of the second via; The second mask layer on the bottom wall of the second via is removed; Part of the dielectric layer at the bottom of the second via is removed to deepen the second via.

13. A three-dimensional memory, comprising: Comprising: The semiconductor structure of any one of claims 1-8; A peripheral device connected with the semiconductor structure.

14. A storage system, characterized by Comprising: The three-dimensional memory of claim 13; A controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

15. An electronic device, comprising: Comprising: A mainboard and the storage system of claim 14, wherein the mainboard is electrically connected with the storage system.

Images