Semiconductor structure, manufacturing method thereof and memory system

Abstract

The invention provides a semiconductor structure, a manufacturing method thereof and a storage system. The semiconductor structure includes a plurality of memory cell arrays distributed along a first direction, each memory cell array including a plurality of memory cells distributed along a second direction and a third direction, and a plurality of bit lines located at one side of the memory cells along the first direction. The bit lines of the memory cell arrays are connected with the bit lines which are located in the adjacent memory cell arrays and are spaced by a preset distance in the second direction. The first direction, the second direction and the third direction intersect pairwise.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and more particularly, to a semiconductor structure, a method for manufacturing the semiconductor structure, and a storage system. BACKGROUND

[0002] With the rise and development of the fields of artificial intelligence, big data, Internet of Things, mobile communication, mobile devices, and cloud storage, the requirement for the storage density of semiconductor structures such as three-dimensional semiconductor memory devices is also increasing. At present, the market mainly increases the storage density of semiconductor structures by reducing the size of the semiconductor structures. However, as the size of the semiconductor structures is reduced, the distance between adjacent components in the semiconductor structures is reduced, the coupling phenomenon is increased, and thus the performance of the semiconductor structures is easily reduced. SUMMARY

[0003] The embodiments provided in the present application can solve or partially solve the deficiencies proposed in the background section or other deficiencies in the prior art.

[0004] The present application provides a semiconductor structure. The semiconductor structure comprises: a plurality of memory cell arrays distributed along a first direction, wherein the memory cell array comprises a plurality of memory cells arrayed along a second direction and a third direction, and a plurality of bit lines located on one side of the memory cells along the first direction, wherein the bit lines of the memory cell array are connected with the bit lines located at a preset distance along the second direction in the adjacent memory cell array; and wherein the first direction, the second direction and the third direction intersect with each other.

[0005] In one embodiment, the plurality of memory cell arrays comprises: a first memory cell array comprising a plurality of first memory cells arrayed along the second direction and the third direction, and a plurality of first bit lines located on one side of the plurality of first memory cells along the first direction; and a second memory cell array located on one side of the first memory cell array along the first direction, and comprising a plurality of second memory cells arrayed along the second direction and the third direction, and a plurality of second bit lines located on one side of the second memory cells along the first direction; wherein the preset distance comprises a first preset distance, and the first bit line is connected with the second bit line located at the first preset distance along the second direction.

[0006] In one embodiment, the semiconductor structure further comprises a sense amplifier, wherein the first bit line is connected with the sense amplifier via the second bit line connected therewith.

[0007] In an embodiment, the first bit line and the second bit line both extend along the third direction and are connected with the first memory cell and the second memory cell distributed along the third direction, respectively.

[0008] In an embodiment, the first preset distance is greater than or equal to a distance between the first bit line and the second bit line adjacent along the second direction.

[0009] In an embodiment, the plurality of memory cell arrays further comprise: a third memory cell array located at one side of the second memory cell array along the first direction and comprising a plurality of third memory cells arrayed along the second direction and the third direction, and a plurality of third bit lines located at one side of the third memory cells along the first direction; wherein the preset distance further comprises a second preset distance, the second bit line is connected with the third bit line at a second preset distance along the second direction, the first bit line is connected with the sense amplifier via the second bit line and the third bit line, and the second preset distance is greater than or equal to a distance between the second bit line and the third bit line adjacent along the second direction.

[0010] In an embodiment, the first memory cell comprises: a channel structure comprising a first end and a second end opposite along the first direction, wherein the first bit line is located at one side of the first end along the first direction; and a capacitor located at one side of the second end along the first direction.

[0011] In an embodiment, the first memory cell array further comprises: a word line extending along the second direction and connected with a plurality of the first memory cells distributed along the second direction.

[0012] In an embodiment, a material of the channel structure comprises a metal oxide semiconductor.

[0013] In an embodiment, the metal oxide semiconductor comprises indium gallium zinc oxide.

[0014] In an embodiment, in response to applying a voltage to a plurality of the first bit lines, a logic potential of at least two adjacent first bit lines is different, and a logic potential of the connected first bit line and the second bit line is the same, wherein a number of the second bit lines adjacent and having the same logic potential is greater than or equal to a number of the first bit lines adjacent and having the same logic potential.

[0015] In one embodiment, in response to applying voltages to the plurality of first bit lines, the logical potentials of at least two adjacent first bit lines are different, and the logical potentials of the connected first bit lines, second bit lines and third bit lines are the same, wherein the number of adjacent third bit lines with the same logical potential is greater than or equal to the number of adjacent first bit lines and / or second bit lines with the same logical potential; and / or the number of adjacent second bit lines with the same logical potential is greater than or equal to the number of adjacent first bit lines with the same logical potential.

[0016] In one embodiment, the semiconductor structure further comprises a peripheral circuit, wherein the sense amplifier is located in the peripheral circuit.

[0017] In one embodiment, the preset distance is greater than or equal to 15 nanometers.

[0018] Another aspect of the present application provides a method for manufacturing a semiconductor structure. The method comprises: forming a plurality of memory cell arrays distributed along a first direction, wherein the memory cell arrays comprise a plurality of memory cells arrayed along a second direction and a third direction, and a plurality of bit lines located on one side of the memory cells along the first direction; and connecting the bit lines of the memory cell arrays with bit lines of adjacent memory cell arrays located at a preset distance along the second direction; wherein the first direction, the second direction and the third direction are orthogonal to each other.

[0019] In one embodiment, forming a plurality of memory cell arrays distributed along a first direction comprises: forming a first memory cell array comprising a plurality of first memory cells arrayed along a second direction and a third direction, and a plurality of first bit lines located on one side of the plurality of first memory cells along the first direction; and forming a second memory cell array on one side of the first memory cell array along the first direction, comprising a plurality of second memory cells arrayed along the second direction and the third direction, and a plurality of second bit lines located on one side of the second memory cells along the first direction; wherein the preset distance comprises a first preset distance, and connecting the bit lines of the memory cell arrays with bit lines of adjacent memory cell arrays located at a preset distance along the second direction comprises: connecting the first bit lines with the second bit lines located at the first preset distance along the second direction.

[0020] In one embodiment, the method further comprises: connecting the first bit lines to a sense amplifier via the second bit lines connected thereto.

[0021] In one embodiment, the first storage unit includes a channel structure and a capacitor, and forming the array of first storage units includes: forming a plurality of the capacitors arrayed along the second direction and the third direction; forming a plurality of the channel structures on a side of the capacitors along the first direction; and forming a plurality of the first bit lines on a side of the channel structures along the first direction.

[0022] In one embodiment, forming the array of first storage units further includes forming a word line extending along the second direction and connected with a plurality of the first storage units arrayed along the second direction.

[0023] In one embodiment, forming the array of second storage units includes: forming the second storage units on a side of the array of first storage units along the first direction; and forming the second bit lines on a side of the second storage units along the first direction.

[0024] In one embodiment, forming the plurality of arrays of storage units arrayed along the first direction further includes: forming, on a side of the array of second storage units along the first direction, a third array of storage units including a plurality of third storage units arrayed along the second direction and the third direction, and a plurality of third bit lines on a side of the third storage units along the first direction; wherein the predetermined distance further includes a second predetermined distance connecting the bit lines of the array of storage units with bit lines of an adjacent array of storage units arrayed along the second direction at a predetermined distance, including: connecting the first bit lines with the second bit lines at the first predetermined distance along the second direction; and connecting the second bit lines with the third bit lines at the second predetermined distance along the second direction; wherein the first bit lines are connected with the sense amplifier via the second bit lines and the third bit lines, and the second predetermined distance is greater than or equal to a distance between the second bit lines and the third bit lines adjacent along the second direction.

[0025] Another aspect of the present application provides a memory system including the semiconductor structure as described above; and a controller coupled to the semiconductor structure for controlling the semiconductor structure to store data. BRIEF DESCRIPTION OF DRAWINGS

[0026] Other features, objects, and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments thereof as taken in conjunction with the accompanying drawings. In the drawings:

[0027] Figure 1 is a partial structural schematic diagram of a semiconductor structure according to an example embodiment of the present application;

[0028] Figure 2is a schematic diagram of spatial position distribution and connection mode of the first bit line and the second bit line according to an example embodiment of the present application;

[0029] Figures 3A-3H are respectively Figure 2 is a projection position distribution diagram of the connected first bit line and the second bit line in the second direction Y and the third direction X in the plane formed by the second direction Y and the third direction X in

[0030] Figure 4 is a logical potential distribution diagram of the bit lines 1121-1128 and the bit lines 1221-1228 according to an example embodiment of the present application;

[0031] Figure 5 is a logical potential distribution diagram of the bit lines 1121-1128 and the bit lines 1226-1228 according to another example embodiment of the present application;

[0032] Figure 6A is a structural schematic diagram of a sense amplifier according to an example embodiment of the present application;

[0033] Figure 6B is a partial circuit structural schematic diagram of the first memory cell array or the second memory cell array according to an example embodiment of the present application;

[0034] Figure 7 is Figure 1 is an enlarged view of a partial structure in Figure 8 is a partial structural schematic diagram of a semiconductor structure according to another example embodiment of the present application;

[0035] Figure 9 is a schematic diagram of spatial position distribution and connection mode of the first bit line, the second bit line and the third bit line according to another example embodiment of the present application;

[0036] Figures 10A-10H are respectively Figure 9 is a projection position distribution diagram of the connected second bit line and the third bit line in the second direction Y and the third direction X in the plane formed by the second direction Y and the third direction X in

[0037] Figure 11 is a logical potential distribution diagram of the bit lines 2121-2128, the bit lines 2221-2228 and the bit lines 2321-2328 according to an example embodiment of the present application;

[0038] Figure 12 is a logical potential distribution diagram of the bit lines 2121-2128, the bit lines 2221-2228 and the bit lines 2321-2328 according to another example embodiment of the present application;

[0039] Figure 13 is a flowchart of a method of manufacturing a semiconductor structure according to an example embodiment of the present application; and

[0040] Figure 14 is an example block diagram of a system having a storage system according to an example embodiment of the present application. DETAILED DESCRIPTION

[0041] For a better understanding of the present application, various aspects of the present application will be described in greater detail below with reference to the accompanying drawings. It is to be noted that these detailed descriptions are merely exemplary of the present application and are not intended to limit the scope of the present application in any way.

[0042] It should be noted that in this specification, the terms first, second, third, etc. are used merely to distinguish one feature from another, and do not imply any priority or order of one feature over another. Thus, the first memory cell array discussed in the present application can also be referred to as a second memory cell array, the first direction can also be referred to as a second direction, a third direction, and vice versa, without departing from the teachings of the present application.

[0043] In the drawings, the thicknesses of the components, the sizes, and the shapes are slightly adjusted for the sake of explanation. The drawings are merely examples and are not strictly drawn to scale. As used in this document, the terms "substantially," "approximately," and similar terms are used as terms of approximation and are not used as terms of degree, and are intended to account for the inherent deviations in measuring or calculating values that would be recognized by those of ordinary skill in the art.

[0044] Further, in this document, when a part is described as being "on" another part, for example, "on," "above," and "over," the meanings are to be interpreted in the broadest possible manner such that "on" means not only "directly on" but also "on" with an intervening feature or layer between the part and the other part, and "above" or "over" does not mean only "above" or "over" in the direction of gravity but also can include "above" or "over" without an intervening feature or layer (i.e., directly on) as well as the meaning of "above" or "over" with an intervening feature or layer.

[0045] It should also be understood that all references to the application herein using expressions such as "including", "containing" and / or "comprising" or "having" refer to the presence of stated features, elements and / or components but do not preclude the presence or addition of one or more other features, elements, components and / or groups thereof. In addition, when describing the application, the use of "or" means "and / or" unless clearly indicated otherwise or dictated by context. Furthermore, the use of the term "including" along with embodiments of the application does not exclude the presence of additional analogous elements or steps. Furthermore, the word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. In addition, "consisting essentially of" or "consisting of" shall not preclude the inclusion of non-substantial elements or steps of insubstantial nature. The use of the term "about" in relation to a numerical value shall mean that the value in question can vary by ±10%.

[0046] The exemplary embodiments disclosed herein are described with reference to the drawings. The exemplary embodiments disclosed herein are not to be construed as limiting the specific shape and size of the drawings, but include various equivalent structures capable of achieving the same function and shape and size deviations resulting from, for example, manufacturing. The positions shown in the drawings are schematic in nature and are not intended to limit the positions of the components.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in a generally used dictionary should be interpreted as having a meaning consistent with its meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0048] As used herein, the term "layer" refers to a portion of material that includes a region having a height. A layer can be a region of a uniform or non-uniform continuous structure having a height less than the height of the continuous structure. For example, a layer can be located at the top surface and the bottom surface of a continuous structure or between any set of horizontal planes therebetween. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above, and / or below. A layer can include multiple layers.

[0049] Furthermore, in the present application, when "connected" or "coupled" is used, it means direct or indirect contact between the corresponding parts, unless expressly defined otherwise or derivable from the context.

[0050] It should be noted that the embodiments and features of the application can be combined with each other, as far as there is no conflict. In addition, the specific steps included in the method described in the present application are not necessarily limited to the order described, but can be executed in any order or in parallel, unless expressly defined or contrary to the context. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0051] The semiconductor structure provided by the present application can include a storage device with storage function. Exemplarily, the storage device can include at least one of dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), magnetoresistive random access memory (MRAM), and resistive random access memory (RRAM), for example. For ease of description, the following mainly takes DRAM memory as an example for introduction.

[0052] Figure 1 is a partial structure schematic diagram of a semiconductor structure 1000 according to an exemplary embodiment of the present application.

[0053] The semiconductor structure 1000 can include a plurality of storage cell arrays, such as a first storage cell array 1100 and a second storage cell array 1200. The plurality of storage cell arrays can be distributed along a first direction Z, such as the first storage cell array 1100 and the second storage cell array 1200 can be adjacently distributed along the first direction Z. Exemplarily, the second storage cell array 1200 can be located at one side of the first storage cell array 1100 along the first direction Z.

[0054] The first storage cell array 1100 can include a plurality of storage cells, such as a first storage cell 1110, and a plurality of bit lines, such as a first bit line 1120. The plurality of first storage cells 1110 can be arrayed along a second direction Y and a third direction X. The plurality of first bit lines 1120 can be located at one side of the plurality of first storage cells 1110 along a first direction Z. The second storage cell array 1200 can include a plurality of storage cells, such as a second storage cell 1210, and a plurality of bit lines, such as a second bit line 1220. The plurality of second storage cells 1210 can be arrayed along the second direction Y and the third direction X. The plurality of bit lines 1220 can be located at one side of the storage cells 1210 along the first direction Z. Exemplarily, the first direction Z, the second direction Y, and the third direction X can intersect with each other. The storage cell array 1100 and the storage cell array 1200 can be DRAM cell arrays. The first storage cell 1110 and the second storage cell 1210 can be DRAM cells.

[0055] Figure 2 is a spatial position distribution and connection mode schematic diagram of the first bit line 1120 and the second bit line 1220 according to an exemplary embodiment of the present application. Figures 3A-3H are respectively Figure 2a projection position distribution diagram of the first bit line 1120 and the second bit line 1220 in the display panel 1000 in the second direction Y and the third direction X.

[0056] As shown in the figure, Figure 2 The plurality of first bit lines 1120 can include a bit line 1121, a bit line 1122, a bit line 1123, a bit line 1124, a bit line 1125, a bit line 1126, a bit line 1127, and a bit line 1128 distributed in sequence along the second direction Y. The plurality of second bit lines 1220 can include a bit line 1221, a bit line 1222, a bit line 1223, a bit line 1224, a bit line 1225, a bit line 1226, a bit line 1227, and a bit line 1228 distributed in sequence along the second direction Y.

[0057] It should be noted that, Figure 2 In the figure, the number of the plurality of first bit lines 1120 and the plurality of second bit lines 1220 is eight. However, in actual applications, the number of the plurality of first bit lines 1120 and the plurality of second bit lines 1220 can be greater than or less than eight. The number of the plurality of first bit lines 1120 and the plurality of second bit lines 1220 is not specifically limited in the present application.

[0058] As shown in the figure,

[0059] As shown in the figure,

[0060] As shown in the figure, Figures 2-3HAs shown, the first bit line 1120 in the first memory cell array 1100 can be connected with the second bit line 1220 in the second memory cell array 1200 which is apart from the first bit line 1120 by a first preset distance S1 along the second direction Y. It should be understood that the preset distance, such as the first preset distance S1, between the connected first bit line 1120 and the second bit line 1220 along the second direction Y can be the distance between the projection of the second bit line 1220 on the plane where the first bit line 1120 is located and the first bit line 1120 along the second direction Y, or the distance between the projection of the first bit line 1120 on the plane where the second bit line 1220 is located and the second bit line 1220 along the second direction Y.

[0061] Exemplarily, the preset distance can be greater than zero, i.e., the first preset distance S1 can be greater than zero. In other words, the first bit line 1120 can be connected with the bit line in the second bit line 1220 which does not correspond to the first bit line 1120. Exemplarily, the first preset distance S1 can be greater than or equal to the distance H between the adjacent first bit line 1120 and the second bit line 1220 along the second direction Y. It should be understood that the distance H can be the distance between two adjacent first bit lines 1120 or two adjacent second bit lines 1220 along the second direction Y.

[0062] It should be noted that the preset distance, such as the first preset distance S1, and the distance H can have a multiple relationship. For example, the first preset distance S1 can be 1 times, 2 times, 3 times, etc. of the distance H. Exemplarily, the distance H can be greater than or equal to 15 nanometers, such as can be in the range of 15 nanometers to 40 nanometers. Exemplarily, the distance H can be in the range of 18 nanometers to 25 nanometers. Exemplarily, the preset distance, such as the first preset distance S1, can be greater than or equal to 15 nanometers.

[0063] As shown, Figures 3A-3H The first preset distance S1 can include a distance S11 and a distance S12. As shown, Figure 3A The distance S11 can be the distance between the first bit line 1120, such as 1121, and the second bit line 1220, such as 1223, along the second direction Y, i.e., the distance S11 can be greater than the distance H, such as the distance S11 can be twice the distance H. In other words, the distance S11 can be in the range of 30 nanometers to 80 nanometers. Exemplarily, the distance S11 can be in the range of 36 nanometers to 50 nanometers. As shown, Figure 3B The distance S12 can be the distance between the first bit line 1120, such as 1122, and the second bit line 1220, such as 1221, along the second direction Y, i.e., the distance S12 can be equal to the distance H. In other words, the distance S12 can be in the range of 15 nanometers to 40 nanometers. Exemplarily, the distance S12 can be in the range of 18 nanometers to 25 nanometers.

[0064] It should be noted that, Figures 3A-3HThe figure only illustrates two cases where the first preset distance S1 includes distance S11 and distance S12. However, in actual applications, the first preset distance S1 may include a variety of different non-zero distances. For example, the first preset distance S1 may also include distance S13 (not shown), where distance S13 is three times, four times, or five times the distance H. This application does not impose any specific restrictions on the types of the first preset distance S1.

[0065] For example, Figures 2-3H As shown, bit line 1121 may be connected to bit line 1223 at a distance S11 along the second direction Y. Bit line 1122 may be connected to bit line 1221 at a distance S12 along the second direction Y. Bit line 1123 may be connected to bit line 1225 at a distance S11 along the second direction Y. Bit line 1124 may be connected to bit line 1222 at a distance S11 along the second direction Y. Bit line 1125 may be connected to bit line 1227 at a distance S11 along the second direction Y. Bit line 1126 may be connected to bit line 1224 at a distance S11 along the second direction Y. Bit line 1127 may be connected to bit line 1228 at a distance S12 along the second direction Y. Bit line 1128 may be connected to bit line 1226 at a distance S11 along the second direction Y.

[0066] The semiconductor structure 1000 provided in the present application can be used to perform at least one operation such as reading, writing, and erasing to access memory cells such as the first memory cell 1110 and / or the second memory cell 1210. During operation, a voltage needs to be applied to, for example, the plurality of first bit lines 1120 to write storage data to, for example, the first memory cell 1110 and / or the second memory cell 1210, wherein the logic potential corresponding to the applied voltage can be 1 or 0.

[0067] It should be noted that during operation of the semiconductor structure 1000, different voltages may be applied to at least two of the plurality of first bit lines 1120, that is, the logic potentials of at least two of the plurality of first bit lines 1120 may be different. Furthermore, it should be understood that during operation of the semiconductor structure 1000, the logic potentials of the connected first bit line 1120 and second bit line 1220 are the same.

[0068] Figure 4 1 is a diagram illustrating a logic potential distribution of bit lines 1121-1128 and bit lines 1221-1228 according to an exemplary embodiment of the present application. For example, in response to applying a voltage to a plurality of first bit lines 1120 and at least two adjacent first bit lines 1120 having different logic potentials, the number of adjacent second bit lines 1220 having the same logic potential may be greater than or equal to the number of adjacent first bit lines 1120 having the same logic potential.

[0069] For example, Figure 4As shown, during operation of semiconductor structure 1000, different voltages may be applied to first bit lines, such as bit lines 1121-1128. The logic potentials of the charged bit lines 1121-1128 may be 0, 0, 1, 0, 0, 1, 0, 0, respectively. It can be seen that adjacent bit lines 1122 and 1123 have different logic potentials. Adjacent bit lines 1123 and 1124 have different logic potentials. Adjacent bit lines 1125 and 1126 have different logic potentials. Adjacent bit lines 1126 and 1127 have different logic potentials. Bit lines 1121 and 1122 (i.e., two bit lines) are adjacent and have the same logic potential, bit lines 1124 and 1125 (i.e., two bit lines) are adjacent and have the same logic potential, and bit lines 1127 and 1128 (i.e., two bit lines) are adjacent and have the same logic potential. In other words, the number of adjacent first bit lines 1120 with the same logic potential may be two.

[0070] Since the connected first bit line 1120 and second bit line 1220 have the same logic potential, the logic potentials of the second bit lines (e.g., bit lines 1221-1228) corresponding to the first bit lines (e.g., bit lines 1121-1128) can be 0, 0, 0, 1, 1, 0, 0, 0, respectively. It can be seen that bit lines 1221-1223 (i.e., three bit lines) are adjacent and have the same logic potential, bit lines 1224 and 1225 (i.e., two bit lines) are adjacent and have the same logic potential, and bit lines 1226-1228 (i.e., three bit lines) are adjacent and have the same logic potential. In other words, the number of adjacent second bit lines 1220 with the same logic potential can be three or two.

[0071] As can be seen from the above, the number of adjacent second bit lines 1220 with the same logic potential, such as 3 or 2, may be greater than or equal to the number of adjacent first bit lines 1120 with the same logic potential, such as 2.

[0072] Figure 5 1 is a logic potential distribution diagram of the bit lines 1121 ˜ 1128 and the bit lines 1226 ˜ 1228 provided according to another exemplary embodiment of the present application.

[0073] like Figure 5 As shown, during operation of semiconductor structure 1000, different voltages may be applied to first bit lines, such as bit lines 1121-1128. The logic potentials of the charged bit lines 1121-1128 may be 0, 1, 0, 1, 0, 1, 0, 1, respectively. As can be seen, any two adjacent bit lines 1121-1128 have different logic potentials. In other words, the number of adjacent first bit lines 1120 with the same logic potential may be zero.

[0074] Since the logic potentials of the connected first bit lines 1120 and second bit lines 1220 are the same, the logic potentials of the second bit lines, such as bit lines 1221-1228, corresponding to the first bit lines, such as bit lines 1121-1128, can be 1, 1, 0, 1, 0, 1, 0, 0, respectively. It can be seen that the bit lines 1221 and 1222 (i.e., two bit lines) are adjacent and have the same logic potential, and the bit lines 1227 and 1228 (i.e., two bit lines) are adjacent and have the same logic potential. In other words, the number of adjacent second bit lines 1220 with the same logic potential can be 2.

[0075] As can be seen from the above, the number of adjacent second bit lines 1220 with the same logic potential, such as 2, can be greater than or equal to the number of adjacent first bit lines 1120 with the same logic potential, such as 0.

[0076] Generally, during operation of the semiconductor structure, the number of adjacent first bit lines with the same logic potential is small. In this way, it can cause the first bit line with a logic potential of 1 (i.e., a high-voltage bit line) to be pulled down by the adjacent first bit line with a logic potential of 0 (i.e., a low-voltage bit line), thereby causing the potential of the first bit line with a logic potential of 1 to decrease, and the coupling phenomenon between adjacent bit lines to be aggravated.

[0077] Based on this, the present application is configured to connect the first bit line to the second bit line spaced apart from the first bit line along the second direction by a first preset distance, which is beneficial to increase the number of adjacent second bit lines with the same logic potential, thereby facilitating the adjacent second bit lines to have the same logic potential, so as to make the voltage of the second bit line more stable, reduce the phenomenon of parasitic capacitance caused by the different logic potentials of adjacent second bit lines, and thereby facilitate to improve the sense margin.

[0078] Exemplarily, as shown in Figure 1 , the semiconductor structure 1000 can further include a sense amplifier 1300. The first bit line 1120 can be connected to the sense amplifier 1300 via the second bit line 1220 connected thereto. The sense amplifier 1300 can be a differential amplifier, and in a read operation, the two ends (such as the first input end 1320 and the second input end 1330 shown in Figure 6A ) of the sense amplifier 1300 can be the sensing signals on a pair of bit lines. The connection of one end of the sense amplifier 1300, such as the first input end 1320, to the second bit line 1220 is beneficial to improve the read accuracy of the sense amplifier 1300, thereby facilitating to improve the sense margin.

[0079] Figure 6Ais a structural schematic diagram of a sense amplifier (SA) 1300 according to an exemplary embodiment of the present application. Exemplarily, the sense amplifier 1300 can include a sense amplification module 1310, a first input end 1320 and a second input end 1330. Taking a second bit line 1220 in a bit line 100 in another memory array as a target bit line and a bit line 100 as a reference bit line as an example, the sense amplifier 1300 can utilize the principle of differential amplification to sense and amplify a tiny voltage change on the target bit line, such as the second bit line 1220, so as to realize signal reading and writing, refreshing and the like.

[0080] Exemplarily, the sense amplification module 1310 can include a plurality of transistors (not shown) for sensing and amplifying a voltage difference signal on the target bit line, such as the second bit line 1220, and the reference bit line, such as the bit line 100. The first input end 1320 can be connected to the sense amplification module 1310 and the second bit line 1220, and the first input end 1320 can be controlled by a first control signal ISOT. The second input end 1330 can be connected to the sense amplification module 1310 and the bit line 100, and the second input end 1330 can be controlled by a second control signal ISOB.

[0081] In response to the first input end 1320 being in a conductive state, the second bit line 1220 is connected to the sense amplification module 1310. In response to the first input end 1320 being in a non-conductive state, the second bit line 1220 is isolated from the sense amplification module. In response to the second input end 1330 being in a conductive state, the bit line 100 is connected to the sense amplification module 1310. In response to the second input end 1330 being in a non-conductive state, the bit line 100 is isolated from the sense amplification module 1310. It can be seen that the first input end 1320 and the second input end 1330 can be respectively turned on at different times under the control of the first control signal ISOT and the second control signal ISOB. In other words, the second bit line 1220 and the bit line 100 can be connected to the sense amplification module 1310 at different times. In this way, the second bit line 1220 and the bit line 100 can be respectively charged or discharged through the sense amplification module 1310 at different times, and before this, the second bit line 1220 and the bit line 100 can be maintained in a charge sharing state.

[0082] Since the first control signal ISOT and the second control signal IOSB can switch the first input 1320 and the second input 1330 to the conductive state at different time, respectively, the corresponding second bit line 1220 and the bit line 100 will be charged or discharged in turn. In this way, the voltage difference on the second bit line 1220 and the bit line 100 will be increased in the period when one of the first input 1320 and the second input 1330 is conductive and the other is non-conductive, so as to achieve the increase of the sensing margin.

[0083] Figure 6B Fig. 1 shows a schematic diagram of a portion of a first memory cell array 1100 or a second memory cell array 1200 according to an example embodiment of the present application.

[0084] For example, as shown in Fig. 1, the first bit line 1120 can extend along a third direction X and can be connected with the first memory cells 1110 distributed along the third direction X. The second bit line 1220 can extend along the third direction X and can be connected with the second memory cells 1210 distributed along the third direction X. For example, the first memory cell array 1100 can further include word lines 1130 extending along a second direction Y and connected with a plurality of the first memory cells 1110 distributed along the second direction Y. The second memory cell array 1200 can further include word lines 1230 extending along the second direction Y and connected with a plurality of the second memory cells 1210 distributed along the second direction Y. Figure 6B For example, the first memory cell 1110 can include a capacitor 1112 for storing a bit of data as a positive or negative charge and one or more transistors 1111’ (also known as pass transistors) for controlling (e.g., switching and selecting) access to the same, which will be described in detail below. For example, the transistors 1111’ can be vertical transistors such as vertical metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0085] The word lines 1130 can be coupled to the first memory cells 1110 along the second direction Y for controlling switching of the transistors 1111’ in the first memory cells 1110 located in a row along the second direction Y. The bit lines 1120 can be coupled to the first memory cells 1110 along the third direction X for sending data to and / or receiving data from the first memory cells 1110 located in a column along the third direction X. That is, each word line 1130 can be coupled to the first memory cells 1110 of a corresponding row and each bit line 1120 can be coupled to the first memory cells 1110 of a corresponding column.

[0086]

[0087] ​Exemplarily, the gate of the transistor 1111' can be connected with the word line 1130, the drain can be connected with the bit line 1120, and the source can be connected with the capacitor 1112. A voltage signal on the word line 1130 can control the opening or closing of the transistor 1111', so as to read data information stored in the capacitor 1112 through the bit line 1120 or write data information into the capacitor 1112 through the bit line 1120 for storage.

[0088] Exemplarily, as shown in FIG. 11B, the transistor 1111' can include a channel structure 1111 and a gate structure 1113 corresponding to a portion of the channel structure 1111. Figure 1 Exemplarily, the channel structure 1111 (i.e., the first extension 1111-1 and the second extension 1111-2) can include one or more of a polycrystalline silicon (Poly-Si), an amorphous silicon (a-Si), a metal oxide semiconductor (e.g., indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium tin oxide (ITO)), and the like semiconductor material. Exemplarily, the material of the channel structure 1111 can be a low-temperature material such as indium gallium zinc oxide (IGZO).

[0089] Exemplarily, the channel structure 1111 (i.e., the first extension 1111-1 and the second extension 1111-2) can include one or more of a polycrystalline silicon (Poly-Si), an amorphous silicon (a-Si), a metal oxide semiconductor (e.g., indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium tin oxide (ITO)), and the like semiconductor material. Exemplarily, the material of the channel structure 1111 can be a low-temperature material such as indium gallium zinc oxide (IGZO).

[0090] In the present application, by setting the material of the channel structure 1111 as a low-temperature material such as indium gallium zinc oxide (IGZO), it is beneficial to form the channel structure 1111 in a lower temperature environment. In this way, not only is it beneficial to improve the density of the channel structure 1111, but it is also beneficial to reduce the damage to other components of the semiconductor structure in a high-temperature environment, such as softening, bending, and the like, thereby facilitating the implementation of more stacked layers, such as the subsequent formation of a second memory cell array 1200 on the first memory cell array 1100, and improving the storage density of the semiconductor structure. In addition, such a setting can also significantly reduce the channel leakage current, improve the data retention characteristics, and improve the sensing margin.

[0091] Exemplarily, a plurality of channel structures 1111 can be arrayed along the second direction Y and the third direction X. In other words, the plurality of channel structures 1111 can be spaced apart along the second direction Y and the third direction X.

[0092] Exemplarily, the gate structure 1113 can be located at one side of the second extension 1111-2 along the first direction Z and opposite to the partial first extension 1111-1 along the third direction X. The gate structure 1113 can extend along the second direction Y and the first direction Z, where an extension size of the gate structure 1113 along the first direction Z can be smaller than an extension size of the first extension 1111-1 along the first direction Z.

[0093] Exemplarily, the gate structure 1113 can include a gate layer (not shown) and a gate dielectric layer (not shown) located between the gate layer and the channel structure 1111. Exemplarily, the gate dielectric layer can include any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride, or high-k material. For example, the gate dielectric layer can include silicon oxide. The gate layer can include one or more conductive materials, for example, metals and / or metal compounds, for example, tungsten W and / or titanium nitride TiN. The gate structure 1113 can be connected with the peripheral circuit 1500 to realize transmission of electrical signals between the gate electrode and the peripheral circuit 1500, where the peripheral circuit 1500 will be described in detail below.

[0094] Figure 7 is Figure 1 Exemplarily, the channel structure 1111 can include a first end 1111-3 and a second end 1111-4 opposite along the first direction Z, where the first end 1111-3 can include an end of the first extension 1111-1 away from the second extension 1111-2 along the first direction Z, and the second end 1111-4 can include at least a part of the second extension 1111-2.

[0095] In the transistor 1111’, the first extension 1111-1 can serve as a channel, the gate structure 1113 corresponding to a part of the first extension 1111-1 can serve as a gate, and the first end 1111-3 and the second end 1111-4 can respectively serve as one of a source and a drain. The gate structure 1113 extending along the second direction Y can be used to control a row of transistors arranged along the second direction Y.

[0096] In this application, the first extension 1111-1 serving as a channel of the transistor is conducive to making the transistor structure more compact, can effectively reduce the planar occupation area, realize more stacked layers, improve the storage density of the semiconductor structure, and is also conducive to improving the iterative micro- shrinking ability of the feature size of the semiconductor structure.

[0097] Exemplarily, as Figure 1As shown, the first memory cell array 1100 can also include a capacitor contact structure 1140. The capacitor contact structure 1140 can be connected with at least a portion of the second end 1111-4, such as the second extension 1111-2. The material of the capacitor contact structure 1140 can include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), metal silicide (e.g., titanium silicide (TiSi2), cobalt silicide (CoSi2), nickel platinum silicide (NiPtSi)), or any other suitable conductive material. Exemplarily, the second end 1111-4 can be in direct contact with the capacitor contact structure 1140 to increase the contact area of both, to improve the transmission efficiency, and to ensure the electrical connection reliability.

[0098] Exemplarily, as shown, Figure 1 The first bit line 1120 can be connected with the first end 1111-3, such as the first extension 1111-1, of the plurality of channel structures 1111 distributed along the third direction X away from the end of the second extension 1111-2 along the first direction Z. The capacitor 1112 can be connected with at least a portion of the second end 1111-4, such as the second extension 1111-2. For example, the capacitor 1112 can be connected with the second end 1111-4 via the capacitor contact structure 1140.

[0099] Exemplarily, the capacitor 1112 can include a first electrode layer 1112-1, a second electrode layer 1112-2, and a capacitor dielectric layer 1112-3 between the first electrode layer 1112-1 and the second electrode layer 1112-2. The first electrode layer 1112-1 can be located on the side of the capacitor contact structure 1140 away from the channel structure 1111 and extend along the third direction X. The second electrode layer 1112-2 can be located in the first electrode layer 1112-1, for example, the second electrode layer 1112-2 can at least partially penetrate the first electrode layer 1112-1. The second electrode layer 1112-2 can be substantially a columnar structure. The second electrode layer 1112-2 can be connected with the capacitor contact structure 1140, i.e., the second electrode layer 1112-2 can be connected with the second end 1111-4 of the channel structure 1111 via the capacitor contact structure 1140. The capacitor dielectric layer 1112-3 can be substantially a barrel structure with an open end, the second electrode layer 1112-2 can be located in the capacitor dielectric layer 1112-3, and the open end of the capacitor dielectric layer 1112-3 can be towards the capacitor contact structure 1140, so that the second electrode layer 1112-2 is in direct contact with the capacitor contact structure 1140.

[0100] Exemplarily, the material of the first electrode layer 1112-1 and the second electrode layer 1112-2 can include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material. The material of the capacitor dielectric layer 1112-3 can include one or more of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or any other suitable insulating material. x N y ) or any other suitable insulating material.

[0101] As mentioned above, the first electrode layer 1112-1, the capacitor dielectric layer 1112-3, and the second electrode layer 1112-2 can be used to form a capacitor 1112. One electrode (e.g., the second electrode layer 1112-2) of the capacitor 1112 is connected to one of the source or the drain (e.g., the first end 1111-3 or the second end 1111-4) of the transistor 1111’ through the capacitor contact structure 1140. The transistor 1111’ and the capacitor 1112 can constitute a first memory cell 1110 (e.g., a DRAM memory cell). The other electrodes (e.g., the first electrode layer 1112-1) of a plurality of capacitors 1112 can be connected to each other.

[0102] It is to be noted that the capacitor can also be implemented in other structure types, for example, the capacitor can be constituted by conductive layers, insulating layers, and conductive layers (not shown) stacked in the first direction Z in sequence. The structure of the capacitor is not specifically limited in the present application, and the capacitor can be implemented in any known structure type in the art.

[0103] Exemplarily, the first bit line 1120 can extend along the third direction X and be connected (e.g., directly contact) to the first end 1111-3 of the channel structure 1111. The first bit line 1120 can be connected to each first end 1111-3 in a column of channel structures 1111 arranged along the third direction X. Thus, one of the source or the drain of a column of transistors 1111’ arranged along the third direction X is connected to the same first bit line 1120. Exemplarily, the material of the first bit line 1120 can include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material.

[0104] Exemplarily, as mentioned above, the first bit line 1120 can extend along the third direction X and be connected (e.g., directly contact) to the first end 1111-3 of the channel structure 1111. The first bit line 1120 can be connected to each first end 1111-3 in a column of channel structures 1111 arranged along the third direction X. Thus, one of the source or the drain of a column of transistors 1111’ arranged along the third direction X is connected to the same first bit line 1120. Exemplarily, the material of the first bit line 1120 can include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material. Figure 1As shown, the first memory cell array 1100 may further include an electrode plate 1150 for connecting the first electrode layers 1112-1 of the plurality of capacitors 1112. Furthermore, the first memory cell array 1100 may further include a support layer 1160 located between adjacent capacitor dielectric layers 1112-3 and corresponding to the first electrode layer 1112-1 along the first direction Z. The support layer 1160 may provide support, thereby facilitating improvement in the mechanical strength of the capacitor 1112 structure and reducing damage to the capacitor 1112 during a formation process (e.g., grinding).

[0105] For example, the material of the electrode plate 1150 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material. The material of the support layer 1160 may include any one of silicon nitride, silicon oxynitride, aluminum oxide, etc., or a combination of any two or more thereof. For example, the material of the support layer 1160 may include silicon nitride.

[0106] For example, Figure 1 As shown, the semiconductor structure 1000 may further include a dielectric layer 1900. The dielectric layer 1900 may be located on one side of the first memory cell array 1100 along the first direction Z, and is used to support the second memory cell array 1200. In other words, the dielectric layer 1900 may be located between the first memory cell array 1100 and the second memory cell array 1200. The material of the dielectric layer 1900 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating materials.

[0107] It should be noted that the structure of the second memory cell array 1200 is substantially the same as or similar to that of the first memory cell array 1100. For the purpose of brevity, other structures of the second memory cell array 1200 that are the same as or similar to those of the first memory cell array 1100 are not further described in this application.

[0108] In the present application, by integrating the first memory cell array 1100 and the second memory cell array 1200 in the first direction Z, the plane area of ​​the semiconductor structure can be saved and the storage density can be effectively improved.

[0109] For example, Figure 1As shown, the semiconductor structure 1000 can also include a substrate 1400, where the first array of memory cells 1100 can be located on one side of the substrate 1400 along the first direction Z. The material of the substrate 1400 can include at least one of single crystalline silicon, polycrystalline silicon, single crystalline germanium, a III-V compound semiconductor material, a II-VI compound semiconductor material, or other semiconductor materials known in the art.

[0110] As shown, the semiconductor structure 1000 can also include a peripheral circuit 1500, where the sense amplifier 1300 can be located in the peripheral circuit 1500. The peripheral circuit 1500 (also referred to as a control and sense circuit) can also include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of memory cell arrays, such as the first array of memory cells 1100 and / or the second array of memory cells 1200. As shown, the peripheral circuit 1500 includes a plurality of control circuits for connection with the first memory cells 1110, the first bit lines 1120, the first word lines 1130, the second memory cells 1210, the second bit lines 1220, and the second word lines 1230, respectively, to transmit electrical signals therebetween. Figure 1

[0111] As shown, the semiconductor structure 1000 can also include a peripheral circuit 1500, where the sense amplifier 1300 can be located in the peripheral circuit 1500. The peripheral circuit 1500 (also referred to as a control and sense circuit) can also include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of memory cell arrays, such as the first array of memory cells 1100 and / or the second array of memory cells 1200. As shown, the peripheral circuit 1500 includes a plurality of control circuits for connection with the first memory cells 1110, the first bit lines 1120, the first word lines 1130, the second memory cells 1210, the second bit lines 1220, and the second word lines 1230, respectively, to transmit electrical signals therebetween.

[0112] As shown, the semiconductor structure 1000 can also include a peripheral circuit 1500, where the sense amplifier 1300 can be located in the peripheral circuit 1500. The peripheral circuit 1500 (also referred to as a control and sense circuit) can also include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of memory cell arrays, such as the first array of memory cells 1100 and / or the second array of memory cells 1200. As shown, the peripheral circuit 1500 includes a plurality of control circuits for connection with the first memory cells 1110, the first bit lines 1120, the first word lines 1130, the second memory cells 1210, the second bit lines 1220, and the second word lines 1230, respectively, to transmit electrical signals therebetween. Figure 1 As shown, the semiconductor structure 1000 can also include a peripheral circuit 1500, where the sense amplifier 1300 can be located in the peripheral circuit 1500. The peripheral circuit 1500 (also referred to as a control and sense circuit) can also include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of memory cell arrays, such as the first array of memory cells 1100 and / or the second array of memory cells 1200. As shown, the peripheral circuit 1500 includes a plurality of control circuits for connection with the first memory cells 1110, the first bit lines 1120, the first word lines 1130, the second memory cells 1210, the second bit lines 1220, and the second word lines 1230, respectively, to transmit electrical signals therebetween.

[0113] Figure 1 ​​As shown, the semiconductor structure 1000 can further include a gate lead-out structure 1710, a bit line lead-out structure 1720, and a capacitor lead-out structure 1730. The gate structures in the first memory cell array 1100 and the second memory cell array 1200, such as the gate structure 1113, the bit lines, such as the first bit line 1120 and the second bit line 1220, and the capacitors, such as the capacitor 1112, can be connected to the peripheral circuitry through the gate lead-out structure 1710, the bit line lead-out structure 1720, and the capacitor lead-out structure 1730, respectively, to facilitate signal transmission between the control circuitry and the gate structures, the bit lines, and the capacitors. Exemplarily, the materials of the gate lead-out structure 1710, the bit line lead-out structure 1720, and the capacitor lead-out structure 1730 can all include conductive materials.

[0114] Exemplarily, the first bit line 1120 and the second bit line 1220 can be connected through the bit line lead-out structure 1720 and / or other metal wiring. The first bit line 1120 can be connected to the sense amplifier 1300 via the second bit line 1220 connected thereto.

[0115] Exemplarily, as shown in FIG. 1A, Figure 1 As shown, the semiconductor structure 1000 can further include an interconnection line 1810 and an interconnection via 1820. The interconnection line 1810 can be located on the peripheral circuitry 1500. The interconnection via 1820 can be connected to the interconnection line 1810 and extend to the peripheral circuitry 1500. The interconnection line 1810 and the interconnection via 1820 can be used to connect the peripheral circuitry 1500 and a power line (not shown), which is advantageous to shorten the length of the interconnection structure between the peripheral circuitry 1500 and the power line, thereby reducing the parasitic capacitance of the interconnection structure, improving the sensing margin and the storage density of the semiconductor structure.

[0116] Exemplarily, as shown in FIG. 1A, Figure 1 As shown, the semiconductor structure 1000 can further include a pad lead-out structure 1830 located on one side of the interconnection line 1810 and extending to the first memory cell array 1100. The pad lead-out structure 1830 can transmit electrical signals between the semiconductor structure 1000 and an external circuit. The pad lead-out structure 1830 can include conductive materials, including but not limited to W, Cu, Al, doped silicon, silicide, or any combination thereof.

[0117] Figure 8 is a partial structure schematic diagram of a semiconductor structure 2000 according to another exemplary embodiment of the present application. Compared with the semiconductor structure 1000 shown in FIG. 1A, Figure 1 the semiconductor structure 2000 shown in FIG. 2A, Figure 8 some components in the semiconductor structure 2000 are omitted.

[0118] The semiconductor structure 2000 can include a plurality of memory cell arrays, such as a first memory cell array 2100, a second memory cell array 2200, and a third memory cell array 2300.

[0119] The structures of the first memory cell array 2100 and the second memory cell array 2200 are similar to those of the first memory cell array 1100 and the second memory cell array 1200, respectively. For the purpose of brevity, the present application will not be described in detail here, and the reader can refer to the above description of the structures of the first memory cell array 1100 and the second memory cell array 1200.

[0120] The first memory cell array 2100 can include a plurality of first bit lines 2120, and the second memory cell array 2200 can include a plurality of second bit lines 2220. The plurality of first bit lines 2120 and the plurality of second bit lines 2220 can be connected, and their structures, spatial position distributions, and connection manners are similar to those of the plurality of first bit lines 1120 and the plurality of second bit lines 1220 shown in FIG. 1B. For the purpose of brevity, the present application will not be described in detail here, and the reader can refer to the above description of the first bit lines 1120 and the second bit lines 1220. Figures 1-3H

[0121] The third memory cell array 2300 can be located at one side of the second memory cell array 2200 along the first direction Z. The third memory cell array 2300 can include a plurality of third memory cells 2310 arranged in the second direction Y and the third direction X, and a plurality of third bit lines 2320 located at one side of the third memory cells 2310 along the first direction Z. Exemplarily, the plurality of third bit lines 2320 can be connected with the plurality of second bit lines 2220.

[0122] It should be noted that the structure of the third memory cell array 2300 is substantially the same as or similar to that of the first memory cell array 2100 and / or the second memory cell array 2200. For the purpose of brevity, the present application will not be described in detail here for other structures in the third memory cell array 2300 that are the same as or similar to those in the first memory cell array 2100 and / or the second memory cell array 2200.

[0123] Figure 9 is a schematic diagram of the spatial position distribution and the connection manner of the first bit lines 2120, the second bit lines 2220, and the third bit lines 2320 according to another exemplary embodiment of the present application. Figures 10A-10H is a schematic diagram of the spatial position distribution and the connection manner of the first bit lines 2120, the second bit lines 2220, and the third bit lines 2320 according to another exemplary embodiment of the present application. Figure 9 is a projection position distribution diagram of the connected second bit lines 2220 and the third bit lines 2320 in the second direction Y and the third direction X in the plane formed by the second direction Y and the third direction X in FIG. 2B.

[0124] Exemplarily, as shown in FIG. 2B, Figure 9 ​As shown, the plurality of first bit lines 2120 can include a bit line 2121, a bit line 2122, a bit line 2123, a bit line 2124, a bit line 2125, a bit line 2126, a bit line 2127 and a bit line 2128 which are sequentially distributed along the second direction Y. The plurality of second bit lines 2220 can include a bit line 2221, a bit line 2222, a bit line 2223, a bit line 2224, a bit line 2225, a bit line 2226, a bit line 2227 and a bit line 2228 which are sequentially distributed along the second direction Y. The plurality of third bit lines 2320 can include a bit line 2321, a bit line 2322, a bit line 2323, a bit line 2324, a bit line 2325, a bit line 2326, a bit line 2327 and a bit line 2328 which are sequentially distributed along the second direction Y.

[0125] It should be noted that, Figure 9 In the embodiment, the number of the plurality of first bit lines 2120, the plurality of second bit lines 2220 and the plurality of third bit lines 2320 is eight. However, in actual applications, the number of the plurality of first bit lines 2120, the plurality of second bit lines 2220 and the plurality of third bit lines 2320 can be greater than or less than eight. The number of the plurality of first bit lines 2120, the plurality of second bit lines 2220 and the plurality of third bit lines 2320 is not limited in the present application.

[0126] In addition, Figure 9 The spatial position distribution and connection mode of the first bit line 2120 and the second bit line 2220 shown in the embodiment are similar to those of the first bit line 1120 and the second bit line 1220 shown in the embodiment, and are not described herein for the purpose of brevity. The spatial position distribution and connection mode of the second bit line 2220 and the third bit line 2320 will be described in detail below. Figure 2 Exemplarily, the plurality of second bit lines 2220 and the plurality of third bit lines 2320 can correspond to each other along the first direction Z. Exemplarily, the second bit line 2220 and the third bit line 2320 corresponding to each other along the first direction Z overlap along the second direction Y, i.e., the distance between the second bit line 2220 and the third bit line 2320 along the second direction Y is zero.

[0127]

[0128] ​For example, bit line 2221 and bit line 2321 may correspond along the first direction Z, and the distance between them along the second direction Y is zero. Bit line 2222 and bit line 2322 may correspond along the first direction Z, and the distance between them along the second direction Y is zero. Bit line 2223 and bit line 2323 may correspond along the first direction Z, and the distance between them along the second direction Y is zero. Bit line 2224 and bit line 2324 may correspond along the first direction Z, and the distance between them along the second direction Y is zero. Bit line 2225 and bit line 2325 may correspond along the first direction Z, and the distance between them along the second direction Y is zero. Bit line 2226 and bit line 2326 may correspond along the first direction Z, and the distance between them along the second direction Y is zero. Bit line 2227 and bit line 2327 may correspond along the first direction Z, and the distance between them along the second direction Y is zero. The bit line 2228 and the bit line 2328 may correspond to each other along the first direction Z, and a distance between the bit line 2228 and the bit line 2328 along the second direction Y is zero.

[0129] For example, Figures 9-10H As shown, the preset distance may further include a second preset distance S2. The second bit line 2220 may be connected to the third bit line 2320 at a second preset distance S2 along the second direction Y. It should be understood that the preset distance between the connected second bit line 2220 and the third bit line 2320 along the second direction Y, such as the second preset distance S2, may be the distance between the projection of the third bit line 2320 on the plane where the second bit line 2220 is located and the second bit line 2220 along the second direction Y, or the distance between the projection of the second bit line 2220 on the plane where the third bit line 2320 is located and the third bit line 2320 along the second direction Y.

[0130] It should be noted that the projection position distribution diagram of the connected first bit line 2120 and the second bit line 2220 on the plane formed by the second direction Y and the third direction X is the same as Figures 3A-3H The projection position distribution diagrams of the connected first bit line 1120 and second bit line 1220 on the plane formed by the second direction Y and the third direction X are similar, and for the purpose of brevity, they are not described in detail in this application.

[0131] By way of example, the second preset distance S2 may be greater than zero. In other words, the second bit line 2220 may be connected to a bit line in the third bit lines 2320 that does not correspond to the second bit line 2220. By way of example, the second preset distance S2 may be greater than or equal to the distance H between the second bit line 2220 and the third bit line 2320 that are adjacent along the second direction Y. It should be understood that the distance H may be the distance along the second direction Y between two adjacent second bit lines 2220 or two adjacent third bit lines 2320.

[0132] It should be noted that the second preset distance S2 may be a multiple of the distance H. For example, the second preset distance S2 may be 1 times, 2 times, 3 times, etc. of the distance H.

[0133] like Figures 10A-10H As shown, the second preset distance S1 may include distance S21 and distance S22. Figure 10A As shown, the distance S21 may be the distance between the second bit line 2220 such as 2221 and the third bit line 2320 such as 2323 along the second direction Y, that is, the distance S21 may be greater than the distance H, such as the distance S21 may be twice the distance H. In other words, the distance S21 may be in the range of 30 nm to 80 nm. For example, the distance S21 may be in the range of 36 nm to 50 nm. Figure 10B As shown, the distance S22 may be the distance between the second bit line 2220 (e.g., 2222) and the third bit line 2320 (e.g., 2321) along the second direction Y. That is, the distance S22 may be equal to the distance H. In other words, the distance S22 may be in the range of 15 nm to 40 nm. For example, the distance S22 may be in the range of 18 nm to 25 nm.

[0134] It should be noted that Figures 10A-10H The figure only illustrates two cases where the second preset distance S2 includes distance S21 and distance S22. However, in actual applications, the second preset distance S2 may include a variety of different non-zero distances. For example, the second preset distance S2 may also include distance S23 (not shown), where distance S23 is three times, four times, or five times the distance H. This application does not impose any specific restrictions on the types of the second preset distance S2.

[0135] For example, Figures 9-10H As shown, bit line 2221 may be connected to bit line 2323 at a distance S21 along the second direction Y. Bit line 2222 may be connected to bit line 2321 at a distance S22 along the second direction Y. Bit line 2223 may be connected to bit line 2325 at a distance S21 along the second direction Y. Bit line 2224 may be connected to bit line 2322 at a distance S21 along the second direction Y. Bit line 2225 may be connected to bit line 2327 at a distance S21 along the second direction Y. Bit line 2226 may be connected to bit line 2324 at a distance S21 along the second direction Y. Bit line 2227 may be connected to bit line 2328 at a distance S22 along the second direction Y. Bit line 2228 may be connected to bit line 2326 at a distance S21 along the second direction Y.

[0136] The semiconductor structure 2000 provided herein can be used to perform at least one operation, such as read, write, or erase, to access a memory cell. During operation, a voltage, such as applied to a plurality of first bit lines 2120, is required to write data to the memory cell. The logic potential corresponding to the applied voltage can be 1 or 0.

[0137] It is to be noted that, during the operation of the semiconductor structure 2000, the voltages applied to at least two of the plurality of first bit lines 2120 can be different, i.e., the logic potentials of at least two of the plurality of first bit lines 2120 can be different. In addition, it is to be understood that, during the operation of the semiconductor structure 2000, the logic potentials of the connected first bit lines 2120, second bit lines 2220 and third bit lines 2320 are the same.

[0138] Figure 11 A logic potential distribution diagram of the bit lines 2121-2128, bit lines 2221-2228 and bit lines 2321-2328 is provided according to an exemplary embodiment of the present application. In response to the voltages applied to the plurality of first bit lines 2120 and the logic potentials of at least two adjacent first bit lines 2120 being different, the number of adjacent and logic potential same third bit lines 2320 can be greater than or equal to the number of adjacent and logic potential same first bit lines 2120 and / or second bit lines 2220; and / or the number of adjacent and logic potential same second bit lines 2220 can be greater than or equal to the number of adjacent and logic potential same first bit lines 2120.

[0139] It is to be noted that, Figure 11 The logic potential distribution of the bit lines 2121-2128 and bit lines 2221-2228 shown is similar to Figure 4 The logic potential distribution of the bit lines 1121-1128 and bit lines 1221-1228 shown is similar. For the purpose of brevity, the present application will not repeat here.

[0140] As can be known from the above, in response to the voltages applied to the plurality of first bit lines 2120 and the logic potentials of at least two adjacent first bit lines 2120 being different, the number of adjacent and logic potential same second bit lines 2220 can be greater than or equal to the number of adjacent and logic potential same first bit lines 2120.

[0141] For example, as Figure 11 shown, during the operation of the semiconductor structure 2000, different voltages can be applied to the first bit lines such as the bit lines 2121-2128, and the logic potentials of the charged bit lines 2121-2128 can be 0, 0, 1, 0, 0, 1, 0, 0, respectively. It can be seen that the number of adjacent and logic potential same first bit lines 2120 can be 2. The logic potentials of the second bit lines such as the bit lines 2221-2228 corresponding to the first bit lines such as the bit lines 2121-2128, respectively, can be 0, 0, 0, 1, 1, 0, 0, 0. It can be seen that the number of adjacent and logic potential same second bit lines 1220 can be 3 or 2. As can be known from the above, the number of adjacent and logic potential same second bit lines 2220 such as 3 or 2 can be greater than or equal to the number of adjacent and logic potential same first bit lines 2120 such as 2.

[0142] Since the connected first bit line 2120, second bit line 2220, and third bit line 2320 have the same logic potential, the logic potentials of the third bit lines (e.g., bit lines 2321-2328) corresponding to the second bit lines (e.g., bit lines 2221-2228) can be 0, 1, 0, 0, 0, 0, 1, 0, respectively. It can be seen that bit lines 2323-2326 (i.e., four bit lines) are adjacent and have the same logic potential. In other words, the number of adjacent third bit lines 2320 with the same logic potential can be four.

[0143] As can be seen from the above, the number of adjacent third bit lines 2320 with the same logic potential, such as 4, may be greater than or equal to the number of adjacent first bit lines 2120 and / or second bit lines 2220 with the same logic potential, such as 2 or 3.

[0144] Figure 12 2 is a logic potential distribution diagram of bit lines 2121 ˜ 2128 , bit lines 2221 ˜ 2228 , and bit lines 2321 ˜ 2328 provided according to another exemplary embodiment of the present application.

[0145] It should be noted that Figure 12 The logic potential distribution of the bit lines 2121 to 2128 and the bit lines 2221 to 2228 is shown in FIG. Figure 5 The logic potential distributions of the bit lines 1121 - 1128 and the bit lines 1221 - 1228 are similar, and for the sake of brevity, they are not described in detail herein.

[0146] Referring to the above, it can be seen that in response to applying voltage to multiple first bit lines 2120 and the logic potentials of at least two adjacent first bit lines 2120 are different, the number of adjacent second bit lines 2220 with the same logic potential can be greater than or equal to the number of adjacent first bit lines 2120 with the same logic potential.

[0147] For example, Figure 12 As shown, during operation of the semiconductor structure 2000, different voltages may be applied to first bit lines, such as bit lines 2121-2128. The logic potentials of the charged bit lines 2121-2128 may be 0, 1, 0, 1, 0, 1, 0, 1, respectively. It can be seen that the number of adjacent first bit lines 2120 having the same logic potential may be 0. The logic potentials of second bit lines, such as bit lines 2221-2228, corresponding to the first bit lines 2121-2128, respectively, may be 1, 1, 0, 1, 0, 1, 0, 0, respectively. It can be seen that the number of adjacent second bit lines 2220 having the same logic potential may be 2. As can be seen from the above, the number of adjacent second bit lines 2220 having the same logic potential, such as 2, may be greater than or equal to the number of adjacent first bit lines 2120 having the same logic potential, such as 0.

[0148] Since the connected first bit line 2120, second bit line 2220, and third bit line 2320 have the same logic potential, the logic potentials of the third bit lines (e.g., bit lines 2321-2328) corresponding to the second bit lines (e.g., bit lines 2221-2228) can be 1, 1, 1, 1, 0, 0, 0, 0, respectively. It can be seen that bit lines 2321-2324 (i.e., four bit lines) are adjacent and have the same logic potential, and bit lines 2325-2328 (i.e., four bit lines) are adjacent and have the same logic potential. In other words, the number of adjacent third bit lines 2320 with the same logic potential can be four.

[0149] As can be seen from the above, the number of adjacent third bit lines 2320 with the same logic potential, such as 4, may be greater than or equal to the number of adjacent first bit lines 2120 and / or second bit lines 2220 with the same logic potential, such as 0 or 2.

[0150] In the present application, by setting the first bit line to be connected to the second bit line at a first preset distance along the second direction and the second bit line to be connected to the third bit line at a second preset distance along the second direction, it is beneficial to increase the number of adjacent third bit lines with the same logic potential, and thus help to make the logic potentials of adjacent third bit lines the same, so as to make the voltage of the third bit line more stable, reduce the phenomenon such as parasitic capacitance generated by the different logic potentials of adjacent third bit lines, and thus help to improve the sense margin.

[0151] For example, Figure 8 As shown, the semiconductor structure 2000 may further include a sense amplifier 2400. The first bit line 2120 is connected to the sense amplifier 2400 via the second bit line 2220 and the third bit line 2320. The sense amplifier 2400 may be a differential amplifier, and in a read operation, both ends of the sense amplifier 2400 may be sensing signals on a pair of bit lines. Connecting one end of the sense amplifier 2400 to the third bit line 2320 is beneficial to improving the reading accuracy of the sense amplifier 2400, thereby improving the sensing margin. It should be understood that the structure of the sense amplifier 2400 is similar to that of the sense amplifier 2400. Figure 6A The structure of the sense amplifier 1300 is similar to that of the sense amplifier 1300. To avoid redundancy, the present application will not describe the structure of the sense amplifier 2400 in detail. Figure 6A Sense amplifier 1300 is shown.

[0152] It should be noted that Figure 8 Only three memory cell arrays are illustrated. However, in actual applications, the number of memory cell arrays can be greater, such as 4 or 5. This application does not impose any specific restrictions on the number of memory cell arrays. Furthermore, this application does not impose any specific restrictions on the number of bit lines and word lines in each memory cell array. It is understood that there is a memory cell at each intersection of a word line and a bit line.

[0153] For example, Figure 8 As shown, the semiconductor structure 2000 may further include a dielectric layer 2700. The dielectric layer 2700 may be located on one side of the second memory cell array 2200 along the first direction Z, and is used to support the third memory cell array 2300. In other words, the dielectric layer 2700 may be located between the second memory cell array 2200 and the third memory cell array 2300. The material of the dielectric layer 2700 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating materials.

[0154] For example, Figure 8 As shown, the semiconductor structure 2000 may further include a peripheral circuit 2500 and a bonding layer 2600. The sense amplifier 2400 may be located in the peripheral circuit 2500. The bonding layer 2600 may be used to bond the third memory cell array 2300 and the peripheral circuit 1500 together. It should be understood that the peripheral circuit 2500 and the bonding layer 2600 are respectively connected to the peripheral circuit 2500 and the bonding layer 2600. Figure 1 The structures of the peripheral circuit 1500 and the bonding layer 1600 shown in FIG. 1 are similar, and for the purpose of brevity, they will not be described in detail in this application.

[0155] For example, Figure 8 As shown, the semiconductor structure 2000 may further include a bit line extraction structure 2800. The bit line extraction structure 2800 may include a first bit line extraction structure 2810, a second bit line extraction structure 2820, and a third bit line extraction structure 2830 for extracting the first bit line 2120, the second bit line 2220, and the third bit line 2320, respectively.

[0156] For example, the first bit line 2120, the second bit line 2220, and the third bit line 2320 may be connected via a first bit line lead-out structure 2810, a second bit line lead-out structure 2820, a third bit line lead-out structure 2830, and / or other metal wiring. The first bit line 2120 may be connected to the sense amplifier 2400 via the second bit line 2220 and the third bit line 2320 connected thereto.

[0157] Figure 13 is a flow chart of a method 3000 of fabricating a semiconductor structure according to an exemplary embodiment of the present application.

[0158] like Figure 13As shown, the method 3000 of manufacturing a semiconductor structure can include: S3100, forming a plurality of memory cell arrays distributed along a first direction, wherein the memory cell arrays include a plurality of memory cells arrayed along a second direction and a third direction, and a plurality of bit lines located at one side of the memory cells along the first direction; and S3200, connecting the bit lines of the memory cell arrays with the bit lines of adjacent memory cell arrays located at a preset distance along the second direction. The steps S3100 and S3200 will be described in detail below.

[0159] In the exemplary embodiments of the present application, as shown, Figure 1 A plurality of memory cell arrays distributed along a first direction Z, such as the first memory cell array 1100 and the second memory cell array 1200, can be formed at one side of the substrate 1400 along the first direction Z. The first memory cell array 1100 and the second memory cell array 1200 can be distributed adjacent along the first direction Z.

[0160] The material of the substrate 1400 can include at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor material, II-VI compound semiconductor material, or other semiconductor materials known in the art.

[0161] Exemplarily, as shown, Figure 1 Forming a plurality of memory cell arrays distributed along a first direction Z can include forming a first memory cell array 1100, and forming a second memory cell array 1200 at one side of the first memory cell array 1100 along the first direction Z.

[0162] The first memory cell array 1100 can include a plurality of memory cells, such as the first memory cell 1110, and a plurality of bit lines, such as the first bit line 1120. The plurality of first memory cells 1110 can be arrayed along a second direction Y and a third direction X. The plurality of first bit lines 1120 can be located at one side of the plurality of first memory cells 1110 along the first direction Z. The second memory cell array 1200 can include a plurality of memory cells, such as the second memory cell 1210, and a plurality of bit lines, such as the second bit line 1220. The plurality of second memory cells 1210 can be arrayed along the second direction Y and the third direction X. The plurality of bit lines 1220 can be located at one side of the memory cells 1210 along the first direction Z. Exemplarily, the first direction Z, the second direction Y, and the third direction X can intersect with each other. The memory cell array 1100 and the memory cell array 1200 can be DRAM cell arrays. The first memory cell 1110 and the second memory cell 1210 can be DRAM cells.

[0163] Exemplarily, as shown, Figure 1As shown, forming the first memory cell array 1100 can include forming a plurality of capacitors 1112 arrayed along the second direction Y and the third direction X; forming a plurality of channel structures 1111 on a side of the capacitors 1112 along the first direction Z; and forming a plurality of first bit lines 1120 on a side of the channel structures 1111 along the first direction Z.

[0164] Exemplarily, the capacitors 1112, the channel structures 1111, and the first bit lines 1120 can be sequentially formed by at least one of thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, and removal processes such as grinding, wet etching, dry etching, and planarization.

[0165] Exemplarily, the first memory cell 1110 can include a transistor 1111’ (including the channel structure 1111) and a capacitor 1112. The plurality of first bit lines 1120 can be located on a side of the plurality of first memory cells 1110 along the first direction Z. As shown in FIG. 6, the first bit lines 1120 can extend along the third direction X and can be connected with the first memory cells 1110 arrayed along the third direction X. The second bit lines 1220 can extend along the third direction X and can be connected with the second memory cells 1210 arrayed along the third direction X.

[0166] Exemplarily, forming the first memory cell array 1100 can further include forming word lines 1130 extending along the second direction Y and connected with the plurality of first memory cells 1110 arrayed along the second direction Y. Exemplarily, the word lines 1130 can be sequentially formed by one or more thin film deposition processes including but not limited to CVD, PVD, ALD, or any combination thereof.

[0167] Exemplarily, as shown in FIG. 6, the word lines 1130 can extend along the second direction Y and be connected with the plurality of first memory cells 1110 arrayed along the second direction Y in the first memory cell array 1100.

[0168] Exemplarily, as shown in FIG. 6, the capacitors 1112 can be used to store bits of data as positive or negative charges. The transistors 1111’ (also known as pass transistors) can be used to control (e.g., switch and select) access to the first memory cells 1110, where the transistors 1111’ will be described in detail below. Exemplarily, the transistors 1111’ can be vertical transistors such as vertical metal-oxide-semiconductor field-effect transistors (MOSFETs) to facilitate forming the capacitors 1112 on a side of the transistors 1111’ along the first direction Z.

[0169] The word lines 1130 can be coupled to the first memory cells 1110 along a second direction Y for controlling switching of the transistors 1111' in the first memory cells 1110 located in a row along the second direction Y. The bit lines 1120 can be coupled to the first memory cells 1110 along a third direction X for sending data to and / or receiving data from the first memory cells 1110 located in a column along the third direction X. That is, each word line 1130 can be coupled to the first memory cells 1110 of a respective row and each bit line 1120 can be coupled to the first memory cells 1110 of a respective column.

[0170] Exemplarily, the gate of the transistor 1111' can be connected with the word line 1130, the drain can be connected with the bit line 1120, and the source can be connected with the capacitor 1112. A voltage signal on the word line 1130 can control the opening or closing of the transistor 1111', so as to read data information stored in the capacitor 1112 through the bit line 1120 or write data information into the capacitor 1112 for storage through the bit line 1120.

[0171] Exemplarily, as shown in FIG. 11B, the transistor 1111' can include a channel structure 1111 and a gate structure 1113 corresponding to a portion of the channel structure 1111. The channel structure 1111 can include a first extension 1111-1 and a second extension 1111-2 connected with each other, where the first extension 1111-1 can extend along a first direction Z and the second extension 1111-2 can extend along a third direction X, and the extension size of the first extension 1111-1 along the first direction Z can be greater than the extension size of the second extension 1111-2 along the third direction X. In other words, the first extension 1111-1 and the second extension 1111-2 can jointly form an L shape. The first extension 1111-1 and the second extension 1111-2 can be an integral structure, and the materials thereof can be the same. Figure 1 Exemplarily, the material of the channel structure 1111 (i.e., the first extension 1111-1 and the second extension 1111-2) can include one or more of a polycrystalline silicon (Poly-Si), an amorphous silicon (a-Si), a metal oxide semiconductor (e.g., indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium tin oxide (ITO)), and the like semiconductor materials. Exemplarily, the material of the channel structure 1111 can be a low-temperature material such as indium gallium zinc oxide (IGZO).

[0172] Exemplarily, the material of the channel structure 1111 (i.e., the first extension 1111-1 and the second extension 1111-2) can include one or more of a polycrystalline silicon (Poly-Si), an amorphous silicon (a-Si), a metal oxide semiconductor (e.g., indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium tin oxide (ITO)), and the like semiconductor materials. Exemplarily, the material of the channel structure 1111 can be a low-temperature material such as indium gallium zinc oxide (IGZO).

[0173] In the present application, by setting the material of the channel structure 1111 as a low-temperature material such as indium-gallium-zinc oxide (IGZO), it is beneficial to form the channel structure 1111 in a lower-temperature environment. This not only helps to improve the density of the channel structure 1111, but also helps to reduce the damage to other components of the semiconductor structure in a high-temperature environment, such as softening, bending, etc., thereby facilitating the implementation of more stacked layers, such as the subsequent formation of a second memory cell array 1200 on the first memory cell array 1100, and improving the storage density of the semiconductor structure. In addition, such a setting can also significantly reduce the channel leakage current, improve the data retention characteristics, and improve the sensing margin.

[0174] Exemplarily, the plurality of channel structures 1111 can be arrayed along the second direction Y and the third direction X. In other words, the plurality of channel structures 1111 can be spaced along the second direction Y and the third direction X.

[0175] Exemplarily, the gate structure 1113 can be located on one side of the second extension 1111-2 along the first direction Z and opposite to the partial first extension 1111-1 along the third direction X. The gate structure 1113 can extend along the second direction Y and the first direction Z, wherein the extension size of the gate structure 1113 along the first direction Z can be smaller than the extension size of the first extension 1111-1 along the first direction Z.

[0176] Exemplarily, the gate structure 1113 can include a gate layer (not shown) and a gate dielectric layer (not shown) located between the gate layer and the channel structure 1111. Exemplarily, the gate dielectric layer can include any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant material. For example, the gate dielectric layer can include silicon oxide. The gate layer can include one or more conductive materials, for example, metals and / or metal compounds, such as tungsten W and / or titanium nitride TiN. The gate structure 1113 can be connected with the peripheral circuit 1500 to realize the transmission of electrical signals between the gate electrode and the peripheral circuit 1500, wherein the peripheral circuit 1500 will be described in detail below.

[0177] Figure 7 is Figure 1 An enlarged view of part of the structure in FIG. 11A. Exemplarily, the channel structure 1111 can include a first end 1111-3 and a second end 1111-4 opposite along the first direction Z, wherein the first end 1111-3 can include an end of the first extension 1111-1 away from the second extension 1111-2 along the first direction Z, and the second end 1111-4 can include at least a portion of the second extension 1111-2.

[0178] In transistor 1111', first extension 1111-1 can function as a channel, the portion of gate structure 1113 corresponding to first extension 1111-1 can function as a gate, and first end 1111-3 and second end 1111-4 can function as a source and a drain, respectively. Gate structure 1113, extending along a second direction Y, can be used to control a row of transistors arranged along the second direction Y.

[0179] In the present application, the first extension portion 1111-1 serves as the channel of the transistor, which helps to make the transistor structure more compact, effectively reduce the plane occupied area, realize more stacking layers, improve the storage density of the semiconductor structure, and also help to improve the iterative miniaturization capability of the characteristic size of the semiconductor structure.

[0180] For example, Figure 1 As shown, forming the first memory cell array 1100 may further include forming a capacitor contact structure 1140 on one side of the capacitor 1112 along the first direction Z. For example, a channel structure 1111 may be formed after forming the capacitor contact structure 1140, wherein the channel structure 1111 may be located on one side of the capacitor contact structure 1140 along the first direction Z.

[0181] Capacitor contact structure 1140 may be connected to second end 1111-4, such as at least a portion of second extension 1111-2. The material of capacitor contact structure 1140 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), metal silicide (e.g., titanium silicide (TiSi2), cobalt silicide (CoSi2), nickel platinum silicide (NiPtSi)), or any other suitable conductive material. For example, second end 1111-4 may directly contact capacitor contact structure 1140 to increase the contact area between the two, improve transmission efficiency, and ensure electrical connection reliability.

[0182] For example, Figure 1 As shown, the first bit line 1120 may be connected to a first end 1111-3 of a plurality of channel structures 1111 distributed along a third direction X, such as an end of the first extension portion 1111-1 away from the second extension portion 1111-2 along the first direction Z. The capacitor 1112 may be connected to a second end 1111-4, such as at least a portion of the second extension portion 1111-2. For example, the capacitor 1112 may be connected to the second end 1111-4 via a capacitor contact structure 1140.

[0183] Exemplarily, the capacitor 1112 can include a first electrode layer 1112-1, a second electrode layer 1112-2, and a capacitor dielectric layer 1112-3 between the first electrode layer 1112-1 and the second electrode layer 1112-2. The first electrode layer 1112-1 can be located on a side of the capacitor contact structure 1140 away from the channel structure 1111 and extend along the third direction X. The second electrode layer 1112-2 can be located in the first electrode layer 1112-1, for example, the second electrode layer 1112-2 can at least partially penetrate the first electrode layer 1112-1. The second electrode layer 1112-2 can be substantially a columnar structure. The second electrode layer 1112-2 can be connected with the capacitor contact structure 1140, that is, the second electrode layer 1112-2 can be connected with the second end 1111-4 of the channel structure 1111 via the capacitor contact structure 1140. The capacitor dielectric layer 1112-3 can be substantially a barrel structure with an open end, the second electrode layer 1112-2 can be located in the capacitor dielectric layer 1112-3, and the open end of the capacitor dielectric layer 1112-3 can be towards the capacitor contact structure 1140, so that the second electrode layer 1112-2 is in direct contact with the capacitor contact structure 1140.

[0184] Exemplarily, the materials of the first electrode layer 1112-1 and the second electrode layer 1112-2 can include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material. The material of the capacitor dielectric layer 1112-3 can include one or more of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or any other suitable insulating material. x N y ) or any other suitable insulating material.

[0185] As described above, the first electrode layer 1112-1, the capacitor dielectric layer 1112-3, and the second electrode layer 1112-2 can be used to form the capacitor 1112. One electrode of the capacitor 1112 (e.g., the second electrode layer 1112-2) is connected with one of the source or the drain (e.g., the first end 1111-3 or the second end 1111-4) of the transistor 1111’ via the capacitor contact structure 1140. The transistor 1111’ and the capacitor 1112 can constitute the first memory cell 1110 (e.g., a DRAM memory cell). The other electrodes of the plurality of capacitors 1112 (e.g., the first electrode layer 1112-1) can be connected with each other.

[0186] It should be noted that the capacitor can also be implemented in other structure types, for example, the capacitor can be constituted by conductive layers, insulating layers, and conductive layers (not shown) stacked in the first direction Z in sequence. The structure of the capacitor is not specifically limited in the present application, and the capacitor can be implemented in any known structure type in the art.

[0187] Exemplarily, the first bit line 1120 can extend along the third direction X and be connected (e.g., directly contact) with the first end 1111-3 of the channel structure 1111. The first bit line 1120 can be connected with each first end 1111-3 in a column of channel structures 1111 arranged along the third direction X. Thus, one of the source or the drain of a transistor 1111’ in a column arranged along the third direction X is connected with the same first bit line 1120. Exemplarily, the material of the first bit line 1120 can include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material.

[0188] Exemplarily, as shown in FIG. 11B, the first storage unit array 1100 can further include a plurality of capacitors 1112. The capacitors 1112 can be located between the adjacent capacitor dielectric layers 1112-3 and can be connected with the first electrode layer 1112-1 along the first direction Z. The capacitors 1112 can be connected with the first electrode layer 1112-1 via the electrode plate 1150. The capacitors 1112 can be connected with the first electrode layer 1112-1 via the support layer 1160. Figure 1 Exemplarily, as shown in FIG. 11B, the first storage unit array 1100 can further include a plurality of capacitors 1112. The capacitors 1112 can be located between the adjacent capacitor dielectric layers 1112-3 and can be connected with the first electrode layer 1112-1 along the first direction Z. The capacitors 1112 can be connected with the first electrode layer 1112-1 via the electrode plate 1150. The capacitors 1112 can be connected with the first electrode layer 1112-1 via the support layer 1160.

[0189] Exemplarily, the material of the electrode plate 1150 can include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material. The material of the support layer 1160 can include any one or a combination of two or more of silicon nitride, silicon oxynitride, aluminum oxide, etc. For example, the material of the support layer 1160 can include silicon nitride.

[0190] Exemplarily, as shown in FIG. 11B, the first storage unit array 1100 can further include a plurality of capacitors 1112. The capacitors 1112 can be located between the adjacent capacitor dielectric layers 1112-3 and can be connected with the first electrode layer 1112-1 along the first direction Z. The capacitors 1112 can be connected with the first electrode layer 1112-1 via the electrode plate 1150. The capacitors 1112 can be connected with the first electrode layer 1112-1 via the support layer 1160. Figure 1 Exemplarily, as shown in FIG. 11B, the first storage unit array 1100 can further include a plurality of capacitors 1112. The capacitors 1112 can be located between the adjacent capacitor dielectric layers 1112-3 and can be connected with the first electrode layer 1112-1 along the first direction Z. The capacitors 1112 can be connected with the first electrode layer 1112-1 via the electrode plate 1150. The capacitors 1112 can be connected with the first electrode layer 1112-1 via the support layer 1160. x N y Exemplarily, the material of the dielectric layer 1900 can include one or more of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or any other suitable insulating material.

[0191] Exemplarily, as shown in FIG. 6, the second storage unit array 1200 can be formed on one side of the first storage unit array 1100 along the first direction Z. The second storage unit array 1200 and the first storage unit array 1100 can be respectively located on opposite sides of the medium layer 1900 along the first direction Z. Figure 1

[0192] Exemplarily, forming the second storage unit array 1200 can include: forming a second storage unit 1210 on one side of the first storage unit array 1100 along the first direction Z; and forming a second bit line 1220 on one side of the second storage unit 1210 along the first direction Z.

[0193] As shown in FIG. 6, the second bit line 1220 can extend along the third direction X and can be connected with the second storage unit 1210 distributed along the third direction X. Exemplarily, the second storage unit array 1200 can further include a word line 1230 extending along the second direction Y and connected with a plurality of second storage units 1210 distributed along the second direction Y.

[0194] It should be noted that the structure of the second storage unit array 1200 is substantially the same as or similar to that of the first storage unit array 1100. The process of forming the second storage unit array 1200 is substantially the same as or similar to that of forming the first storage unit array 1100. For the purpose of brief description, the process of forming the second storage unit array 1200 will not be described herein. In addition, other structures in the second storage unit array 1200 that are the same as or similar to those in the first storage unit array 1100 will not be described herein.

[0195] In the present application, by integrating the first storage unit array 1100 and the second storage unit array 1200 in the first direction Z, the planar area of the semiconductor structure can be saved, and the storage density can be effectively improved.

[0196] Exemplarily, as shown in FIG. 6, the second storage unit array 1200 can be formed on one side of the first storage unit array 1100 along the first direction Z. The second storage unit array 1200 and the first storage unit array 1100 can be respectively located on opposite sides of the medium layer 1900 along the first direction Z. Figure 1 Exemplarily, as shown in FIG. 6, the second storage unit array 1200 can be formed on one side of the first storage unit array 1100 along the first direction Z. The second storage unit array 1200 and the first storage unit array 1100 can be respectively located on opposite sides of the medium layer 1900 along the first direction Z.

[0197] ​For example, the first bit line 1120 and the second bit line 1220 may be connected via the bit line extraction structure 1720 and / or other metal wirings. The first bit line 1120 may be connected to the subsequently formed sense amplifier 1300 via the second bit line 1220 connected thereto.

[0198] For example, Figure 2 As shown, the plurality of first bit lines 1120 may include a bit line 1121, a bit line 1122, a bit line 1123, a bit line 1124, a bit line 1125, a bit line 1126, a bit line 1127, and a bit line 1128 sequentially distributed along the second direction Y. The plurality of second bit lines 1220 may include a bit line 1221, a bit line 1222, a bit line 1223, a bit line 1224, a bit line 1225, a bit line 1226, a bit line 1227, and a bit line 1228 sequentially distributed along the second direction Y.

[0199] It should be noted that Figure 2 The figure only illustrates that the number of the plurality of first bit lines 1120 and the plurality of second bit lines 1220 are both eight. However, in actual applications, the number of the plurality of first bit lines 1120 and the plurality of second bit lines 1220 may be greater than or less than eight. This application does not impose any specific limitation on the number of the plurality of first bit lines 1120 and the plurality of second bit lines 1220.

[0200] Illustratively, the plurality of first bit lines 1120 and the plurality of second bit lines 1220 may correspond to each other along the first direction Z. Illustratively, the first bit lines 1120 and the second bit lines 1220 corresponding to each other along the first direction Z overlap along the second direction Y, that is, the distance between them along the second direction Y is zero.

[0201] For example, bit line 1121 and bit line 1221 may correspond along the first direction Z, and the distance between them along the second direction Y is zero. Bit line 1122 and bit line 1222 may correspond along the first direction Z, and the distance between them along the second direction Y is zero. Bit line 1123 and bit line 1223 may correspond along the first direction Z, and the distance between them along the second direction Y is zero. Bit line 1124 and bit line 1224 may correspond along the first direction Z, and the distance between them along the second direction Y is zero. Bit line 1125 and bit line 1225 may correspond along the first direction Z, and the distance between them along the second direction Y is zero. Bit line 1126 and bit line 1226 may correspond along the first direction Z, and the distance between them along the second direction Y is zero. Bit line 1127 and bit line 1227 may correspond along the first direction Z, and the distance between them along the second direction Y is zero. The bit line 1128 and the bit line 1228 may correspond to each other along the first direction Z, and a distance between the bit line 1128 and the bit line 1228 along the second direction Y is zero.

[0202] For example, Figure 2As shown, the bit line of the storage unit array, such as the bit line 1121, can be connected with the bit line, such as the bit line 1223, of the adjacent storage unit array which is apart from the bit line 1121 by a preset distance along the second direction Y. For example, the preset distance can include a first preset distance S1. As shown, Figures 2-3H As shown, the first bit line 1120 in the first storage unit array 1100 can be connected with the second bit line 1220 in the second storage unit array 1200 which is apart from the first bit line 1120 by the first preset distance S1 along the second direction Y.

[0203] For example, the preset distance can be greater than zero, i.e. the first preset distance S1 can be greater than zero. In other words, the first bit line 1120 can be connected with the bit line in the second bit line 1220 which does not correspond to the first bit line 1120. For example, the first preset distance S1 can be greater than or equal to the distance H between the adjacent first bit line 1120 and the second bit line 1220 along the second direction Y. It should be understood that the distance H can be the distance between two adjacent first bit lines 1120 or two adjacent second bit lines 1220 along the second direction Y.

[0204] As shown, Figures 3A-3H The first preset distance S1 can include a distance S11 and a distance S12. As shown, Figure 3A The distance S11 can be the distance between the first bit line 1120, such as 1121, and the second bit line 1220, such as 1223, along the second direction Y, i.e. the distance S11 can be greater than the distance H, such as the distance S11 can be twice the distance H. As shown, Figure 3B The distance S12 can be the distance between the first bit line 1120, such as 1122, and the second bit line 1220, such as 1221, along the second direction Y, i.e. the distance S12 can be equal to the distance H.

[0205] It should be noted that, Figures 3A-3H In the above embodiments, only two cases are shown in which the first preset distance S1 includes the distance S11 and the distance S12. However, in actual applications, the first preset distance S1 can include a plurality of different and non-zero distances, such as the first preset distance S1 can also include a distance S13 (not shown) and the like, wherein the distance S13 is three times, four times, five times, etc. of the distance H. The present application does not make specific limitations on the types of the first preset distance S1.

[0206] For example, as shown, Figures 2-3HAs shown, the bit line 1121 can be connected with the bit line 1223 at a distance S11 along the second direction Y. The bit line 1122 can be connected with the bit line 1221 at a distance S12 along the second direction Y. The bit line 1123 can be connected with the bit line 1225 at a distance S11 along the second direction Y. The bit line 1124 can be connected with the bit line 1222 at a distance S11 along the second direction Y. The bit line 1125 can be connected with the bit line 1227 at a distance S11 along the second direction Y. The bit line 1126 can be connected with the bit line 1224 at a distance S11 along the second direction Y. The bit line 1127 can be connected with the bit line 1228 at a distance S12 along the second direction Y. The bit line 1128 can be connected with the bit line 1226 at a distance S11 along the second direction Y.

[0207] The semiconductor structure 1000 provided by the present application can be used to perform at least one operation such as reading, writing, erasing, etc. to realize access of a memory cell such as the first memory cell 1110 and / or the second memory cell 1210. During operation, a voltage needs to be applied to a plurality of first bit lines 1120 to realize writing of storage data to the first memory cell 1110 and / or the second memory cell 1210, wherein the logic potential corresponding to the applied voltage can be 1 or 0.

[0208] It should be noted that during operation of the semiconductor structure 1000, the voltage applied to at least two bit lines in the plurality of first bit lines 1120 can be different, i.e. the logic potential of at least two bit lines in the plurality of first bit lines 1120 can be different. In addition, it should be understood that during operation of the semiconductor structure 1000, the logic potential of the connected first bit line 1120 and second bit line 1220 is the same.

[0209] Figure 4 The logic potential distribution diagram of the bit lines 1121-1128 and the bit lines 1221-1228 is provided according to an exemplary embodiment of the present application. Exemplarily, in response to applying a voltage to the plurality of first bit lines 1120 and the logic potential of at least two adjacent first bit lines 1120 being different, the number of adjacent second bit lines 1220 with the same logic potential can be greater than or equal to the number of adjacent first bit lines 1120 with the same logic potential.

[0210] For example, as shown in FIG. 1, the logic potential of the bit line 1121 is 1, the logic potential of the bit line 1122 is 0, the logic potential of the bit line 1123 is 1, the logic potential of the bit line 1124 is 0, the logic potential of the bit line 1125 is 1, the logic potential of the bit line 1126 is 0, the logic potential of the bit line 1127 is 1, and the logic potential of the bit line 1128 is 0. Figure 4As shown, during the operation of the semiconductor structure 1000, different voltages can be applied to the first bit lines, such as the bit lines 1121-1128, and the logic potentials of the charged bit lines 1121-1128 can be 0, 0, 1, 0, 0, 1, 0, 0, respectively. It can be seen that the logic potentials of the adjacent bit line 1122 and the bit line 1123 are different. The logic potentials of the adjacent bit line 1123 and the bit line 1124 are different. The logic potentials of the adjacent bit line 1125 and the bit line 1126 are different. The logic potentials of the adjacent bit line 1126 and the bit line 1127 are different. The bit line 1121 and the bit line 1122 (i.e., two bit lines) are adjacent and have the same logic potential, the bit line 1124 and the bit line 1125 (i.e., two bit lines) are adjacent and have the same logic potential, and the bit line 1127 and the bit line 1128 (i.e., two bit lines) are adjacent and have the same logic potential. In other words, the number of the first bit lines 1120 that are adjacent and have the same logic potential can be 2.

[0211] Since the logic potentials of the connected first bit lines 1120 and the second bit lines 1220 are the same, the logic potentials of the second bit lines corresponding to the first bit lines 1121-1128, such as the bit lines 1221-1228, can be 0, 0, 0, 1, 1, 0, 0, 0, respectively. It can be seen that the bit lines 1221-1223 (i.e., three bit lines) are adjacent and have the same logic potential, the bit line 1224 and the bit line 1225 (i.e., two bit lines) are adjacent and have the same logic potential, and the bit lines 1226-1228 (i.e., three bit lines) are adjacent and have the same logic potential. In other words, the number of the second bit lines 1220 that are adjacent and have the same logic potential can be 3 or 2.

[0212] As can be seen from the above, the number of the second bit lines 1220 that are adjacent and have the same logic potential, such as 3 or 2, can be greater than or equal to the number of the first bit lines 1120 that are adjacent and have the same logic potential, such as 2.

[0213] Figure 5 A logic potential distribution diagram of the bit lines 1121-1128 and the bit lines 1226-1228 is provided according to another exemplary embodiment of the present application.

[0214] As Figure 5 As shown, during the operation of the semiconductor structure 1000, different voltages can be applied to the first bit lines, such as the bit lines 1121-1128, and the logic potentials of the charged bit lines 1121-1128 can be 0, 1, 0, 1, 0, 1, 0, 1, respectively. It can be seen that the logic potentials of any two adjacent bit lines in the bit lines 1121-1128 are different. In other words, the number of the first bit lines 1120 that are adjacent and have the same logic potential can be 0.

[0215] Since the logic potentials of the connected first bit lines 1120 and second bit lines 1220 are the same, the logic potentials of the second bit lines, such as bit lines 1221-1228, corresponding to the first bit lines, such as bit lines 1121-1128, can be 1, 1, 0, 1, 0, 1, 0, 0, respectively. It can be seen that the bit lines 1221 and 1222 (i.e., two bit lines) are adjacent and have the same logic potential, and the bit lines 1227 and 1228 (i.e., two bit lines) are adjacent and have the same logic potential. In other words, the number of adjacent second bit lines 1220 with the same logic potential can be 2.

[0216] As can be seen from the above, the number of adjacent second bit lines 1220 with the same logic potential, such as 2, can be greater than or equal to the number of adjacent first bit lines 1120 with the same logic potential, such as 0.

[0217] Generally, during operation of the semiconductor structure, the number of adjacent first bit lines with the same logic potential is small. In this way, it can cause the first bit line with a logic potential of 1 (i.e., a high-voltage bit line) to be pulled down by the adjacent first bit line with a logic potential of 0 (i.e., a low-voltage bit line), thereby causing the potential of the first bit line with a logic potential of 1 to decrease, and the coupling phenomenon between adjacent bit lines to be aggravated.

[0218] Based on this, the present application is configured to connect the first bit line with the second bit line spaced apart from the first bit line along the second direction by a first preset distance, which is beneficial to increase the number of adjacent second bit lines with the same logic potential, and thereby beneficial to make the logic potentials of adjacent second bit lines the same, so as to make the voltage of the second bit line more stable, reduce the phenomenon of parasitic capacitance caused by the different logic potentials of adjacent second bit lines, and thereby beneficial to improve the sense margin.

[0219] Exemplarily, as shown in Figure 1 The peripheral circuit 1500 (also referred to as a control and sensing circuit) can also include any suitable digital, analog, and / or mixed-signal circuitry for facilitating operation of the memory cell array, such as the first memory cell array 1100 and / or the second memory cell array 1200. Exemplarily, the peripheral circuit includes a plurality of control circuits for connecting with the first memory cells 1110, the first bit lines 1120, the first word lines 1130, the second memory cells 1210, the second bit lines 1220, and the second word lines 1230, respectively, to transmit electrical signals therebetween.

[0220] Illustratively, the peripheral circuit 1500 may also include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a driver, an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion (e.g., a sub-circuit) of the above functional circuits, or any active or passive component of the circuit (e.g., a peripheral transistor, diode, resistor, or capacitor).

[0221] For example, Figure 1 As shown, the second memory cell array 1200 and the peripheral circuit 1500 can be bonded together by a bonding process to form a bonding layer 1600. The bonding layer 1600 may include a plurality of bonding contacts 1610 and a dielectric 1620 isolating the bonding contacts 1610. The bonding contacts 1610 may include a conductive material, such as copper (Cu). The remaining area of ​​the bonding layer 1600 may be formed of a dielectric material (not shown, such as silicon oxide) to form the dielectric 1620. The bonding contacts 1610 and the surrounding dielectric 1620 in the bonding layer 1600 may be used for hybrid bonding.

[0222] For example, in the bonding process, the first bit line 1120 may be connected to the sense amplifier 1300 via the second bit line 1220 connected thereto. The sense amplifier 1300 may be a differential amplifier, and in a read operation, both ends of the sense amplifier 1300 (eg, Figure 6A The first input terminal 1320 and the second input terminal 1330 shown in FIG can be sensing signals on a pair of bit lines. Connecting one end of the sense amplifier 1300 to the second bit line 1220 is beneficial for improving the reading accuracy of the sense amplifier 1300, thereby improving the sensing margin.

[0223] For example, Figure 1 As shown, interconnection line 1810 and interconnection via 1820 may also be formed. Interconnection line 1810 may be located on peripheral circuit 1500. Interconnection via 1820 may be connected to interconnection line 1810 and extend to peripheral circuit 1500. Interconnection line 1810 and interconnection via 1820 may be used to connect peripheral circuit 1500 and a power supply line (not shown), thereby shortening the length of the interconnection structure between peripheral circuit 1500 and the power supply line, thereby reducing the parasitic capacitance of the interconnection structure and improving the sensing margin and storage density of the semiconductor structure.

[0224] For example, Figure 1 As shown, a pad lead-out structure 1830 extending to the first memory cell array 1100 may be formed on one side of the interconnect line 1810. The pad lead-out structure 1830 may transmit electrical signals between the semiconductor structure 1000 and an external circuit. The pad lead-out structure 1830 may include a conductive material, including but not limited to W, Cu, Al, doped silicon, silicide, or any combination thereof.

[0225] Figure 8 is a partial structure diagram of a formed semiconductor structure 2000 according to another exemplary embodiment of the present application. Compared with the semiconductor structure 1000 shown in FIG. 1A, Figure 1 the semiconductor structure 1000 shown in FIG. 1A, Figure 8 omitted in the semiconductor structure 2000.

[0226] Exemplarily, as shown in FIG. 2A, a plurality of memory cell arrays such as the first memory cell array 2100, the second memory cell array 2200 and the third memory cell array 2300 can be sequentially formed along the first direction Z. Figure 8

[0227] It should be noted that the forming process and structure of the first memory cell array 2100 and the second memory cell array 2200 are similar to those of the first memory cell array 1100 and the second memory cell array 1200 respectively. For the purpose of brevity, the present application will not be described in detail here, and the specific can be referred to the above description of the forming process and structure of the first memory cell array 1100 and the second memory cell array 1200.

[0228] Exemplarily, forming a plurality of memory cell arrays distributed along the first direction Z can further include forming the third memory cell array 2300 on one side of the second memory cell array 1200 along the first direction Z. Exemplarily, a dielectric layer 2700 is formed on one side of the second memory cell array 1200 along the first direction Z; and the third memory cell array 2300 is formed on the dielectric layer 2700. The material of the dielectric layer 2700 can include one or more of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other appropriate insulating material.

[0229] Exemplarily, the dielectric layer 2700 and the third memory cell array 2300 can be sequentially formed by at least one of a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, and a removal process such as grinding, wet etching, dry etching and planarization treatment.

[0230] ​The third memory cell array 2300 may include a plurality of third memory cells 2310 arranged in an array along the second direction Y and the third direction X, and a plurality of third bit lines 2320 located on one side of the third memory cells 2310 along the first direction Z. For example, the plurality of third bit lines 2320 may be connected to the plurality of second bit lines 2220.

[0231] It should be noted that the formation process and structure of the third memory cell array 2300 are substantially the same as or similar to those of the first memory cell array 2100 and / or the second memory cell array 2200. For the purpose of brevity, other formation processes and structures of the third memory cell array 2300 that are the same as or similar to those of the first memory cell array 2100 and / or the second memory cell array 2200 are not further described in this application.

[0232] In the present application, by integrating the first memory cell array 2100 , the second memory cell array 2200 , and the third memory cell array 2300 in the first direction Z, the plane area of ​​the semiconductor structure can be saved and the storage density can be effectively improved.

[0233] For example, Figure 8 As shown, a bit line lead-out structure 2800 may also be formed. The bit line lead-out structure 2800 may include a first bit line lead-out structure 2810, a second bit line lead-out structure 2820, and a third bit line lead-out structure 2830 for respectively leading out the first bit line 2120, the second bit line 2220, and the third bit line 2320. For example, the first bit line 2120, the second bit line 2220, and the third bit line 2320 may be connected via the first bit line lead-out structure 2810, the second bit line lead-out structure 2820, the third bit line lead-out structure 2830, and / or other metal wiring. The first bit line 2120 may be connected to the subsequently formed sense amplifier 2400 via the second bit line 2220 and the third bit line 2320 connected thereto.

[0234] For example, Figure 9 As shown, the plurality of first bit lines 2120 may include bit lines 2121, 2122, 2123, 2124, 2125, 2126, 2127, and 2128 sequentially distributed along the second direction Y. The plurality of second bit lines 2220 may include bit lines 2221, 2222, 2223, 2224, 2225, 2226, 2227, and 2228 sequentially distributed along the second direction Y. The plurality of third bit lines 2320 may include bit lines 2321, 2322, 2323, 2324, 2325, 2326, 2327, and 2328 sequentially distributed along the second direction Y.

[0235] It should be noted thatFigure 9 In the embodiment, the number of the plurality of first bit lines 2120, the plurality of second bit lines 2220 and the plurality of third bit lines 2320 is eight. However, in practical applications, the number of the plurality of first bit lines 2120, the plurality of second bit lines 2220 and the plurality of third bit lines 2320 can be greater than or less than eight. The number of the plurality of first bit lines 2120, the plurality of second bit lines 2220 and the plurality of third bit lines 2320 is not specifically limited in the present application.

[0236] In addition, Figure 9 The spatial position distribution and connection mode of the first bit line 2120 and the second bit line 2220 shown in the embodiment are similar to those of the first bit line 1120 and the second bit line 1220 shown in the embodiment, and will not be described here for the sake of brevity. The spatial position distribution and connection mode of the second bit line 2220 and the third bit line 2320 will be described in detail below. Figure 2

[0237] Exemplarily, the plurality of second bit lines 2220 and the plurality of third bit lines 2320 can correspond to each other along the first direction Z. Exemplarily, the second bit line 2220 and the third bit line 2320 corresponding to each other along the first direction Z overlap along the second direction Y, i.e., the distance between the second bit line 2220 and the third bit line 2320 along the second direction Y is zero.

[0238] Exemplarily, the bit line 2221 and the bit line 2321 can correspond to each other along the first direction Z, and the distance between the bit line 2221 and the bit line 2321 along the second direction Y is zero. The bit line 2222 and the bit line 2322 can correspond to each other along the first direction Z, and the distance between the bit line 2222 and the bit line 2322 along the second direction Y is zero. The bit line 2223 and the bit line 2323 can correspond to each other along the first direction Z, and the distance between the bit line 2223 and the bit line 2323 along the second direction Y is zero. The bit line 2224 and the bit line 2324 can correspond to each other along the first direction Z, and the distance between the bit line 2224 and the bit line 2324 along the second direction Y is zero. The bit line 2225 and the bit line 2325 can correspond to each other along the first direction Z, and the distance between the bit line 2225 and the bit line 2325 along the second direction Y is zero. The bit line 2226 and the bit line 2326 can correspond to each other along the first direction Z, and the distance between the bit line 2226 and the bit line 2326 along the second direction Y is zero. The bit line 2227 and the bit line 2327 can correspond to each other along the first direction Z, and the distance between the bit line 2227 and the bit line 2327 along the second direction Y is zero. The bit line 2228 and the bit line 2328 can correspond to each other along the first direction Z, and the distance between the bit line 2228 and the bit line 2328 along the second direction Y is zero.

[0239] Exemplarily, as shown in FIG. 2B, the preset distance can further include a second preset distance S2. The second bit line 2220 can be connected with the third bit line 2320 which is spaced apart from the second bit line 2220 by the second preset distance S2 along the second direction Y. Figures 9-10H

[0240] It should be noted that the projection position distribution of the connected first bit line 2120 and second bit line 2220 on the plane formed by the second direction Y and the third direction X is similar to that of the first bit line 1120 and the second bit line 1220 shown in the embodiment, and will not be described here for the sake of brevity. The projection position distribution of the second bit line 2220 and the third bit line 2320 on the plane formed by the second direction Y and the third direction X will be described in detail below. Figures 3A-3H ​​The distribution of the projection positions of the connected first bit lines 1120 and second bit lines 1220 on the plane formed by the second direction Y and the third direction X is similar, and for the purpose of brevity, the present application will not be described here again.

[0241] Exemplarily, the second preset distance S2 can be greater than zero. In other words, the second bit lines 2220 can be connected with the bit lines in the third bit lines 2320 which do not correspond to the second bit lines 2220. Exemplarily, the second preset distance S2 can be greater than or equal to the distance H between the adjacent second bit lines 2220 and the third bit lines 2320 along the second direction Y. It should be understood that the distance H can be the distance between two adjacent second bit lines 2220 or two adjacent third bit lines 2320 along the second direction Y.

[0242] As shown in the figure, Figures 10A-10H As shown in the figure, Figure 10A The distance S21 can be the distance between the second bit line 2220 such as 2221 and the third bit line 2320 such as 2323 along the second direction Y, that is, the distance S21 can be greater than the distance H, such as the distance S21 can be twice the distance H. As shown in the figure, Figure 10B The distance S22 can be the distance between the second bit line 2220 such as 2222 and the third bit line 2320 such as 2321 along the second direction Y, that is, the distance S22 can be equal to the distance H.

[0243] It should be noted that, Figures 10A-10H In the figure, only two cases are shown in which the second preset distance S2 includes the distance S21 and the distance S22. However, in actual application, the second preset distance S2 can include a plurality of different and non-zero distances, for example, the second preset distance S2 can also include a distance S23 (not shown) and the like, wherein the distance S23 is three times, four times, five times, etc. of the distance H. The present application does not make specific limitations on the types of the second preset distance S2.

[0244] Exemplarily, as shown in the figure, Figures 9-10H The bit line 2221 can be connected with the bit line 2323 which is away from the bit line 2221 by the distance S21 along the second direction Y. The bit line 2222 can be connected with the bit line 2321 which is away from the bit line 2222 by the distance S22 along the second direction Y. The bit line 2223 can be connected with the bit line 2325 which is away from the bit line 2223 by the distance S21 along the second direction Y. The bit line 2224 can be connected with the bit line 2322 which is away from the bit line 2224 by the distance S21 along the second direction Y. The bit line 2225 can be connected with the bit line 2327 which is away from the bit line 2225 by the distance S21 along the second direction Y. The bit line 2226 can be connected with the bit line 2324 which is away from the bit line 2226 by the distance S21 along the second direction Y. The bit line 2227 can be connected with the bit line 2328 which is away from the bit line 2227 by the distance S22 along the second direction Y. The bit line 2228 can be connected with the bit line 2326 which is away from the bit line 2228 by the distance S21 along the second direction Y.

[0245] The semiconductor structure 2000 provided by the present application can be used to perform at least one operation such as reading, writing, erasing, etc. to realize the access of the memory cell. During the operation, the voltage is required to be applied to the plurality of first bit lines 2120 to realize the writing of the storage data to the memory cell, wherein the logic potential corresponding to the applied voltage can be 1 or 0.

[0246] It should be noted that the voltage applied to at least two bit lines in the plurality of first bit lines 2120 during the operation of the semiconductor structure 2000 can be different, i.e. the logic potentials of at least two bit lines in the plurality of first bit lines 2120 can be different. In addition, it should be understood that the logic potentials of the connected first bit line 2120, second bit line 2220 and third bit line 2320 are the same during the operation of the semiconductor structure 2000.

[0247] Figure 11 The logic potential distribution diagram of the bit lines 2121-2128, bit lines 2221-2228 and bit lines 2321-2328 is provided according to an exemplary embodiment of the present application. In response to the voltage applied to the plurality of first bit lines 2120 and the logic potentials of at least two adjacent first bit lines 2120 being different, the number of adjacent and same logic potential third bit lines 2320 can be greater than or equal to the number of adjacent and same logic potential first bit lines 2120 and / or second bit lines 2220; and / or the number of adjacent and same logic potential second bit lines 2220 can be greater than or equal to the number of adjacent and same logic potential first bit lines 2120.

[0248] It should be noted that, Figure 11 The logic potential distribution of the bit lines 2121-2128 and bit lines 2221-2228 shown is similar to Figure 4 The logic potential distribution of the bit lines 1121-1128 and bit lines 1221-1228 shown is similar. For the purpose of brevity, the present application will not be repeated here.

[0249] As can be known from the above, in response to the voltage applied to the plurality of first bit lines 2120 and the logic potentials of at least two adjacent first bit lines 2120 being different, the number of adjacent and same logic potential second bit lines 2220 can be greater than or equal to the number of adjacent and same logic potential first bit lines 2120.

[0250] For example, as Figure 11As shown, during the operation of the semiconductor structure 2000, different voltages can be applied to the first bit lines, such as the bit lines 2121-2128, and the logic potentials of the charged bit lines 2121-2128 can be 0, 0, 1, 0, 0, 1, 0, 0, respectively. It can be seen that the number of adjacent and same-logic-potential first bit lines 2120 can be 2. The logic potentials of the second bit lines, such as the bit lines 2221-2228, corresponding to the first bit lines, such as the bit lines 2121-2128, respectively, can be 0, 0, 0, 1, 1, 0, 0, 0, respectively. It can be seen that the number of adjacent and same-logic-potential second bit lines 1220 can be 3 or 2. As can be seen from the above, the number of adjacent and same-logic-potential second bit lines 2220, such as 3 or 2, can be greater than or equal to the number of adjacent and same-logic-potential first bit lines 2120, such as 2.

[0251] Since the logic potentials of the connected first bit lines 2120, second bit lines 2220, and third bit lines 2320 are the same, the logic potentials of the third bit lines, such as the bit lines 2321-2328, corresponding to the second bit lines, such as the bit lines 2221-2228, respectively, can be 0, 1, 0, 0, 0, 0, 1, 0. It can be seen that the bit lines 2323-2326, i.e., four bit lines, are adjacent and have the same logic potential. In other words, the number of adjacent and same-logic-potential third bit lines 2320 can be 4.

[0252] As can be seen from the above, the number of adjacent and same-logic-potential third bit lines 2320, such as 4, can be greater than or equal to the number of adjacent and same-logic-potential first bit lines 2120 and / or second bit lines 2220, such as 2 or 3.

[0253] Figure 12 A logic potential distribution diagram of the bit lines 2121-2128, the bit lines 2221-2228, and the bit lines 2321-2328 is provided according to another exemplary embodiment of the present application.

[0254] It should be noted that, Figure 12 The logic potential distribution of the bit lines 2121-2128 and the bit lines 2221-2228 shown is similar to Figure 5 The logic potential distribution of the bit lines 1121-1128 and the bit lines 1221-1228 shown is similar. For the purpose of brevity, the present application will not repeat the same here.

[0255] As can be known from the above, in response to the application of voltages to the plurality of first bit lines 2120 and the logic potentials of at least two adjacent first bit lines 2120 being different, the number of adjacent and same-logic-potential second bit lines 2220 can be greater than or equal to the number of adjacent and same-logic-potential first bit lines 2120.

[0256] For example, as Figure 12As shown, during operation of the semiconductor structure 2000, different voltages may be applied to first bit lines, such as bit lines 2121-2128. The logic potentials of the charged bit lines 2121-2128 may be 0, 1, 0, 1, 0, 1, 0, 1, respectively. It can be seen that the number of adjacent first bit lines 2120 having the same logic potential may be 0. The logic potentials of second bit lines, such as bit lines 2221-2228, corresponding to the first bit lines 2121-2128, respectively, may be 1, 1, 0, 1, 0, 1, 0, 0, respectively. It can be seen that the number of adjacent second bit lines 2220 having the same logic potential may be 2. As can be seen from the above, the number of adjacent second bit lines 2220 having the same logic potential, such as 2, may be greater than or equal to the number of adjacent first bit lines 2120 having the same logic potential, such as 0.

[0257] Since the connected first bit line 2120, second bit line 2220, and third bit line 2320 have the same logic potential, the logic potentials of the third bit lines (e.g., bit lines 2321-2328) corresponding to the second bit lines (e.g., bit lines 2221-2228) can be 1, 1, 1, 1, 0, 0, 0, 0, respectively. It can be seen that bit lines 2321-2324 (i.e., four bit lines) are adjacent and have the same logic potential, and bit lines 2325-2328 (i.e., four bit lines) are adjacent and have the same logic potential. In other words, the number of adjacent third bit lines 2320 with the same logic potential can be four.

[0258] As can be seen from the above, the number of adjacent third bit lines 2320 with the same logic potential, such as 4, may be greater than or equal to the number of adjacent first bit lines 2120 and / or second bit lines 2220 with the same logic potential, such as 0 or 2.

[0259] In the present application, by setting the first bit line to be connected to the second bit line at a first preset distance along the second direction and the second bit line to be connected to the third bit line at a second preset distance along the second direction, it is beneficial to increase the number of adjacent third bit lines with the same logic potential, and thus help to make the logic potentials of adjacent third bit lines the same, so as to make the voltage of the third bit line more stable, reduce the phenomenon such as parasitic capacitance generated by the different logic potentials of adjacent third bit lines, and thus help to improve the sense margin.

[0260] For example, Figure 8 As shown in FIG. 2 , a peripheral circuit 2500 including the sense amplifier 2400 may also be formed. Figure 1 The formation process and structure of the peripheral circuit 1500 shown in FIG1 are similar, and for the purpose of brevity, this application will not repeat them here.

[0261] For example, Figure 8As shown, the third memory cell array 2300 and the peripheral circuit 2500 can be bonded together to form a bonded layer 2600 through a bonding process. The bonded layer 2600 is similar to the bonded layer 1600 shown in FIG. 1B, and thus, the details of the bonded layer 1600 shown in FIG. 1B will not be repeated here for brevity. Figure 1 The structure of the bonded layer 1600 shown in FIG. 1B is similar to that of the bonded layer 2600 shown in FIG. 2B, and thus, the details of the bonded layer 1600 shown in FIG. 1B will not be repeated here for brevity.

[0262] Exemplarily, in the bonding process, the first bit line 2120 can be connected to the sense amplifier 2400 via the second bit line 2220 and the third bit line 2320. In other words, the first bit line 2120 can be connected to the sense amplifier 2400 via the second bit line 2220 and the third bit line 2320 connected thereto. The sense amplifier 2400 can be a differential amplifier, and in a read operation, the two terminals of the sense amplifier 2400 can be the sensing signals on a pair of bit lines. The connection of one terminal of the sense amplifier 2400 to the third bit line 2320 is beneficial to improve the read accuracy of the sense amplifier 2400, and thus, is beneficial to improve the sensing margin.

[0263] Since the content and structure involved in the description of the semiconductor structures 1000 and / or 2000 above can be fully or partially applicable to the method 3000 of manufacturing a semiconductor structure described herein, the content related or similar thereto will not be repeated here for brevity.

[0264] Although the exemplary structure and preparation method of the semiconductor structure are described herein, it can be understood that one or more features can be omitted, replaced or added from the preparation method of the semiconductor structure. In addition, the layers exemplified and their materials are merely exemplary.

[0265] Figure 14 is a block diagram of a system 10 having a storage system 12 according to an exemplary embodiment of the present application.

[0266] The system 10 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other appropriate electronic device having a storage system 12 located therein. As Figure 14As shown, the system 10 can include a host 18 and a memory system 12 having one or more three-dimensional memories 14 and a controller 16. The host 18 can be a processor of an electronic device, such as a central processing unit (CPU), or can be a system-on-chip (SoC), such as an application processor (AP). The host 18 can be configured to send or receive data to or from the three-dimensional memory 14.

[0267] The three-dimensional memory 14 can include the semiconductor structure 1000 and / or 2000 described in any embodiment of the present application. According to some embodiments, the controller 16 is coupled to the three-dimensional memory 14 and the host 18, and is configured to control the three-dimensional memory 14. The controller 16 can manage data stored in the three-dimensional memory 14 and communicate with the host 18. For example, the controller 16 can communicate with external devices (e.g., the host 18) according to a particular communication protocol.

[0268] The above description is merely exemplary of the application and of the application of the principles of the application. It is not intended to limit the scope of the disclosure to the precise form described. The disclosure encompasses numerous implementations of the application. The scope of the disclosure is both the following claims and any amendments during the pendency of this application.

Claims

1. A semiconductor structure, wherein, Comprising: a plurality of memory cell arrays distributed along a first direction, wherein the memory cell arrays comprise a plurality of memory cells arrayed along a second direction and a third direction, and a plurality of bit lines located at a side of the memory cells along the first direction, wherein the bit lines of the memory cell arrays are connected with bit lines located at a preset distance along the second direction of adjacent memory cell arrays; wherein the first direction, the second direction, and the third direction are pairwise intersected.

2. The semiconductor structure of claim 1, wherein, The plurality of memory cell arrays comprises: a first memory cell array comprising a plurality of first memory cells arrayed along the second direction and the third direction, and a plurality of first bit lines located at a side of the plurality of first memory cells along the first direction; and a second memory cell array located at a side of the first memory cell array along the first direction, and comprising a plurality of second memory cells arrayed along the second direction and the third direction, and a plurality of second bit lines located at a side of the second memory cells along the first direction; wherein the preset distance comprises a first preset distance, and the first bit lines are connected with the second bit lines at the first preset distance along the second direction.

3. The semiconductor structure of claim 2, wherein, The semiconductor structure further comprises: a sense amplifier, wherein the first bit lines are connected with the sense amplifier via the second bit lines connected therewith.

4. The semiconductor structure of claim 2, wherein, The first bit lines and the second bit lines both extend along the third direction and are connected with the first memory cells and the second memory cells distributed along the third direction, respectively.

5. The semiconductor structure according to claim 2, wherein: The first preset distance is greater than or equal to a distance between the first bit lines and the second bit lines adjacent along the second direction.

6. The semiconductor structure of claim 3, wherein, The plurality of memory cell arrays further comprises: a third memory cell array located at a side of the second memory cell array along the first direction, and comprising a plurality of third memory cells arrayed along the second direction and the third direction, and a plurality of third bit lines located at a side of the third memory cells along the first direction; wherein the preset distance further comprises a second preset distance, the second bit lines are connected with the third bit lines at the second preset distance along the second direction, the first bit lines are connected with the sense amplifier via the second bit lines and the third bit lines, and the second preset distance is greater than or equal to a distance between the second bit lines and the third bit lines adjacent along the second direction.

7. The semiconductor structure of any one of claims 2-5, wherein, The first memory cell comprises: a channel structure comprising a first end and a second end opposite along the first direction, wherein the first bit lines are located at a side of the first end along the first direction; and a capacitor located at a side of the second end along the first direction.

8. The semiconductor structure of claim 7, wherein, The first memory cell array further comprises: a word line extending along the second direction and connected with the plurality of first memory cells distributed along the second direction.

9. The semiconductor structure of claim 7, wherein, A material of the channel structure comprises a metal oxide semiconductor.

10. The semiconductor structure of claim 9, wherein, The metal oxide semiconductor comprises indium gallium zinc oxide.

11. The semiconductor structure of any one of claims 2-5, wherein, In response to applying voltages to a plurality of the first bit lines, at least two adjacent first bit lines have different logic potentials, and the first bit lines and the second bit lines connected thereto have the same logic potential, wherein the number of adjacent second bit lines having the same logic potential is greater than or equal to the number of adjacent first bit lines having the same logic potential.

12. The semiconductor structure of claim 6, wherein, In response to applying voltages to a plurality of the first bit lines, at least two adjacent first bit lines have different logic potentials, and the first bit lines, the second bit lines, and third bit lines connected thereto have the same logic potential, wherein the number of adjacent third bit lines having the same logic potential is greater than or equal to the number of adjacent first bit lines and / or the number of adjacent second bit lines having the same logic potential; and / or the number of adjacent second bit lines having the same logic potential is greater than or equal to the number of adjacent first bit lines having the same logic potential.

13. The semiconductor structure of claim 3, wherein, The semiconductor structure further comprises: a peripheral circuit, wherein the sense amplifier is located in the peripheral circuit.

14. The semiconductor structure of any one of claims 1-6, wherein, The preset distance is greater than or equal to 15 nanometers.

15. A method of fabricating a semiconductor structure, wherein, Comprising: forming a plurality of memory cell arrays distributed along a first direction, wherein the memory cell arrays comprise a plurality of memory cells arrayed along a second direction and a third direction, and a plurality of bit lines located on one side of the memory cells along the first direction; and connecting the bit lines of the memory cell arrays with bit lines of adjacent memory cell arrays located at a preset distance along the second direction; wherein the first direction, the second direction, and the third direction intersect each other.

16. The method of claim 15, wherein, Forming a plurality of memory cell arrays distributed along a first direction comprises: forming a first memory cell array comprising a plurality of first memory cells arrayed along a second direction and a third direction, and a plurality of first bit lines located on one side of the plurality of first memory cells along the first direction; and forming a second memory cell array on one side of the first memory cell array along the first direction, comprising a plurality of second memory cells arrayed along the second direction and the third direction, and a plurality of second bit lines located on one side of the second memory cells along the first direction; wherein the preset distance comprises a first preset distance, and connecting the bit lines of the memory cell arrays with bit lines of adjacent memory cell arrays located at a preset distance along the second direction comprises: connecting the first bit lines with the second bit lines located at the first preset distance along the second direction.

17. The method of claim 16, wherein, The method further comprises: connecting the first bit lines to a sense amplifier via the second bit lines connected thereto.

18. The method of claim 16, wherein, The first memory cells comprise a channel structure and a capacitor, wherein forming a first memory cell array comprises: forming a plurality of the capacitors arrayed along the second direction and the third direction; forming a plurality of the channel structures on one side of the capacitors along the first direction; and forming a plurality of the first bit lines on one side of the channel structures along the first direction.

19. The method of claim 18, wherein, Forming a first memory cell array further comprises: forming a word line extending along the second direction and connected with a plurality of the first memory cells distributed along the second direction.

20. The method of any one of claims 16-19, wherein, forming a second memory cell array includes: forming the second memory cell at a side of the first memory cell array along the first direction; and forming the second bit line at a side of the second memory cell along the first direction.

21. The method of claim 17, wherein, forming a plurality of memory cell arrays distributed along a first direction further includes: forming a third memory cell array at a side of the second memory cell array along the first direction, including a plurality of third memory cells arrayed along the second direction and the third direction, and a plurality of third bit lines located at a side of the third memory cells along the first direction; wherein the preset distance further includes a second preset distance, connecting the bit line of the memory cell array with a bit line of an adjacent memory cell array located at a preset distance along the second direction, including: connecting the first bit line with the second bit line at a distance of the first preset distance along the second direction; and connecting the second bit line with the third bit line at a distance of the second preset distance along the second direction; wherein the first bit line is connected with the sense amplifier via the second bit line and the third bit line, and the second preset distance is greater than or equal to a distance between the second bit line and the third bit line adjacent along the second direction.

22. A storage system, wherein, including: the semiconductor structure of any one of claims 1-14; and a controller coupled to the semiconductor structure for controlling the semiconductor structure to store data.

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