Semiconductor element with bit line structure and manufacturing method thereof

Abstract

The invention provides a semiconductor element and a manufacturing method of the semiconductor element. The semiconductor device includes: a substrate having a first recessed region; and a first bit line structure located in the first recessed region. The first bit line structure has a first spacer, a second spacer and a third spacer. The first spacer, the second spacer, and the third spacer have different materials.

Description

TECHNICAL FIELD

[0001] This application claims priority to U.S. Patent Application No. 18 / 640,236 (i.e., priority date of “April 19, 2024”), the contents of which are incorporated herein in their entirety.

[0002] The present disclosure relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a bit line structure having spacers. BACKGROUND

[0003] In a semiconductor device, a storage node contact can be formed between adjacent bit line structures. In a conventional process, a recess region can be formed adjacent to a bit line structure, and a material of the storage node contact can fill the recess region. In the operation of forming the recess region, the spacers of the bit line structure can inevitably be consumed, potentially increasing the likelihood of a problem of leakage current of the bit line structure to the storage node contact. The problem of leakage current can cause the performance of the semiconductor device to deteriorate, and is a limiting factor that must be addressed to further improve the integration of the semiconductor device.

[0004] Furthermore, as semiconductor devices become more highly integrated, the distance between bit line structures and / or the distance between bit line structures and storage node contacts is decreasing, which can increase the likelihood of a problem of significant parasitic capacitance.

[0005] The discussion of the background art in the preceding paragraphs is provided merely for background information. Statements in the discussion of the background art are not an admission that this section of the disclosure is prior art to the present disclosure, and any part of the discussion of the background art does not constitute admission that any part of the discussion of the background art, including its constituent paragraphs, is prior art to the present disclosure. SUMMARY

[0006] One aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a first recess region, and a first bit line structure in the first recess region. The first bit line structure has a first spacer, a second spacer, and a third spacer. The first spacer, the second spacer, and the third spacer have different materials.

[0007] Another aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate, and a first bit line structure disposed over the substrate. The first bit line structure has a first spacer continuously disposed on a sidewall of the first bit line structure and filling a space between the first bit line structure and the substrate.

[0008] Another aspect of the present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a first recessed region in a substrate, forming a bit line structure in the first recessed region, and disposing a first spacer in the first recessed region. The method further includes performing a surface treatment on the first spacer and partially removing the first spacer.

[0009] The first spacer can prevent the first bit line structure from being damaged or consumed. Thus, the problem of bit line structure leakage current to the storage node contact can be solved. The performance and operation reliability of the semiconductor device can also be improved.

[0010] Furthermore, by using a spacer with a low dielectric constant, the problem of parasitic capacitance between the bit line structures and / or between the bit line structures and the storage node contact can be further reduced.

[0011] The foregoing has outlined rather broadly the technical features of the present disclosure in order that the detailed description of the present disclosure that follows can be better understood. Additional technical features and advantages of the present disclosure will be described hereinafter. The present disclosure is directed to all such technically practical applications of the concepts disclosed herein and to structurally analogous or equivalent constructions of its other structural or process features that can be claimed as modifications or design alternatives to the specific embodiments disclosed herein. As will be realized by those skilled in the art applying current knowledge, the concepts disclosed herein and specific embodiments thereof can be alternatively realized. Without departing from the spirit of the present disclosure, such equivalent constructions can not be encompassed by the claims appended hereto. BRIEF DESCRIPTION OF DRAWINGS

[0012] The disclosure will be more fully understood from the following detailed description taken in connection with the accompanying drawings, in which:

[0013] FIG. 1A is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure;

[0014] FIG. 1B is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure;

[0015] FIG. 1C is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure;

[0016] FIG. 2A is a top view illustrating one or more stages of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0017] FIG. 2B is a cross-sectional view illustrating a semiconductor device taken along the cross-sectional line A-A’ in FIG. 2A

[0018] FIG. 2C ​is a cross-sectional view illustrating a semiconductor element taken along the cross-sectional line B-B' in FIG. 2A

[0019] FIG. 3A is a top view illustrating one or more stages of a method of manufacturing a semiconductor element according to some embodiments of the present disclosure;

[0020] FIG. 3B is a cross-sectional view illustrating a semiconductor element taken along the cross-sectional line A-A' in FIG. 3A

[0021] FIG. 4A is a top view illustrating one or more stages of a method of manufacturing a semiconductor element according to some embodiments of the present disclosure;

[0022] FIG. 4B is a cross-sectional view illustrating a semiconductor element taken along the cross-sectional line A-A' in FIG. 4A

[0023] FIG. 4C is a cross-sectional view illustrating a semiconductor element taken along the cross-sectional line B-B' in FIG. 4A

[0024] FIG. 5A is a cross-sectional view illustrating one or more stages of a method of manufacturing a semiconductor element according to some embodiments of the present disclosure;

[0025] FIG. 5B is a cross-sectional view illustrating one or more stages of a method of manufacturing a semiconductor element according to some embodiments of the present disclosure;

[0026] FIG. 6A is a cross-sectional view illustrating one or more stages of a method of manufacturing a semiconductor element according to some embodiments of the present disclosure;

[0027] FIG. 6B is a cross-sectional view illustrating one or more stages of a method of manufacturing a semiconductor element according to some embodiments of the present disclosure;

[0028] FIG. 7A is a cross-sectional view illustrating one or more stages of a method of manufacturing a semiconductor element according to some embodiments of the present disclosure;

[0029] FIG. 7B is a cross-sectional view illustrating one or more stages of a method of manufacturing a semiconductor element according to some embodiments of the present disclosure;

[0030] FIG. 8A is a cross-sectional view illustrating one or more stages of a method of manufacturing a semiconductor element according to some embodiments of the present disclosure;

[0031] FIG. 8B ​​​​is a cross-sectional view illustrating one or more stages of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0032] FIG. 9A is a cross-sectional view illustrating one or more stages of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0033] FIG. 9B is a cross-sectional view illustrating one or more stages of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0034] FIG. 10A is a cross-sectional view illustrating one or more stages of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0035] FIG. 10B is a cross-sectional view illustrating one or more stages of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0036] FIG. 11 is a cross-sectional view illustrating one or more stages of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0037] FIG. 12 is a cross-sectional view illustrating one or more stages of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure; and

[0038] FIG. 13 is a flowchart illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0039] Wherein the reference numerals are explained as follows:

[0040] 1a: semiconductor device

[0041] 1b: semiconductor device

[0042] 1c: semiconductor device

[0043] 10: substrate

[0044] 10a: active region

[0045] 10d1: intermediate layer

[0046] 10d2: dielectric layer

[0047] 10h1: recessed region

[0048] 10h1b: bottom surface

[0049] 10h1s: sidewall

[0050] 10h2: recessed region

[0051] 10i: isolation region

[0052] 101: first doped region

[0053] 102: second doped region

[0054] 11: bit line structure

[0055] 11a: bit line overlay pattern

[0056] 11b: conductive pattern

[0057] 11c: conductive pattern

[0058] 11d: bit line contact

[0059] 11s: sidewall

[0060] 11s1: spacer

[0061] 11s1': treated material

[0062] 11s2: spacer

[0063] 11s3: spacer

[0064] 12: bit line structure

[0065] 12a: bit line overlay pattern

[0066] 12b: conductive pattern

[0067] 12c: conductive pattern

[0068] 12d: bit line contact

[0069] 12s1: spacer

[0070] 12s1': treated material

[0071] 12s2: spacer

[0072] 12s3: spacer

[0073] 13: storage node contact

[0074] 14: sacrificial pattern

[0075] 15: insulating pattern

[0076] WL: word line

[0077] WLc: cap layer

[0078] 130: method

[0079] S131: step

[0080] S132: step

[0081] S133: step

[0082] S134: step

[0083] S135: step

[0084] S136: step

[0085] S137: step DETAILED DESCRIPTION

[0086] Embodiments or examples of the disclosure shown in the drawings will now be described using specific language. It will be understood that such embodiments are not intended to limit the scope of the disclosure. Any alterations or modifications to the described embodiments, and any further applications of the principles disclosed herein, are contemplated as falling within the scope of the present disclosure. Element(s) shown with broken lines can be optional elements in the particular embodiments. Any reference to claims in this document is to be construed in accordance with 35 U.S.C. § 122(b)(2) and 35 U.S.C. § 101.

[0087] It will be understood that, although the terms first, second, third, etc. can be used herein to describe various components, members, regions, layers or sections, these components, members, regions, layers or sections should not be limited by these terms. Instead, these terms are only used to distinguish one component, member, region, layer or section from another component, member, region, layer or section. Thus, a first component, member, region, layer or section discussed below could be termed a second component, member, region, layer or section without departing from the teachings of the present disclosure.

[0088] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the inventive concept. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, components, and / or groups of features, integers, steps, operations, components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, and / or groups thereof.

[0089] FIG. 1A is a cross-sectional view illustrating a semiconductor element 1a of some embodiments of the present disclosure. In some embodiments, the semiconductor element 1a can be disposed adjacent to a circuit. For example, the semiconductor element 1a can be disposed adjacent to a memory element, such as a dynamic random-access memory (DRAM) element or the like.

[0090] Referring to FIG. 1AThe semiconductor element 1a can include a substrate 10 and a bit line structure 11 and a bit line structure 12. The bit line structure 11 and the bit line structure 12 can be disposed on the substrate 10.

[0091] The substrate 10 can include a semiconductor substrate. In some embodiments, the semiconductor material of the substrate 10 can include, for example, silicon (Si) (e.g., single crystal silicon, polycrystalline silicon, and amorphous silicon), germanium (Ge), gallium (Ga), and indium (In). In some embodiments, the semiconductor material of the substrate 10 can include a compound semiconductor including silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium arsenide (GaAs), gallium phosphide (GaP), indium arsenide (InAs), indium phosphide (InP), or other IV-IV, III-V, or II-VI semiconductor materials.

[0092] In some embodiments, the substrate 10 can include a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, a multilayer substrate, or a graded substrate. For example, an SOI substrate can include a layer of semiconductor material formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or similar material. The insulator layer can be disposed on a substrate, typically a silicon or glass substrate. In some embodiments, the substrate 10 can be a wafer, such as a silicon wafer. The substrate 10 can be doped (e.g., with P-type or N-type dopants) or undoped.

[0093] From a cross-sectional view as shown in FIG. 1A, the substrate 10 can include active regions 10a and isolation regions 10i. From a top view as shown in FIG. 1B, a plurality of active regions 10a can be defined by the isolation regions 10i. For example, the plurality of active regions 10a can be separated from each other by the isolation regions 10i. FIG. 1A FIG. 2A From a cross-sectional view as shown in FIG. 1A, the substrate 10 can include active regions 10a and isolation regions 10i. From a top view as shown in FIG. 1B, a plurality of active regions 10a can be defined by the isolation regions 10i. For example, the plurality of active regions 10a can be separated from each other by the isolation regions 10i.

[0094] The active regions 10a and the isolation regions 10i can be formed in the substrate 10. In some embodiments, the isolation regions 10i can include shallow trench isolation (STI) structures.

[0095] ​The wall oxide, the liner, and the gap fill dielectric can be formed sequentially as the isolation region 10i. The liner can be formed by stacking silicon oxide (SiO2) and silicon nitride (Si3N4). The gap fill dielectric can include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), low dielectric constant (e.g., dielectric constant less than that of silicon oxide, which is about 3.9) dielectric materials (e.g., phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.), similar materials, or combinations thereof. In another embodiment, silicon nitride can be used as the gap fill dielectric in the isolation region 10i.

[0096] The substrate 10 can include a plurality of doped regions, such as a first doped region 101 and a second doped region 102. The first doped region 101 and the second doped region 102 can be formed in the active region 10a. In some embodiments, the first doped region 101 and the second doped region 102 can be disposed on or adjacent to a top surface of the active region 10a. The first doped region 101 and the second doped region 102 can be separated from each other by the isolation region 10i. From the top view shown, the first doped region 101 and the second doped region 102 can be located on opposite sides of one of the word lines WL. FIG. 2A

[0097] In some embodiments, the first doped region 101 and the second doped region 102 can be doped with N-type dopants, such as phosphorus (P), arsenic (As), or antimony (Sb). In some other embodiments, the first doped region 101 and the second doped region 102 can be doped with P-type dopants, such as boron (B) or indium (In). In some embodiments, the first doped region 101 and the second doped region 102 can be doped with dopants or impurity ions of the same conductivity type. In some embodiments, the first doped region 101 and the second doped region 102 can be doped with dopants or impurity ions of different conductivity types.

[0098] The bottom surfaces of the first doped region 101 and the second doped region 102 can be located at a predetermined depth from the top surface of the active region 10a. The first doped region 101 and the second doped region 102 can be adjacent to the sidewalls of the isolation region 10i. The bottom surfaces of the first doped region 101 and the second doped region 102 can be higher than the bottom surface of the isolation region 10i.

[0099] ​In some embodiments, the first doped region 101 and the second doped region 102 can be referred to as source / drain regions. In some embodiments, the first doped region 101 can include a bit line contact region and can be electrically connected with a bit line structure 11. The second doped region 102 can include a storage node contact region and can be electrically connected with a memory element through a storage node contact 13. In some embodiments, the memory element can be a capacitor and can include a lower electrode, an upper electrode, and a dielectric layer therebetween. In other embodiments, the memory element can be a variable resistance pattern capable of switching between two resistance states by an electrical pulse applied to the memory element. For example, the memory element can include a phase change material capable of changing a crystalline state according to an amount of current, such as a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an anti-ferromagnetic material.

[0100] An intermediate layer 10d1 can be disposed on the substrate 10. The intermediate layer 10d1 can be disposed on a top surface of the active region 10a. The intermediate layer 10d1 can be formed of a single insulating layer or a plurality of insulating layers. The intermediate layer 10d1 can include an isolation material or a dielectric material. The intermediate layer 10d1 can include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), and / or silicon oxynitride. The intermediate layer 10d1 can define a bit line contact region, as shown. FIG. 3B

[0101] A recessed region 10h1 can be formed in the substrate 10. The bit line structure 11 can be disposed in the recessed region 10h1 and contact (e.g., directly contact) the first doped region 101. Thus, the first doped region 101 can include a bit line contact region.

[0102] The recessed region 10h1 can be formed between the isolation regions 10i. The recessed region 10h1 can be formed to expose the first doped region 101 between the isolation regions 10i.

[0103] The recessed region 10h1 can be recessed into the substrate 10 from a top surface of the active region 10a and / or from the intermediate layer 10d1. The recessed region 10h1 can have a sidewall 10h1s and a bottom surface 10h1b. The sidewall 10h1s can extend from the bottom surface 10h1b to a top surface of the active region 10a and / or the intermediate layer 10d1.

[0104] ​The sidewall 10hl s of the recessed region 10hl can be sloped with respect to a top surface of the active region 10a and / or the intermediate layer 10dl. The recessed region 10hl can taper or narrow toward an interior of the substrate 10. The width of the recessed region 10hl can vary. For example, the width of the recessed region 10hl adjacent to the top surface of the active region 10a can be greater than the width of the recessed region 10hl adjacent to the bottom surface 10hlb. The minimum width of the recessed region 10hl can be the width of the bottom surface 10hlb of the recessed region 10hl.

[0105] The width of the bottom surface 10hlb of the recessed region 10hl can be greater than the distance between the isolation regions 10i. The minimum width of the bottom surface 10hlb of the recessed region 10hl can be greater than the width of the bit line structure 11. For example, the bottom surface of the bit line structure 11 can contact the exposed surfaces of the first doped region 101 and the isolation regions 10i.

[0106] The bottom surface 10hlb of the recessed region 10hl can be positioned higher than the bottom surface of the first doped region 101. For example, the recessed region 10hl can not extend beyond the bottom surface of the first doped region 101.

[0107] A recessed region 10h2 can be formed in the substrate 10 to expose a second doped region 102. The second doped region 102 can contact a storage node contact 13. Thus, the second doped region 102 can comprise a storage node contact region.

[0108] The recessed region 10h2 can be recessed from the top surface of the active region 10a and / or from the intermediate layer 10dl. The recessed region 10h2 can be adjacent to the recessed region 10hl.

[0109] The storage node contact 13 can be formed from, for example, a doped polysilicon layer, and can extend through the intermediate layer 10dl to contact (e.g., directly contact) the second doped region 102.

[0110] A bottom surface of the storage node contact 13 can be positioned lower than the bottom surface 10hlb of the recessed region 10hl.

[0111] The bit line structure 11 can comprise a bit line contact 11d and a stack pattern (e.g., a conductive pattern 11c, a conductive pattern 11b, and a bit line cover pattern 11a).

[0112] The bit line contact 11d can be disposed in the recessed region 10hl. A portion of the bit line contact 11d can contact (e.g., directly contact) the first doped region 101. A bottom surface of the bit line contact 11d can be positioned lower than a top surface of the active region 10a or lower than the intermediate layer 10dl. The bit line contact 11d can comprise a doped polysilicon.

[0113] The conductive pattern 11c can include any suitable material, such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (W2N, WN, WN2), similar materials, or combinations thereof.

[0114] The conductive pattern 11b can include any suitable metal, such as tungsten (W), copper (Cu), ruthenium (Ru), aluminum (Al), gold (Au), cobalt (Co), similar materials, or combinations thereof.

[0115] The bit line overlay pattern 11a can include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), and / or silicon oxynitride.

[0116] The bit line structure 11 can include a spacer 11s1, a spacer 11s2, and a spacer 11s3 formed on two sidewalls 11s of the bit line structure 11. The spacer 11s1, the spacer 11s2, and the spacer 11s3 can also be referred to as a first spacer, a second spacer, and a third spacer. The spacer 11s1 can be disposed between the spacer 11s2 and the sidewall 11s of the bit line structure 11. For example, the spacer 11s1 can directly contact the sidewall of the bit line structure 11. The spacer 11s2 can be disposed between the spacer 11s1 and the spacer 11s3. The spacer 11s3 can be the outermost spacer of the bit line structure 11.

[0117] The spacer 11s1, the spacer 11s2, and the spacer 11s3 can have different materials. In some embodiments, the spacer 11s1 can include a carbon-containing material, such as SiC (silicon carbide), SiOC (silicon oxycarbide), SiCN (silicon carbonitride), and SiOCN (silicon oxycarbonitride). The spacer 11s2 can include an oxygen-containing material, such as silicon oxide (SiO2). The spacer 11s3 can include a nitrogen-containing material, such as silicon nitride (Si3N4).

[0118] The spacer 11s1, the spacer 11s2, and the spacer 11s3 can have different dielectric constants. In some embodiments, the spacer 11s1 can have a first dielectric constant, the spacer 11s2 can have a second dielectric constant, and the spacer 11s3 can have a third dielectric constant.

[0119] The first dielectric constant can be lower than the second dielectric constant. The second dielectric constant can be lower than the third dielectric constant. For example, the third dielectric constant can be about 7.5, and the second dielectric constant can be less than about 7.5. For example, the second dielectric constant can be about 3.9, and the first dielectric constant can be less than about 3.9. For example, the first dielectric constant can be in a range of about 1.0 to 3.9. In some embodiments, the spacer 11s1 can include a low-k material.

[0120] The spacer 11s1 can have a thickness of about 10 nanometers (nm) or less. In one embodiment, the spacer 11s1 can have a thickness from about 5 nm to about 8 nm.

[0121] The spacer 11s1 can be continuously disposed on the sidewall of the bit line structure 11. For example, the spacer 11s1 can contact (e.g., directly contact) the bit line cover pattern 11a, the conductive pattern 11b, the conductive pattern 11c, and the bit line contact 11d. The spacer 11s1 can be disposed in the recessed region 10h1. The spacer 11s1 can fill the space between the bit line structure 11 and the substrate 10. The spacer 11s1 can fill the space between the bit line structure 11 and the isolation region 10i.

[0122] The spacer 11s1 can extend between the sidewall 10h1s and the bit line contact 11d. The spacer 11s1 can contact (e.g., directly contact) the sidewall 10h1s and the bottom surface 10h1b of the recessed region 10h1. In some embodiments, there can be no other material between the sidewall 10h1s and the bit line contact 11d other than the spacer 11s1.

[0123] In some embodiments, the storage node contact 13 can truncate the sidewall 10h1s, and the spacer 11s1 can contact (e.g., directly contact) the storage node contact 13.

[0124] The bit line structure 12 can be separated (or isolated) from the bit line structure 11 by the storage node contact 13. The bit line structure 12 can be disposed on the intermediate layer 10d1. The bit line structure 12 can be separated (or isolated) from the substrate 10 by the intermediate layer 10d1.

[0125] The bit line structure 12 can include a bit line contact 12d and stacked patterns (e.g., a conductive pattern 12c, a conductive pattern 12b, and a bit line cover pattern 12a). The bit line structure 12 can include spacers 12s1, 12s2, and 12s3 formed on two sidewalls of the bit line structure 12. Detailed descriptions of the bit line structure 12 can refer to the detailed descriptions of the bit line structure 11 provided above, which are not repeated for brevity.

[0126] FIG. 1B is a cross-sectional view illustrating a semiconductor element of some embodiments of the present disclosure. FIG. 1A is a cross-sectional view taken along the cross-sectional line A-A’ in FIG. 4A is a cross-sectional view taken along the cross-sectional line A-A’ in FIG. 1B is a cross-sectional view taken along the cross-sectional line B-B’ in FIG. 4A is a cross-sectional view taken along the cross-sectional line B-B’ in FIG. 1B The semiconductor element 1b of FIG. 10B is similar to the semiconductor element 1a of FIG. 10A. FIG. 1AThe semiconductor device 1a of FIG. 1A is similar to the semiconductor device 1 of FIG. 1, except for the differences described below.

[0127] The active region 10a can protrude more than the isolation region 10i. The dielectric layer 10d2 can be conformally formed on the active region 10a and the isolation region 10i.

[0128] The word line WL can be disposed on the dielectric layer 10d2. The word line WL can include a gate electrode. The word line WL can extend through the active region 10a and the isolation region 10i. A cap layer WLc of the word line WL can be disposed on the gate electrode of the word line WL. The cap layer WLc can be used to protect the gate electrode of the word line WL.

[0129] The bit line contact 11d of the bit line structure 11 can be partially surrounded by the cap layer WLc. The bit line contact 12d of the bit line structure 12 can be partially surrounded by the cap layer WLc.

[0130] The spacer 11s1 and the spacer 12s1 can be connected. For example, the spacer 11s1 and the spacer 12s1 can extend between the bit line structure 11 and the bit line structure 12. For example, the carbon-containing material of the spacer 11s1 and the spacer 12s1 can extend between the bit line structure 11 and the bit line structure 12.

[0131] The spacer 11s2 and the spacer 12s2 can be connected. For example, the spacer 11s2 and the spacer 12s2 can extend between the bit line structure 11 and the bit line structure 12. For example, the oxygen-containing material of the spacer 11s2 and the spacer 12s2 can extend between the bit line structure 11 and the bit line structure 12.

[0132] The spacer 11s3 and the spacer 12s3 can be connected. For example, the spacer 11s3 and the spacer 12s3 can extend between the bit line structure 11 and the bit line structure 12. For example, the nitrogen-containing material of the spacer 11s3 and the spacer 12s3 can extend between the bit line structure 11 and the bit line structure 12.

[0133] The insulating pattern 15 can be formed between the bit line structure 11 and the bit line structure 12. For example, the insulating pattern 15 can be disposed on the spacer 11s3 and the spacer 12s3.

[0134] FIG. 1C is a cross-sectional view illustrating a semiconductor device 1c of some embodiments of the present disclosure. FIG. 1C The semiconductor device 1c of FIG. 1C is similar to the semiconductor device 1 of FIG. 1, except for the differences described below. FIG. 1Asemiconductor element 1a, except that the bottom surface of the storage node contact 13 can be positioned at a position higher than the bottom surface 10h1b of the recessed region 10h1 with respect to the substrate 10. For example, the bottom surface 10h1b of the recessed region 10h1 can be positioned at a position lower than the bottom surface of the storage node contact 13 with respect to the substrate 10. For example, the bottom surface of the bit line structure 11 (at the same height as the bottom surface 10h1b) can be positioned at a position lower than the bottom surface of the storage node contact 13 with respect to the substrate 10.

[0135] In a conventional process, a recessed region (e.g., the recessed region 10h2) can be formed adjacent to a bit line structure (e.g., the bit line structure 11), and a material of a storage node contact (e.g., the storage node contact 13) can fill the recessed region. The spacers (e.g., the spacers 11s1, 11s2, and 11s3) of the bit line structure can be inevitably consumed in the operation (e.g., the operation in the recessed region 10h2) of forming the recessed region, which increases the possibility of the problem of the bit line structure leakage current to the storage node contact. The problem of the leakage current causes the performance of the semiconductor element to deteriorate, and is a limiting factor that must be addressed to further improve the integration of the semiconductor element. FIG. 11

[0136] The first spacer (e.g., the spacer 11s1) can prevent the first bit line structure (e.g., the bit line structure 11) from being damaged or consumed. Thus, the problem of the bit line structure leakage current to the storage node contact can be addressed. The performance and the operation reliability of the semiconductor element can also be improved.

[0137] In addition, by using the spacer (e.g., the spacer 11s1) with a low dielectric constant, the problem of parasitic capacitance between the bit line structures and / or between the bit line structure and the storage node contact can be further reduced.

[0138] FIG. 2A , FIG. 2B , FIG. 2C , FIG. 3A , FIG. 3B , FIG. 4A , FIG. 4B , FIG. 4C , FIG. 5A , FIG. 5B , FIG. 6A , FIG. 6B , FIG. 7A , FIG. 7B , FIG. 8A , FIG. 8B , FIG. 9A , FIG. 9B , FIG. 10A , FIG. 10B , FIG. 11 and FIG. 12 ​Stages of a method of manufacturing a semiconductor device exemplifying some embodiments of the present disclosure. At least some of these drawings have been simplified for a better understanding. In some embodiments, FIG. 1A Semiconductor element 1a in FIG. 1A can be manufactured by operations described below FIG. 2A , FIG. 2B , FIG. 2C , FIG. 3A , FIG. 3B , FIG. 4A , FIG. 4B , FIG. 4C , FIG. 5A , FIG. 5B , FIG. 6A , FIG. 6B , FIG. 7A , FIG. 7B , FIG. 8A , FIG. 8B , FIG. 9A , FIG. 9B , FIG. 10A , FIG. 10B , FIG. 11 and FIG. 12 .

[0139] As shown in FIG. 1A, the semiconductor element can include a plurality of active regions 10a. The active regions 10a can be arranged in a zigzag form. For example, the active regions 10a can be two-dimensionally arranged along a first direction D1 and a second direction D2 intersecting or crossing (e.g., perpendicular to) the first direction D1. The active regions 10a can have a long axis oblique to the first direction D1 and the second direction D2. FIG. 2A

[0140] The isolation regions 10i can be formed by an STI (shallow trench isolation) process. For example, after a pad layer (not shown) is formed on the substrate 10, the pad layer and the substrate 10 are etched using an isolation mask (not shown) to define isolation trenches. The isolation trenches are filled with a dielectric material, and the isolation regions 10i are accordingly formed.

[0141] The isolation trenches can be filled with the dielectric material by a chemical vapor deposition (CVD) process. In addition, a planarization process, such as chemical-mechanical polishing (CMP), can be additionally performed.

[0142] The semiconductor element can also include a plurality of word lines WL. Each active region 10a can intersect two word lines WL and can be divided into three doped regions by the two word lines WL. For example, the active region 10a can be divided into a first doped region 101 disposed between the two word lines WL and second doped regions 102 located on both sides of the first doped region 101. ​

[0143] The word lines WL may each have a line shape extending in any direction, for example, the first direction D1 . The word lines WL may each be a buried gate buried in a trench penetrating the active region 10 a and the isolation region 10 i .

[0144] FIG. 2B Examples along FIG. 2A A sectional view taken along the section line AA' in FIG. FIG. 2C Examples along FIG. 2A A cross-sectional view taken along the section line BB'.

[0145] like FIG. 2B As shown, the first doping region 101 and the two second doping regions 102 may be formed in the active region 10a. The first doping region 101 and the two second doping regions 102 may be separated from each other by isolation regions 10i. FIG. 2C As shown, a dielectric layer 10d2 may be disposed between the word line WL and the active region 10a, and may also be disposed between the word line WL and the isolation region 10i. The active region 10a may protrude into the word line WL. The active region 10a may form a fin structure relative to the isolation region 10i.

[0146] like FIG. 3A As shown, one or more recessed regions may be formed in the substrate 10. For example, a recessed region 10h1 may be formed in the first doped region 101 between two word lines WL. In some embodiments, the substrate 10 may be patterned to form one or more recessed regions that expose the first doped region 101. In some embodiments, the substrate 10 may be patterned to form one or more recessed regions in the first doped region 101 that expose a bit line contact region, and the bit line contact region is configured to be electrically connected to the bit line structure.

[0147] In some embodiments, the recessed areas may be arranged in a honeycomb form or a zigzag form in a top view. In some embodiments, the recessed areas may each have a circular shape or an elliptical shape.

[0148] FIG. 3B Examples along FIG. 3A The intermediate layer 10d1 may be disposed on the substrate 10. The intermediate layer 10d1 may be disposed on the top surface of the active region 10a.

[0149] In some embodiments, the recessed region 10 h 1 may be formed by an etching operation, such as an anisotropic etching operation. For example, the intermediate layer 10 d 1 may define the first doped region 101 or a bit line contact region in the first doped region 101 .

[0150] In some embodiments, a portion of the isolation region 10i and a portion of the intermediate layer 10d1 adjacent to the first doped region 101 can be etched together. For example, the sidewall 10h1s can be inclined with respect to the active region 10a and / or a top surface of the intermediate layer 10d1. The recessed region 10h1 can taper or taper inwardly toward an interior of the substrate 10. The sidewall of the intermediate layer 10d1 can be substantially aligned with the sidewall 10h1s.

[0151] As shown in FIG. 4A , a plurality of bit line structures (e.g., bit line structure 11 and bit line structure 12) can be formed over the substrate 10.

[0152] The bit line structures can each have a linear shape extending in a second direction D2 crossing the word line WL. The bit line structures can each overlap a plurality of recessed regions. For example, the bit line structure 11 can overlap the recessed region 10h1.

[0153] FIG. 4B A cross-sectional view taken along the section line A-A’ in FIG. 4A is illustrated. FIG. 4C A cross-sectional view taken along the section line B-B’ in FIG. 4A is illustrated.

[0154] As shown in FIG. 4B and FIG. 4C , the bit line structure 11 can include a bit line contact 11d to connect a bit line contact region in the first doped region 101. The bit line structure 12 can include a bit line contact 12d disposed over the intermediate layer 10d1. The bit line structures can each include a bit line contact, a conductive pattern, a conductive pattern, and a bit line cover pattern stacked in sequence.

[0155] In some embodiments, the bit line structure 11 can be formed by disposing a material of the bit line contact 11d over the intermediate layer 10d1 to fill the recessed region 10h1, and sequentially disposing materials of the conductive pattern 11c, the conductive pattern 11b, and the bit line cover pattern 11a. Thereafter, the materials can be etched by a bit line mask pattern.

[0156] FIG. 5A and FIG. 5B operations following the operations of FIG. 4A are illustrated. FIG. 5A A cross-sectional view taken along the line A-A’ of FIG. 4A is illustrated. FIG. 5B A cross-sectional view taken along the line B-B’ of FIG. 4A is illustrated.

[0157] As shown in FIG. 5A and FIG. 5BAs shown, a material of the spacer 11s1 can be formed on the opposing sidewalls 11s of the bitline structure 11. A material of the spacer 12s1 can be formed on the opposing sidewalls 11s of the bitline structure 12. In some embodiments, the spacer 11s1 and the spacer 12s1 can each include a carbon-containing material, such as SiC (silicon carbide), SiOC (silicon oxycarbide), SiCN (silicon carbon nitride), and SiOCN (silicon oxycarbonitride). In some embodiments, the spacer 11s1 and the spacer 12s1 can be formed by any suitable process, such as low-pressure chemical vapor deposition (LPCVD), plasma enhanced-chemical vapor deposition (PECVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), thermal growth, or chemical growth.

[0158] In some embodiments, the material of the spacer 11s1 and the spacer 12s1 can fill the recessed region 10h1 and conformably cover the bitline structure 11 and the bitline structure 12.

[0159] In some embodiments, a thickness of the material of the spacer 11s1 on the bitline structure 11 can be in a range from about 15 nm to about 20 nm. In some embodiments, a thickness of the material of the spacer 12s1 on the bitline structure 12 can be in a range from about 15 nm to about 20 nm.

[0160] FIG. 6A and FIG. 6B illustrated FIG. 5A and FIG. 5B operations following the operations of

[0161] As illustrated in FIG. 6A and FIG. 6B the material of the spacer 11s1 and the spacer 12s1 can be surface treated to change or modify surface properties of the material of the spacer 11s1 and the spacer 12s1. For example, portions of the material of the spacer 11s1 and the spacer 12s1 can be oxidized by oxygen plasma to increase an etch rate of the surface of the material of the spacer 11s1 and the spacer 12s1.

[0162] Following the surface treatment, a treated material (such as a treated material 11s1’ of the spacer 11s1 and a treated material 12s1’ of the spacer 12s1) can be formed.

[0163] FIG. 7A andFIG. 7B operations following the operations of FIG. 6A and FIG. 6B .

[0164] As shown in FIG. 7A and FIG. 7B , the processed material (e.g., the processed material 11s1’ of the spacer 11s1 and the processed material 12s1’ of the spacer 12s1) can be removed by any suitable etching operation (e.g., a wet etching operation). After the etching operation, the thickness of the material of the spacer 11s1 on the bit line structure 11 can be in a range from about 5 nm to about 8 nm, and the thickness of the material of the spacer 12s1 on the bit line structure 12 can be in a range from about 5 nm to about 8 nm.

[0165] FIG. 8A and FIG. 8B operations following the operations of FIG. 7A and FIG. 7B .

[0166] As shown in FIG. 8A and FIG. 8B , the material of the spacer 11s2 can be formed on the opposing sidewalls of the bit line structure 11. The material of the spacer 12s2 can be formed on the opposing sidewalls of the bit line structure 12. In some embodiments, the spacer 11s2 and the spacer 12s2 can each include an oxygen-containing material, e.g., silicon oxide (SiO2). In some embodiments, the material of the spacer 11s2 and the spacer 12s2 can be formed by any suitable process, e.g., atomic layer deposition (ALD).

[0167] FIG. 9A and FIG. 9B operations following the operations of FIG. 8A and FIG. 8B .

[0168] As shown in FIG. 9A and FIG. 9B , the material of the spacer 11s3 can be formed on the opposing sidewalls of the bit line structure 11. The material of the spacer 12s3 can be formed on the opposing sidewalls of the bit line structure 12. In some embodiments, the spacer 11s3 and the spacer 12s3 can each include a nitrogen-containing material, e.g., silicon nitride (Si3N4). In some embodiments, the material of the spacer 11s3 and the spacer 12s3 can be formed by any suitable process, e.g., atomic layer deposition (ALD).

[0169] FIG. 10A and FIG. 10B operations following the operations of FIG. 9A and FIG. 9B .

[0170] As shown in FIG. 10A , the sacrificial patterns 14 can be formed between the plurality of bitline structures (e.g., the bitline structure 11 and the bitline structure 12). In FIG. 4A , the upper view, the sacrificial patterns 14 can be spaced apart from each other in the second direction D2 and can be disposed between the wordlines WL. The sacrificial patterns 14 can have an etch selectivity with respect to the material of the spacers 11s3 and 12s3. For example, the sacrificial patterns 14 can have a higher etch rate than the material of the spacers 11s3 and 12s3. For example, the sacrificial patterns 14 can be formed by a spin-on-hard mask (SOH) material (e.g., SOH silicon oxide).

[0171] As shown in FIG. 10B , the insulating patterns 15 can be formed between the plurality of bitline structures (e.g., the bitline structure 11 and the bitline structure 12). In FIG. 4A , the upper view, the insulating patterns 15 can fill the spaces defined by the plurality of bitline structures and the sacrificial patterns 14 and can overlap the wordlines WL. The insulating patterns 15 can include an insulating material that has an etch selectivity with respect to the sacrificial patterns 14. For example, the insulating patterns 15 can include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), and / or silicon oxynitride.

[0172] In some embodiments, the sacrificial patterns 14 and the insulating patterns 15 can be alternately formed and can be arranged between the bitline structures along the second direction D2.

[0173] In some embodiments, the formation of the sacrificial patterns 14 and the insulating patterns 15 can include forming a material of the sacrificial patterns 14 to fill the spaces between the bitline structures; forming a mask pattern (which can extend in the first direction D1 parallel to the wordlines WL) over the material of the sacrificial patterns 14; anisotropically etching the material of the sacrificial patterns 14 using the mask pattern and the bitline structures as etch masks to form the sacrificial patterns 14 that expose the wordlines WL; forming a material of the insulating patterns 15 to fill the spaces between the sacrificial patterns 14 and between the bitline structures; and planarizing the material of the insulating patterns 15 to expose a top surface of the mask pattern.

[0174] FIG. 11 Operation after the operations of FIG. 10A and FIG. 10B are illustrated. FIG. 11 A cross-sectional view taken along the section line A-A’ in FIG. 4A is illustrated.

[0175] As shown in FIG. 11As shown, the sacrificial pattern 14 can be removed by using a suitable etching operation, such as an isotropic or anisotropic dry etching operation. After the etching operation, a recessed region 10h2 can be formed in the substrate 10 to expose the second doped region 102.

[0176] During the etching operation, the spacer 11s1 can protect the bit line contact 11d from being etched, consumed, or damaged. Therefore, the spacer 11s1 can serve as a protection layer or passivation layer for the bit line contact 11d.

[0177] FIG. 12 Draw FIG. 11 The operation after the operation. FIG. 12 Draw along FIG. 4A A cross-sectional view taken along line AA'.

[0178] like FIG. 12 As shown, the material of the storage node contact 13 can be disposed in the recessed region 10h2. The material of the storage node contact 13 can be disposed adjacent to the bit line structure 11. Subsequently, the material of the storage node contact 13 can be recessed. The recessing process can be performed by a dry etching process, such as an etch-back process.

[0179] FIG. 13 is a flow chart illustrating a method 130 for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0180] In some embodiments, the method 130 may include a step S131 of forming a recessed region in the substrate. FIG. 3A As shown, a recessed region 10h1 may be formed in the first doping region 101 between two word lines WL.

[0181] In some embodiments, the method 130 may include step S132 of forming a bit line structure in the recessed region. FIG. 4A As shown, a plurality of bit line structures (eg, bit line structure 11 and bit line structure 12 ) may be formed on a substrate 10 .

[0182] In some embodiments, the method 130 may include a step S133 of providing a first spacer in the recessed region. FIG. 5A As shown, a material for spacers 11s1 may be formed on opposite sidewalls 11s of the bit line structure 11. A material for spacers 12s1 may be formed on opposite sidewalls of the bit line structure 12. In some embodiments, the materials of the spacers 11s1 and 12s1 may fill the recessed region 10h1 and conformably cover the bit line structures 11 and 12.

[0183] In some embodiments, the method 130 can include a step S134 of performing a surface treatment on the first spacer. For example, as shown in FIG. 13B, a surface treatment can be performed on the material of the spacer 11s1 and the spacer 12s1 to change or modify the surface properties of the material of the spacer 11s1 and the spacer 12s1. FIG. 6A

[0184] In some embodiments, the method 130 can include a step S135 of disposing a second spacer on the bit line structure. For example, as shown in FIG. 13C, a material of the spacer 11s2 can be formed on the opposite sidewalls of the bit line structure 11. A material of the spacer 12s2 can be formed on the opposite sidewalls of the bit line structure 12. FIG. 8A

[0185] In some embodiments, the method 130 can include a step S136 of disposing a third spacer on the bit line structure. For example, as shown in FIG. 13D, a material of the spacer 11s3 can be formed on the opposite sidewalls of the bit line structure 11. A material of the spacer 12s3 can be formed on the opposite sidewalls of the bit line structure 12. FIG. 9A

[0186] In some embodiments, the method 130 can include a step S137 of forming a storage node contact adjacent to the bit line structure. For example, as shown in FIG. 13E, a material of the storage node contact 13 can be disposed in the recessed region 10h2. FIG. 12

[0187] One aspect of the present disclosure provides a semiconductor element. The semiconductor element includes a substrate having a first recessed region, and a first bit line structure in the first recessed region. The first bit line structure has a first spacer, a second spacer, and a third spacer. The first spacer, the second spacer, and the third spacer have different materials.

[0188] Another aspect of the present disclosure provides a semiconductor element. The semiconductor element includes a substrate, and a first bit line structure disposed on the substrate. The first bit line structure has a first spacer continuously disposed on a sidewall of the first bit line structure and filling a space between the first bit line structure and the substrate.

[0189] Another aspect of the present disclosure provides a method of manufacturing a semiconductor element. The method includes forming a first recessed region in a substrate, forming a bit line structure in the first recessed region, and disposing a first spacer in the first recessed region. The method further includes performing a surface treatment on the first spacer and partially removing the first spacer.

[0190] ​​​​The first spacers can prevent the first bit line structure from being damaged or consumed. Thus, the problem of bit line structure leakage current to the storage node contact can be solved. The performance and operation reliability of the semiconductor element can also be improved.

[0191] Furthermore, by using spacers with low dielectric constant, the problem of parasitic capacitance between the bit line structures and / or between the bit line structures and the storage node contact can be further reduced.

[0192] While the disclosure and its advantages have been disclosed in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes can be under taken in a different time sequence than that described, or with other processes or combinations of processes being substituted.

[0193] Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily understand, the disclosure can be practiced with other processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or developed in the future, that can perform substantially the same function or achieve substantially the same result. Accordingly, the present application is not limited to those processes, machines, manufacture, compositions of matter, means, methods, or steps described in the specification.

Claims

1. A semiconductor device, comprising: a substrate having a first recessed region; and a first bit line structure disposed in the first recessed region; wherein the first bit line structure has a first spacer, a second spacer, and a third spacer, and wherein the first spacer, the second spacer, and the third spacer have different materials.

2. The semiconductor device of claim 1, wherein the first bit line structure contacts a first doped region disposed in the substrate.

3. The semiconductor device of claim 1, wherein a sidewall of the first recessed region is sloped with respect to the substrate.

4. The semiconductor device of claim 1, wherein the first spacer comprises a carbon-containing material.

5. The semiconductor device of claim 1, wherein the second spacer is disposed between the first spacer and the third spacer, and a first dielectric constant of the first spacer is less than a second dielectric constant of the second spacer.

6. The semiconductor device of claim 1, wherein the first spacer is disposed in the first recessed region.

7. The semiconductor device of claim 6, wherein the first spacer extends between the first bit line structure and a sidewall of the first recessed region.

8. The semiconductor device of claim 1, further comprising: a second recessed region disposed in the substrate and adjacent to the first recessed region.

9. The semiconductor device of claim 8, further comprising: a storage node contact disposed in the second recessed region.

10. The semiconductor device of claim 9, wherein the first spacer contacts the storage node contact.

11. The semiconductor device of claim 9, wherein the storage node contact contacts a second doped region disposed in the substrate.

12. The semiconductor device of claim 9, wherein a bottom surface of the first recessed region is lower than the storage node contact with respect to the substrate.

13. The semiconductor device of claim 1, further comprising: a second bit line structure disposed over the substrate, wherein the first spacer extends between the first bit line structure and the second bit line structure.

14. The semiconductor device of claim 13, wherein the second bit line structure is separated from the substrate by an intervening layer. ​

Images